drivers/mtd/nand/cafe_nand.c

   1 /*
   2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
   3  *
   4  * The data sheet for this device can be found at:
   5  *    http://wiki.laptop.org/go/Datasheets
   6  *
   7  * Copyright © 2006 Red Hat, Inc.
   8  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/device.h>
  14 #undef DEBUG
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/rslib.h>
  19 #include <linux/pci.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <asm/io.h>
  26
  27 #define CAFE_NAND_CTRL1         0x00
  28 #define CAFE_NAND_CTRL2         0x04
  29 #define CAFE_NAND_CTRL3         0x08
  30 #define CAFE_NAND_STATUS        0x0c
  31 #define CAFE_NAND_IRQ           0x10
  32 #define CAFE_NAND_IRQ_MASK      0x14
  33 #define CAFE_NAND_DATA_LEN      0x18
  34 #define CAFE_NAND_ADDR1         0x1c
  35 #define CAFE_NAND_ADDR2         0x20
  36 #define CAFE_NAND_TIMING1       0x24
  37 #define CAFE_NAND_TIMING2       0x28
  38 #define CAFE_NAND_TIMING3       0x2c
  39 #define CAFE_NAND_NONMEM        0x30
  40 #define CAFE_NAND_ECC_RESULT    0x3C
  41 #define CAFE_NAND_DMA_CTRL      0x40
  42 #define CAFE_NAND_DMA_ADDR0     0x44
  43 #define CAFE_NAND_DMA_ADDR1     0x48
  44 #define CAFE_NAND_ECC_SYN01     0x50
  45 #define CAFE_NAND_ECC_SYN23     0x54
  46 #define CAFE_NAND_ECC_SYN45     0x58
  47 #define CAFE_NAND_ECC_SYN67     0x5c
  48 #define CAFE_NAND_READ_DATA     0x1000
  49 #define CAFE_NAND_WRITE_DATA    0x2000
  50
  51 #define CAFE_GLOBAL_CTRL        0x3004
  52 #define CAFE_GLOBAL_IRQ         0x3008
  53 #define CAFE_GLOBAL_IRQ_MASK    0x300c
  54 #define CAFE_NAND_RESET         0x3034
  55
  56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
  57 #define CTRL1_CHIPSELECT        (1<<19)
  58
  59 struct cafe_priv {
  60         struct nand_chip nand;
  61         struct pci_dev *pdev;
  62         void __iomem *mmio;
  63         struct rs_control *rs;
  64         uint32_t ctl1;
  65         uint32_t ctl2;
  66         int datalen;
  67         int nr_data;
  68         int data_pos;
  69         int page_addr;
  70         dma_addr_t dmaaddr;
  71         unsigned char *dmabuf;
  72 };
  73
  74 static int usedma = 1;
  75 module_param(usedma, int, 0644);
  76
  77 static int skipbbt = 0;
  78 module_param(skipbbt, int, 0644);
  79
  80 static int debug = 0;
  81 module_param(debug, int, 0644);
  82
  83 static int regdebug = 0;
  84 module_param(regdebug, int, 0644);
  85
  86 static int checkecc = 1;
  87 module_param(checkecc, int, 0644);
  88
  89 static unsigned int numtimings;
  90 static int timing[3];
  91 module_param_array(timing, int, &numtimings, 0644);
  92
  93 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
  94
  95 /* Hrm. Why isn't this already conditional on something in the struct device? */
  96 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  97
  98 /* Make it easier to switch to PIO if we need to */
  99 #define cafe_readl(cafe, addr)                  readl((cafe)->mmio + CAFE_##addr)
 100 #define cafe_writel(cafe, datum, addr)          writel(datum, (cafe)->mmio + CAFE_##addr)
 101
 102 static int cafe_device_ready(struct mtd_info *mtd)
 103 {
 104         struct cafe_priv *cafe = mtd->priv;
 105         int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
 106         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
 107
 108         cafe_writel(cafe, irqs, NAND_IRQ);
 109
 110         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
 111                 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
 112                 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 113
 114         return result;
 115 }
 116
 117
 118 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 119 {
 120         struct cafe_priv *cafe = mtd->priv;
 121
 122         if (usedma)
 123                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
 124         else
 125                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
 126
 127         cafe->datalen += len;
 128
 129         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
 130                 len, cafe->datalen);
 131 }
 132
 133 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 134 {
 135         struct cafe_priv *cafe = mtd->priv;
 136
 137         if (usedma)
 138                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
 139         else
 140                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 141
 142         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 143                   len, cafe->datalen);
 144         cafe->datalen += len;
 145 }
 146
 147 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 148 {
 149         struct cafe_priv *cafe = mtd->priv;
 150         uint8_t d;
 151
 152         cafe_read_buf(mtd, &d, 1);
 153         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 154
 155         return d;
 156 }
 157
 158 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 159                               int column, int page_addr)
 160 {
 161         struct cafe_priv *cafe = mtd->priv;
 162         int adrbytes = 0;
 163         uint32_t ctl1;
 164         uint32_t doneint = 0x80000000;
 165
 166         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 167                 command, column, page_addr);
 168
 169         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 170                 /* Second half of a command we already calculated */
 171                 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
 172                 ctl1 = cafe->ctl1;
 173                 cafe->ctl2 &= ~(1<<30);
 174                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 175                           cafe->ctl1, cafe->nr_data);
 176                 goto do_command;
 177         }
 178         /* Reset ECC engine */
 179         cafe_writel(cafe, 0, NAND_CTRL2);
 180
 181         /* Emulate NAND_CMD_READOOB on large-page chips */
 182         if (mtd->writesize > 512 &&
 183             command == NAND_CMD_READOOB) {
 184                 column += mtd->writesize;
 185                 command = NAND_CMD_READ0;
 186         }
 187
 188         /* FIXME: Do we need to send read command before sending data
 189            for small-page chips, to position the buffer correctly? */
 190
 191         if (column != -1) {
 192                 cafe_writel(cafe, column, NAND_ADDR1);
 193                 adrbytes = 2;
 194                 if (page_addr != -1)
 195                         goto write_adr2;
 196         } else if (page_addr != -1) {
 197                 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
 198                 page_addr >>= 16;
 199         write_adr2:
 200                 cafe_writel(cafe, page_addr, NAND_ADDR2);
 201                 adrbytes += 2;
 202                 if (mtd->size > mtd->writesize << 16)
 203                         adrbytes++;
 204         }
 205
 206         cafe->data_pos = cafe->datalen = 0;
 207
 208         /* Set command valid bit, mask in the chip select bit  */
 209         ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
 210
 211         /* Set RD or WR bits as appropriate */
 212         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 213                 ctl1 |= (1<<26); /* rd */
 214                 /* Always 5 bytes, for now */
 215                 cafe->datalen = 4;
 216                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 217                 adrbytes = 1;
 218         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 219                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 220                 ctl1 |= 1<<26; /* rd */
 221                 /* For now, assume just read to end of page */
 222                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 223         } else if (command == NAND_CMD_SEQIN)
 224                 ctl1 |= 1<<25; /* wr */
 225
 226         /* Set number of address bytes */
 227         if (adrbytes)
 228                 ctl1 |= ((adrbytes-1)|8) << 27;
 229
 230         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 231                 /* Ignore the first command of a pair; the hardware
 232                    deals with them both at once, later */
 233                 cafe->ctl1 = ctl1;
 234                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 235                           cafe->ctl1, cafe->datalen);
 236                 return;
 237         }
 238         /* RNDOUT and READ0 commands need a following byte */
 239         if (command == NAND_CMD_RNDOUT)
 240                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
 241         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 242                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
 243
 244  do_command:
 245         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 246                 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
 247
 248         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 249         cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
 250         cafe_writel(cafe, 0x90000000, NAND_IRQ);
 251         if (usedma && (ctl1 & (3<<25))) {
 252                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 253                 /* If WR or RD bits set, set up DMA */
 254                 if (ctl1 & (1<<26)) {
 255                         /* It's a read */
 256                         dmactl |= (1<<29);
 257                         /* ... so it's done when the DMA is done, not just
 258                            the command. */
 259                         doneint = 0x10000000;
 260                 }
 261                 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
 262         }
 263         cafe->datalen = 0;
 264
 265         if (unlikely(regdebug)) {
 266                 int i;
 267                 printk("About to write command %08x to register 0\n", ctl1);
 268                 for (i=4; i< 0x5c; i+=4)
 269                         printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 270         }
 271
 272         cafe_writel(cafe, ctl1, NAND_CTRL1);
 273         /* Apply this short delay always to ensure that we do wait tWB in
 274          * any case on any machine. */
 275         ndelay(100);
 276
 277         if (1) {
 278                 int c;
 279                 uint32_t irqs;
 280
 281                 for (c = 500000; c != 0; c--) {
 282                         irqs = cafe_readl(cafe, NAND_IRQ);
 283                         if (irqs & doneint)
 284                                 break;
 285                         udelay(1);
 286                         if (!(c % 100000))
 287                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 288                         cpu_relax();
 289                 }
 290                 cafe_writel(cafe, doneint, NAND_IRQ);
 291                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
 292                              command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
 293         }
 294
 295         WARN_ON(cafe->ctl2 & (1<<30));
 296
 297         switch (command) {
 298
 299         case NAND_CMD_CACHEDPROG:
 300         case NAND_CMD_PAGEPROG:
 301         case NAND_CMD_ERASE1:
 302         case NAND_CMD_ERASE2:
 303         case NAND_CMD_SEQIN:
 304         case NAND_CMD_RNDIN:
 305         case NAND_CMD_STATUS:
 306         case NAND_CMD_DEPLETE1:
 307         case NAND_CMD_RNDOUT:
 308         case NAND_CMD_STATUS_ERROR:
 309         case NAND_CMD_STATUS_ERROR0:
 310         case NAND_CMD_STATUS_ERROR1:
 311         case NAND_CMD_STATUS_ERROR2:
 312         case NAND_CMD_STATUS_ERROR3:
 313                 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 314                 return;
 315         }
 316         nand_wait_ready(mtd);
 317         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 318 }
 319
 320 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 321 {
 322         struct cafe_priv *cafe = mtd->priv;
 323
 324         cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 325
 326         /* Mask the appropriate bit into the stored value of ctl1
 327            which will be used by cafe_nand_cmdfunc() */
 328         if (chipnr)
 329                 cafe->ctl1 |= CTRL1_CHIPSELECT;
 330         else
 331                 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
 332 }
 333
 334 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
 335 {
 336         struct mtd_info *mtd = id;
 337         struct cafe_priv *cafe = mtd->priv;
 338         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
 339         cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
 340         if (!irqs)
 341                 return IRQ_NONE;
 342
 343         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
 344         return IRQ_HANDLED;
 345 }
 346
 347 static void cafe_nand_bug(struct mtd_info *mtd)
 348 {
 349         BUG();
 350 }
 351
 352 static int cafe_nand_write_oob(struct mtd_info *mtd,
 353                                struct nand_chip *chip, int page)
 354 {
 355         int status = 0;
 356
 357         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 358         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 359         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 360         status = chip->waitfunc(mtd, chip);
 361
 362         return status & NAND_STATUS_FAIL ? -EIO : 0;
 363 }
 364
 365 /* Don't use -- use nand_read_oob_std for now */
 366 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 367                               int page, int sndcmd)
 368 {
 369         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 370         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 371         return 1;
 372 }
 373 /**
 374  * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
 375  * @mtd:        mtd info structure
 376  * @chip:       nand chip info structure
 377  * @buf:        buffer to store read data
 378  *
 379  * The hw generator calculates the error syndrome automatically. Therefor
 380  * we need a special oob layout and handling.
 381  */
 382 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 383                                uint8_t *buf, int page)
 384 {
 385         struct cafe_priv *cafe = mtd->priv;
 386
 387         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
 388                      cafe_readl(cafe, NAND_ECC_RESULT),
 389                      cafe_readl(cafe, NAND_ECC_SYN01));
 390
 391         chip->read_buf(mtd, buf, mtd->writesize);
 392         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 393
 394         if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
 395                 unsigned short syn[8], pat[4];
 396                 int pos[4];
 397                 u8 *oob = chip->oob_poi;
 398                 int i, n;
 399
 400                 for (i=0; i<8; i+=2) {
 401                         uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
 402                         syn[i] = cafe->rs->index_of[tmp & 0xfff];
 403                         syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
 404                 }
 405
 406                 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
 407                                 pat);
 408
 409                 for (i = 0; i < n; i++) {
 410                         int p = pos[i];
 411
 412                         /* The 12-bit symbols are mapped to bytes here */
 413
 414                         if (p > 1374) {
 415                                 /* out of range */
 416                                 n = -1374;
 417                         } else if (p == 0) {
 418                                 /* high four bits do not correspond to data */
 419                                 if (pat[i] > 0xff)
 420                                         n = -2048;
 421                                 else
 422                                         buf[0] ^= pat[i];
 423                         } else if (p == 1365) {
 424                                 buf[2047] ^= pat[i] >> 4;
 425                                 oob[0] ^= pat[i] << 4;
 426                         } else if (p > 1365) {
 427                                 if ((p & 1) == 1) {
 428                                         oob[3*p/2 - 2048] ^= pat[i] >> 4;
 429                                         oob[3*p/2 - 2047] ^= pat[i] << 4;
 430                                 } else {
 431                                         oob[3*p/2 - 2049] ^= pat[i] >> 8;
 432                                         oob[3*p/2 - 2048] ^= pat[i];
 433                                 }
 434                         } else if ((p & 1) == 1) {
 435                                 buf[3*p/2] ^= pat[i] >> 4;
 436                                 buf[3*p/2 + 1] ^= pat[i] << 4;
 437                         } else {
 438                                 buf[3*p/2 - 1] ^= pat[i] >> 8;
 439                                 buf[3*p/2] ^= pat[i];
 440                         }
 441                 }
 442
 443                 if (n < 0) {
 444                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
 445                                 cafe_readl(cafe, NAND_ADDR2) * 2048);
 446                         for (i = 0; i < 0x5c; i += 4)
 447                                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 448                         mtd->ecc_stats.failed++;
 449                 } else {
 450                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
 451                         mtd->ecc_stats.corrected += n;
 452                 }
 453         }
 454
 455         return 0;
 456 }
 457
 458 static struct nand_ecclayout cafe_oobinfo_2048 = {
 459         .eccbytes = 14,
 460         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 461         .oobfree = {{14, 50}}
 462 };
 463
 464 /* Ick. The BBT code really ought to be able to work this bit out
 465    for itself from the above, at least for the 2KiB case */
 466 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
 467 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
 468
 469 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
 470 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
 471
 472
 473 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 474         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 475                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 476         .offs = 14,
 477         .len = 4,
 478         .veroffs = 18,
 479         .maxblocks = 4,
 480         .pattern = cafe_bbt_pattern_2048
 481 };
 482
 483 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 484         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 485                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 486         .offs = 14,
 487         .len = 4,
 488         .veroffs = 18,
 489         .maxblocks = 4,
 490         .pattern = cafe_mirror_pattern_2048
 491 };
 492
 493 static struct nand_ecclayout cafe_oobinfo_512 = {
 494         .eccbytes = 14,
 495         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 496         .oobfree = {{14, 2}}
 497 };
 498
 499 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
 500         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 501                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 502         .offs = 14,
 503         .len = 1,
 504         .veroffs = 15,
 505         .maxblocks = 4,
 506         .pattern = cafe_bbt_pattern_512
 507 };
 508
 509 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 510         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 511                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 512         .offs = 14,
 513         .len = 1,
 514         .veroffs = 15,
 515         .maxblocks = 4,
 516         .pattern = cafe_mirror_pattern_512
 517 };
 518
 519
 520 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 521                                           struct nand_chip *chip, const uint8_t *buf)
 522 {
 523         struct cafe_priv *cafe = mtd->priv;
 524
 525         chip->write_buf(mtd, buf, mtd->writesize);
 526         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 527
 528         /* Set up ECC autogeneration */
 529         cafe->ctl2 |= (1<<30);
 530 }
 531
 532 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 533                                 const uint8_t *buf, int page, int cached, int raw)
 534 {
 535         int status;
 536
 537         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 538
 539         if (unlikely(raw))
 540                 chip->ecc.write_page_raw(mtd, chip, buf);
 541         else
 542                 chip->ecc.write_page(mtd, chip, buf);
 543
 544         /*
 545          * Cached progamming disabled for now, Not sure if its worth the
 546          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 547          */
 548         cached = 0;
 549
 550         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 551
 552                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 553                 status = chip->waitfunc(mtd, chip);
 554                 /*
 555                  * See if operation failed and additional status checks are
 556                  * available
 557                  */
 558                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 559                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 560                                                page);
 561
 562                 if (status & NAND_STATUS_FAIL)
 563                         return -EIO;
 564         } else {
 565                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 566                 status = chip->waitfunc(mtd, chip);
 567         }
 568
 569 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 570         /* Send command to read back the data */
 571         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 572
 573         if (chip->verify_buf(mtd, buf, mtd->writesize))
 574                 return -EIO;
 575 #endif
 576         return 0;
 577 }
 578
 579 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 580 {
 581         return 0;
 582 }
 583
 584 /* F_2[X]/(X**6+X+1)  */
 585 static unsigned short __devinit gf64_mul(u8 a, u8 b)
 586 {
 587         u8 c;
 588         unsigned int i;
 589
 590         c = 0;
 591         for (i = 0; i < 6; i++) {
 592                 if (a & 1)
 593                         c ^= b;
 594                 a >>= 1;
 595                 b <<= 1;
 596                 if ((b & 0x40) != 0)
 597                         b ^= 0x43;
 598         }
 599
 600         return c;
 601 }
 602
 603 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X]  */
 604 static u16 __devinit gf4096_mul(u16 a, u16 b)
 605 {
 606         u8 ah, al, bh, bl, ch, cl;
 607
 608         ah = a >> 6;
 609         al = a & 0x3f;
 610         bh = b >> 6;
 611         bl = b & 0x3f;
 612
 613         ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
 614         cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
 615
 616         return (ch << 6) ^ cl;
 617 }
 618
 619 static int __devinit cafe_mul(int x)
 620 {
 621         if (x == 0)
 622                 return 1;
 623         return gf4096_mul(x, 0xe01);
 624 }
 625
 626 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 627                                      const struct pci_device_id *ent)
 628 {
 629         struct mtd_info *mtd;
 630         struct cafe_priv *cafe;
 631         uint32_t ctrl;
 632         int err = 0;
 633
 634         /* Very old versions shared the same PCI ident for all three
 635            functions on the chip. Verify the class too... */
 636         if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
 637                 return -ENODEV;
 638
 639         err = pci_enable_device(pdev);
 640         if (err)
 641                 return err;
 642
 643         pci_set_master(pdev);
 644
 645         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 646         if (!mtd) {
 647                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 648                 return  -ENOMEM;
 649         }
 650         cafe = (void *)(&mtd[1]);
 651
 652         mtd->dev.parent = &pdev->dev;
 653         mtd->priv = cafe;
 654         mtd->owner = THIS_MODULE;
 655
 656         cafe->pdev = pdev;
 657         cafe->mmio = pci_iomap(pdev, 0, 0);
 658         if (!cafe->mmio) {
 659                 dev_warn(&pdev->dev, "failed to iomap\n");
 660                 err = -ENOMEM;
 661                 goto out_free_mtd;
 662         }
 663         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 664                                           &cafe->dmaaddr, GFP_KERNEL);
 665         if (!cafe->dmabuf) {
 666                 err = -ENOMEM;
 667                 goto out_ior;
 668         }
 669         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 670
 671         cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
 672         if (!cafe->rs) {
 673                 err = -ENOMEM;
 674                 goto out_ior;
 675         }
 676
 677         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 678         cafe->nand.dev_ready = cafe_device_ready;
 679         cafe->nand.read_byte = cafe_read_byte;
 680         cafe->nand.read_buf = cafe_read_buf;
 681         cafe->nand.write_buf = cafe_write_buf;
 682         cafe->nand.select_chip = cafe_select_chip;
 683
 684         cafe->nand.chip_delay = 0;
 685
 686         /* Enable the following for a flash based bad block table */
 687         cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
 688         cafe->nand.options = NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 689
 690         if (skipbbt) {
 691                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 692                 cafe->nand.block_bad = cafe_nand_block_bad;
 693         }
 694
 695         if (numtimings && numtimings != 3) {
 696                 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
 697         }
 698
 699         if (numtimings == 3) {
 700                 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
 701                              timing[0], timing[1], timing[2]);
 702         } else {
 703                 timing[0] = cafe_readl(cafe, NAND_TIMING1);
 704                 timing[1] = cafe_readl(cafe, NAND_TIMING2);
 705                 timing[2] = cafe_readl(cafe, NAND_TIMING3);
 706
 707                 if (timing[0] | timing[1] | timing[2]) {
 708                         cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
 709                                      timing[0], timing[1], timing[2]);
 710                 } else {
 711                         dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
 712                         timing[0] = timing[1] = timing[2] = 0xffffffff;
 713                 }
 714         }
 715
 716         /* Start off by resetting the NAND controller completely */
 717         cafe_writel(cafe, 1, NAND_RESET);
 718         cafe_writel(cafe, 0, NAND_RESET);
 719
 720         cafe_writel(cafe, timing[0], NAND_TIMING1);
 721         cafe_writel(cafe, timing[1], NAND_TIMING2);
 722         cafe_writel(cafe, timing[2], NAND_TIMING3);
 723
 724         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 725         err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
 726                           "CAFE NAND", mtd);
 727         if (err) {
 728                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 729                 goto out_free_dma;
 730         }
 731
 732         /* Disable master reset, enable NAND clock */
 733         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
 734         ctrl &= 0xffffeff0;
 735         ctrl |= 0x00007000;
 736         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
 737         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
 738         cafe_writel(cafe, 0, NAND_DMA_CTRL);
 739
 740         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
 741         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
 742
 743         /* Set up DMA address */
 744         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
 745         if (sizeof(cafe->dmaaddr) > 4)
 746                 /* Shift in two parts to shut the compiler up */
 747                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
 748         else
 749                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
 750
 751         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 752                 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
 753
 754         /* Enable NAND IRQ in global IRQ mask register */
 755         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
 756         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 757                 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 758
 759         /* Scan to find existence of the device */
 760         if (nand_scan_ident(mtd, 2, NULL)) {
 761                 err = -ENXIO;
 762                 goto out_irq;
 763         }
 764
 765         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 766         if (mtd->writesize == 2048)
 767                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 768
 769         /* Set up ECC according to the type of chip we found */
 770         if (mtd->writesize == 2048) {
 771                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 772                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 773                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 774         } else if (mtd->writesize == 512) {
 775                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
 776                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
 777                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
 778         } else {
 779                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
 780                        mtd->writesize);
 781                 goto out_irq;
 782         }
 783         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 784         cafe->nand.ecc.size = mtd->writesize;
 785         cafe->nand.ecc.bytes = 14;
 786         cafe->nand.ecc.strength = 4;
 787         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 788         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 789         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 790         cafe->nand.write_page = cafe_nand_write_page;
 791         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 792         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 793         cafe->nand.ecc.read_page = cafe_nand_read_page;
 794         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 795
 796         err = nand_scan_tail(mtd);
 797         if (err)
 798                 goto out_irq;
 799
 800         pci_set_drvdata(pdev, mtd);
 801
 802         mtd->name = "cafe_nand";
 803         mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
 804
 805         goto out;
 806
 807  out_irq:
 808         /* Disable NAND IRQ in global IRQ mask register */
 809         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 810         free_irq(pdev->irq, mtd);
 811  out_free_dma:
 812         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 813  out_ior:
 814         pci_iounmap(pdev, cafe->mmio);
 815  out_free_mtd:
 816         kfree(mtd);
 817  out:
 818         return err;
 819 }
 820
 821 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 822 {
 823         struct mtd_info *mtd = pci_get_drvdata(pdev);
 824         struct cafe_priv *cafe = mtd->priv;
 825
 826         /* Disable NAND IRQ in global IRQ mask register */
 827         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 828         free_irq(pdev->irq, mtd);
 829         nand_release(mtd);
 830         free_rs(cafe->rs);
 831         pci_iounmap(pdev, cafe->mmio);
 832         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 833         kfree(mtd);
 834 }
 835
 836 static const struct pci_device_id cafe_nand_tbl[] = {
 837         { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
 838           PCI_ANY_ID, PCI_ANY_ID },
 839         { }
 840 };
 841
 842 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 843
 844 static int cafe_nand_resume(struct pci_dev *pdev)
 845 {
 846         uint32_t ctrl;
 847         struct mtd_info *mtd = pci_get_drvdata(pdev);
 848         struct cafe_priv *cafe = mtd->priv;
 849
 850        /* Start off by resetting the NAND controller completely */
 851         cafe_writel(cafe, 1, NAND_RESET);
 852         cafe_writel(cafe, 0, NAND_RESET);
 853         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 854
 855         /* Restore timing configuration */
 856         cafe_writel(cafe, timing[0], NAND_TIMING1);
 857         cafe_writel(cafe, timing[1], NAND_TIMING2);
 858         cafe_writel(cafe, timing[2], NAND_TIMING3);
 859
 860         /* Disable master reset, enable NAND clock */
 861         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
 862         ctrl &= 0xffffeff0;
 863         ctrl |= 0x00007000;
 864         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
 865         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
 866         cafe_writel(cafe, 0, NAND_DMA_CTRL);
 867         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
 868         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
 869
 870         /* Set up DMA address */
 871         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
 872         if (sizeof(cafe->dmaaddr) > 4)
 873         /* Shift in two parts to shut the compiler up */
 874                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
 875         else
 876                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
 877
 878         /* Enable NAND IRQ in global IRQ mask register */
 879         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
 880         return 0;
 881 }
 882
 883 static struct pci_driver cafe_nand_pci_driver = {
 884         .name = "CAFÉ NAND",
 885         .id_table = cafe_nand_tbl,
 886         .probe = cafe_nand_probe,
 887         .remove = __devexit_p(cafe_nand_remove),
 888         .resume = cafe_nand_resume,
 889 };
 890
 891 static int __init cafe_nand_init(void)
 892 {
 893         return pci_register_driver(&cafe_nand_pci_driver);
 894 }
 895
 896 static void __exit cafe_nand_exit(void)
 897 {
 898         pci_unregister_driver(&cafe_nand_pci_driver);
 899 }
 900 module_init(cafe_nand_init);
 901 module_exit(cafe_nand_exit);
 902
 903 MODULE_LICENSE("GPL");
 904 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 905 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");