2 * Toshiba PCI Secure Digital Host Controller Interface driver
4 * Copyright (C) 2014 Ondrej Zary
5 * Copyright (C) 2007 Richard Betts, All Rights Reserved.
7 * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
8 * sdhci.c, copyright (C) 2005-2006 Pierre Ossman
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/scatterlist.h>
21 #include <linux/interrupt.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
29 #define DRIVER_NAME "toshsd"
31 static const struct pci_device_id pci_ids[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0805) },
33 { /* end: all zeroes */ },
36 MODULE_DEVICE_TABLE(pci, pci_ids);
38 static void toshsd_init(struct toshsd_host *host)
41 pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP,
42 SD_PCICFG_CLKSTOP_ENABLE_ALL);
43 pci_write_config_byte(host->pdev, SD_PCICFG_CARDDETECT, 2);
46 iowrite16(0, host->ioaddr + SD_SOFTWARERESET); /* assert */
48 iowrite16(1, host->ioaddr + SD_SOFTWARERESET); /* deassert */
51 /* Clear card registers */
52 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
53 iowrite32(0, host->ioaddr + SD_CARDSTATUS);
54 iowrite32(0, host->ioaddr + SD_ERRORSTATUS0);
55 iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
58 iowrite16(0x100, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
61 pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE1,
62 SD_PCICFG_LED_ENABLE1_START);
63 pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE2,
64 SD_PCICFG_LED_ENABLE2_START);
66 /* set interrupt masks */
67 iowrite32(~(u32)(SD_CARD_RESP_END | SD_CARD_RW_END
68 | SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0
69 | SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE
70 | SD_BUF_CMD_TIMEOUT),
71 host->ioaddr + SD_INTMASKCARD);
73 iowrite16(0x1000, host->ioaddr + SD_TRANSACTIONCTRL);
76 /* Set MMC clock / power.
77 * Note: This controller uses a simple divider scheme therefore it cannot run
78 * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
79 * and the next slowest is 16MHz (div=2).
81 static void __toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
83 struct toshsd_host *host = mmc_priv(mmc);
89 while (ios->clock < HCLK / div)
94 if (div == 1) { /* disable the divider */
95 pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE,
96 SD_PCICFG_CLKMODE_DIV_DISABLE);
97 clk |= SD_CARDCLK_DIV_DISABLE;
99 pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE, 0);
101 clk |= SD_CARDCLK_ENABLE_CLOCK;
102 iowrite16(clk, host->ioaddr + SD_CARDCLOCKCTRL);
106 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
108 switch (ios->power_mode) {
110 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
117 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
119 pci_write_config_byte(host->pdev, SD_PCICFG_POWER2,
120 SD_PCICFG_PWR2_AUTO);
125 switch (ios->bus_width) {
126 case MMC_BUS_WIDTH_1:
127 iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
128 | SD_CARDOPT_C2_MODULE_ABSENT
129 | SD_CARDOPT_DATA_XFR_WIDTH_1,
130 host->ioaddr + SD_CARDOPTIONSETUP);
132 case MMC_BUS_WIDTH_4:
133 iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
134 | SD_CARDOPT_C2_MODULE_ABSENT
135 | SD_CARDOPT_DATA_XFR_WIDTH_4,
136 host->ioaddr + SD_CARDOPTIONSETUP);
141 static void toshsd_set_led(struct toshsd_host *host, unsigned char state)
143 iowrite16(state, host->ioaddr + SDIO_BASE + SDIO_LEDCTRL);
146 static void toshsd_finish_request(struct toshsd_host *host)
148 struct mmc_request *mrq = host->mrq;
150 /* Write something to end the command */
155 toshsd_set_led(host, 0);
156 mmc_request_done(host->mmc, mrq);
159 static irqreturn_t toshsd_thread_irq(int irq, void *dev_id)
161 struct toshsd_host *host = dev_id;
162 struct mmc_data *data = host->data;
163 struct sg_mapping_iter *sg_miter = &host->sg_miter;
169 dev_warn(&host->pdev->dev, "Spurious Data IRQ\n");
171 host->cmd->error = -EIO;
172 toshsd_finish_request(host);
176 spin_lock_irqsave(&host->lock, flags);
178 if (!sg_miter_next(sg_miter))
180 buf = sg_miter->addr;
182 /* Ensure we dont read more than one block. The chip will interrupt us
183 * When the next block is available.
185 count = sg_miter->length;
186 if (count > data->blksz)
189 dev_dbg(&host->pdev->dev, "count: %08x, flags %08x\n", count,
192 /* Transfer the data */
193 if (data->flags & MMC_DATA_READ)
194 ioread32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
196 iowrite32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
198 sg_miter->consumed = count;
199 sg_miter_stop(sg_miter);
201 spin_unlock_irqrestore(&host->lock, flags);
206 static void toshsd_cmd_irq(struct toshsd_host *host)
208 struct mmc_command *cmd = host->cmd;
213 dev_warn(&host->pdev->dev, "Spurious CMD irq\n");
216 buf = (u8 *)cmd->resp;
219 if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) {
222 data = ioread16(host->ioaddr + SD_RESPONSE0);
223 buf[13] = data & 0xff;
225 data = ioread16(host->ioaddr + SD_RESPONSE1);
226 buf[15] = data & 0xff;
228 data = ioread16(host->ioaddr + SD_RESPONSE2);
229 buf[9] = data & 0xff;
231 data = ioread16(host->ioaddr + SD_RESPONSE3);
232 buf[11] = data & 0xff;
234 data = ioread16(host->ioaddr + SD_RESPONSE4);
235 buf[5] = data & 0xff;
237 data = ioread16(host->ioaddr + SD_RESPONSE5);
238 buf[7] = data & 0xff;
240 data = ioread16(host->ioaddr + SD_RESPONSE6);
241 buf[1] = data & 0xff;
243 data = ioread16(host->ioaddr + SD_RESPONSE7);
244 buf[3] = data & 0xff;
245 } else if (cmd->flags & MMC_RSP_PRESENT) {
246 /* R1, R1B, R3, R6, R7 */
247 data = ioread16(host->ioaddr + SD_RESPONSE0);
248 buf[0] = data & 0xff;
250 data = ioread16(host->ioaddr + SD_RESPONSE1);
251 buf[2] = data & 0xff;
255 dev_dbg(&host->pdev->dev, "Command IRQ complete %d %d %x\n",
256 cmd->opcode, cmd->error, cmd->flags);
258 /* If there is data to handle we will
259 * finish the request in the mmc_data_end_irq handler.*/
263 toshsd_finish_request(host);
266 static void toshsd_data_end_irq(struct toshsd_host *host)
268 struct mmc_data *data = host->data;
273 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
277 if (data->error == 0)
278 data->bytes_xfered = data->blocks * data->blksz;
280 data->bytes_xfered = 0;
282 dev_dbg(&host->pdev->dev, "Completed data request xfr=%d\n",
285 iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
287 toshsd_finish_request(host);
290 static irqreturn_t toshsd_irq(int irq, void *dev_id)
292 struct toshsd_host *host = dev_id;
293 u32 int_reg, int_mask, int_status, detail;
294 int error = 0, ret = IRQ_HANDLED;
296 spin_lock(&host->lock);
297 int_status = ioread32(host->ioaddr + SD_CARDSTATUS);
298 int_mask = ioread32(host->ioaddr + SD_INTMASKCARD);
299 int_reg = int_status & ~int_mask & ~IRQ_DONT_CARE_BITS;
301 dev_dbg(&host->pdev->dev, "IRQ status:%x mask:%x\n",
302 int_status, int_mask);
304 /* nothing to do: it's not our IRQ */
310 if (int_reg & SD_BUF_CMD_TIMEOUT) {
312 dev_dbg(&host->pdev->dev, "Timeout\n");
313 } else if (int_reg & SD_BUF_CRC_ERR) {
315 dev_err(&host->pdev->dev, "BadCRC\n");
316 } else if (int_reg & (SD_BUF_ILLEGAL_ACCESS
317 | SD_BUF_CMD_INDEX_ERR
318 | SD_BUF_STOP_BIT_END_ERR
321 | SD_BUF_DATA_TIMEOUT)) {
322 dev_err(&host->pdev->dev, "Buffer status error: { %s%s%s%s%s%s}\n",
323 int_reg & SD_BUF_ILLEGAL_ACCESS ? "ILLEGAL_ACC " : "",
324 int_reg & SD_BUF_CMD_INDEX_ERR ? "CMD_INDEX " : "",
325 int_reg & SD_BUF_STOP_BIT_END_ERR ? "STOPBIT_END " : "",
326 int_reg & SD_BUF_OVERFLOW ? "OVERFLOW " : "",
327 int_reg & SD_BUF_UNDERFLOW ? "UNDERFLOW " : "",
328 int_reg & SD_BUF_DATA_TIMEOUT ? "DATA_TIMEOUT " : "");
330 detail = ioread32(host->ioaddr + SD_ERRORSTATUS0);
331 dev_err(&host->pdev->dev, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
332 detail & SD_ERR0_RESP_CMD_ERR ? "RESP_CMD " : "",
333 detail & SD_ERR0_RESP_NON_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
334 detail & SD_ERR0_RESP_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
335 detail & SD_ERR0_READ_DATA_END_BIT_ERR ? "READ_DATA_END_BIT " : "",
336 detail & SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR ? "WRITE_CMD_END_BIT " : "",
337 detail & SD_ERR0_RESP_NON_CMD12_CRC_ERR ? "RESP_CRC " : "",
338 detail & SD_ERR0_RESP_CMD12_CRC_ERR ? "RESP_CRC " : "",
339 detail & SD_ERR0_READ_DATA_CRC_ERR ? "READ_DATA_CRC " : "",
340 detail & SD_ERR0_WRITE_CMD_CRC_ERR ? "WRITE_CMD_CRC " : "",
341 detail & SD_ERR1_NO_CMD_RESP ? "NO_CMD_RESP " : "",
342 detail & SD_ERR1_TIMEOUT_READ_DATA ? "READ_DATA_TIMEOUT " : "",
343 detail & SD_ERR1_TIMEOUT_CRS_STATUS ? "CRS_STATUS_TIMEOUT " : "",
344 detail & SD_ERR1_TIMEOUT_CRC_BUSY ? "CRC_BUSY_TIMEOUT " : "");
350 host->cmd->error = error;
352 if (error == -ETIMEDOUT) {
353 iowrite32(int_status &
354 ~(SD_BUF_CMD_TIMEOUT | SD_CARD_RESP_END),
355 host->ioaddr + SD_CARDSTATUS);
358 __toshsd_set_ios(host->mmc, &host->mmc->ios);
363 /* Card insert/remove. The mmc controlling code is stateless. */
364 if (int_reg & (SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0)) {
365 iowrite32(int_status &
366 ~(SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0),
367 host->ioaddr + SD_CARDSTATUS);
369 if (int_reg & SD_CARD_CARD_INSERTED_0)
372 mmc_detect_change(host->mmc, 1);
376 if (int_reg & (SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE)) {
377 iowrite32(int_status &
378 ~(SD_BUF_WRITE_ENABLE | SD_BUF_READ_ENABLE),
379 host->ioaddr + SD_CARDSTATUS);
381 ret = IRQ_WAKE_THREAD;
385 /* Command completion */
386 if (int_reg & SD_CARD_RESP_END) {
387 iowrite32(int_status & ~(SD_CARD_RESP_END),
388 host->ioaddr + SD_CARDSTATUS);
389 toshsd_cmd_irq(host);
392 /* Data transfer completion */
393 if (int_reg & SD_CARD_RW_END) {
394 iowrite32(int_status & ~(SD_CARD_RW_END),
395 host->ioaddr + SD_CARDSTATUS);
396 toshsd_data_end_irq(host);
399 spin_unlock(&host->lock);
403 static void toshsd_start_cmd(struct toshsd_host *host, struct mmc_command *cmd)
405 struct mmc_data *data = host->data;
408 dev_dbg(&host->pdev->dev, "Command opcode: %d\n", cmd->opcode);
410 if (cmd->opcode == MMC_STOP_TRANSMISSION) {
411 iowrite16(SD_STOPINT_ISSUE_CMD12,
412 host->ioaddr + SD_STOPINTERNAL);
414 cmd->resp[0] = cmd->opcode;
419 toshsd_finish_request(host);
423 switch (mmc_resp_type(cmd)) {
425 c |= SD_CMD_RESP_TYPE_NONE;
429 c |= SD_CMD_RESP_TYPE_EXT_R1;
432 c |= SD_CMD_RESP_TYPE_EXT_R1B;
435 c |= SD_CMD_RESP_TYPE_EXT_R2;
438 c |= SD_CMD_RESP_TYPE_EXT_R3;
442 dev_err(&host->pdev->dev, "Unknown response type %d\n",
449 if (cmd->opcode == MMC_APP_CMD)
450 c |= SD_CMD_TYPE_ACMD;
452 if (cmd->opcode == MMC_GO_IDLE_STATE)
453 c |= (3 << 8); /* removed from ipaq-asic3.h for some reason */
456 c |= SD_CMD_DATA_PRESENT;
458 if (data->blocks > 1) {
459 iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12,
460 host->ioaddr + SD_STOPINTERNAL);
461 c |= SD_CMD_MULTI_BLOCK;
464 if (data->flags & MMC_DATA_READ)
465 c |= SD_CMD_TRANSFER_READ;
467 /* MMC_DATA_WRITE does not require a bit to be set */
470 /* Send the command */
471 iowrite32(cmd->arg, host->ioaddr + SD_ARG0);
472 iowrite16(c, host->ioaddr + SD_CMD);
475 static void toshsd_start_data(struct toshsd_host *host, struct mmc_data *data)
477 unsigned int flags = SG_MITER_ATOMIC;
479 dev_dbg(&host->pdev->dev, "setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n",
480 data->blksz, data->blocks, data->sg->offset);
484 if (data->flags & MMC_DATA_READ)
485 flags |= SG_MITER_TO_SG;
487 flags |= SG_MITER_FROM_SG;
489 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
491 /* Set transfer length and blocksize */
492 iowrite16(data->blocks, host->ioaddr + SD_BLOCKCOUNT);
493 iowrite16(data->blksz, host->ioaddr + SD_CARDXFERDATALEN);
496 /* Process requests from the MMC layer */
497 static void toshsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
499 struct toshsd_host *host = mmc_priv(mmc);
502 /* abort if card not present */
503 if (!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0)) {
504 mrq->cmd->error = -ENOMEDIUM;
505 mmc_request_done(mmc, mrq);
509 spin_lock_irqsave(&host->lock, flags);
511 WARN_ON(host->mrq != NULL);
516 toshsd_start_data(host, mrq->data);
518 toshsd_set_led(host, 1);
520 toshsd_start_cmd(host, mrq->cmd);
522 spin_unlock_irqrestore(&host->lock, flags);
525 static void toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
527 struct toshsd_host *host = mmc_priv(mmc);
530 spin_lock_irqsave(&host->lock, flags);
531 __toshsd_set_ios(mmc, ios);
532 spin_unlock_irqrestore(&host->lock, flags);
535 static int toshsd_get_ro(struct mmc_host *mmc)
537 struct toshsd_host *host = mmc_priv(mmc);
540 return !(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_WRITE_PROTECT);
543 static int toshsd_get_cd(struct mmc_host *mmc)
545 struct toshsd_host *host = mmc_priv(mmc);
547 return !!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0);
550 static struct mmc_host_ops toshsd_ops = {
551 .request = toshsd_request,
552 .set_ios = toshsd_set_ios,
553 .get_ro = toshsd_get_ro,
554 .get_cd = toshsd_get_cd,
558 static void toshsd_powerdown(struct toshsd_host *host)
560 /* mask all interrupts */
561 iowrite32(0xffffffff, host->ioaddr + SD_INTMASKCARD);
562 /* disable card clock */
563 iowrite16(0x000, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
564 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
565 /* power down card */
566 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1, SD_PCICFG_PWR1_OFF);
568 pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP, 0);
571 #ifdef CONFIG_PM_SLEEP
572 static int toshsd_pm_suspend(struct device *dev)
574 struct pci_dev *pdev = to_pci_dev(dev);
575 struct toshsd_host *host = pci_get_drvdata(pdev);
577 toshsd_powerdown(host);
579 pci_save_state(pdev);
580 pci_enable_wake(pdev, PCI_D3hot, 0);
581 pci_disable_device(pdev);
582 pci_set_power_state(pdev, PCI_D3hot);
587 static int toshsd_pm_resume(struct device *dev)
589 struct pci_dev *pdev = to_pci_dev(dev);
590 struct toshsd_host *host = pci_get_drvdata(pdev);
593 pci_set_power_state(pdev, PCI_D0);
594 pci_restore_state(pdev);
595 ret = pci_enable_device(pdev);
603 #endif /* CONFIG_PM_SLEEP */
605 static int toshsd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
608 struct toshsd_host *host;
609 struct mmc_host *mmc;
610 resource_size_t base;
612 ret = pci_enable_device(pdev);
616 mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev);
622 host = mmc_priv(mmc);
626 pci_set_drvdata(pdev, host);
628 ret = pci_request_regions(pdev, DRIVER_NAME);
632 host->ioaddr = pci_iomap(pdev, 0, 0);
638 /* Set MMC host parameters */
639 mmc->ops = &toshsd_ops;
640 mmc->caps = MMC_CAP_4_BIT_DATA;
641 mmc->ocr_avail = MMC_VDD_32_33;
643 mmc->f_min = HCLK / 512;
646 spin_lock_init(&host->lock);
650 ret = request_threaded_irq(pdev->irq, toshsd_irq, toshsd_thread_irq,
651 IRQF_SHARED, DRIVER_NAME, host);
657 base = pci_resource_start(pdev, 0);
658 dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq);
660 pm_suspend_ignore_children(&pdev->dev, 1);
665 pci_iounmap(pdev, host->ioaddr);
667 pci_release_regions(pdev);
670 pci_set_drvdata(pdev, NULL);
672 pci_disable_device(pdev);
676 static void toshsd_remove(struct pci_dev *pdev)
678 struct toshsd_host *host = pci_get_drvdata(pdev);
680 mmc_remove_host(host->mmc);
681 toshsd_powerdown(host);
682 free_irq(pdev->irq, host);
683 pci_iounmap(pdev, host->ioaddr);
684 pci_release_regions(pdev);
685 mmc_free_host(host->mmc);
686 pci_set_drvdata(pdev, NULL);
687 pci_disable_device(pdev);
690 static const struct dev_pm_ops toshsd_pm_ops = {
691 SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend, toshsd_pm_resume)
694 static struct pci_driver toshsd_driver = {
697 .probe = toshsd_probe,
698 .remove = toshsd_remove,
699 .driver.pm = &toshsd_pm_ops,
702 static int __init toshsd_drv_init(void)
704 return pci_register_driver(&toshsd_driver);
707 static void __exit toshsd_drv_exit(void)
709 pci_unregister_driver(&toshsd_driver);
712 module_init(toshsd_drv_init);
713 module_exit(toshsd_drv_exit);
715 MODULE_AUTHOR("Ondrej Zary, Richard Betts");
716 MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
717 MODULE_LICENSE("GPL");