2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
8 * Based on sdhci-of-esdhc.c
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/regmap.h>
28 #include "sdhci-pltfm.h"
30 #define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
31 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
33 #define VENDOR_ENHANCED_STROBE BIT(0)
34 #define CLK_CTRL_TIMEOUT_SHIFT 16
35 #define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
36 #define CLK_CTRL_TIMEOUT_MIN_EXP 13
38 #define PHY_CLK_TOO_SLOW_HZ 400000
41 * On some SoCs the syscon area has a feature where the upper 16-bits of
42 * each 32-bit register act as a write mask for the lower 16-bits. This allows
43 * atomic updates of the register without locking. This macro is used on SoCs
44 * that have that feature.
46 #define HIWORD_UPDATE(val, mask, shift) \
47 ((val) << (shift) | (mask) << ((shift) + 16))
50 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
52 * @reg: Offset within the syscon of the register containing this field
53 * @width: Number of bits for this field
54 * @shift: Bit offset within @reg of this field (or -1 if not avail)
56 struct sdhci_arasan_soc_ctl_field {
63 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
65 * It's up to the licensee of the Arsan IP block to make these available
66 * somewhere if needed. Presumably these will be scattered somewhere that's
67 * accessible via the syscon API.
69 * @baseclkfreq: Where to find corecfg_baseclkfreq
70 * @clockmultiplier: Where to find corecfg_clockmultiplier
71 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
73 struct sdhci_arasan_soc_ctl_map {
74 struct sdhci_arasan_soc_ctl_field baseclkfreq;
75 struct sdhci_arasan_soc_ctl_field clockmultiplier;
80 * struct sdhci_arasan_data
81 * @host: Pointer to the main SDHCI host structure.
82 * @clk_ahb: Pointer to the AHB clock
83 * @phy: Pointer to the generic phy
84 * @is_phy_on: True if the PHY is on; false if not.
85 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
86 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
87 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
88 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
90 struct sdhci_arasan_data {
91 struct sdhci_host *host;
96 struct clk_hw sdcardclk_hw;
97 struct clk *sdcardclk;
99 struct regmap *soc_ctl_base;
100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
103 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
104 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
105 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
106 .hiword_update = true,
110 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
112 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
113 * Note that if a field is specified as not available (shift < 0) then
114 * this function will silently return an error code. It will be noisy
115 * and print errors for any other (unexpected) errors.
117 * @host: The sdhci_host
118 * @fld: The field to write to
119 * @val: The value to write
121 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
122 const struct sdhci_arasan_soc_ctl_field *fld,
125 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
126 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
127 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
129 u16 width = fld->width;
130 s16 shift = fld->shift;
134 * Silently return errors for shift < 0 so caller doesn't have
135 * to check for fields which are optional. For fields that
136 * are required then caller needs to do something special
142 if (sdhci_arasan->soc_ctl_map->hiword_update)
143 ret = regmap_write(soc_ctl_base, reg,
144 HIWORD_UPDATE(val, GENMASK(width, 0),
147 ret = regmap_update_bits(soc_ctl_base, reg,
148 GENMASK(shift + width, shift),
151 /* Yell about (unexpected) regmap errors */
153 pr_warn("%s: Regmap write fail: %d\n",
154 mmc_hostname(host->mmc), ret);
159 static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
165 div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
166 div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
168 freq = clk_get_rate(pltfm_host->clk);
169 freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
174 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
177 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
178 bool ctrl_phy = false;
180 if (!IS_ERR(sdhci_arasan->phy)) {
181 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
183 * If PHY off, set clock to max speed and power PHY on.
185 * Although PHY docs apparently suggest power cycling
186 * when changing the clock the PHY doesn't like to be
187 * powered on while at low speeds like those used in ID
188 * mode. Even worse is powering the PHY on while the
191 * To workaround the PHY limitations, the best we can
192 * do is to power it on at a faster speed and then slam
193 * through low speeds without power cycling.
195 sdhci_set_clock(host, host->max_clk);
196 spin_unlock_irq(&host->lock);
197 phy_power_on(sdhci_arasan->phy);
198 spin_lock_irq(&host->lock);
199 sdhci_arasan->is_phy_on = true;
202 * We'll now fall through to the below case with
203 * ctrl_phy = false (so we won't turn off/on). The
204 * sdhci_set_clock() will set the real clock.
206 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
208 * At higher clock speeds the PHY is fine being power
209 * cycled and docs say you _should_ power cycle when
210 * changing clock speeds.
216 if (ctrl_phy && sdhci_arasan->is_phy_on) {
217 spin_unlock_irq(&host->lock);
218 phy_power_off(sdhci_arasan->phy);
219 spin_lock_irq(&host->lock);
220 sdhci_arasan->is_phy_on = false;
223 sdhci_set_clock(host, clock);
226 spin_unlock_irq(&host->lock);
227 phy_power_on(sdhci_arasan->phy);
228 spin_lock_irq(&host->lock);
229 sdhci_arasan->is_phy_on = true;
233 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
237 struct sdhci_host *host = mmc_priv(mmc);
239 vendor = readl(host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
240 if (ios->enhanced_strobe)
241 vendor |= VENDOR_ENHANCED_STROBE;
243 vendor &= ~VENDOR_ENHANCED_STROBE;
245 writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
248 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
251 switch (ios->signal_voltage) {
252 case MMC_SIGNAL_VOLTAGE_180:
254 * Plese don't switch to 1V8 as arasan,5.1 doesn't
255 * actually refer to this setting to indicate the
256 * signal voltage and the state machine will be broken
257 * actually if we force to enable 1V8. That's something
258 * like broken quirk but we could work around here.
261 case MMC_SIGNAL_VOLTAGE_330:
262 case MMC_SIGNAL_VOLTAGE_120:
263 /* We don't support 3V3 and 1V2 */
270 static struct sdhci_ops sdhci_arasan_ops = {
271 .set_clock = sdhci_arasan_set_clock,
272 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
273 .get_timeout_clock = sdhci_arasan_get_timeout_clock,
274 .set_bus_width = sdhci_set_bus_width,
275 .reset = sdhci_reset,
276 .set_uhs_signaling = sdhci_set_uhs_signaling,
279 static struct sdhci_pltfm_data sdhci_arasan_pdata = {
280 .ops = &sdhci_arasan_ops,
281 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
282 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
283 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
286 #ifdef CONFIG_PM_SLEEP
288 * sdhci_arasan_suspend - Suspend method for the driver
289 * @dev: Address of the device structure
290 * Returns 0 on success and error value on error
292 * Put the device in a low power state.
294 static int sdhci_arasan_suspend(struct device *dev)
296 struct platform_device *pdev = to_platform_device(dev);
297 struct sdhci_host *host = platform_get_drvdata(pdev);
298 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
299 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
302 ret = sdhci_suspend_host(host);
306 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
307 ret = phy_power_off(sdhci_arasan->phy);
309 dev_err(dev, "Cannot power off phy.\n");
310 sdhci_resume_host(host);
313 sdhci_arasan->is_phy_on = false;
316 clk_disable(pltfm_host->clk);
317 clk_disable(sdhci_arasan->clk_ahb);
323 * sdhci_arasan_resume - Resume method for the driver
324 * @dev: Address of the device structure
325 * Returns 0 on success and error value on error
327 * Resume operation after suspend
329 static int sdhci_arasan_resume(struct device *dev)
331 struct platform_device *pdev = to_platform_device(dev);
332 struct sdhci_host *host = platform_get_drvdata(pdev);
333 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
334 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
337 ret = clk_enable(sdhci_arasan->clk_ahb);
339 dev_err(dev, "Cannot enable AHB clock.\n");
343 ret = clk_enable(pltfm_host->clk);
345 dev_err(dev, "Cannot enable SD clock.\n");
349 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
350 ret = phy_power_on(sdhci_arasan->phy);
352 dev_err(dev, "Cannot power on phy.\n");
355 sdhci_arasan->is_phy_on = true;
358 return sdhci_resume_host(host);
360 #endif /* ! CONFIG_PM_SLEEP */
362 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
363 sdhci_arasan_resume);
365 static const struct of_device_id sdhci_arasan_of_match[] = {
366 /* SoC-specific compatible strings w/ soc_ctl_map */
368 .compatible = "rockchip,rk3399-sdhci-5.1",
369 .data = &rk3399_soc_ctl_map,
372 /* Generic compatible below here */
373 { .compatible = "arasan,sdhci-8.9a" },
374 { .compatible = "arasan,sdhci-5.1" },
375 { .compatible = "arasan,sdhci-4.9a" },
379 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
382 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
384 * Return the current actual rate of the SD card clock. This can be used
385 * to communicate with out PHY.
387 * @hw: Pointer to the hardware clock structure.
388 * @parent_rate The parent rate (should be rate of clk_xin).
389 * Returns the card clock rate.
391 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
392 unsigned long parent_rate)
395 struct sdhci_arasan_data *sdhci_arasan =
396 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
397 struct sdhci_host *host = sdhci_arasan->host;
399 return host->mmc->actual_clock;
402 static const struct clk_ops arasan_sdcardclk_ops = {
403 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
407 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
409 * The corecfg_clockmultiplier is supposed to contain clock multiplier
410 * value of programmable clock generator.
413 * - Many existing devices don't seem to do this and work fine. To keep
414 * compatibility for old hardware where the device tree doesn't provide a
415 * register map, this function is a noop if a soc_ctl_map hasn't been provided
417 * - The value of corecfg_clockmultiplier should sync with that of corresponding
418 * value reading from sdhci_capability_register. So this function is called
419 * once at probe time and never called again.
421 * @host: The sdhci_host
423 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
426 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
427 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
428 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
429 sdhci_arasan->soc_ctl_map;
431 /* Having a map is optional */
435 /* If we have a map, we expect to have a syscon */
436 if (!sdhci_arasan->soc_ctl_base) {
437 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
438 mmc_hostname(host->mmc));
442 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
446 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
448 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
449 * function can be used to make that happen.
452 * - Many existing devices don't seem to do this and work fine. To keep
453 * compatibility for old hardware where the device tree doesn't provide a
454 * register map, this function is a noop if a soc_ctl_map hasn't been provided
456 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
457 * to achieve lower clock rates. That means that this function is called once
458 * at probe time and never called again.
460 * @host: The sdhci_host
462 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
465 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
466 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
467 sdhci_arasan->soc_ctl_map;
468 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
470 /* Having a map is optional */
474 /* If we have a map, we expect to have a syscon */
475 if (!sdhci_arasan->soc_ctl_base) {
476 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
477 mmc_hostname(host->mmc));
481 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
485 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
487 * Some PHY devices need to know what the actual card clock is. In order for
488 * them to find out, we'll provide a clock through the common clock framework
491 * Note: without seriously re-architecting SDHCI's clock code and testing on
492 * all platforms, there's no way to create a totally beautiful clock here
493 * with all clock ops implemented. Instead, we'll just create a clock that can
494 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
495 * framework that we're doing things behind its back. This should be sufficient
496 * to create nice clean device tree bindings and later (if needed) we can try
497 * re-architecting SDHCI if we see some benefit to it.
499 * @sdhci_arasan: Our private data structure.
500 * @clk_xin: Pointer to the functional clock
501 * @dev: Pointer to our struct device.
502 * Returns 0 on success and error value on error
504 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
508 struct device_node *np = dev->of_node;
509 struct clk_init_data sdcardclk_init;
510 const char *parent_clk_name;
513 /* Providing a clock to the PHY is optional; no error if missing */
514 if (!of_find_property(np, "#clock-cells", NULL))
517 ret = of_property_read_string_index(np, "clock-output-names", 0,
518 &sdcardclk_init.name);
520 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
524 parent_clk_name = __clk_get_name(clk_xin);
525 sdcardclk_init.parent_names = &parent_clk_name;
526 sdcardclk_init.num_parents = 1;
527 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
528 sdcardclk_init.ops = &arasan_sdcardclk_ops;
530 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
531 sdhci_arasan->sdcardclk =
532 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
533 sdhci_arasan->sdcardclk_hw.init = NULL;
535 ret = of_clk_add_provider(np, of_clk_src_simple_get,
536 sdhci_arasan->sdcardclk);
538 dev_err(dev, "Failed to add clock provider\n");
544 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
546 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
549 * @dev: Pointer to our struct device.
551 static void sdhci_arasan_unregister_sdclk(struct device *dev)
553 struct device_node *np = dev->of_node;
555 if (!of_find_property(np, "#clock-cells", NULL))
558 of_clk_del_provider(dev->of_node);
561 static int sdhci_arasan_probe(struct platform_device *pdev)
564 const struct of_device_id *match;
565 struct device_node *node;
567 struct sdhci_host *host;
568 struct sdhci_pltfm_host *pltfm_host;
569 struct sdhci_arasan_data *sdhci_arasan;
571 host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
572 sizeof(*sdhci_arasan));
574 return PTR_ERR(host);
576 pltfm_host = sdhci_priv(host);
577 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
578 sdhci_arasan->host = host;
580 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
581 sdhci_arasan->soc_ctl_map = match->data;
583 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
585 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
588 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
589 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
590 if (ret != -EPROBE_DEFER)
591 dev_err(&pdev->dev, "Can't get syscon: %d\n",
597 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
598 if (IS_ERR(sdhci_arasan->clk_ahb)) {
599 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
600 ret = PTR_ERR(sdhci_arasan->clk_ahb);
604 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
605 if (IS_ERR(clk_xin)) {
606 dev_err(&pdev->dev, "clk_xin clock not found.\n");
607 ret = PTR_ERR(clk_xin);
611 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
613 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
617 ret = clk_prepare_enable(clk_xin);
619 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
623 sdhci_get_of_property(pdev);
624 pltfm_host->clk = clk_xin;
626 if (of_device_is_compatible(pdev->dev.of_node,
627 "rockchip,rk3399-sdhci-5.1"))
628 sdhci_arasan_update_clockmultiplier(host, 0x0);
630 sdhci_arasan_update_baseclkfreq(host);
632 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
634 goto clk_disable_all;
636 ret = mmc_of_parse(host->mmc);
638 dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
642 sdhci_arasan->phy = ERR_PTR(-ENODEV);
643 if (of_device_is_compatible(pdev->dev.of_node,
644 "arasan,sdhci-5.1")) {
645 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
647 if (IS_ERR(sdhci_arasan->phy)) {
648 ret = PTR_ERR(sdhci_arasan->phy);
649 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
653 ret = phy_init(sdhci_arasan->phy);
655 dev_err(&pdev->dev, "phy_init err.\n");
659 host->mmc_host_ops.hs400_enhanced_strobe =
660 sdhci_arasan_hs400_enhanced_strobe;
661 host->mmc_host_ops.start_signal_voltage_switch =
662 sdhci_arasan_voltage_switch;
665 ret = sdhci_add_host(host);
669 device_init_wakeup(&pdev->dev, 1);
674 if (!IS_ERR(sdhci_arasan->phy))
675 phy_exit(sdhci_arasan->phy);
677 sdhci_arasan_unregister_sdclk(&pdev->dev);
679 clk_disable_unprepare(clk_xin);
681 clk_disable_unprepare(sdhci_arasan->clk_ahb);
683 sdhci_pltfm_free(pdev);
687 static int sdhci_arasan_remove(struct platform_device *pdev)
690 struct sdhci_host *host = platform_get_drvdata(pdev);
691 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
692 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
693 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
695 if (!IS_ERR(sdhci_arasan->phy)) {
696 if (sdhci_arasan->is_phy_on)
697 phy_power_off(sdhci_arasan->phy);
698 phy_exit(sdhci_arasan->phy);
701 sdhci_arasan_unregister_sdclk(&pdev->dev);
703 ret = sdhci_pltfm_unregister(pdev);
705 clk_disable_unprepare(clk_ahb);
710 static struct platform_driver sdhci_arasan_driver = {
712 .name = "sdhci-arasan",
713 .of_match_table = sdhci_arasan_of_match,
714 .pm = &sdhci_arasan_dev_pm_ops,
716 .probe = sdhci_arasan_probe,
717 .remove = sdhci_arasan_remove,
720 module_platform_driver(sdhci_arasan_driver);
722 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
723 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
724 MODULE_LICENSE("GPL");