2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
33 #define ESDHC_CTRL_D3CD 0x08
34 /* VENDOR SPEC register */
35 #define ESDHC_VENDOR_SPEC 0xc0
36 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
37 #define ESDHC_WTMK_LVL 0x44
38 #define ESDHC_MIX_CTRL 0x48
39 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
40 /* Bits 3 and 6 are not SDHCI standard definitions */
41 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
44 * Our interpretation of the SDHCI_HOST_CONTROL register
46 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
47 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
48 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
51 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
52 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
53 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
54 * Define this macro DMA error INT for fsl eSDHC
56 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
59 * The CMDTYPE of the CMD register (offset 0xE) should be set to
60 * "11" when the STOP CMD12 is issued on imx53 to abort one
61 * open ended multi-blk IO. Otherwise the TC INT wouldn't
63 * In exact block transfer, the controller doesn't complete the
64 * operations automatically as required at the end of the
65 * transfer and remains on hold if the abort command is not sent.
66 * As a result, the TC flag is not asserted and SW received timeout
67 * exeception. Bit1 of Vendor Spec registor is used to fix it.
69 #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
79 struct pltfm_imx_data {
82 enum imx_esdhc_type devtype;
83 struct pinctrl *pinctrl;
84 struct esdhc_platform_data boarddata;
89 NO_CMD_PENDING, /* no multiblock command pending*/
90 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
91 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
96 static struct platform_device_id imx_esdhc_devtype[] = {
98 .name = "sdhci-esdhc-imx25",
99 .driver_data = IMX25_ESDHC,
101 .name = "sdhci-esdhc-imx35",
102 .driver_data = IMX35_ESDHC,
104 .name = "sdhci-esdhc-imx51",
105 .driver_data = IMX51_ESDHC,
107 .name = "sdhci-esdhc-imx53",
108 .driver_data = IMX53_ESDHC,
110 .name = "sdhci-usdhc-imx6q",
111 .driver_data = IMX6Q_USDHC,
116 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
118 static const struct of_device_id imx_esdhc_dt_ids[] = {
119 { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
120 { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
121 { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
122 { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
123 { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
126 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
128 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
130 return data->devtype == IMX25_ESDHC;
133 static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
135 return data->devtype == IMX35_ESDHC;
138 static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
140 return data->devtype == IMX51_ESDHC;
143 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
145 return data->devtype == IMX53_ESDHC;
148 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
150 return data->devtype == IMX6Q_USDHC;
153 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
155 void __iomem *base = host->ioaddr + (reg & ~0x3);
156 u32 shift = (reg & 0x3) * 8;
158 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
161 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
164 struct pltfm_imx_data *imx_data = pltfm_host->priv;
165 u32 val = readl(host->ioaddr + reg);
167 if (unlikely(reg == SDHCI_CAPABILITIES)) {
168 /* In FSL esdhc IC module, only bit20 is used to indicate the
169 * ADMA2 capability of esdhc, but this bit is messed up on
170 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
171 * don't actually support ADMA2). So set the BROKEN_ADMA
172 * uirk on MX25/35 platforms.
175 if (val & SDHCI_CAN_DO_ADMA1) {
176 val &= ~SDHCI_CAN_DO_ADMA1;
177 val |= SDHCI_CAN_DO_ADMA2;
181 if (unlikely(reg == SDHCI_INT_STATUS)) {
182 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
183 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
184 val |= SDHCI_INT_ADMA_ERROR;
188 * mask off the interrupt we get in response to the manually
191 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
192 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
193 val &= ~SDHCI_INT_RESPONSE;
194 writel(SDHCI_INT_RESPONSE, host->ioaddr +
196 imx_data->multiblock_status = NO_CMD_PENDING;
203 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
206 struct pltfm_imx_data *imx_data = pltfm_host->priv;
209 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
210 if (val & SDHCI_INT_CARD_INT) {
212 * Clear and then set D3CD bit to avoid missing the
213 * card interrupt. This is a eSDHC controller problem
214 * so we need to apply the following workaround: clear
215 * and set D3CD bit will make eSDHC re-sample the card
216 * interrupt. In case a card interrupt was lost,
217 * re-sample it by the following steps.
219 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
220 data &= ~ESDHC_CTRL_D3CD;
221 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
222 data |= ESDHC_CTRL_D3CD;
223 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
227 if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
228 && (reg == SDHCI_INT_STATUS)
229 && (val & SDHCI_INT_DATA_END))) {
231 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
232 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
233 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
235 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
237 /* send a manual CMD12 with RESPTYP=none */
238 data = MMC_STOP_TRANSMISSION << 24 |
239 SDHCI_CMD_ABORTCMD << 16;
240 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
241 imx_data->multiblock_status = WAIT_FOR_INT;
245 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
246 if (val & SDHCI_INT_ADMA_ERROR) {
247 val &= ~SDHCI_INT_ADMA_ERROR;
248 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
252 writel(val, host->ioaddr + reg);
255 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
257 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
258 struct pltfm_imx_data *imx_data = pltfm_host->priv;
260 if (unlikely(reg == SDHCI_HOST_VERSION)) {
262 if (is_imx6q_usdhc(imx_data)) {
264 * The usdhc register returns a wrong host version.
267 return SDHCI_SPEC_300;
271 return readw(host->ioaddr + reg);
274 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
276 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
277 struct pltfm_imx_data *imx_data = pltfm_host->priv;
280 case SDHCI_TRANSFER_MODE:
281 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
282 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
283 && (host->cmd->data->blocks > 1)
284 && (host->cmd->data->flags & MMC_DATA_READ)) {
286 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
287 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
288 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
291 if (is_imx6q_usdhc(imx_data)) {
292 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
294 if (val & SDHCI_TRNS_AUTO_CMD23) {
295 val &= ~SDHCI_TRNS_AUTO_CMD23;
296 val |= ESDHC_MIX_CTRL_AC23EN;
298 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
299 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
302 * Postpone this write, we must do it together with a
303 * command write that is down below.
305 imx_data->scratchpad = val;
309 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
310 val |= SDHCI_CMD_ABORTCMD;
312 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
313 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
314 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
316 if (is_imx6q_usdhc(imx_data))
318 host->ioaddr + SDHCI_TRANSFER_MODE);
320 writel(val << 16 | imx_data->scratchpad,
321 host->ioaddr + SDHCI_TRANSFER_MODE);
323 case SDHCI_BLOCK_SIZE:
324 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
327 esdhc_clrset_le(host, 0xffff, val, reg);
330 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
332 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
333 struct pltfm_imx_data *imx_data = pltfm_host->priv;
338 case SDHCI_POWER_CONTROL:
340 * FSL put some DMA bits here
341 * If your board has a regulator, code should be here
344 case SDHCI_HOST_CONTROL:
345 /* FSL messed up here, so we need to manually compose it. */
346 new_val = val & SDHCI_CTRL_LED;
347 /* ensure the endianness */
348 new_val |= ESDHC_HOST_CONTROL_LE;
349 /* bits 8&9 are reserved on mx25 */
350 if (!is_imx25_esdhc(imx_data)) {
351 /* DMA mode bits are shifted */
352 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
356 * Do not touch buswidth bits here. This is done in
357 * esdhc_pltfm_bus_width.
358 * Do not touch the D3CD bit either which is used for the
359 * SDIO interrupt errata workaround.
361 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
363 esdhc_clrset_le(host, mask, new_val, reg);
366 esdhc_clrset_le(host, 0xff, val, reg);
369 * The esdhc has a design violation to SDHC spec which tells
370 * that software reset should not affect card detection circuit.
371 * But esdhc clears its SYSCTL register bits [0..2] during the
372 * software reset. This will stop those clocks that card detection
373 * circuit relies on. To work around it, we turn the clocks on back
374 * to keep card detection circuit functional.
376 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
377 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
379 * The reset on usdhc fails to clear MIX_CTRL register.
380 * Do it manually here.
382 if (is_imx6q_usdhc(imx_data))
383 writel(0, host->ioaddr + ESDHC_MIX_CTRL);
387 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
389 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
391 return clk_get_rate(pltfm_host->clk) / 256 / 16;
394 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
396 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
397 struct pltfm_imx_data *imx_data = pltfm_host->priv;
398 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
400 switch (boarddata->wp_type) {
402 return mmc_gpio_get_ro(host->mmc);
403 case ESDHC_WP_CONTROLLER:
404 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
405 SDHCI_WRITE_PROTECT);
413 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
418 case MMC_BUS_WIDTH_8:
419 ctrl = ESDHC_CTRL_8BITBUS;
421 case MMC_BUS_WIDTH_4:
422 ctrl = ESDHC_CTRL_4BITBUS;
429 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
435 static const struct sdhci_ops sdhci_esdhc_ops = {
436 .read_l = esdhc_readl_le,
437 .read_w = esdhc_readw_le,
438 .write_l = esdhc_writel_le,
439 .write_w = esdhc_writew_le,
440 .write_b = esdhc_writeb_le,
441 .set_clock = esdhc_set_clock,
442 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
443 .get_min_clock = esdhc_pltfm_get_min_clock,
444 .get_ro = esdhc_pltfm_get_ro,
445 .platform_bus_width = esdhc_pltfm_bus_width,
448 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
449 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
450 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
451 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
452 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
453 .ops = &sdhci_esdhc_ops,
458 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
459 struct esdhc_platform_data *boarddata)
461 struct device_node *np = pdev->dev.of_node;
466 if (of_get_property(np, "non-removable", NULL))
467 boarddata->cd_type = ESDHC_CD_PERMANENT;
469 if (of_get_property(np, "fsl,cd-controller", NULL))
470 boarddata->cd_type = ESDHC_CD_CONTROLLER;
472 if (of_get_property(np, "fsl,wp-controller", NULL))
473 boarddata->wp_type = ESDHC_WP_CONTROLLER;
475 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
476 if (gpio_is_valid(boarddata->cd_gpio))
477 boarddata->cd_type = ESDHC_CD_GPIO;
479 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
480 if (gpio_is_valid(boarddata->wp_gpio))
481 boarddata->wp_type = ESDHC_WP_GPIO;
483 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
489 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
490 struct esdhc_platform_data *boarddata)
496 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
498 const struct of_device_id *of_id =
499 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
500 struct sdhci_pltfm_host *pltfm_host;
501 struct sdhci_host *host;
502 struct esdhc_platform_data *boarddata;
504 struct pltfm_imx_data *imx_data;
506 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
508 return PTR_ERR(host);
510 pltfm_host = sdhci_priv(host);
512 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
519 pdev->id_entry = of_id->data;
520 imx_data->devtype = pdev->id_entry->driver_data;
521 pltfm_host->priv = imx_data;
523 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
524 if (IS_ERR(imx_data->clk_ipg)) {
525 err = PTR_ERR(imx_data->clk_ipg);
529 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
530 if (IS_ERR(imx_data->clk_ahb)) {
531 err = PTR_ERR(imx_data->clk_ahb);
535 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
536 if (IS_ERR(imx_data->clk_per)) {
537 err = PTR_ERR(imx_data->clk_per);
541 pltfm_host->clk = imx_data->clk_per;
543 clk_prepare_enable(imx_data->clk_per);
544 clk_prepare_enable(imx_data->clk_ipg);
545 clk_prepare_enable(imx_data->clk_ahb);
547 imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
548 if (IS_ERR(imx_data->pinctrl)) {
549 err = PTR_ERR(imx_data->pinctrl);
553 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
555 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
556 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
557 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
558 | SDHCI_QUIRK_BROKEN_ADMA;
560 if (is_imx53_esdhc(imx_data))
561 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
564 * The imx6q ROM code will change the default watermark level setting
565 * to something insane. Change it back here.
567 if (is_imx6q_usdhc(imx_data))
568 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
570 boarddata = &imx_data->boarddata;
571 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
572 if (!host->mmc->parent->platform_data) {
573 dev_err(mmc_dev(host->mmc), "no board data!\n");
577 imx_data->boarddata = *((struct esdhc_platform_data *)
578 host->mmc->parent->platform_data);
582 if (boarddata->wp_type == ESDHC_WP_GPIO) {
583 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
585 dev_err(mmc_dev(host->mmc),
586 "failed to request write-protect gpio!\n");
589 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
593 switch (boarddata->cd_type) {
595 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
597 dev_err(mmc_dev(host->mmc),
598 "failed to request card-detect gpio!\n");
603 case ESDHC_CD_CONTROLLER:
604 /* we have a working card_detect back */
605 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
608 case ESDHC_CD_PERMANENT:
609 host->mmc->caps = MMC_CAP_NONREMOVABLE;
616 switch (boarddata->max_bus_width) {
618 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
621 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
625 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
629 err = sdhci_add_host(host);
636 clk_disable_unprepare(imx_data->clk_per);
637 clk_disable_unprepare(imx_data->clk_ipg);
638 clk_disable_unprepare(imx_data->clk_ahb);
640 sdhci_pltfm_free(pdev);
644 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
646 struct sdhci_host *host = platform_get_drvdata(pdev);
647 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
648 struct pltfm_imx_data *imx_data = pltfm_host->priv;
649 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
651 sdhci_remove_host(host, dead);
653 clk_disable_unprepare(imx_data->clk_per);
654 clk_disable_unprepare(imx_data->clk_ipg);
655 clk_disable_unprepare(imx_data->clk_ahb);
657 sdhci_pltfm_free(pdev);
662 static struct platform_driver sdhci_esdhc_imx_driver = {
664 .name = "sdhci-esdhc-imx",
665 .owner = THIS_MODULE,
666 .of_match_table = imx_esdhc_dt_ids,
667 .pm = SDHCI_PLTFM_PMOPS,
669 .id_table = imx_esdhc_devtype,
670 .probe = sdhci_esdhc_imx_probe,
671 .remove = sdhci_esdhc_imx_remove,
674 module_platform_driver(sdhci_esdhc_imx_driver);
676 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
677 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
678 MODULE_LICENSE("GPL v2");