2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
34 #define ESDHC_CTRL_D3CD 0x08
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC 0xc0
37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40 #define ESDHC_WTMK_LVL 0x44
41 #define ESDHC_MIX_CTRL 0x48
42 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
43 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
44 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
45 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
46 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
47 /* Bits 3 and 6 are not SDHCI standard definitions */
48 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
50 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
52 /* dll control register */
53 #define ESDHC_DLL_CTRL 0x60
54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
57 /* tune control register */
58 #define ESDHC_TUNE_CTRL_STATUS 0x68
59 #define ESDHC_TUNE_CTRL_STEP 1
60 #define ESDHC_TUNE_CTRL_MIN 0
61 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
63 #define ESDHC_TUNING_CTRL 0xcc
64 #define ESDHC_STD_TUNING_EN (1 << 24)
65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
66 #define ESDHC_TUNING_START_TAP 0x1
69 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
70 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
73 * Our interpretation of the SDHCI_HOST_CONTROL register
75 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
76 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
77 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
80 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
81 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
82 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
83 * Define this macro DMA error INT for fsl eSDHC
85 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
88 * The CMDTYPE of the CMD register (offset 0xE) should be set to
89 * "11" when the STOP CMD12 is issued on imx53 to abort one
90 * open ended multi-blk IO. Otherwise the TC INT wouldn't
92 * In exact block transfer, the controller doesn't complete the
93 * operations automatically as required at the end of the
94 * transfer and remains on hold if the abort command is not sent.
95 * As a result, the TC flag is not asserted and SW received timeout
96 * exeception. Bit1 of Vendor Spec registor is used to fix it.
98 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
100 * The flag enables the workaround for ESDHC errata ENGcm07207 which
101 * affects i.MX25 and i.MX35.
103 #define ESDHC_FLAG_ENGCM07207 BIT(2)
105 * The flag tells that the ESDHC controller is an USDHC block that is
106 * integrated on the i.MX6 series.
108 #define ESDHC_FLAG_USDHC BIT(3)
109 /* The IP supports manual tuning process */
110 #define ESDHC_FLAG_MAN_TUNING BIT(4)
111 /* The IP supports standard tuning process */
112 #define ESDHC_FLAG_STD_TUNING BIT(5)
113 /* The IP has SDHCI_CAPABILITIES_1 register */
114 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
116 struct esdhc_soc_data {
120 static struct esdhc_soc_data esdhc_imx25_data = {
121 .flags = ESDHC_FLAG_ENGCM07207,
124 static struct esdhc_soc_data esdhc_imx35_data = {
125 .flags = ESDHC_FLAG_ENGCM07207,
128 static struct esdhc_soc_data esdhc_imx51_data = {
132 static struct esdhc_soc_data esdhc_imx53_data = {
133 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
136 static struct esdhc_soc_data usdhc_imx6q_data = {
137 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
140 static struct esdhc_soc_data usdhc_imx6sl_data = {
141 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
142 | ESDHC_FLAG_HAVE_CAP1,
145 struct pltfm_imx_data {
147 struct pinctrl *pinctrl;
148 struct pinctrl_state *pins_default;
149 struct pinctrl_state *pins_100mhz;
150 struct pinctrl_state *pins_200mhz;
151 const struct esdhc_soc_data *socdata;
152 struct esdhc_platform_data boarddata;
157 NO_CMD_PENDING, /* no multiblock command pending*/
158 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
159 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
164 static struct platform_device_id imx_esdhc_devtype[] = {
166 .name = "sdhci-esdhc-imx25",
167 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
169 .name = "sdhci-esdhc-imx35",
170 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
172 .name = "sdhci-esdhc-imx51",
173 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
178 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
180 static const struct of_device_id imx_esdhc_dt_ids[] = {
181 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
182 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
183 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
184 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
185 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
186 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
189 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
191 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
193 return data->socdata == &esdhc_imx25_data;
196 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
198 return data->socdata == &esdhc_imx53_data;
201 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
203 return data->socdata == &usdhc_imx6q_data;
206 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
208 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
211 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
213 void __iomem *base = host->ioaddr + (reg & ~0x3);
214 u32 shift = (reg & 0x3) * 8;
216 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
219 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
222 struct pltfm_imx_data *imx_data = pltfm_host->priv;
223 u32 val = readl(host->ioaddr + reg);
225 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
227 /* save the least 20 bits */
228 val = fsl_prss & 0x000FFFFF;
229 /* move dat[0-3] bits */
230 val |= (fsl_prss & 0x0F000000) >> 4;
231 /* move cmd line bit */
232 val |= (fsl_prss & 0x00800000) << 1;
235 if (unlikely(reg == SDHCI_CAPABILITIES)) {
236 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
237 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
240 /* In FSL esdhc IC module, only bit20 is used to indicate the
241 * ADMA2 capability of esdhc, but this bit is messed up on
242 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
243 * don't actually support ADMA2). So set the BROKEN_ADMA
244 * uirk on MX25/35 platforms.
247 if (val & SDHCI_CAN_DO_ADMA1) {
248 val &= ~SDHCI_CAN_DO_ADMA1;
249 val |= SDHCI_CAN_DO_ADMA2;
253 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
254 if (esdhc_is_usdhc(imx_data)) {
255 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
256 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
258 /* imx6q/dl does not have cap_1 register, fake one */
259 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
260 | SDHCI_SUPPORT_SDR50
261 | SDHCI_USE_SDR50_TUNING;
265 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
267 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
268 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
269 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
272 if (unlikely(reg == SDHCI_INT_STATUS)) {
273 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
274 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
275 val |= SDHCI_INT_ADMA_ERROR;
279 * mask off the interrupt we get in response to the manually
282 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
283 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
284 val &= ~SDHCI_INT_RESPONSE;
285 writel(SDHCI_INT_RESPONSE, host->ioaddr +
287 imx_data->multiblock_status = NO_CMD_PENDING;
294 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
296 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
297 struct pltfm_imx_data *imx_data = pltfm_host->priv;
300 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
301 if (val & SDHCI_INT_CARD_INT) {
303 * Clear and then set D3CD bit to avoid missing the
304 * card interrupt. This is a eSDHC controller problem
305 * so we need to apply the following workaround: clear
306 * and set D3CD bit will make eSDHC re-sample the card
307 * interrupt. In case a card interrupt was lost,
308 * re-sample it by the following steps.
310 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
311 data &= ~ESDHC_CTRL_D3CD;
312 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
313 data |= ESDHC_CTRL_D3CD;
314 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
318 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
319 && (reg == SDHCI_INT_STATUS)
320 && (val & SDHCI_INT_DATA_END))) {
322 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
323 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
324 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
326 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
328 /* send a manual CMD12 with RESPTYP=none */
329 data = MMC_STOP_TRANSMISSION << 24 |
330 SDHCI_CMD_ABORTCMD << 16;
331 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
332 imx_data->multiblock_status = WAIT_FOR_INT;
336 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
337 if (val & SDHCI_INT_ADMA_ERROR) {
338 val &= ~SDHCI_INT_ADMA_ERROR;
339 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
343 writel(val, host->ioaddr + reg);
346 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
348 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
349 struct pltfm_imx_data *imx_data = pltfm_host->priv;
353 if (unlikely(reg == SDHCI_HOST_VERSION)) {
355 if (esdhc_is_usdhc(imx_data)) {
357 * The usdhc register returns a wrong host version.
360 return SDHCI_SPEC_300;
364 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
365 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
366 if (val & ESDHC_VENDOR_SPEC_VSELECT)
367 ret |= SDHCI_CTRL_VDD_180;
369 if (esdhc_is_usdhc(imx_data)) {
370 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
371 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
372 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
373 /* the std tuning bits is in ACMD12_ERR for imx6sl */
374 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
377 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
378 ret |= SDHCI_CTRL_EXEC_TUNING;
379 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
380 ret |= SDHCI_CTRL_TUNED_CLK;
382 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
387 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
388 if (esdhc_is_usdhc(imx_data)) {
389 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
390 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
392 if (m & ESDHC_MIX_CTRL_AC23EN) {
393 ret &= ~ESDHC_MIX_CTRL_AC23EN;
394 ret |= SDHCI_TRNS_AUTO_CMD23;
397 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
403 return readw(host->ioaddr + reg);
406 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
408 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
409 struct pltfm_imx_data *imx_data = pltfm_host->priv;
413 case SDHCI_CLOCK_CONTROL:
414 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
415 if (val & SDHCI_CLOCK_CARD_EN)
416 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
418 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
419 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
421 case SDHCI_HOST_CONTROL2:
422 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
423 if (val & SDHCI_CTRL_VDD_180)
424 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
426 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
427 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
428 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
429 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
430 if (val & SDHCI_CTRL_TUNED_CLK)
431 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
433 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
434 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
435 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
436 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
437 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
438 if (val & SDHCI_CTRL_TUNED_CLK) {
439 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
441 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
442 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
445 if (val & SDHCI_CTRL_EXEC_TUNING) {
446 v |= ESDHC_MIX_CTRL_EXE_TUNE;
447 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
449 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
452 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
453 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
456 case SDHCI_TRANSFER_MODE:
457 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
458 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
459 && (host->cmd->data->blocks > 1)
460 && (host->cmd->data->flags & MMC_DATA_READ)) {
462 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
463 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
464 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
467 if (esdhc_is_usdhc(imx_data)) {
468 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
470 if (val & SDHCI_TRNS_AUTO_CMD23) {
471 val &= ~SDHCI_TRNS_AUTO_CMD23;
472 val |= ESDHC_MIX_CTRL_AC23EN;
474 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
475 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
478 * Postpone this write, we must do it together with a
479 * command write that is down below.
481 imx_data->scratchpad = val;
485 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
486 val |= SDHCI_CMD_ABORTCMD;
488 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
489 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
490 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
492 if (esdhc_is_usdhc(imx_data))
494 host->ioaddr + SDHCI_TRANSFER_MODE);
496 writel(val << 16 | imx_data->scratchpad,
497 host->ioaddr + SDHCI_TRANSFER_MODE);
499 case SDHCI_BLOCK_SIZE:
500 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
503 esdhc_clrset_le(host, 0xffff, val, reg);
506 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
508 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
509 struct pltfm_imx_data *imx_data = pltfm_host->priv;
514 case SDHCI_POWER_CONTROL:
516 * FSL put some DMA bits here
517 * If your board has a regulator, code should be here
520 case SDHCI_HOST_CONTROL:
521 /* FSL messed up here, so we need to manually compose it. */
522 new_val = val & SDHCI_CTRL_LED;
523 /* ensure the endianness */
524 new_val |= ESDHC_HOST_CONTROL_LE;
525 /* bits 8&9 are reserved on mx25 */
526 if (!is_imx25_esdhc(imx_data)) {
527 /* DMA mode bits are shifted */
528 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
532 * Do not touch buswidth bits here. This is done in
533 * esdhc_pltfm_bus_width.
534 * Do not touch the D3CD bit either which is used for the
535 * SDIO interrupt errata workaround.
537 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
539 esdhc_clrset_le(host, mask, new_val, reg);
542 esdhc_clrset_le(host, 0xff, val, reg);
545 * The esdhc has a design violation to SDHC spec which tells
546 * that software reset should not affect card detection circuit.
547 * But esdhc clears its SYSCTL register bits [0..2] during the
548 * software reset. This will stop those clocks that card detection
549 * circuit relies on. To work around it, we turn the clocks on back
550 * to keep card detection circuit functional.
552 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
553 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
555 * The reset on usdhc fails to clear MIX_CTRL register.
556 * Do it manually here.
558 if (esdhc_is_usdhc(imx_data)) {
559 /* the tuning bits should be kept during reset */
560 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
561 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
562 host->ioaddr + ESDHC_MIX_CTRL);
563 imx_data->is_ddr = 0;
568 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
571 struct pltfm_imx_data *imx_data = pltfm_host->priv;
572 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
574 if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock))
575 return boarddata->f_max;
577 return pltfm_host->clock;
580 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
582 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
584 return pltfm_host->clock / 256 / 16;
587 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
591 struct pltfm_imx_data *imx_data = pltfm_host->priv;
592 unsigned int host_clock = pltfm_host->clock;
598 host->mmc->actual_clock = 0;
600 if (esdhc_is_usdhc(imx_data)) {
601 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
602 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
603 host->ioaddr + ESDHC_VENDOR_SPEC);
608 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
611 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
612 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
614 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
616 while (host_clock / pre_div / 16 > clock && pre_div < 256)
619 while (host_clock / pre_div / div > clock && div < 16)
622 host->mmc->actual_clock = host_clock / pre_div / div;
623 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
624 clock, host->mmc->actual_clock);
626 if (imx_data->is_ddr)
632 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
633 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
634 | (div << ESDHC_DIVIDER_SHIFT)
635 | (pre_div << ESDHC_PREDIV_SHIFT));
636 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
638 if (esdhc_is_usdhc(imx_data)) {
639 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
640 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
641 host->ioaddr + ESDHC_VENDOR_SPEC);
647 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
649 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
650 struct pltfm_imx_data *imx_data = pltfm_host->priv;
651 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
653 switch (boarddata->wp_type) {
655 return mmc_gpio_get_ro(host->mmc);
656 case ESDHC_WP_CONTROLLER:
657 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
658 SDHCI_WRITE_PROTECT);
666 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
671 case MMC_BUS_WIDTH_8:
672 ctrl = ESDHC_CTRL_8BITBUS;
674 case MMC_BUS_WIDTH_4:
675 ctrl = ESDHC_CTRL_4BITBUS;
682 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
686 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
690 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
693 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
694 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
695 ESDHC_MIX_CTRL_FBCLK_SEL;
696 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
697 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
698 dev_dbg(mmc_dev(host->mmc),
699 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
700 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
703 static void esdhc_post_tuning(struct sdhci_host *host)
707 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
708 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
709 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
712 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
714 int min, max, avg, ret;
716 /* find the mininum delay first which can pass tuning */
717 min = ESDHC_TUNE_CTRL_MIN;
718 while (min < ESDHC_TUNE_CTRL_MAX) {
719 esdhc_prepare_tuning(host, min);
720 if (!mmc_send_tuning(host->mmc))
722 min += ESDHC_TUNE_CTRL_STEP;
725 /* find the maxinum delay which can not pass tuning */
726 max = min + ESDHC_TUNE_CTRL_STEP;
727 while (max < ESDHC_TUNE_CTRL_MAX) {
728 esdhc_prepare_tuning(host, max);
729 if (mmc_send_tuning(host->mmc)) {
730 max -= ESDHC_TUNE_CTRL_STEP;
733 max += ESDHC_TUNE_CTRL_STEP;
736 /* use average delay to get the best timing */
737 avg = (min + max) / 2;
738 esdhc_prepare_tuning(host, avg);
739 ret = mmc_send_tuning(host->mmc);
740 esdhc_post_tuning(host);
742 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
743 ret ? "failed" : "passed", avg, ret);
748 static int esdhc_change_pinstate(struct sdhci_host *host,
751 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
752 struct pltfm_imx_data *imx_data = pltfm_host->priv;
753 struct pinctrl_state *pinctrl;
755 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
757 if (IS_ERR(imx_data->pinctrl) ||
758 IS_ERR(imx_data->pins_default) ||
759 IS_ERR(imx_data->pins_100mhz) ||
760 IS_ERR(imx_data->pins_200mhz))
764 case MMC_TIMING_UHS_SDR50:
765 pinctrl = imx_data->pins_100mhz;
767 case MMC_TIMING_UHS_SDR104:
768 case MMC_TIMING_MMC_HS200:
769 pinctrl = imx_data->pins_200mhz;
772 /* back to default state for other legacy timing */
773 pinctrl = imx_data->pins_default;
776 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
779 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
782 struct pltfm_imx_data *imx_data = pltfm_host->priv;
783 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
786 case MMC_TIMING_UHS_SDR12:
787 case MMC_TIMING_UHS_SDR25:
788 case MMC_TIMING_UHS_SDR50:
789 case MMC_TIMING_UHS_SDR104:
790 case MMC_TIMING_MMC_HS200:
792 case MMC_TIMING_UHS_DDR50:
793 case MMC_TIMING_MMC_DDR52:
794 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
795 ESDHC_MIX_CTRL_DDREN,
796 host->ioaddr + ESDHC_MIX_CTRL);
797 imx_data->is_ddr = 1;
798 if (boarddata->delay_line) {
800 v = boarddata->delay_line <<
801 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
802 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
803 if (is_imx53_esdhc(imx_data))
805 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
810 esdhc_change_pinstate(host, timing);
813 static void esdhc_reset(struct sdhci_host *host, u8 mask)
815 sdhci_reset(host, mask);
817 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
818 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
821 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
823 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
824 struct pltfm_imx_data *imx_data = pltfm_host->priv;
826 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
829 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
832 struct pltfm_imx_data *imx_data = pltfm_host->priv;
834 /* use maximum timeout counter */
835 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
836 SDHCI_TIMEOUT_CONTROL);
839 static struct sdhci_ops sdhci_esdhc_ops = {
840 .read_l = esdhc_readl_le,
841 .read_w = esdhc_readw_le,
842 .write_l = esdhc_writel_le,
843 .write_w = esdhc_writew_le,
844 .write_b = esdhc_writeb_le,
845 .set_clock = esdhc_pltfm_set_clock,
846 .get_max_clock = esdhc_pltfm_get_max_clock,
847 .get_min_clock = esdhc_pltfm_get_min_clock,
848 .get_max_timeout_count = esdhc_get_max_timeout_count,
849 .get_ro = esdhc_pltfm_get_ro,
850 .set_timeout = esdhc_set_timeout,
851 .set_bus_width = esdhc_pltfm_set_bus_width,
852 .set_uhs_signaling = esdhc_set_uhs_signaling,
853 .reset = esdhc_reset,
856 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
857 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
858 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
859 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
860 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
861 .ops = &sdhci_esdhc_ops,
866 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
867 struct sdhci_host *host,
868 struct esdhc_platform_data *boarddata)
870 struct device_node *np = pdev->dev.of_node;
875 if (of_get_property(np, "non-removable", NULL))
876 boarddata->cd_type = ESDHC_CD_PERMANENT;
878 if (of_get_property(np, "fsl,cd-controller", NULL))
879 boarddata->cd_type = ESDHC_CD_CONTROLLER;
881 if (of_get_property(np, "fsl,wp-controller", NULL))
882 boarddata->wp_type = ESDHC_WP_CONTROLLER;
884 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
885 if (gpio_is_valid(boarddata->cd_gpio))
886 boarddata->cd_type = ESDHC_CD_GPIO;
888 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
889 if (gpio_is_valid(boarddata->wp_gpio))
890 boarddata->wp_type = ESDHC_WP_GPIO;
892 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
894 of_property_read_u32(np, "max-frequency", &boarddata->f_max);
896 if (of_find_property(np, "no-1-8-v", NULL))
897 boarddata->support_vsel = false;
899 boarddata->support_vsel = true;
901 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
902 boarddata->delay_line = 0;
904 mmc_of_parse_voltage(np, &host->ocr_mask);
910 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
911 struct sdhci_host *host,
912 struct esdhc_platform_data *boarddata)
918 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
920 const struct of_device_id *of_id =
921 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
922 struct sdhci_pltfm_host *pltfm_host;
923 struct sdhci_host *host;
924 struct esdhc_platform_data *boarddata;
926 struct pltfm_imx_data *imx_data;
928 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
930 return PTR_ERR(host);
932 pltfm_host = sdhci_priv(host);
934 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
940 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
941 pdev->id_entry->driver_data;
942 pltfm_host->priv = imx_data;
944 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
945 if (IS_ERR(imx_data->clk_ipg)) {
946 err = PTR_ERR(imx_data->clk_ipg);
950 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
951 if (IS_ERR(imx_data->clk_ahb)) {
952 err = PTR_ERR(imx_data->clk_ahb);
956 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
957 if (IS_ERR(imx_data->clk_per)) {
958 err = PTR_ERR(imx_data->clk_per);
962 pltfm_host->clk = imx_data->clk_per;
963 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
964 clk_prepare_enable(imx_data->clk_per);
965 clk_prepare_enable(imx_data->clk_ipg);
966 clk_prepare_enable(imx_data->clk_ahb);
968 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
969 if (IS_ERR(imx_data->pinctrl)) {
970 err = PTR_ERR(imx_data->pinctrl);
974 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
975 PINCTRL_STATE_DEFAULT);
976 if (IS_ERR(imx_data->pins_default))
977 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
979 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
981 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
982 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
983 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
984 | SDHCI_QUIRK_BROKEN_ADMA;
987 * The imx6q ROM code will change the default watermark level setting
988 * to something insane. Change it back here.
990 if (esdhc_is_usdhc(imx_data)) {
991 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
992 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
993 host->mmc->caps |= MMC_CAP_1_8V_DDR;
996 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
997 sdhci_esdhc_ops.platform_execute_tuning =
998 esdhc_executing_tuning;
1000 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1001 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1002 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1003 host->ioaddr + ESDHC_TUNING_CTRL);
1005 boarddata = &imx_data->boarddata;
1006 if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) {
1007 if (!host->mmc->parent->platform_data) {
1008 dev_err(mmc_dev(host->mmc), "no board data!\n");
1012 imx_data->boarddata = *((struct esdhc_platform_data *)
1013 host->mmc->parent->platform_data);
1017 if (boarddata->cd_type == ESDHC_CD_CONTROLLER)
1018 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1020 switch (boarddata->max_bus_width) {
1022 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1025 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1029 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1033 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1034 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1035 !IS_ERR(imx_data->pins_default)) {
1036 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1037 ESDHC_PINCTRL_STATE_100MHZ);
1038 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1039 ESDHC_PINCTRL_STATE_200MHZ);
1040 if (IS_ERR(imx_data->pins_100mhz) ||
1041 IS_ERR(imx_data->pins_200mhz)) {
1042 dev_warn(mmc_dev(host->mmc),
1043 "could not get ultra high speed state, work on normal mode\n");
1044 /* fall back to not support uhs by specify no 1.8v quirk */
1045 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1048 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1051 /* call to generic mmc_of_parse to support additional capabilities */
1052 err = mmc_of_parse(host->mmc);
1056 err = sdhci_add_host(host);
1060 pm_runtime_set_active(&pdev->dev);
1061 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1062 pm_runtime_use_autosuspend(&pdev->dev);
1063 pm_suspend_ignore_children(&pdev->dev, 1);
1064 pm_runtime_enable(&pdev->dev);
1069 clk_disable_unprepare(imx_data->clk_per);
1070 clk_disable_unprepare(imx_data->clk_ipg);
1071 clk_disable_unprepare(imx_data->clk_ahb);
1073 sdhci_pltfm_free(pdev);
1077 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1079 struct sdhci_host *host = platform_get_drvdata(pdev);
1080 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1081 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1082 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1084 pm_runtime_get_sync(&pdev->dev);
1085 pm_runtime_disable(&pdev->dev);
1086 pm_runtime_put_noidle(&pdev->dev);
1088 sdhci_remove_host(host, dead);
1090 clk_disable_unprepare(imx_data->clk_per);
1091 clk_disable_unprepare(imx_data->clk_ipg);
1092 clk_disable_unprepare(imx_data->clk_ahb);
1094 sdhci_pltfm_free(pdev);
1100 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1102 struct sdhci_host *host = dev_get_drvdata(dev);
1103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1104 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1107 ret = sdhci_runtime_suspend_host(host);
1109 if (!sdhci_sdio_irq_enabled(host)) {
1110 clk_disable_unprepare(imx_data->clk_per);
1111 clk_disable_unprepare(imx_data->clk_ipg);
1113 clk_disable_unprepare(imx_data->clk_ahb);
1118 static int sdhci_esdhc_runtime_resume(struct device *dev)
1120 struct sdhci_host *host = dev_get_drvdata(dev);
1121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1122 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1124 if (!sdhci_sdio_irq_enabled(host)) {
1125 clk_prepare_enable(imx_data->clk_per);
1126 clk_prepare_enable(imx_data->clk_ipg);
1128 clk_prepare_enable(imx_data->clk_ahb);
1130 return sdhci_runtime_resume_host(host);
1134 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1135 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1136 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1137 sdhci_esdhc_runtime_resume, NULL)
1140 static struct platform_driver sdhci_esdhc_imx_driver = {
1142 .name = "sdhci-esdhc-imx",
1143 .of_match_table = imx_esdhc_dt_ids,
1144 .pm = &sdhci_esdhc_pmops,
1146 .id_table = imx_esdhc_devtype,
1147 .probe = sdhci_esdhc_imx_probe,
1148 .remove = sdhci_esdhc_imx_remove,
1151 module_platform_driver(sdhci_esdhc_imx_driver);
1153 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1154 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1155 MODULE_LICENSE("GPL v2");