drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/suspend.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/mmc.h>
  36 #include <linux/mmc/sd.h>
  37 #include <linux/mmc/card.h>
  38 #include <linux/mmc/sdio.h>
  39 #include <linux/mmc/rk_mmc.h>
  40 #include <linux/bitops.h>
  41 #include <linux/regulator/consumer.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/of.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/mmc/slot-gpio.h>
  46 #include <linux/clk-private.h>
  47 #include <linux/rockchip/cpu.h>
  48 #include <linux/rfkill-wlan.h>
  49 #include <linux/mfd/syscon.h>
  50 #include <linux/regmap.h>
  51 #include <linux/log2.h>
  52 #include "rk_sdmmc.h"
  53 #include "rk_sdmmc_dbg.h"
  54 #include <linux/regulator/rockchip_io_vol_domain.h>
  55 #include "../../clk/rockchip/clk-ops.h"
  56
  57 #define RK_SDMMC_DRIVER_VERSION "Ver 1.13 2014-09-05"
  58
  59 /* Common flag combinations */
  60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  61                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  62                                  SDMMC_INT_EBE)
  63 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  64                                  SDMMC_INT_RESP_ERR)
  65 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  66                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  67 #define DW_MCI_SEND_STATUS      1
  68 #define DW_MCI_RECV_STATUS      2
  69 #define DW_MCI_DMA_THRESHOLD    16
  70
  71 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  72 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  73
  74 /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  75 #define SDMMC_DATA_TIMEOUT_SD   500
  76 #define SDMMC_DATA_TIMEOUT_SDIO 250
  77 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  78
  79 #define SDMMC_CMD_RTO_MAX_HOLD  200
  80 #define SDMMC_WAIT_FOR_UNBUSY   2500
  81
  82 #ifdef CONFIG_MMC_DW_IDMAC
  83 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  84                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  85                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  86                                  SDMMC_IDMAC_INT_TI)
  87
  88 struct idmac_desc {
  89         u32             des0;   /* Control Descriptor */
  90 #define IDMAC_DES0_DIC  BIT(1)
  91 #define IDMAC_DES0_LD   BIT(2)
  92 #define IDMAC_DES0_FD   BIT(3)
  93 #define IDMAC_DES0_CH   BIT(4)
  94 #define IDMAC_DES0_ER   BIT(5)
  95 #define IDMAC_DES0_CES  BIT(30)
  96 #define IDMAC_DES0_OWN  BIT(31)
  97
  98         u32             des1;   /* Buffer sizes */
  99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 100         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 101
 102         u32             des2;   /* buffer 1 physical address */
 103
 104         u32             des3;   /* buffer 2 physical address */
 105 };
 106 #endif /* CONFIG_MMC_DW_IDMAC */
 107
 108 static const u8 tuning_blk_pattern_4bit[] = {
 109         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 110         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 111         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 112         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 113         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 114         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 115         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 116         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 117 };
 118
 119 static const u8 tuning_blk_pattern_8bit[] = {
 120         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 121         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 122         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 123         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 124         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 125         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 126         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 127         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 128         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 129         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 130         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 131         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 132         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 133         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 134         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 135         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 136 };
 137
 138 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 139 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 140 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 141 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 142
 143 /*printk the all register of current host*/
 144 #if 0
 145 static int dw_mci_regs_printk(struct dw_mci *host)
 146 {
 147     struct sdmmc_reg *regs = dw_mci_regs;
 148
 149     while( regs->name != 0 ){
 150         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 151         regs++;
 152     }
 153     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 154     return 0;
 155 }
 156 #endif
 157
 158 #if defined(CONFIG_DEBUG_FS)
 159 static int dw_mci_req_show(struct seq_file *s, void *v)
 160 {
 161         struct dw_mci_slot *slot = s->private;
 162         struct mmc_request *mrq;
 163         struct mmc_command *cmd;
 164         struct mmc_command *stop;
 165         struct mmc_data *data;
 166
 167         /* Make sure we get a consistent snapshot */
 168         spin_lock_bh(&slot->host->lock);
 169         mrq = slot->mrq;
 170
 171         if (mrq) {
 172                 cmd = mrq->cmd;
 173                 data = mrq->data;
 174                 stop = mrq->stop;
 175
 176                 if (cmd)
 177                         seq_printf(s,
 178                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 179                                    cmd->opcode, cmd->arg, cmd->flags,
 180                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 181                                    cmd->resp[2], cmd->error);
 182                 if (data)
 183                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 184                                    data->bytes_xfered, data->blocks,
 185                                    data->blksz, data->flags, data->error);
 186                 if (stop)
 187                         seq_printf(s,
 188                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 189                                    stop->opcode, stop->arg, stop->flags,
 190                                    stop->resp[0], stop->resp[1], stop->resp[2],
 191                                    stop->resp[2], stop->error);
 192         }
 193
 194         spin_unlock_bh(&slot->host->lock);
 195
 196         return 0;
 197 }
 198
 199 static int dw_mci_req_open(struct inode *inode, struct file *file)
 200 {
 201         return single_open(file, dw_mci_req_show, inode->i_private);
 202 }
 203
 204 static const struct file_operations dw_mci_req_fops = {
 205         .owner          = THIS_MODULE,
 206         .open           = dw_mci_req_open,
 207         .read           = seq_read,
 208         .llseek         = seq_lseek,
 209         .release        = single_release,
 210 };
 211
 212 static int dw_mci_regs_show(struct seq_file *s, void *v)
 213 {
 214         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 215         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 216         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 217         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 218         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 219         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 220
 221         return 0;
 222 }
 223
 224 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 225 {
 226         return single_open(file, dw_mci_regs_show, inode->i_private);
 227 }
 228
 229 static const struct file_operations dw_mci_regs_fops = {
 230         .owner          = THIS_MODULE,
 231         .open           = dw_mci_regs_open,
 232         .read           = seq_read,
 233         .llseek         = seq_lseek,
 234         .release        = single_release,
 235 };
 236
 237 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 238 {
 239         struct mmc_host *mmc = slot->mmc;
 240         struct dw_mci *host = slot->host;
 241         struct dentry *root;
 242         struct dentry *node;
 243
 244         root = mmc->debugfs_root;
 245         if (!root)
 246                 return;
 247
 248         node = debugfs_create_file("regs", S_IRUSR, root, host,
 249                                    &dw_mci_regs_fops);
 250         if (!node)
 251                 goto err;
 252
 253         node = debugfs_create_file("req", S_IRUSR, root, slot,
 254                                    &dw_mci_req_fops);
 255         if (!node)
 256                 goto err;
 257
 258         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 259         if (!node)
 260                 goto err;
 261
 262         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 263                                   (u32 *)&host->pending_events);
 264         if (!node)
 265                 goto err;
 266
 267         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 268                                   (u32 *)&host->completed_events);
 269         if (!node)
 270                 goto err;
 271
 272         return;
 273
 274 err:
 275         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 276 }
 277 #endif /* defined(CONFIG_DEBUG_FS) */
 278
 279 static void dw_mci_set_timeout(struct dw_mci *host)
 280 {
 281         /* timeout (maximum) */
 282         mci_writel(host, TMOUT, 0xffffffff);
 283 }
 284
 285 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 286 {
 287         struct mmc_data *data;
 288         struct dw_mci_slot *slot = mmc_priv(mmc);
 289         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 290         u32 cmdr;
 291         cmd->error = -EINPROGRESS;
 292
 293         cmdr = cmd->opcode;
 294
 295         if (cmdr == MMC_STOP_TRANSMISSION)
 296                 cmdr |= SDMMC_CMD_STOP;
 297         else
 298                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 299
 300         if (cmd->flags & MMC_RSP_PRESENT) {
 301                 /* We expect a response, so set this bit */
 302                 cmdr |= SDMMC_CMD_RESP_EXP;
 303                 if (cmd->flags & MMC_RSP_136)
 304                         cmdr |= SDMMC_CMD_RESP_LONG;
 305         }
 306
 307         if (cmd->flags & MMC_RSP_CRC)
 308                 cmdr |= SDMMC_CMD_RESP_CRC;
 309
 310         data = cmd->data;
 311         if (data) {
 312                 cmdr |= SDMMC_CMD_DAT_EXP;
 313                 if (data->flags & MMC_DATA_STREAM)
 314                         cmdr |= SDMMC_CMD_STRM_MODE;
 315                 if (data->flags & MMC_DATA_WRITE)
 316                         cmdr |= SDMMC_CMD_DAT_WR;
 317         }
 318
 319         if (drv_data && drv_data->prepare_command)
 320                 drv_data->prepare_command(slot->host, &cmdr);
 321
 322         return cmdr;
 323 }
 324
 325 #if 0
 326 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 327 {
 328         struct mmc_command *stop;
 329         u32 cmdr;
 330
 331         if (!cmd->data)
 332                 return 0;
 333
 334         stop = &host->stop_abort;
 335         cmdr = cmd->opcode;
 336         memset(stop, 0, sizeof(struct mmc_command));
 337
 338         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 339             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 340             cmdr == MMC_WRITE_BLOCK ||
 341             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 342                 stop->opcode = MMC_STOP_TRANSMISSION;
 343                 stop->arg = 0;
 344                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 345         } else if (cmdr == SD_IO_RW_EXTENDED) {
 346                 stop->opcode = SD_IO_RW_DIRECT;
 347                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 348                              ((cmd->arg >> 28) & 0x7);
 349                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 350         } else {
 351                 return 0;
 352         }
 353
 354         cmdr = stop->opcode | SDMMC_CMD_STOP |
 355                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 356
 357         return cmdr;
 358 }
 359 #endif
 360 static void dw_mci_start_command(struct dw_mci *host,
 361                                  struct mmc_command *cmd, u32 cmd_flags)
 362 {
 363         struct dw_mci_slot *slot = host->slot[0];
 364         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 365
 366         host->pre_cmd = host->cmd;
 367         host->cmd = cmd;
 368         dev_vdbg(host->dev,
 369                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 370                 cmd->arg, cmd_flags);
 371
 372         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 373                 /*confirm non-low-power mode*/
 374                 mci_writel(host, CMDARG, 0);
 375                 dw_mci_disable_low_power(slot);
 376
 377                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 378                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 379
 380                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 381         }
 382
 383         mci_writel(host, CMDARG, cmd->arg);
 384         wmb();
 385
 386         /* fix the value to 1 in some Soc,for example RK3188. */
 387         if(host->mmc->hold_reg_flag)
 388                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 389
 390         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 391         wmb();
 392 }
 393
 394 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 395 {
 396         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 397 }
 398
 399 /* DMA interface functions */
 400 static void dw_mci_stop_dma(struct dw_mci *host)
 401 {
 402         if (host->using_dma) {
 403                 /* Fixme: No need to terminate edma, may cause flush op */
 404                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 405                         host->dma_ops->stop(host);
 406                 host->dma_ops->cleanup(host);
 407         }
 408
 409         /* Data transfer was stopped by the interrupt handler */
 410         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 411 }
 412
 413 static int dw_mci_get_dma_dir(struct mmc_data *data)
 414 {
 415         if (data->flags & MMC_DATA_WRITE)
 416                 return DMA_TO_DEVICE;
 417         else
 418                 return DMA_FROM_DEVICE;
 419 }
 420
 421 #ifdef CONFIG_MMC_DW_IDMAC
 422 static void dw_mci_dma_cleanup(struct dw_mci *host)
 423 {
 424         struct mmc_data *data = host->data;
 425
 426         if (data)
 427                 if (!data->host_cookie)
 428                         dma_unmap_sg(host->dev,
 429                                      data->sg,
 430                                      data->sg_len,
 431                                      dw_mci_get_dma_dir(data));
 432 }
 433
 434 static void dw_mci_idmac_reset(struct dw_mci *host)
 435 {
 436         u32 bmod = mci_readl(host, BMOD);
 437         /* Software reset of DMA */
 438         bmod |= SDMMC_IDMAC_SWRESET;
 439         mci_writel(host, BMOD, bmod);
 440 }
 441
 442 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 443 {
 444         u32 temp;
 445
 446         /* Disable and reset the IDMAC interface */
 447         temp = mci_readl(host, CTRL);
 448         temp &= ~SDMMC_CTRL_USE_IDMAC;
 449         temp |= SDMMC_CTRL_DMA_RESET;
 450         mci_writel(host, CTRL, temp);
 451
 452         /* Stop the IDMAC running */
 453         temp = mci_readl(host, BMOD);
 454         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 455         temp |= SDMMC_IDMAC_SWRESET;
 456         mci_writel(host, BMOD, temp);
 457 }
 458
 459 static void dw_mci_idmac_complete_dma(void *arg)
 460 {
 461         struct dw_mci *host = arg;
 462         struct mmc_data *data = host->data;
 463
 464         dev_vdbg(host->dev, "DMA complete\n");
 465
 466         /*
 467         MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 468                 host->mrq->cmd->opcode,host->mrq->cmd->arg,
 469                 data->blocks,data->blksz,mmc_hostname(host->mmc));
 470         */
 471
 472         host->dma_ops->cleanup(host);
 473
 474         /*
 475          * If the card was removed, data will be NULL. No point in trying to
 476          * send the stop command or waiting for NBUSY in this case.
 477          */
 478         if(data){
 479                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 480                 tasklet_schedule(&host->tasklet);
 481         }
 482 }
 483
 484 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 485                                     unsigned int sg_len)
 486 {
 487         int i;
 488         struct idmac_desc *desc = host->sg_cpu;
 489
 490         for (i = 0; i < sg_len; i++, desc++) {
 491                 unsigned int length = sg_dma_len(&data->sg[i]);
 492                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 493
 494                 /* Set the OWN bit and disable interrupts for this descriptor */
 495                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 496
 497                 /* Buffer length */
 498                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 499
 500                 /* Physical address to DMA to/from */
 501                 desc->des2 = mem_addr;
 502         }
 503
 504         /* Set first descriptor */
 505         desc = host->sg_cpu;
 506         desc->des0 |= IDMAC_DES0_FD;
 507
 508         /* Set last descriptor */
 509         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 510         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 511         desc->des0 |= IDMAC_DES0_LD;
 512
 513         wmb();
 514 }
 515
 516 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 517 {
 518         u32 temp;
 519
 520         dw_mci_translate_sglist(host, host->data, sg_len);
 521
 522         /* Select IDMAC interface */
 523         temp = mci_readl(host, CTRL);
 524         temp |= SDMMC_CTRL_USE_IDMAC;
 525         mci_writel(host, CTRL, temp);
 526
 527         wmb();
 528
 529         /* Enable the IDMAC */
 530         temp = mci_readl(host, BMOD);
 531         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 532         mci_writel(host, BMOD, temp);
 533
 534         /* Start it running */
 535         mci_writel(host, PLDMND, 1);
 536 }
 537
 538 static int dw_mci_idmac_init(struct dw_mci *host)
 539 {
 540         struct idmac_desc *p;
 541         int i;
 542
 543         /* Number of descriptors in the ring buffer */
 544         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 545
 546         /* Forward link the descriptor list */
 547         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 548                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 549
 550         /* Set the last descriptor as the end-of-ring descriptor */
 551         p->des3 = host->sg_dma;
 552         p->des0 = IDMAC_DES0_ER;
 553
 554         dw_mci_idmac_reset(host);
 555
 556         /* Mask out interrupts - get Tx & Rx complete only */
 557         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 558         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 559                    SDMMC_IDMAC_INT_TI);
 560
 561         /* Set the descriptor base address */
 562         mci_writel(host, DBADDR, host->sg_dma);
 563         return 0;
 564 }
 565
 566 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 567         .init = dw_mci_idmac_init,
 568         .start = dw_mci_idmac_start_dma,
 569         .stop = dw_mci_idmac_stop_dma,
 570         .complete = dw_mci_idmac_complete_dma,
 571         .cleanup = dw_mci_dma_cleanup,
 572 };
 573
 574
 575 static void dw_mci_edma_cleanup(struct dw_mci *host)
 576 {
 577         struct mmc_data *data = host->data;
 578
 579         if (data)
 580                 if (!data->host_cookie)
 581                         dma_unmap_sg(host->dev,
 582                                         data->sg, data->sg_len,
 583                                         dw_mci_get_dma_dir(data));
 584 }
 585
 586 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 587 {
 588         dmaengine_terminate_all(host->dms->ch);
 589 }
 590
 591 static void dw_mci_edmac_complete_dma(void *arg)
 592 {
 593         struct dw_mci *host = arg;
 594         struct mmc_data *data = host->data;
 595
 596         dev_vdbg(host->dev, "DMA complete\n");
 597
 598         if(data)
 599                 if(data->flags & MMC_DATA_READ)
 600                         /* Invalidate cache after read */
 601                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 602                                 data->sg_len, DMA_FROM_DEVICE);
 603
 604         host->dma_ops->cleanup(host);
 605
 606         /*
 607          * If the card was removed, data will be NULL. No point in trying to
 608          * send the stop command or waiting for NBUSY in this case.
 609          */
 610         if (data) {
 611                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 612                 tasklet_schedule(&host->tasklet);
 613         }
 614 }
 615
 616 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 617 {
 618         struct dma_slave_config slave_config;
 619         struct dma_async_tx_descriptor *desc = NULL;
 620         struct scatterlist *sgl = host->data->sg;
 621         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 622         u32 sg_elems = host->data->sg_len;
 623         u32 fifoth_val, mburst;
 624         u32 burst_limit = 0;
 625         u32 idx, rx_wmark, tx_wmark;
 626         int ret = 0;
 627
 628         /* Set external dma config: burst size, burst width*/
 629         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 630         slave_config.src_addr = slave_config.dst_addr;
 631         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 632         slave_config.src_addr_width = slave_config.dst_addr_width;
 633
 634         /* Match FIFO dma burst MSIZE with external dma config*/
 635         fifoth_val = mci_readl(host, FIFOTH);
 636         mburst = mszs[(fifoth_val >> 28) & 0x7];
 637
 638         /* edmac limit burst to 16, but work around for rk3036 to 8 */
 639         if (unlikely(cpu_is_rk3036()))
 640                 burst_limit = 8;
 641         else
 642                 burst_limit = 16;
 643
 644         if (mburst > burst_limit) {
 645                 mburst = burst_limit;
 646                 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
 647
 648                 if (soc_is_rk3126b()) {
 649                         idx = 0;
 650                         rx_wmark = (host->fifo_depth) / 2 - 1;
 651                 } else {
 652                         rx_wmark = mszs[idx] - 1;
 653                 }
 654
 655                 tx_wmark = (host->fifo_depth) / 2;
 656                 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
 657
 658                 mci_writel(host, FIFOTH, fifoth_val);
 659         }
 660
 661         slave_config.dst_maxburst = mburst;
 662         slave_config.src_maxburst = slave_config.dst_maxburst;
 663
 664         if(host->data->flags & MMC_DATA_WRITE){
 665                 slave_config.direction = DMA_MEM_TO_DEV;
 666                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 667                 if(ret){
 668                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 669                         return;
 670                 }
 671
 672                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 673                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 674                 if (!desc) {
 675                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 676                         return;
 677                 }
 678                 /* Set dw_mci_edmac_complete_dma as callback */
 679                 desc->callback = dw_mci_edmac_complete_dma;
 680                 desc->callback_param = (void *)host;
 681                 dmaengine_submit(desc);
 682
 683                 /* Flush cache before write */
 684                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 685                                 sg_elems, DMA_TO_DEVICE);
 686                 dma_async_issue_pending(host->dms->ch);
 687         } else {
 688                 /* MMC_DATA_READ*/
 689                 slave_config.direction = DMA_DEV_TO_MEM;
 690                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 691                 if (ret) {
 692                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 693                         return;
 694                 }
 695                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 696                                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 697                 if (!desc) {
 698                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 699                         return;
 700                 }
 701                 /* set dw_mci_edmac_complete_dma as callback */
 702                 desc->callback = dw_mci_edmac_complete_dma;
 703                 desc->callback_param = (void *)host;
 704                 dmaengine_submit(desc);
 705                 dma_async_issue_pending(host->dms->ch);
 706         }
 707 }
 708
 709 static int dw_mci_edmac_init(struct dw_mci *host)
 710 {
 711         /* Request external dma channel, SHOULD decide chn in dts */
 712         host->dms = NULL;
 713         host->dms = (struct dw_mci_dma_slave *)kmalloc
 714                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 715         if (NULL == host->dms) {
 716                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 717                 goto err_exit;
 718         }
 719
 720         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 721         if (!host->dms->ch) {
 722                 dev_err(host->dev, "Failed to get external DMA channel: channel id = %d\n",
 723                                 host->dms->ch->chan_id);
 724                 goto err_exit;
 725         }
 726
 727         return 0;
 728
 729 err_exit:
 730         if (NULL != host->dms) {
 731                 kfree(host->dms);
 732                 host->dms = NULL;
 733         }
 734         return -ENXIO;
 735
 736 }
 737
 738 static void dw_mci_edmac_exit(struct dw_mci *host)
 739 {
 740         if (NULL != host->dms) {
 741                 if (NULL != host->dms->ch) {
 742                         dma_release_channel(host->dms->ch);
 743                         host->dms->ch = NULL;
 744                 }
 745                 kfree(host->dms);
 746                 host->dms = NULL;
 747         }
 748 }
 749
 750 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 751         .init = dw_mci_edmac_init,
 752         .exit = dw_mci_edmac_exit,
 753         .start = dw_mci_edmac_start_dma,
 754         .stop = dw_mci_edmac_stop_dma,
 755         .complete = dw_mci_edmac_complete_dma,
 756         .cleanup = dw_mci_edma_cleanup,
 757 };
 758 #endif /* CONFIG_MMC_DW_IDMAC */
 759
 760 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 761                                    struct mmc_data *data,
 762                                    bool next)
 763 {
 764         struct scatterlist *sg;
 765         unsigned int i, sg_len;
 766
 767         if (!next && data->host_cookie)
 768                 return data->host_cookie;
 769
 770         /*
 771          * We don't do DMA on "complex" transfers, i.e. with
 772          * non-word-aligned buffers or lengths. Also, we don't bother
 773          * with all the DMA setup overhead for short transfers.
 774          */
 775         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 776                 return -EINVAL;
 777
 778         if (data->blksz & 3)
 779                 return -EINVAL;
 780
 781         for_each_sg(data->sg, sg, data->sg_len, i) {
 782                 if (sg->offset & 3 || sg->length & 3)
 783                         return -EINVAL;
 784         }
 785
 786         sg_len = dma_map_sg(host->dev,
 787                             data->sg,
 788                             data->sg_len,
 789                             dw_mci_get_dma_dir(data));
 790         if (sg_len == 0)
 791                 return -EINVAL;
 792
 793         if (next)
 794                 data->host_cookie = sg_len;
 795
 796         return sg_len;
 797 }
 798
 799 static void dw_mci_pre_req(struct mmc_host *mmc,
 800                            struct mmc_request *mrq,
 801                            bool is_first_req)
 802 {
 803         struct dw_mci_slot *slot = mmc_priv(mmc);
 804         struct mmc_data *data = mrq->data;
 805
 806         if (!slot->host->use_dma || !data)
 807                 return;
 808
 809         if (data->host_cookie) {
 810                 data->host_cookie = 0;
 811                 return;
 812         }
 813
 814         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 815                 data->host_cookie = 0;
 816 }
 817
 818 static void dw_mci_post_req(struct mmc_host *mmc,
 819                             struct mmc_request *mrq,
 820                             int err)
 821 {
 822         struct dw_mci_slot *slot = mmc_priv(mmc);
 823         struct mmc_data *data = mrq->data;
 824
 825         if (!slot->host->use_dma || !data)
 826                 return;
 827
 828         if (data->host_cookie)
 829                 dma_unmap_sg(slot->host->dev,
 830                              data->sg,
 831                              data->sg_len,
 832                              dw_mci_get_dma_dir(data));
 833         data->host_cookie = 0;
 834 }
 835
 836 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 837 {
 838 #ifdef CONFIG_MMC_DW_IDMAC
 839         unsigned int blksz = data->blksz;
 840         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 841         u32 fifo_width = 1 << host->data_shift;
 842         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 843         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 844         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 845
 846         tx_wmark = (host->fifo_depth) / 2;
 847         tx_wmark_invers = host->fifo_depth - tx_wmark;
 848
 849         /*
 850          * MSIZE is '1',
 851          * if blksz is not a multiple of the FIFO width
 852          */
 853         if (blksz % fifo_width) {
 854                 msize = 0;
 855                 rx_wmark = 1;
 856                 goto done;
 857         }
 858
 859         do {
 860                 if (!((blksz_depth % mszs[idx]) ||
 861                      (tx_wmark_invers % mszs[idx]))) {
 862                         msize = idx;
 863                         rx_wmark = mszs[idx] - 1;
 864                         break;
 865                 }
 866         } while (--idx > 0);
 867         /*
 868          * If idx is '0', it won't be tried
 869          * Thus, initial values are uesed
 870          */
 871 done:
 872         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 873         mci_writel(host, FIFOTH, fifoth_val);
 874
 875 #endif
 876 }
 877
 878 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 879 {
 880         unsigned int blksz = data->blksz;
 881         u32 blksz_depth, fifo_depth;
 882         u16 thld_size;
 883
 884         WARN_ON(!(data->flags & MMC_DATA_READ));
 885
 886         if (host->timing != MMC_TIMING_MMC_HS200 &&
 887             host->timing != MMC_TIMING_UHS_SDR104)
 888                 goto disable;
 889
 890         blksz_depth = blksz / (1 << host->data_shift);
 891         fifo_depth = host->fifo_depth;
 892
 893         if (blksz_depth > fifo_depth)
 894                 goto disable;
 895
 896         /*
 897          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 898          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 899          * Currently just choose blksz.
 900          */
 901         thld_size = blksz;
 902         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 903         return;
 904
 905 disable:
 906         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 907 }
 908
 909 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 910 {
 911         int sg_len;
 912         unsigned long flags;
 913         u32 temp;
 914
 915         host->using_dma = 0;
 916
 917         /* If we don't have a channel, we can't do DMA */
 918         if (!host->use_dma)
 919                 return -ENODEV;
 920
 921         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 922         if (sg_len < 0) {
 923                 /* Fixme: No need terminate edma, may cause flush op */
 924                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 925                         host->dma_ops->stop(host);
 926                 return sg_len;
 927         }
 928
 929         host->using_dma = 1;
 930
 931         dev_vdbg(host->dev,
 932                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 933                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 934                  sg_len);
 935
 936         /*
 937          * Decide the MSIZE and RX/TX Watermark.
 938          * If current block size is same with previous size,
 939          * no need to update fifoth.
 940          */
 941         if (host->prev_blksz != data->blksz)
 942                 dw_mci_adjust_fifoth(host, data);
 943
 944         /* Reset DMA FIFO*/
 945         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 946
 947         /* Enable the DMA interface */
 948         temp = mci_readl(host, CTRL);
 949         temp |= SDMMC_CTRL_DMA_ENABLE;
 950         mci_writel(host, CTRL, temp);
 951
 952         /* Disable RX/TX IRQs, let DMA handle it */
 953         spin_lock_irqsave(&host->slock, flags);
 954         temp = mci_readl(host, INTMASK);
 955         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 956         mci_writel(host, INTMASK, temp);
 957         spin_unlock_irqrestore(&host->slock, flags);
 958
 959         host->dma_ops->start(host, sg_len);
 960
 961         return 0;
 962 }
 963
 964 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 965 {
 966         u32 temp;
 967         unsigned long flag;
 968
 969         data->error = -EINPROGRESS;
 970
 971         //WARN_ON(host->data);
 972         host->sg = NULL;
 973         host->data = data;
 974
 975         /* Reset FIFO*/
 976         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
 977
 978         if (data->flags & MMC_DATA_READ) {
 979                 host->dir_status = DW_MCI_RECV_STATUS;
 980                 dw_mci_ctrl_rd_thld(host, data);
 981         } else {
 982                 host->dir_status = DW_MCI_SEND_STATUS;
 983         }
 984
 985     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
 986          data->blocks, data->blksz, mmc_hostname(host->mmc));
 987
 988         if (dw_mci_submit_data_dma(host, data)) {
 989                 int flags = SG_MITER_ATOMIC;
 990                 if (host->data->flags & MMC_DATA_READ)
 991                         flags |= SG_MITER_TO_SG;
 992                 else
 993                         flags |= SG_MITER_FROM_SG;
 994
 995                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 996                 host->sg = data->sg;
 997                 host->part_buf_start = 0;
 998                 host->part_buf_count = 0;
 999
1000                 spin_lock_irqsave(&host->slock, flag);
1001                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1002                 temp = mci_readl(host, INTMASK);
1003                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1004                 mci_writel(host, INTMASK, temp);
1005                 spin_unlock_irqrestore(&host->slock, flag);
1006
1007                 temp = mci_readl(host, CTRL);
1008                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1009                 mci_writel(host, CTRL, temp);
1010
1011                 /*
1012                  * Use the initial fifoth_val for PIO mode.
1013                  * If next issued data may be transfered by DMA mode,
1014                  * prev_blksz should be invalidated.
1015                  */
1016                 mci_writel(host, FIFOTH, host->fifoth_val);
1017                 host->prev_blksz = 0;
1018         } else {
1019                 /*
1020                  * Keep the current block size.
1021                  * It will be used to decide whether to update
1022                  * fifoth register next time.
1023                  */
1024                 host->prev_blksz = data->blksz;
1025         }
1026 }
1027
1028 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1029 {
1030         struct dw_mci *host = slot->host;
1031         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
1032         unsigned int cmd_status = 0;
1033 #ifdef SDMMC_WAIT_FOR_UNBUSY
1034         bool ret = true;
1035         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1036
1037     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1038         while (ret) {
1039                 ret =  time_before(jiffies, timeout);
1040                 cmd_status = mci_readl(host, STATUS);
1041                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1042                         break;
1043         } ;
1044         if(false == ret)
1045             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
1046                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
1047     }
1048 #endif
1049         mci_writel(host, CMDARG, arg);
1050         wmb();
1051         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1052         if(cmd & SDMMC_CMD_UPD_CLK)
1053                 timeout = jiffies + msecs_to_jiffies(50);
1054         else
1055                 timeout = jiffies + msecs_to_jiffies(500);
1056         while (time_before(jiffies, timeout)) {
1057                 cmd_status = mci_readl(host, CMD);
1058                 if (!(cmd_status & SDMMC_CMD_START))
1059                         return ;
1060         }
1061         dev_err(&slot->mmc->class_dev,
1062                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1063                 cmd, arg, cmd_status);
1064 }
1065
1066 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1067 {
1068         struct dw_mci *host = slot->host;
1069         unsigned int tempck,clock = slot->clock;
1070         u32 div;
1071         u32 clk_en_a;
1072         u32 sdio_int;
1073
1074         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
1075                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
1076
1077         if (!clock) {
1078                 mci_writel(host, CLKENA, 0);
1079                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1080                 if(host->svi_flags == 0)
1081                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1082                 #else
1083                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1084                 #endif
1085         } else if (clock != host->current_speed || force_clkinit) {
1086                 div = host->bus_hz / clock;
1087                 if (host->bus_hz % clock && host->bus_hz > clock)
1088                         /*
1089                          * move the + 1 after the divide to prevent
1090                          * over-clocking the card.
1091                          */
1092                         div += 1;
1093
1094                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1095
1096                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1097                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1098                         dev_info(&slot->mmc->class_dev,
1099                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1100                                  slot->id, host->bus_hz, clock,
1101                                  tempck, div);
1102
1103                         host->set_speed = tempck;
1104                         host->set_div = div;
1105                 }
1106
1107                 /* disable clock */
1108                 mci_writel(host, CLKENA, 0);
1109                 mci_writel(host, CLKSRC, 0);
1110
1111                 /* inform CIU */
1112                 mci_send_cmd(slot,
1113                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1114
1115                 if(clock <= 400*1000){
1116                         MMC_DBG_BOOT_FUNC(host->mmc,
1117                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1118                                 clock * 2, mmc_hostname(host->mmc));
1119                         /* clk_mmc will change parents to 24MHz xtal*/
1120                         clk_set_rate(host->clk_mmc, clock * 2);
1121
1122                         div = 0;
1123                         host->set_div = div;
1124                 }
1125                 else
1126                 {
1127                         MMC_DBG_BOOT_FUNC(host->mmc,
1128                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1129                                 mmc_hostname(host->mmc));
1130                         if(div > 1)
1131                         {
1132                                 MMC_DBG_ERR_FUNC(host->mmc,
1133                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1134                                         mmc_hostname(host->mmc));
1135                                  div = 1;
1136                                  host->set_div = div;
1137                                  host->bus_hz = host->set_speed * 2;
1138                                  MMC_DBG_BOOT_FUNC(host->mmc,
1139                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1140                                         div, host->bus_hz, mmc_hostname(host->mmc));
1141                         }
1142                         /* BUG may be here, come on,  Linux BSP engineer looks!
1143                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1144                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1145                            some oops happened like that:
1146                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1147                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1148                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1149                            mmc0: new high speed DDR MMC card at address 0001
1150                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1151                            ....
1152                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1153                            mmcblk0: retrying using single block read
1154                            mmcblk0: error -110 sending status command, retrying
1155
1156                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1157                          */
1158                         if ((div == 0) &&
1159                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1160                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1161                                 /*  Fixup DDR MMC */
1162                                 div = 1;
1163                                 host->set_div = div;
1164                                 host->bus_hz = host->set_speed * 2;
1165                                 MMC_DBG_BOOT_FUNC(host->mmc,
1166                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1167                                         div, host->bus_hz, mmc_hostname(host->mmc));
1168                         }
1169
1170                         if (host->verid < DW_MMC_240A)
1171                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1172                         else
1173                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1174
1175
1176
1177                 }
1178
1179                 /* set clock to desired speed */
1180                 mci_writel(host, CLKDIV, div);
1181
1182                 /* inform CIU */
1183                 mci_send_cmd(slot,
1184                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1185
1186                 /* enable clock; only low power if no SDIO */
1187                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1188
1189                 if (host->verid < DW_MMC_240A)
1190                     sdio_int = SDMMC_INT_SDIO(slot->id);
1191                 else
1192                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1193
1194                 if (!(mci_readl(host, INTMASK) & sdio_int))
1195                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1196                 mci_writel(host, CLKENA, clk_en_a);
1197
1198                 /* inform CIU */
1199                 mci_send_cmd(slot,
1200                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1201                 /* keep the clock with reflecting clock dividor */
1202                 slot->__clk_old = clock << div;
1203         }
1204
1205         host->current_speed = clock;
1206
1207     if(slot->ctype != slot->pre_ctype)
1208         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
1209             host->set_speed,
1210             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
1211             mmc_hostname(host->mmc));
1212     slot->pre_ctype = slot->ctype;
1213
1214         /* Set the current slot bus width */
1215         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1216 }
1217
1218 extern struct mmc_card *this_card;
1219 static void dw_mci_wait_unbusy(struct dw_mci *host)
1220 {
1221
1222         unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1223         unsigned long   time_loop;
1224         unsigned int    status;
1225         u32 se_flag = 0;
1226
1227         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1228
1229         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1230                 if (host->cmd && (host->cmd->opcode == MMC_ERASE)) {
1231                 /* Special care for (secure)erase timeout calculation */
1232                         if(this_card){
1233                                 if((host->cmd->arg & (0x1 << 31)) == 1) /* secure erase */
1234                                         se_flag = 0x1;
1235
1236                                 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1237                                         se_flag ? (timeout = (this_card->ext_csd.hc_erase_timeout) *
1238                                                         300000 * (this_card->ext_csd.sec_erase_mult)) :
1239                                                         (timeout = (this_card->ext_csd.hc_erase_timeout) * 300000);
1240                         }
1241                 }
1242
1243                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1244                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1245         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1246                 timeout = SDMMC_DATA_TIMEOUT_SD;
1247         }
1248
1249         time_loop = jiffies + msecs_to_jiffies(timeout);
1250         do {
1251                 status = mci_readl(host, STATUS);
1252                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1253                         break;
1254         } while (time_before(jiffies, time_loop));
1255 }
1256
1257
1258
1259 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1260 /*
1261 *   result:
1262 *   0--status is busy.
1263 *   1--status is unbusy.
1264 */
1265 int dw_mci_card_busy(struct mmc_host *mmc)
1266 {
1267         struct dw_mci_slot *slot = mmc_priv(mmc);
1268         struct dw_mci *host = slot->host;
1269
1270         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1271                                 host->svi_flags, mmc_hostname(host->mmc));
1272
1273         /* svi toggle*/
1274         if(host->svi_flags == 0){
1275                 /*first svi*/
1276                 host->svi_flags = 1;
1277                 return host->svi_flags;
1278
1279         }else{
1280                 host->svi_flags = 0;
1281                 return host->svi_flags;
1282         }
1283
1284
1285 }
1286 #endif
1287 static void __dw_mci_start_request(struct dw_mci *host,
1288                                    struct dw_mci_slot *slot,
1289                                    struct mmc_command *cmd)
1290 {
1291         struct mmc_request *mrq;
1292         struct mmc_data *data;
1293         u32 cmdflags;
1294
1295         mrq = slot->mrq;
1296         if (host->pdata->select_slot)
1297                 host->pdata->select_slot(slot->id);
1298
1299         host->cur_slot = slot;
1300         host->mrq = mrq;
1301
1302         dw_mci_wait_unbusy(host);
1303
1304         host->pending_events = 0;
1305         host->completed_events = 0;
1306         host->data_status = 0;
1307
1308         data = cmd->data;
1309         if (data) {
1310                 dw_mci_set_timeout(host);
1311                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1312                 mci_writel(host, BLKSIZ, data->blksz);
1313         }
1314
1315         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1316
1317         /* this is the first command, send the initialization clock */
1318         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1319                 cmdflags |= SDMMC_CMD_INIT;
1320
1321         if (data) {
1322                 dw_mci_submit_data(host, data);
1323                 wmb();
1324         }
1325
1326         dw_mci_start_command(host, cmd, cmdflags);
1327
1328         if (mrq->stop)
1329                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1330 }
1331
1332 static void dw_mci_start_request(struct dw_mci *host,
1333                                  struct dw_mci_slot *slot)
1334 {
1335         struct mmc_request *mrq = slot->mrq;
1336         struct mmc_command *cmd;
1337
1338         MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1339                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1340
1341         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1342         __dw_mci_start_request(host, slot, cmd);
1343 }
1344
1345 /* must be called with host->lock held */
1346 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1347                                  struct mmc_request *mrq)
1348 {
1349         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1350                  host->state);
1351
1352         slot->mrq = mrq;
1353
1354         if (host->state == STATE_IDLE) {
1355                 host->state = STATE_SENDING_CMD;
1356                 dw_mci_start_request(host, slot);
1357         } else {
1358                 list_add_tail(&slot->queue_node, &host->queue);
1359         }
1360 }
1361
1362 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1363 {
1364         struct dw_mci_slot *slot = mmc_priv(mmc);
1365         struct dw_mci *host = slot->host;
1366
1367         WARN_ON(slot->mrq);
1368
1369         /*
1370          * The check for card presence and queueing of the request must be
1371          * atomic, otherwise the card could be removed in between and the
1372          * request wouldn't fail until another card was inserted.
1373          */
1374         spin_lock_bh(&host->lock);
1375
1376         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1377                 spin_unlock_bh(&host->lock);
1378                 mrq->cmd->error = -ENOMEDIUM;
1379                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1380                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1381
1382                 mmc_request_done(mmc, mrq);
1383                 return;
1384         }
1385
1386         MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1387                                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1388
1389         dw_mci_queue_request(host, slot, mrq);
1390
1391         spin_unlock_bh(&host->lock);
1392 }
1393
1394 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1395 {
1396         struct dw_mci_slot *slot = mmc_priv(mmc);
1397         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1398         struct dw_mci *host = slot->host;
1399         #endif
1400         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1401         u32 regs;
1402
1403         #ifdef SDMMC_WAIT_FOR_UNBUSY
1404         unsigned long   time_loop;
1405         bool ret = true;
1406
1407         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1408         if(host->svi_flags == 1)
1409                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1410         else
1411                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1412         #else
1413                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1414         #endif
1415
1416         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1417                 printk("%d..%s:  no card. [%s]\n", \
1418                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1419                 goto EXIT_POWER;
1420         }
1421
1422         while (ret) {
1423                 ret = time_before(jiffies, time_loop);
1424                 regs = mci_readl(slot->host, STATUS);
1425                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1426                         break;
1427         };
1428
1429         if(false == ret)
1430         {
1431                 printk("slot->flags = %lu ", slot->flags);
1432                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1433                 if(host->svi_flags != 1)
1434                 #endif
1435                         dump_stack();
1436                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1437                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1438         }
1439         #endif
1440
1441         switch (ios->bus_width) {
1442         case MMC_BUS_WIDTH_4:
1443                 slot->ctype = SDMMC_CTYPE_4BIT;
1444                 break;
1445         case MMC_BUS_WIDTH_8:
1446                 slot->ctype = SDMMC_CTYPE_8BIT;
1447                 break;
1448         default:
1449                 /* set default 1 bit mode */
1450                 slot->ctype = SDMMC_CTYPE_1BIT;
1451                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1452         }
1453
1454         regs = mci_readl(slot->host, UHS_REG);
1455
1456         /* DDR mode set */
1457         if (ios->timing == MMC_TIMING_UHS_DDR50)
1458                 regs |= ((0x1 << slot->id) << 16);
1459         else
1460                 regs &= ~((0x1 << slot->id) << 16);
1461
1462         mci_writel(slot->host, UHS_REG, regs);
1463         slot->host->timing = ios->timing;
1464
1465         /*
1466          * Use mirror of ios->clock to prevent race with mmc
1467          * core ios update when finding the minimum.
1468          */
1469         slot->clock = ios->clock;
1470
1471         if (drv_data && drv_data->set_ios)
1472                 drv_data->set_ios(slot->host, ios);
1473
1474         /* Slot specific timing and width adjustment */
1475         dw_mci_setup_bus(slot, false);
1476                 //return -EAGAIN;
1477
1478 EXIT_POWER:
1479         switch (ios->power_mode) {
1480                 case MMC_POWER_UP:
1481                         set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1482                         /* Power up slot */
1483                         if (slot->host->pdata->setpower)
1484                                 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1485                         regs = mci_readl(slot->host, PWREN);
1486                         regs |= (1 << slot->id);
1487                         mci_writel(slot->host, PWREN, regs);
1488                         break;
1489                 case MMC_POWER_OFF:
1490                         /* Power down slot */
1491                         if(slot->host->pdata->setpower)
1492                                 slot->host->pdata->setpower(slot->id, 0);
1493                         regs = mci_readl(slot->host, PWREN);
1494                         regs &= ~(1 << slot->id);
1495                         mci_writel(slot->host, PWREN, regs);
1496                         break;
1497                 default:
1498                         break;
1499         }
1500 }
1501
1502 static int dw_mci_get_ro(struct mmc_host *mmc)
1503 {
1504         int read_only;
1505         struct dw_mci_slot *slot = mmc_priv(mmc);
1506         struct dw_mci_board *brd = slot->host->pdata;
1507
1508         /* Use platform get_ro function, else try on board write protect */
1509         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1510                 read_only = 0;
1511         else if(brd->get_ro)
1512                 read_only = brd->get_ro(slot->id);
1513         else if(gpio_is_valid(slot->wp_gpio))
1514                 read_only = gpio_get_value(slot->wp_gpio);
1515         else
1516                 read_only =
1517                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1518
1519         dev_dbg(&mmc->class_dev, "card is %s\n",
1520                 read_only ? "read-only" : "read-write");
1521
1522         return read_only;
1523 }
1524
1525 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1526 {
1527         struct dw_mci_slot *slot = mmc_priv(mmc);
1528         struct dw_mci *host = slot->host;
1529         /*struct dw_mci_board *brd = slot->host->pdata;*/
1530
1531         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1532                 return 0;
1533
1534         spin_lock_bh(&host->lock);
1535
1536         if(val)
1537                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1538         else
1539                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1540
1541         spin_unlock_bh(&host->lock);
1542
1543         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1544                 if (__clk_is_enabled(host->hclk_mmc) == false)
1545                         clk_prepare_enable(host->hclk_mmc);
1546                 if (__clk_is_enabled(host->clk_mmc) == false)
1547                         clk_prepare_enable(host->clk_mmc);
1548         } else {
1549                 if (__clk_is_enabled(host->clk_mmc) == true)
1550                         clk_disable_unprepare(slot->host->clk_mmc);
1551                 if (__clk_is_enabled(host->hclk_mmc) == true)
1552                         clk_disable_unprepare(slot->host->hclk_mmc);
1553         }
1554
1555         mmc_detect_change(slot->mmc, 20);
1556         return 0;
1557 }
1558
1559
1560
1561 static int dw_mci_get_cd(struct mmc_host *mmc)
1562 {
1563         int present;
1564         struct dw_mci_slot *slot = mmc_priv(mmc);
1565         struct dw_mci_board *brd = slot->host->pdata;
1566         struct dw_mci *host = slot->host;
1567         int gpio_cd = mmc_gpio_get_cd(mmc);
1568         int force_jtag_bit, force_jtag_reg;
1569         int gpio_val;
1570         int irq;
1571
1572         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1573                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1574                 gpio_cd = slot->cd_gpio;
1575                 irq = gpio_to_irq(gpio_cd);
1576                 if (gpio_is_valid(gpio_cd)) {
1577                         gpio_val = gpio_get_value(gpio_cd);
1578                         if (soc_is_rk3036()) {
1579                                 force_jtag_bit = 11;
1580                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1581                         } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1582                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1583                                 force_jtag_bit = 8;
1584                         }
1585                         msleep(10);
1586                         if (gpio_val == gpio_get_value(gpio_cd)) {
1587                                 gpio_cd = (gpio_val == 0 ? 1 : 0);
1588                                 if (gpio_cd == 0) {
1589                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1590                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1591                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1592                                                         force_jtag_reg);
1593
1594                                         dw_mci_ctrl_all_reset(host);
1595                                 } else {
1596                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1597                                         /* Really card detected: SHOULD disable force_jtag */
1598                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1599                                                         force_jtag_reg);
1600                                 }
1601                         } else {
1602                                 /* Jitter */
1603                                 gpio_val = gpio_get_value(gpio_cd);
1604                                 (gpio_val == 0) ?
1605                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
1606                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW  | IRQF_ONESHOT);
1607                                 return slot->last_detect_state;
1608                         }
1609                 } else {
1610                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1611                 }
1612         }
1613
1614         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1615                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1616
1617         /* Use platform get_cd function, else try onboard card detect */
1618         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1619                 present = 1;
1620         else if (brd->get_cd)
1621                 present = !brd->get_cd(slot->id);
1622         else if (!IS_ERR_VALUE(gpio_cd))
1623                 present = gpio_cd;
1624         else
1625                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1626                         == 0 ? 1 : 0;
1627
1628         spin_lock_bh(&host->lock);
1629         if (present) {
1630                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1631                 dev_dbg(&mmc->class_dev, "card is present\n");
1632         } else {
1633                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1634                 dev_dbg(&mmc->class_dev, "card is not present\n");
1635         }
1636         spin_unlock_bh(&host->lock);
1637
1638         return present;
1639 }
1640
1641
1642 /*
1643  * Dts Should caps emmc controller with poll-hw-reset
1644  */
1645 static void dw_mci_hw_reset(struct mmc_host *mmc)
1646 {
1647         struct dw_mci_slot *slot = mmc_priv(mmc);
1648         struct dw_mci *host = slot->host;
1649         u32 regs;
1650
1651         #if 0
1652         u32 cmd_flags;
1653         unsigned long timeout;
1654         bool ret = true;
1655
1656         /* (1) CMD12 to end any transfer in process */
1657         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1658                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1659
1660         if(host->mmc->hold_reg_flag)
1661                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1662         mci_writel(host, CMDARG, 0);
1663         wmb();
1664         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1665         wmb();
1666         timeout = jiffies + msecs_to_jiffies(500);
1667         while(ret){
1668                 ret = time_before(jiffies, timeout);
1669                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1670                         break;
1671         }
1672
1673         if(false == ret)
1674                 MMC_DBG_ERR_FUNC(host->mmc,
1675                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1676                         __func__, mmc_hostname(host->mmc));
1677
1678         /* (2) wait DTO, even if no response is sent back by card */
1679         ret = true;
1680         timeout = jiffies + msecs_to_jiffies(5);
1681         while(ret){
1682                 ret = time_before(jiffies, timeout);
1683                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1684                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1685                         break;
1686                 }
1687         }
1688         #endif
1689
1690         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1691
1692         /* Software reset - BMOD[0] for IDMA only */
1693         regs = mci_readl(host, BMOD);
1694         regs |= SDMMC_IDMAC_SWRESET;
1695         mci_writel(host, BMOD, regs);
1696         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1697         regs = mci_readl(host, BMOD);
1698         if(regs & SDMMC_IDMAC_SWRESET)
1699                 MMC_DBG_WARN_FUNC(host->mmc,
1700                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1701                         __func__, mmc_hostname(host->mmc));
1702
1703         /* DMA reset - CTRL[2] */
1704         regs = mci_readl(host, CTRL);
1705         regs |= SDMMC_CTRL_DMA_RESET;
1706         mci_writel(host, CTRL, regs);
1707         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1708         regs = mci_readl(host, CTRL);
1709         if(regs & SDMMC_CTRL_DMA_RESET)
1710                 MMC_DBG_WARN_FUNC(host->mmc,
1711                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1712                         __func__, mmc_hostname(host->mmc));
1713
1714         /* FIFO reset - CTRL[1] */
1715         regs = mci_readl(host, CTRL);
1716         regs |= SDMMC_CTRL_FIFO_RESET;
1717         mci_writel(host, CTRL, regs);
1718         mdelay(1); /* no timing limited, 1ms is random value */
1719         regs = mci_readl(host, CTRL);
1720         if(regs & SDMMC_CTRL_FIFO_RESET)
1721                 MMC_DBG_WARN_FUNC(host->mmc,
1722                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1723                         __func__, mmc_hostname(host->mmc));
1724
1725         /* (4) CARD_RESET
1726         According to eMMC spec
1727         tRstW >= 1us ;   RST_n pulse width
1728         tRSCA >= 200us ; RST_n to Command time
1729         tRSTH >= 1us ;   RST_n high period
1730         */
1731         mci_writel(slot->host, PWREN, 0x0);
1732         mci_writel(slot->host, RST_N, 0x0);
1733         dsb(sy);
1734         udelay(10); /* 10us for bad quality eMMc. */
1735
1736         mci_writel(slot->host, PWREN, 0x1);
1737         mci_writel(slot->host, RST_N, 0x1);
1738         dsb(sy);
1739         usleep_range(500, 1000); /* at least 500(> 200us) */
1740 }
1741
1742 /*
1743  * Disable lower power mode.
1744  *
1745  * Low power mode will stop the card clock when idle.  According to the
1746  * description of the CLKENA register we should disable low power mode
1747  * for SDIO cards if we need SDIO interrupts to work.
1748  *
1749  * This function is fast if low power mode is already disabled.
1750  */
1751 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1752 {
1753         struct dw_mci *host = slot->host;
1754         u32 clk_en_a;
1755         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1756
1757         clk_en_a = mci_readl(host, CLKENA);
1758
1759         if (clk_en_a & clken_low_pwr) {
1760                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1761                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1762                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1763         }
1764 }
1765
1766 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1767 {
1768         struct dw_mci_slot *slot = mmc_priv(mmc);
1769         struct dw_mci *host = slot->host;
1770         unsigned long flags;
1771         u32 int_mask;
1772         u32 sdio_int;
1773
1774         spin_lock_irqsave(&host->slock, flags);
1775
1776         /* Enable/disable Slot Specific SDIO interrupt */
1777         int_mask = mci_readl(host, INTMASK);
1778
1779         if (host->verid < DW_MMC_240A)
1780                 sdio_int = SDMMC_INT_SDIO(slot->id);
1781         else
1782                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1783
1784         if (enb) {
1785                 /*
1786                  * Turn off low power mode if it was enabled.  This is a bit of
1787                  * a heavy operation and we disable / enable IRQs a lot, so
1788                  * we'll leave low power mode disabled and it will get
1789                  * re-enabled again in dw_mci_setup_bus().
1790                  */
1791                 dw_mci_disable_low_power(slot);
1792
1793                 mci_writel(host, INTMASK,
1794                            (int_mask | sdio_int));
1795         } else {
1796                 mci_writel(host, INTMASK,
1797                            (int_mask & ~sdio_int));
1798         }
1799
1800         spin_unlock_irqrestore(&host->slock, flags);
1801 }
1802
1803 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1804 enum{
1805         IO_DOMAIN_12 = 1200,
1806         IO_DOMAIN_18 = 1800,
1807         IO_DOMAIN_33 = 3300,
1808 };
1809 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1810 {
1811         switch(voltage){
1812                 case IO_DOMAIN_33:
1813                         voltage = 0;
1814                         break;
1815                 case IO_DOMAIN_18:
1816                         voltage = 1;
1817                         break;
1818                 case IO_DOMAIN_12:
1819                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Not support io domain voltage [%s]\n",
1820                                                         __FUNCTION__, mmc_hostname(host->mmc));
1821                         break;
1822                 default:
1823                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Err io domain voltage [%s]\n",
1824                                                         __FUNCTION__, mmc_hostname(host->mmc));
1825                         break;
1826         }
1827
1828         if (cpu_is_rk3288()) {
1829                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1830                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1831                 else
1832                         return ;
1833         } else if (host->cid == DW_MCI_TYPE_RK3368) {
1834                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1835                          regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1836                 else
1837                         return;
1838         } else {
1839                 MMC_DBG_ERR_FUNC(host->mmc,"%s : unknown chip [%s]\n",
1840                                         __FUNCTION__, mmc_hostname(host->mmc));
1841         }
1842 }
1843
1844 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1845                                                 struct mmc_ios *ios)
1846 {
1847         int ret;
1848         unsigned int value,uhs_reg;
1849
1850         /*
1851          * Signal Voltage Switching is only applicable for Host Controllers
1852          * v3.00 and above.
1853          */
1854         if (host->verid < DW_MMC_240A)
1855                 return 0;
1856
1857         uhs_reg = mci_readl(host, UHS_REG);
1858         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1859                 __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1860
1861         switch (ios->signal_voltage) {
1862         case MMC_SIGNAL_VOLTAGE_330:
1863                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1864                 if (host->vmmc) {
1865                         if (cpu_is_rk3288())
1866                                 ret = io_domain_regulator_set_voltage(
1867                                                 host->vmmc, 3300000, 3300000);
1868                         else
1869                                 ret = regulator_set_voltage(host->vmmc, 3300000, 3300000);
1870
1871                         /* regulator_put(host->vmmc); //to be done in remove function. */
1872
1873                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1874                             __func__, regulator_get_voltage(host->vmmc), ret);
1875                         if (ret) {
1876                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 3.3V signalling voltage "
1877                                                 " failed\n", mmc_hostname(host->mmc));
1878                                 return -EIO;
1879                         }
1880                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1881                 }
1882                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__,
1883                                         __FUNCTION__, mmc_hostname(host->mmc));
1884
1885                 /* set High-power mode */
1886                 value = mci_readl(host, CLKENA);
1887                 value &= ~SDMMC_CLKEN_LOW_PWR;
1888                 mci_writel(host,CLKENA , value);
1889                 /* SDMMC_UHS_REG */
1890                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1891                 mci_writel(host,UHS_REG , uhs_reg);
1892
1893                 /* Wait for 5ms */
1894                 usleep_range(5000, 5500);
1895
1896                 /* 3.3V regulator output should be stable within 5 ms */
1897                 uhs_reg = mci_readl(host, UHS_REG);
1898                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1899                         return 0;
1900
1901                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 3.3V regulator output did not became stable\n",
1902                                 mmc_hostname(host->mmc));
1903
1904                 return -EAGAIN;
1905         case MMC_SIGNAL_VOLTAGE_180:
1906                 if (host->vmmc) {
1907                         if (cpu_is_rk3288())
1908                                 ret = io_domain_regulator_set_voltage(
1909                                                         host->vmmc,
1910                                                         1800000, 1800000);
1911                         else
1912                                 ret = regulator_set_voltage(
1913                                                         host->vmmc,
1914                                                         1800000, 1800000);
1915                         /* regulator_put(host->vmmc);//to be done in remove function. */
1916
1917                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1918                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1919                         if (ret) {
1920                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.8V signalling voltage "
1921                                                 " failed\n", mmc_hostname(host->mmc));
1922                                 return -EIO;
1923                         }
1924                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1925                 }
1926
1927                 /*
1928                  * Enable 1.8V Signal Enable in the Host Control2
1929                  * register
1930                  */
1931                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1932
1933                 /* Wait for 5ms */
1934                 usleep_range(5000, 5500);
1935                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__,
1936                                         __FUNCTION__,mmc_hostname(host->mmc));
1937
1938                 /* 1.8V regulator output should be stable within 5 ms */
1939                 uhs_reg = mci_readl(host, UHS_REG);
1940                 if(uhs_reg & SDMMC_UHS_VOLT_REG_18)
1941                         return 0;
1942
1943                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 1.8V regulator output did not became stable\n",
1944                                 mmc_hostname(host->mmc));
1945
1946                 return -EAGAIN;
1947         case MMC_SIGNAL_VOLTAGE_120:
1948                 if (host->vmmc) {
1949                         if (cpu_is_rk3288())
1950                                 ret = io_domain_regulator_set_voltage(
1951                                                         host->vmmc,
1952                                                         1200000, 1200000);
1953                         else
1954                                 ret = regulator_set_voltage(host->vmmc,
1955                                                         1200000, 1200000);
1956                         if (ret) {
1957                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.2V signalling voltage "
1958                                                 " failed\n", mmc_hostname(host->mmc));
1959                                 return -EIO;
1960                         }
1961                 }
1962                 return 0;
1963         default:
1964                 /* No signal voltage switch required */
1965                 return 0;
1966         }
1967 }
1968
1969
1970 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1971         struct mmc_ios *ios)
1972 {
1973         struct dw_mci_slot *slot = mmc_priv(mmc);
1974         struct dw_mci *host = slot->host;
1975         int err;
1976
1977         if (host->verid < DW_MMC_240A)
1978                 return 0;
1979
1980         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1981         return err;
1982 }
1983
1984 #endif
1985
1986 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1987 {
1988         struct dw_mci_slot *slot = mmc_priv(mmc);
1989         struct dw_mci *host = slot->host;
1990         const struct dw_mci_drv_data *drv_data = host->drv_data;
1991         struct dw_mci_tuning_data tuning_data;
1992         int err = -ENOSYS;
1993
1994         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1995         if(cpu_is_rk3036() || cpu_is_rk312x())
1996                 return err;
1997
1998         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1999                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
2000                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
2001                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
2002                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
2003                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
2004                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
2005                 } else {
2006                         return -EINVAL;
2007                 }
2008         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
2009                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
2010                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
2011         } else {
2012                 dev_err(host->dev,
2013                         "Undefined command(%d) for tuning\n", opcode);
2014                 return -EINVAL;
2015         }
2016
2017
2018         /* Recommend sample phase and delayline
2019            Fixme: Mix-use these three controllers will cause
2020            con_id mismatch.
2021          */
2022         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
2023             tuning_data.con_id = 3;
2024         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2025             tuning_data.con_id = 1;
2026         else
2027             tuning_data.con_id = 0;
2028
2029         /* 0: driver, from host->devices
2030            1: sample, from devices->host
2031          */
2032         tuning_data.tuning_type = 1;
2033
2034         if (drv_data && drv_data->execute_tuning)
2035                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
2036
2037         return err;
2038 }
2039
2040 static void dw_mci_post_tmo(struct mmc_host *mmc)
2041 {
2042         struct dw_mci_slot *slot = mmc_priv(mmc);
2043         struct dw_mci *host = slot->host;
2044         host->cur_slot->mrq = NULL;
2045         host->mrq = NULL;
2046         host->state = STATE_IDLE;
2047 }
2048
2049 static const struct mmc_host_ops dw_mci_ops = {
2050         .request                = dw_mci_request,
2051         .pre_req                = dw_mci_pre_req,
2052         .post_req               = dw_mci_post_req,
2053         .set_ios                = dw_mci_set_ios,
2054         .get_ro                 = dw_mci_get_ro,
2055         .get_cd                 = dw_mci_get_cd,
2056         .set_sdio_status    = dw_mci_set_sdio_status,
2057         .hw_reset       = dw_mci_hw_reset,
2058         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
2059         .execute_tuning         = dw_mci_execute_tuning,
2060         .post_tmo               = dw_mci_post_tmo,
2061         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2062         .start_signal_voltage_switch    = dw_mci_start_signal_voltage_switch,
2063         .card_busy  = dw_mci_card_busy,
2064         #endif
2065 };
2066
2067 #if 0
2068 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
2069 {
2070         unsigned long flags;
2071
2072     if(!host)
2073         return;
2074
2075         local_irq_save(flags);
2076         if(host->irq_state != irqflag)
2077         {
2078             host->irq_state = irqflag;
2079             if(irqflag)
2080             {
2081                 enable_irq(host->irq);
2082             }
2083             else
2084             {
2085                 disable_irq(host->irq);
2086             }
2087         }
2088         local_irq_restore(flags);
2089 }
2090 #endif
2091
2092 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2093         __releases(&host->lock)
2094         __acquires(&host->lock)
2095 {
2096         if(DW_MCI_SEND_STATUS == host->dir_status){
2097             #if 0
2098             if( MMC_BUS_TEST_W != host->cmd->opcode){
2099                 if(host->data_status & SDMMC_INT_DCRC)
2100                     host->data->error = -EILSEQ;
2101                 else if(host->data_status & SDMMC_INT_EBE)
2102                     host->data->error = -ETIMEDOUT;
2103             } else {
2104                 dw_mci_wait_unbusy(host);
2105             }
2106             #else
2107             dw_mci_wait_unbusy(host);
2108             #endif
2109         }
2110 }
2111
2112 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2113         __releases(&host->lock)
2114         __acquires(&host->lock)
2115 {
2116         struct dw_mci_slot *slot;
2117         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2118
2119         //WARN_ON(host->cmd || host->data);
2120
2121         dw_mci_deal_data_end(host, mrq);
2122
2123         if(mrq->cmd)
2124                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
2125                         mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
2126         if(mrq->data)
2127                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
2128                         mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
2129
2130         host->cur_slot->mrq = NULL;
2131         host->mrq = NULL;
2132         if (!list_empty(&host->queue)) {
2133                 slot = list_entry(host->queue.next,
2134                                   struct dw_mci_slot, queue_node);
2135                 list_del(&slot->queue_node);
2136                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2137                          mmc_hostname(slot->mmc));
2138                 host->state = STATE_SENDING_CMD;
2139                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
2140                 dw_mci_start_request(host, slot);
2141         } else {
2142                 dev_vdbg(host->dev, "list empty\n");
2143                 host->state = STATE_IDLE;
2144         }
2145
2146         spin_unlock(&host->lock);
2147         mmc_request_done(prev_mmc, mrq);
2148         spin_lock(&host->lock);
2149 }
2150
2151 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2152 {
2153         u32 status = host->cmd_status;
2154
2155         host->cmd_status = 0;
2156
2157         /* Read the response from the card (up to 16 bytes) */
2158         if (cmd->flags & MMC_RSP_PRESENT) {
2159                 if (cmd->flags & MMC_RSP_136) {
2160                         cmd->resp[3] = mci_readl(host, RESP0);
2161                         cmd->resp[2] = mci_readl(host, RESP1);
2162                         cmd->resp[1] = mci_readl(host, RESP2);
2163                         cmd->resp[0] = mci_readl(host, RESP3);
2164
2165             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
2166                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
2167                 } else {
2168                         cmd->resp[0] = mci_readl(host, RESP0);
2169                         cmd->resp[1] = 0;
2170                         cmd->resp[2] = 0;
2171                         cmd->resp[3] = 0;
2172             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
2173                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2174                 }
2175         }
2176
2177         if (status & SDMMC_INT_RTO)
2178         {
2179             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2180                 host->cmd_rto += 1;
2181
2182                 cmd->error = -ETIMEDOUT;
2183         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2184                 cmd->error = -EILSEQ;
2185         }else if (status & SDMMC_INT_RESP_ERR){
2186                 cmd->error = -EIO;
2187         }else{
2188                 cmd->error = 0;
2189         }
2190         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",
2191                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2192
2193         if (cmd->error) {
2194             if(MMC_SEND_STATUS != cmd->opcode)
2195                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2196                         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
2197                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2198                         host->cmd_rto = 0;
2199                 }
2200
2201                 /* newer ip versions need a delay between retries */
2202                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2203                         mdelay(20);
2204         }
2205
2206 }
2207
2208 static void dw_mci_tasklet_func(unsigned long priv)
2209 {
2210         struct dw_mci *host = (struct dw_mci *)priv;
2211         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2212         struct mmc_data *data;
2213         struct mmc_command *cmd;
2214         enum dw_mci_state state;
2215         enum dw_mci_state prev_state;
2216         u32 status, cmd_flags;
2217         unsigned long timeout = 0;
2218         bool ret = true;
2219
2220         spin_lock(&host->lock);
2221
2222         state = host->state;
2223         data = host->data;
2224
2225         do {
2226                 prev_state = state;
2227
2228                 switch (state) {
2229                 case STATE_IDLE:
2230                         break;
2231
2232                 case STATE_SENDING_CMD:
2233                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2234                                                 &host->pending_events))
2235                                 break;
2236
2237                         cmd = host->cmd;
2238                         host->cmd = NULL;
2239                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2240                         dw_mci_command_complete(host, cmd);
2241                         if (cmd == host->mrq->sbc && !cmd->error) {
2242                                 prev_state = state = STATE_SENDING_CMD;
2243                                 __dw_mci_start_request(host, host->cur_slot,
2244                                                        host->mrq->cmd);
2245                                 goto unlock;
2246                         }
2247
2248                         if (cmd->data && cmd->error) {
2249                                 dw_mci_stop_dma(host);
2250                                 #if 1
2251                                 if (data->stop) {
2252                                         send_stop_cmd(host, data);
2253                                         state = STATE_SENDING_STOP;
2254                                         break;
2255                                 }else{
2256                                        /*  host->data = NULL; */
2257                                 }
2258                                 #else
2259                                 send_stop_abort(host, data);
2260                                 state = STATE_SENDING_STOP;
2261                                 break;
2262                                 #endif
2263                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2264                         }
2265
2266                         if (!host->mrq->data || cmd->error) {
2267                                 dw_mci_request_end(host, host->mrq);
2268                                 goto unlock;
2269                         }
2270
2271                         prev_state = state = STATE_SENDING_DATA;
2272                         /* fall through */
2273
2274                 case STATE_SENDING_DATA:
2275                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
2276                                 dw_mci_stop_dma(host);
2277                                 #if 1
2278                                 if (data->stop){
2279                                         send_stop_cmd(host, data);
2280                                 }else{
2281                                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
2282                                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
2283                                                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
2284
2285                                         mci_writel(host, CMDARG, 0);
2286                                         wmb();
2287                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
2288                                                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2289
2290                                         if(host->mmc->hold_reg_flag)
2291                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2292
2293                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2294                                         wmb();
2295                                         timeout = jiffies + msecs_to_jiffies(500);
2296
2297                                         while(ret){
2298                                                 ret = time_before(jiffies, timeout);
2299                                                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2300                                                         break;
2301                                         }
2302                                         if(false == ret)
2303                                                 MMC_DBG_ERR_FUNC(host->mmc,
2304                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2305                                                         __func__, mmc_hostname(host->mmc));
2306                                 }
2307                                 #else
2308                                 send_stop_abort(host, data);
2309                                 #endif
2310                                 state = STATE_DATA_ERROR;
2311                                 break;
2312                         }
2313
2314                         MMC_DBG_CMD_FUNC(host->mmc,
2315                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
2316                         prev_state,state, mmc_hostname(host->mmc));
2317
2318                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2319                                                 &host->pending_events))
2320                                 break;
2321                         MMC_DBG_INFO_FUNC(host->mmc,
2322                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
2323                                           prev_state,state,mmc_hostname(host->mmc));
2324
2325                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2326                         prev_state = state = STATE_DATA_BUSY;
2327                         /* fall through */
2328
2329                 case STATE_DATA_BUSY:
2330                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2331                                                 &host->pending_events))
2332                                 break;
2333
2334                         dw_mci_deal_data_end(host, host->mrq);
2335                         MMC_DBG_INFO_FUNC(host->mmc,
2336                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
2337                                           prev_state,state,mmc_hostname(host->mmc));
2338
2339                         /* host->data = NULL; */
2340                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2341                         status = host->data_status;
2342
2343                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2344                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2345                                 MMC_DBG_ERR_FUNC(host->mmc,
2346                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
2347                             prev_state,state, status, mmc_hostname(host->mmc));
2348
2349                         if (status & SDMMC_INT_DRTO) {
2350                                         data->error = -ETIMEDOUT;
2351                                 } else if (status & SDMMC_INT_DCRC) {
2352                                         data->error = -EILSEQ;
2353                                 } else if (status & SDMMC_INT_EBE &&
2354                                 host->dir_status == DW_MCI_SEND_STATUS){
2355                                         /*
2356                                          * No data CRC status was returned.
2357                                          * The number of bytes transferred will
2358                                          * be exaggerated in PIO mode.
2359                                          */
2360                                         data->bytes_xfered = 0;
2361                                         data->error = -ETIMEDOUT;
2362                                 } else {
2363                                         dev_err(host->dev,
2364                                                 "data FIFO error "
2365                                                 "(status=%08x)\n",
2366                                                 status);
2367                                         data->error = -EIO;
2368                                 }
2369                                 /*
2370                                  * After an error, there may be data lingering
2371                                  * in the FIFO, so reset it - doing so
2372                                  * generates a block interrupt, hence setting
2373                                  * the scatter-gather pointer to NULL.
2374                                  */
2375                                 dw_mci_fifo_reset(host);
2376                         } else {
2377                                 data->bytes_xfered = data->blocks * data->blksz;
2378                                 data->error = 0;
2379                         }
2380
2381                         if (!data->stop) {
2382                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2383                                       prev_state,state,mmc_hostname(host->mmc));
2384                                 dw_mci_request_end(host, host->mrq);
2385                                 goto unlock;
2386                         }
2387                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2388                                                 prev_state,state,mmc_hostname(host->mmc));
2389
2390                         if (host->mrq->sbc && !data->error) {
2391                                 data->stop->error = 0;
2392
2393                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2394                                                 prev_state,state,mmc_hostname(host->mmc));
2395
2396                                 dw_mci_request_end(host, host->mrq);
2397                                 goto unlock;
2398                         }
2399
2400                         prev_state = state = STATE_SENDING_STOP;
2401                         if (!data->error)
2402                             send_stop_cmd(host, data);
2403                         #if 0
2404                         if (data->stop && !data->error) {
2405                                 /* stop command for open-ended transfer*/
2406
2407                                 send_stop_abort(host, data);
2408                         }
2409                         #endif
2410                         /* fall through */
2411                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2412                                                 prev_state,state,mmc_hostname(host->mmc));
2413
2414                 case STATE_SENDING_STOP:
2415                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2416                                 break;
2417
2418                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2419                                                 prev_state, state, mmc_hostname(host->mmc));
2420
2421                         /* CMD error in data command */
2422                         if (host->mrq->cmd->error && host->mrq->data) {
2423                                 dw_mci_fifo_reset(host);
2424                         }
2425
2426                         /*host->cmd = NULL;
2427                         host->data = NULL; */
2428                         #if 1
2429                         dw_mci_command_complete(host, host->mrq->stop);
2430                         #else
2431                         if (host->mrq->stop)
2432                                 dw_mci_command_complete(host, host->mrq->stop);
2433                         else
2434                                 host->cmd_status = 0;
2435                         #endif
2436
2437                         dw_mci_request_end(host, host->mrq);
2438                         goto unlock;
2439
2440                 case STATE_DATA_ERROR:
2441                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2442                                                 &host->pending_events))
2443                                 break;
2444
2445                         state = STATE_DATA_BUSY;
2446                         break;
2447                 }
2448         } while (state != prev_state);
2449
2450         host->state = state;
2451 unlock:
2452         spin_unlock(&host->lock);
2453
2454 }
2455
2456 /* push final bytes to part_buf, only use during push */
2457 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2458 {
2459         memcpy((void *)&host->part_buf, buf, cnt);
2460         host->part_buf_count = cnt;
2461 }
2462
2463 /* append bytes to part_buf, only use during push */
2464 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2465 {
2466         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2467         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2468         host->part_buf_count += cnt;
2469         return cnt;
2470 }
2471
2472 /* pull first bytes from part_buf, only use during pull */
2473 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2474 {
2475         cnt = min(cnt, (int)host->part_buf_count);
2476         if (cnt) {
2477                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2478                        cnt);
2479                 host->part_buf_count -= cnt;
2480                 host->part_buf_start += cnt;
2481         }
2482         return cnt;
2483 }
2484
2485 /* pull final bytes from the part_buf, assuming it's just been filled */
2486 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2487 {
2488         memcpy(buf, &host->part_buf, cnt);
2489         host->part_buf_start = cnt;
2490         host->part_buf_count = (1 << host->data_shift) - cnt;
2491 }
2492
2493 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2494 {
2495         struct mmc_data *data = host->data;
2496         int init_cnt = cnt;
2497
2498         /* try and push anything in the part_buf */
2499         if (unlikely(host->part_buf_count)) {
2500                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2501                 buf += len;
2502                 cnt -= len;
2503                 if (host->part_buf_count == 2) {
2504                         mci_writew(host, DATA(host->data_offset),
2505                                         host->part_buf16);
2506                         host->part_buf_count = 0;
2507                 }
2508         }
2509 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2510         if (unlikely((unsigned long)buf & 0x1)) {
2511                 while (cnt >= 2) {
2512                         u16 aligned_buf[64];
2513                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2514                         int items = len >> 1;
2515                         int i;
2516                         /* memcpy from input buffer into aligned buffer */
2517                         memcpy(aligned_buf, buf, len);
2518                         buf += len;
2519                         cnt -= len;
2520                         /* push data from aligned buffer into fifo */
2521                         for (i = 0; i < items; ++i)
2522                                 mci_writew(host, DATA(host->data_offset),
2523                                                 aligned_buf[i]);
2524                 }
2525         } else
2526 #endif
2527         {
2528                 u16 *pdata = buf;
2529                 for (; cnt >= 2; cnt -= 2)
2530                         mci_writew(host, DATA(host->data_offset), *pdata++);
2531                 buf = pdata;
2532         }
2533         /* put anything remaining in the part_buf */
2534         if (cnt) {
2535                 dw_mci_set_part_bytes(host, buf, cnt);
2536                  /* Push data if we have reached the expected data length */
2537                 if ((data->bytes_xfered + init_cnt) ==
2538                     (data->blksz * data->blocks))
2539                         mci_writew(host, DATA(host->data_offset),
2540                                    host->part_buf16);
2541         }
2542 }
2543
2544 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2545 {
2546 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2547         if (unlikely((unsigned long)buf & 0x1)) {
2548                 while (cnt >= 2) {
2549                         /* pull data from fifo into aligned buffer */
2550                         u16 aligned_buf[64];
2551                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2552                         int items = len >> 1;
2553                         int i;
2554                         for (i = 0; i < items; ++i)
2555                                 aligned_buf[i] = mci_readw(host,
2556                                                 DATA(host->data_offset));
2557                         /* memcpy from aligned buffer into output buffer */
2558                         memcpy(buf, aligned_buf, len);
2559                         buf += len;
2560                         cnt -= len;
2561                 }
2562         } else
2563 #endif
2564         {
2565                 u16 *pdata = buf;
2566                 for (; cnt >= 2; cnt -= 2)
2567                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2568                 buf = pdata;
2569         }
2570         if (cnt) {
2571                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2572                 dw_mci_pull_final_bytes(host, buf, cnt);
2573         }
2574 }
2575
2576 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2577 {
2578         struct mmc_data *data = host->data;
2579         int init_cnt = cnt;
2580
2581         /* try and push anything in the part_buf */
2582         if (unlikely(host->part_buf_count)) {
2583                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2584                 buf += len;
2585                 cnt -= len;
2586                 if (host->part_buf_count == 4) {
2587                         mci_writel(host, DATA(host->data_offset),
2588                                         host->part_buf32);
2589                         host->part_buf_count = 0;
2590                 }
2591         }
2592 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2593         if (unlikely((unsigned long)buf & 0x3)) {
2594                 while (cnt >= 4) {
2595                         u32 aligned_buf[32];
2596                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2597                         int items = len >> 2;
2598                         int i;
2599                         /* memcpy from input buffer into aligned buffer */
2600                         memcpy(aligned_buf, buf, len);
2601                         buf += len;
2602                         cnt -= len;
2603                         /* push data from aligned buffer into fifo */
2604                         for (i = 0; i < items; ++i)
2605                                 mci_writel(host, DATA(host->data_offset),
2606                                                 aligned_buf[i]);
2607                 }
2608         } else
2609 #endif
2610         {
2611                 u32 *pdata = buf;
2612                 for (; cnt >= 4; cnt -= 4)
2613                         mci_writel(host, DATA(host->data_offset), *pdata++);
2614                 buf = pdata;
2615         }
2616         /* put anything remaining in the part_buf */
2617         if (cnt) {
2618                 dw_mci_set_part_bytes(host, buf, cnt);
2619                  /* Push data if we have reached the expected data length */
2620                 if ((data->bytes_xfered + init_cnt) ==
2621                     (data->blksz * data->blocks))
2622                         mci_writel(host, DATA(host->data_offset),
2623                                    host->part_buf32);
2624         }
2625 }
2626
2627 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2628 {
2629 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2630         if (unlikely((unsigned long)buf & 0x3)) {
2631                 while (cnt >= 4) {
2632                         /* pull data from fifo into aligned buffer */
2633                         u32 aligned_buf[32];
2634                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2635                         int items = len >> 2;
2636                         int i;
2637                         for (i = 0; i < items; ++i)
2638                                 aligned_buf[i] = mci_readl(host,
2639                                                 DATA(host->data_offset));
2640                         /* memcpy from aligned buffer into output buffer */
2641                         memcpy(buf, aligned_buf, len);
2642                         buf += len;
2643                         cnt -= len;
2644                 }
2645         } else
2646 #endif
2647         {
2648                 u32 *pdata = buf;
2649                 for (; cnt >= 4; cnt -= 4)
2650                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2651                 buf = pdata;
2652         }
2653         if (cnt) {
2654                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2655                 dw_mci_pull_final_bytes(host, buf, cnt);
2656         }
2657 }
2658
2659 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2660 {
2661         struct mmc_data *data = host->data;
2662         int init_cnt = cnt;
2663
2664         /* try and push anything in the part_buf */
2665         if (unlikely(host->part_buf_count)) {
2666                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2667                 buf += len;
2668                 cnt -= len;
2669
2670                 if (host->part_buf_count == 8) {
2671                         mci_writeq(host, DATA(host->data_offset),
2672                                         host->part_buf);
2673                         host->part_buf_count = 0;
2674                 }
2675         }
2676 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2677         if (unlikely((unsigned long)buf & 0x7)) {
2678                 while (cnt >= 8) {
2679                         u64 aligned_buf[16];
2680                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2681                         int items = len >> 3;
2682                         int i;
2683                         /* memcpy from input buffer into aligned buffer */
2684                         memcpy(aligned_buf, buf, len);
2685                         buf += len;
2686                         cnt -= len;
2687                         /* push data from aligned buffer into fifo */
2688                         for (i = 0; i < items; ++i)
2689                                 mci_writeq(host, DATA(host->data_offset),
2690                                                 aligned_buf[i]);
2691                 }
2692         } else
2693 #endif
2694         {
2695                 u64 *pdata = buf;
2696                 for (; cnt >= 8; cnt -= 8)
2697                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2698                 buf = pdata;
2699         }
2700         /* put anything remaining in the part_buf */
2701         if (cnt) {
2702                 dw_mci_set_part_bytes(host, buf, cnt);
2703                 /* Push data if we have reached the expected data length */
2704                 if ((data->bytes_xfered + init_cnt) ==
2705                     (data->blksz * data->blocks))
2706                         mci_writeq(host, DATA(host->data_offset),
2707                                    host->part_buf);
2708         }
2709 }
2710
2711 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2712 {
2713 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2714         if (unlikely((unsigned long)buf & 0x7)) {
2715                 while (cnt >= 8) {
2716                         /* pull data from fifo into aligned buffer */
2717                         u64 aligned_buf[16];
2718                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2719                         int items = len >> 3;
2720                         int i;
2721                         for (i = 0; i < items; ++i)
2722                                 aligned_buf[i] = mci_readq(host,
2723                                                 DATA(host->data_offset));
2724                         /* memcpy from aligned buffer into output buffer */
2725                         memcpy(buf, aligned_buf, len);
2726                         buf += len;
2727                         cnt -= len;
2728                 }
2729         } else
2730 #endif
2731         {
2732                 u64 *pdata = buf;
2733                 for (; cnt >= 8; cnt -= 8)
2734                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2735                 buf = pdata;
2736         }
2737         if (cnt) {
2738                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2739                 dw_mci_pull_final_bytes(host, buf, cnt);
2740         }
2741 }
2742
2743 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2744 {
2745         int len;
2746
2747         /* get remaining partial bytes */
2748         len = dw_mci_pull_part_bytes(host, buf, cnt);
2749         if (unlikely(len == cnt))
2750                 return;
2751         buf += len;
2752         cnt -= len;
2753
2754         /* get the rest of the data */
2755         host->pull_data(host, buf, cnt);
2756 }
2757
2758 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2759 {
2760         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2761         void *buf;
2762         unsigned int offset;
2763         struct mmc_data *data = host->data;
2764         int shift = host->data_shift;
2765         u32 status;
2766         unsigned int len;
2767         unsigned int remain, fcnt;
2768
2769         if(!host->mmc->bus_refs){
2770                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2771                 goto host_put;
2772         }
2773         do {
2774                 if (!sg_miter_next(sg_miter))
2775                         goto done;
2776
2777                 host->sg = sg_miter->piter.sg;
2778                 buf = sg_miter->addr;
2779                 remain = sg_miter->length;
2780                 offset = 0;
2781
2782                 do {
2783                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2784                                         << shift) + host->part_buf_count;
2785                         len = min(remain, fcnt);
2786                         if (!len)
2787                                 break;
2788                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2789                         data->bytes_xfered += len;
2790                         offset += len;
2791                         remain -= len;
2792                 } while (remain);
2793
2794                 sg_miter->consumed = offset;
2795                 status = mci_readl(host, MINTSTS);
2796                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2797         /* if the RXDR is ready read again */
2798         } while ((status & SDMMC_INT_RXDR) ||
2799                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2800
2801         if (!remain) {
2802                 if (!sg_miter_next(sg_miter))
2803                         goto done;
2804                 sg_miter->consumed = 0;
2805         }
2806         sg_miter_stop(sg_miter);
2807         return;
2808
2809 done:
2810         sg_miter_stop(sg_miter);
2811 host_put:
2812         host->sg = NULL;
2813         smp_wmb();
2814         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2815 }
2816
2817 static void dw_mci_write_data_pio(struct dw_mci *host)
2818 {
2819         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2820         void *buf;
2821         unsigned int offset;
2822         struct mmc_data *data = host->data;
2823         int shift = host->data_shift;
2824         u32 status;
2825         unsigned int len;
2826         unsigned int fifo_depth = host->fifo_depth;
2827         unsigned int remain, fcnt;
2828
2829         if(!host->mmc->bus_refs){
2830                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2831                 goto host_put;
2832         }
2833
2834         do {
2835                 if (!sg_miter_next(sg_miter))
2836                         goto done;
2837
2838                 host->sg = sg_miter->piter.sg;
2839                 buf = sg_miter->addr;
2840                 remain = sg_miter->length;
2841                 offset = 0;
2842
2843                 do {
2844                         fcnt = ((fifo_depth -
2845                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2846                                         << shift) - host->part_buf_count;
2847                         len = min(remain, fcnt);
2848                         if (!len)
2849                                 break;
2850                         host->push_data(host, (void *)(buf + offset), len);
2851                         data->bytes_xfered += len;
2852                         offset += len;
2853                         remain -= len;
2854                 } while (remain);
2855
2856                 sg_miter->consumed = offset;
2857                 status = mci_readl(host, MINTSTS);
2858                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2859         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2860
2861         if (!remain) {
2862                 if (!sg_miter_next(sg_miter))
2863                         goto done;
2864                 sg_miter->consumed = 0;
2865         }
2866         sg_miter_stop(sg_miter);
2867         return;
2868
2869 done:
2870         sg_miter_stop(sg_miter);
2871 host_put:
2872         host->sg = NULL;
2873         smp_wmb();
2874         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2875 }
2876
2877 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2878 {
2879         if (!host->cmd_status)
2880             host->cmd_status = status;
2881
2882         if (!host->cmd)
2883                 goto cmd_exit;
2884
2885 cmd_exit:
2886         smp_wmb();
2887         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2888         tasklet_schedule(&host->tasklet);
2889 }
2890
2891 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2892 {
2893         struct dw_mci *host = dev_id;
2894         u32 pending, sdio_int;
2895         int i;
2896
2897         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2898
2899         /*
2900         * DTO fix - version 2.10a and below, and only if internal DMA
2901         * is configured.
2902         */
2903         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2904                         if (!pending &&
2905                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2906                                 pending |= SDMMC_INT_DATA_OVER;
2907         }
2908
2909         if (pending) {
2910                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2911                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2912                         host->cmd_status = pending;
2913                         smp_wmb();
2914                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
2915                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
2916
2917                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2918                 }
2919
2920                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2921                         /* if there is an error report DATA_ERROR */
2922                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2923                         host->data_status = pending;
2924                         smp_wmb();
2925                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2926
2927                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
2928                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
2929                         tasklet_schedule(&host->tasklet);
2930                 }
2931
2932                 if (pending & SDMMC_INT_DATA_OVER) {
2933                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2934                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2935                         if (!host->data_status)
2936                                 host->data_status = pending;
2937                         smp_wmb();
2938                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2939                                 if (host->sg != NULL)
2940                                         dw_mci_read_data_pio(host, true);
2941                         }
2942                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2943                         tasklet_schedule(&host->tasklet);
2944                 }
2945
2946                 if (pending & SDMMC_INT_RXDR) {
2947                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2948                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2949                                 dw_mci_read_data_pio(host, false);
2950                 }
2951
2952                 if (pending & SDMMC_INT_TXDR) {
2953                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2954                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2955                                 dw_mci_write_data_pio(host);
2956                 }
2957
2958                 if (pending & SDMMC_INT_VSI) {
2959                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2960                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2961                         dw_mci_cmd_interrupt(host, pending);
2962                 }
2963
2964                 if (pending & SDMMC_INT_CMD_DONE) {
2965                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
2966                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2967                         dw_mci_cmd_interrupt(host, pending);
2968                 }
2969
2970                 if (pending & SDMMC_INT_CD) {
2971                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2972                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
2973                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2974                         queue_work(host->card_workqueue, &host->card_work);
2975                 }
2976
2977                 if (pending & SDMMC_INT_HLE) {
2978                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2979                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
2980
2981                 }
2982
2983                 /* Handle SDIO Interrupts */
2984                 for (i = 0; i < host->num_slots; i++) {
2985                         struct dw_mci_slot *slot = host->slot[i];
2986
2987                         if (host->verid < DW_MMC_240A)
2988                                 sdio_int = SDMMC_INT_SDIO(i);
2989                         else
2990                                 sdio_int = SDMMC_INT_SDIO(i + 8);
2991
2992                         if (pending & sdio_int) {
2993                                 mci_writel(host, RINTSTS, sdio_int);
2994                                 mmc_signal_sdio_irq(slot->mmc);
2995                         }
2996                 }
2997
2998         }
2999
3000 #ifdef CONFIG_MMC_DW_IDMAC
3001         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3002         if(!(cpu_is_rk3036() || cpu_is_rk312x())){
3003                 /* Handle DMA interrupts */
3004                 pending = mci_readl(host, IDSTS);
3005                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3006                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3007                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3008                         host->dma_ops->complete((void *)host);
3009                 }
3010         }
3011 #endif
3012
3013         return IRQ_HANDLED;
3014 }
3015
3016 static void dw_mci_work_routine_card(struct work_struct *work)
3017 {
3018         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3019         int i;
3020
3021         for (i = 0; i < host->num_slots; i++) {
3022                 struct dw_mci_slot *slot = host->slot[i];
3023                 struct mmc_host *mmc = slot->mmc;
3024                 struct mmc_request *mrq;
3025                 int present;
3026
3027                 present = dw_mci_get_cd(mmc);
3028
3029                 /* Card insert, switch data line to uart function, and vice verse.
3030             eONLY audi chip need switched by software, using udbg tag in dts!
3031                  */
3032                 if (!(IS_ERR(host->pins_udbg)) && !(IS_ERR(host->pins_default))) {
3033                          if (present) {
3034                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3035                                         dev_err(host->dev, "%s: Default pinctrl setting failed!\n",
3036                                                 mmc_hostname(host->mmc));
3037                          } else {
3038                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3039                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3040                                                 mmc_hostname(host->mmc));
3041                         }
3042                 }
3043
3044                 while (present != slot->last_detect_state) {
3045                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
3046                                 present ? "inserted" : "removed");
3047                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
3048                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
3049
3050                         dw_mci_ctrl_all_reset(host);
3051                         /* Stop edma when rountine card triggered */
3052                         if(cpu_is_rk3036() || cpu_is_rk312x())
3053                                 if(host->dma_ops && host->dma_ops->stop)
3054                                         host->dma_ops->stop(host);
3055                         rk_send_wakeup_key();//wake up system
3056                         spin_lock_bh(&host->lock);
3057
3058                         /* Card change detected */
3059                         slot->last_detect_state = present;
3060
3061                         /* Clean up queue if present */
3062                         mrq = slot->mrq;
3063                         if (mrq) {
3064                                 if (mrq == host->mrq) {
3065                                         host->data = NULL;
3066                                         host->cmd = NULL;
3067
3068                                         switch (host->state) {
3069                                         case STATE_IDLE:
3070                                                 break;
3071                                         case STATE_SENDING_CMD:
3072                                                 mrq->cmd->error = -ENOMEDIUM;
3073                                                 if (!mrq->data)
3074                                                         break;
3075                                                 /* fall through */
3076                                         case STATE_SENDING_DATA:
3077                                                 mrq->data->error = -ENOMEDIUM;
3078                                                 dw_mci_stop_dma(host);
3079                                                 break;
3080                                         case STATE_DATA_BUSY:
3081                                         case STATE_DATA_ERROR:
3082                                                 if (mrq->data->error == -EINPROGRESS)
3083                                                         mrq->data->error = -ENOMEDIUM;
3084                                                 if (!mrq->stop)
3085                                                         break;
3086                                                 /* fall through */
3087                                         case STATE_SENDING_STOP:
3088                                                 mrq->stop->error = -ENOMEDIUM;
3089                                                 break;
3090                                         }
3091
3092                                         dw_mci_request_end(host, mrq);
3093                                 } else {
3094                                         list_del(&slot->queue_node);
3095                                         mrq->cmd->error = -ENOMEDIUM;
3096                                         if (mrq->data)
3097                                                 mrq->data->error = -ENOMEDIUM;
3098                                         if (mrq->stop)
3099                                                 mrq->stop->error = -ENOMEDIUM;
3100
3101                                         MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",
3102                                                         mrq->cmd->opcode, mmc_hostname(mmc));
3103
3104                                         spin_unlock(&host->lock);
3105                                         mmc_request_done(slot->mmc, mrq);
3106                                         spin_lock(&host->lock);
3107                                 }
3108                         }
3109
3110                         /* Power down slot */
3111                         if (present == 0) {
3112                                 /* Clear down the FIFO */
3113                                 dw_mci_fifo_reset(host);
3114 #ifdef CONFIG_MMC_DW_IDMAC
3115                                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3116                                         dw_mci_idmac_reset(host);
3117 #endif
3118
3119                         }
3120
3121                         spin_unlock_bh(&host->lock);
3122
3123                         present = dw_mci_get_cd(mmc);
3124                 }
3125
3126                 mmc_detect_change(slot->mmc,
3127                 msecs_to_jiffies(host->pdata->detect_delay_ms));
3128         }
3129 }
3130
3131 #ifdef CONFIG_OF
3132 /* given a slot id, find out the device node representing that slot */
3133 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3134 {
3135         struct device_node *np;
3136         const __be32 *addr;
3137         int len;
3138
3139         if (!dev || !dev->of_node)
3140                 return NULL;
3141
3142         for_each_child_of_node(dev->of_node, np) {
3143                 addr = of_get_property(np, "reg", &len);
3144                 if (!addr || (len < sizeof(int)))
3145                         continue;
3146                 if (be32_to_cpup(addr) == slot)
3147                         return np;
3148         }
3149         return NULL;
3150 }
3151
3152 static struct dw_mci_of_slot_quirks {
3153         char *quirk;
3154         int id;
3155 } of_slot_quirks[] = {
3156         {
3157                 .quirk  = "disable-wp",
3158                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3159         },
3160 };
3161
3162 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3163 {
3164         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3165         int quirks = 0;
3166         int idx;
3167
3168         /* get quirks */
3169         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3170                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3171                         quirks |= of_slot_quirks[idx].id;
3172
3173         return quirks;
3174 }
3175
3176 /* find out bus-width for a given slot */
3177 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3178 {
3179         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3180         u32 bus_wd = 1;
3181
3182         if (!np)
3183                 return 1;
3184
3185         if (of_property_read_u32(np, "bus-width", &bus_wd))
3186                 dev_err(dev, "bus-width property not found, assuming width"
3187                                " as 1\n");
3188         return bus_wd;
3189 }
3190
3191
3192 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3193 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3194 {
3195         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3196         int gpio;
3197
3198         if (!np)
3199                 return -EINVAL;
3200
3201         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3202
3203         /* Having a missing entry is valid; return silently */
3204         if (!gpio_is_valid(gpio))
3205                 return -EINVAL;
3206
3207         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3208                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3209                 return -EINVAL;
3210         }
3211
3212     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3213
3214         return gpio;
3215 }
3216
3217
3218 /* find the write protect gpio for a given slot; or -1 if none specified */
3219 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3220 {
3221         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3222         int gpio;
3223
3224         if (!np)
3225                 return -EINVAL;
3226
3227         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3228
3229         /* Having a missing entry is valid; return silently */
3230         if (!gpio_is_valid(gpio))
3231                 return -EINVAL;
3232
3233         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3234                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3235                 return -EINVAL;
3236         }
3237
3238         return gpio;
3239 }
3240
3241 /* find the cd gpio for a given slot */
3242 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3243                                         struct mmc_host *mmc)
3244 {
3245         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3246         int gpio;
3247
3248         if (!np)
3249                 return;
3250
3251         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3252
3253         /* Having a missing entry is valid; return silently */
3254         if (!gpio_is_valid(gpio))
3255                 return;
3256
3257         if (mmc_gpio_request_cd(mmc, gpio, 0))
3258                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3259 }
3260
3261 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3262 {
3263         struct mmc_host *mmc = dev_id;
3264         struct dw_mci_slot *slot = mmc_priv(mmc);
3265         struct dw_mci *host = slot->host;
3266         int gpio_cd = slot->cd_gpio;
3267
3268         (gpio_get_value(gpio_cd)  == 0) ?
3269                 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
3270                 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3271
3272         /* wakeup system whether gpio debounce or not */
3273         rk_send_wakeup_key();
3274
3275         /* no need to trigger detect flow when rescan is disabled.
3276            This case happended in dpm, that we just wakeup system and
3277            let suspend_post notify callback handle it.
3278          */
3279         if(mmc->rescan_disable == 0)
3280                 queue_work(host->card_workqueue, &host->card_work);
3281         else
3282                 printk("%s: rescan been disabled!\n", __FUNCTION__);
3283
3284         return IRQ_HANDLED;
3285 }
3286
3287 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3288                                         struct mmc_host *mmc)
3289 {
3290         struct dw_mci_slot *slot = mmc_priv(mmc);
3291         struct dw_mci *host = slot->host;
3292         int irq;
3293         int ret;
3294
3295         /* Having a missing entry is valid; return silently */
3296         if (!gpio_is_valid(gpio))
3297                 return;
3298
3299         irq = gpio_to_irq(gpio);
3300         if (irq >= 0) {
3301                 ret = devm_request_threaded_irq(&mmc->class_dev, irq,
3302                                                 NULL, dw_mci_gpio_cd_irqt,
3303                                                 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3304                                                 "dw_mci_cd", mmc);
3305                 if (ret < 0) {
3306                         irq = ret;
3307                         dev_err(host->dev, "Request cd-gpio %d interrupt error!\n", gpio);
3308                 } else{
3309                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3310                         enable_irq_wake(irq);
3311                 }
3312         } else {
3313                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3314         }
3315 }
3316
3317 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3318                                         struct mmc_host *mmc)
3319 {
3320         if (!gpio_is_valid(gpio))
3321                 return;
3322
3323         if (gpio_to_irq(gpio) >= 0) {
3324                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3325                 devm_gpio_free(&mmc->class_dev, gpio);
3326         }
3327 }
3328 #else /* CONFIG_OF */
3329 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3330 {
3331         return 0;
3332 }
3333 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3334 {
3335         return 1;
3336 }
3337 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3338 {
3339         return NULL;
3340 }
3341 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3342 {
3343         return -EINVAL;
3344 }
3345 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3346                                         struct mmc_host *mmc)
3347 {
3348         return;
3349 }
3350 #endif /* CONFIG_OF */
3351
3352 /* @host: dw_mci host prvdata
3353  * Init pinctrl for each platform. Usually we assign
3354  * "defalut" tag for functional usage, "idle" tag for gpio
3355  * state and "udbg" tag for uart_dbg if any.
3356  */
3357 static void dw_mci_init_pinctrl(struct dw_mci *host)
3358 {
3359         /* Fixme: DON'T TOUCH EMMC SETTING! */
3360         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3361                 return;
3362
3363         /* Get pinctrl for DTS */
3364         host->pinctrl = devm_pinctrl_get(host->dev);
3365         if (IS_ERR(host->pinctrl)) {
3366                 dev_err(host->dev, "%s: No pinctrl used!\n",
3367                         mmc_hostname(host->mmc));
3368                 return;
3369         }
3370
3371         /* Lookup idle state */
3372         host->pins_idle = pinctrl_lookup_state(host->pinctrl,
3373                                                 PINCTRL_STATE_IDLE);
3374         if (IS_ERR(host->pins_idle)) {
3375                 dev_err(host->dev, "%s: No idle tag found!\n",
3376                         mmc_hostname(host->mmc));
3377         } else {
3378                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3379                         dev_err(host->dev, "%s: Idle pinctrl setting failed!\n",
3380                                 mmc_hostname(host->mmc));
3381         }
3382
3383         /* Lookup default state */
3384         host->pins_default = pinctrl_lookup_state(host->pinctrl,
3385                                                         PINCTRL_STATE_DEFAULT);
3386         if (IS_ERR(host->pins_default)) {
3387                 dev_err(host->dev, "%s: No default pinctrl found!\n",
3388                         mmc_hostname(host->mmc));
3389         } else {
3390                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3391                         dev_err(host->dev, "%s:  Default pinctrl setting failed!\n",
3392                                 mmc_hostname(host->mmc));
3393         }
3394
3395         /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3396         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3397                 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3398                 if (IS_ERR(host->pins_udbg)) {
3399                         dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3400                                         mmc_hostname(host->mmc));
3401                 } else {
3402                         if (!dw_mci_get_cd(host->mmc))
3403                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3404                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3405                                                 mmc_hostname(host->mmc));
3406                 }
3407         }
3408 }
3409
3410 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3411                                         unsigned long mode, void *unused)
3412 {
3413         struct mmc_host *host = container_of(
3414                 notify_block, struct mmc_host, pm_notify);
3415         unsigned long flags;
3416
3417         switch (mode) {
3418         case PM_HIBERNATION_PREPARE:
3419         case PM_SUSPEND_PREPARE:
3420                 dev_err(host->parent, "dw_mci_pm_notify:  suspend prepare\n");
3421                 spin_lock_irqsave(&host->lock, flags);
3422                 host->rescan_disable = 1;
3423                 spin_unlock_irqrestore(&host->lock, flags);
3424                 if (cancel_delayed_work(&host->detect))
3425                         wake_unlock(&host->detect_wake_lock);
3426                 break;
3427
3428         case PM_POST_SUSPEND:
3429         case PM_POST_HIBERNATION:
3430         case PM_POST_RESTORE:
3431                 dev_err(host->parent, "dw_mci_pm_notify:  post suspend\n");
3432                 spin_lock_irqsave(&host->lock, flags);
3433                 host->rescan_disable = 0;
3434                 spin_unlock_irqrestore(&host->lock, flags);
3435                 mmc_detect_change(host, 10);
3436         }
3437
3438         return 0;
3439 }
3440
3441 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3442 {
3443         struct mmc_host *mmc;
3444         struct dw_mci_slot *slot;
3445         const struct dw_mci_drv_data *drv_data = host->drv_data;
3446         int ctrl_id, ret;
3447         u32 freq[2];
3448         u8 bus_width;
3449
3450         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3451         if (!mmc)
3452                 return -ENOMEM;
3453
3454         slot = mmc_priv(mmc);
3455         slot->id = id;
3456         slot->mmc = mmc;
3457         slot->host = host;
3458         host->slot[id] = slot;
3459         host->mmc = mmc;
3460
3461         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3462
3463         mmc->ops = &dw_mci_ops;
3464
3465         if (of_property_read_u32_array(host->dev->of_node,
3466                                        "clock-freq-min-max", freq, 2)) {
3467                 mmc->f_min = DW_MCI_FREQ_MIN;
3468                 mmc->f_max = DW_MCI_FREQ_MAX;
3469
3470                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3471                         mmc->f_min, mmc->f_max, mmc_hostname(mmc));
3472         } else {
3473                 mmc->f_min = freq[0];
3474                 mmc->f_max = freq[1];
3475
3476                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3477                         mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
3478         }
3479
3480         printk("%s : Rockchip specific MHSC: %s\n", mmc_hostname(mmc), RK_SDMMC_DRIVER_VERSION);
3481
3482         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3483                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3484         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3485                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3486         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3487                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3488
3489         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3490                 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3491                 if (register_pm_notifier(&mmc->pm_notify)) {
3492                         printk(KERN_ERR "dw_mci: register_pm_notifier failed\n");
3493                         goto err_pm_notifier;
3494                 }
3495         }
3496
3497         if (host->cid == DW_MCI_TYPE_RK3368) {
3498                 if (IS_ERR(host->grf))
3499                         pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3500                 else
3501                         /* Disable force_jtag */
3502                         regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3503         } else if (cpu_is_rk3288()) {
3504                 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3505         }
3506
3507
3508         /* We assume only low-level chip use gpio_cd */
3509         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3510                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3511                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3512                 if (gpio_is_valid(slot->cd_gpio)) {
3513                         /* Request gpio int for card detection */
3514                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3515                 } else {
3516                         slot->cd_gpio = -ENODEV;
3517                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3518                 }
3519         }
3520
3521         if (host->pdata->get_ocr)
3522                 mmc->ocr_avail = host->pdata->get_ocr(id);
3523         else
3524         {
3525                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
3526                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
3527                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
3528                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
3529         }
3530
3531         /*
3532          * Start with slot power disabled, it will be enabled when a card
3533          * is detected.
3534          */
3535         if (host->pdata->setpower)
3536                 host->pdata->setpower(id, 0);
3537
3538         if (host->pdata->caps)
3539                 mmc->caps = host->pdata->caps;
3540
3541         if (host->pdata->pm_caps)
3542                 mmc->pm_caps = host->pdata->pm_caps;
3543
3544         if (host->dev->of_node) {
3545                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3546                 if (ctrl_id < 0)
3547                         ctrl_id = 0;
3548         } else {
3549                 ctrl_id = to_platform_device(host->dev)->id;
3550         }
3551         if (drv_data && drv_data->caps)
3552                 mmc->caps |= drv_data->caps[ctrl_id];
3553         if (drv_data && drv_data->hold_reg_flag)
3554                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3555
3556         /* set the compatibility of driver. */
3557         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3558                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3559
3560         if (host->pdata->caps2)
3561                 mmc->caps2 = host->pdata->caps2;
3562
3563         if (host->pdata->get_bus_wd)
3564                 bus_width = host->pdata->get_bus_wd(slot->id);
3565         else if (host->dev->of_node)
3566                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3567         else
3568                 bus_width = 1;
3569
3570         switch (bus_width) {
3571                 case 8:
3572                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3573                 case 4:
3574                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3575         }
3576
3577         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3578                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3579         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3580                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3581         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3582                 mmc->caps |= MMC_CAP_HW_RESET;
3583         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3584                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3585         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3586                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3587         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3588                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3589         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3590                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3591
3592         /*Assign pm_caps pass to pm_flags*/
3593         mmc->pm_flags = mmc->pm_caps;
3594
3595         if (host->pdata->blk_settings) {
3596                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3597                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3598                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3599                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3600                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3601         } else {
3602                 /* Useful defaults if platform data is unset. */
3603 #ifdef CONFIG_MMC_DW_IDMAC
3604                 mmc->max_segs = host->ring_size;
3605                 mmc->max_blk_size = 65536;
3606                 mmc->max_blk_count = host->ring_size;
3607                 mmc->max_seg_size = 0x1000;
3608                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3609                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3610                         /* fixup for external dmac setting */
3611                         mmc->max_segs = 64;
3612                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3613                         mmc->max_blk_count = 65535;
3614                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3615                         mmc->max_seg_size = mmc->max_req_size;
3616                 }
3617 #else
3618                 mmc->max_segs = 64;
3619                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3620                 mmc->max_blk_count = 512;
3621                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3622                 mmc->max_seg_size = mmc->max_req_size;
3623 #endif /* CONFIG_MMC_DW_IDMAC */
3624
3625         }
3626         /* pwr_en */
3627         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3628
3629         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3630         {
3631                 host->vmmc = NULL;
3632         }else{
3633
3634                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3635                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3636                 else
3637                         host->vmmc = NULL;
3638
3639                 if (IS_ERR(host->vmmc)) {
3640                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3641                         host->vmmc = NULL;
3642                 }else{
3643                         ret = regulator_enable(host->vmmc);
3644                         if (ret) {
3645                                 dev_err(host->dev,
3646                                         "failed to enable regulator: %d\n", ret);
3647                                 host->vmmc = NULL;
3648                                 goto err_setup_bus;
3649                         }
3650                 }
3651         }
3652
3653         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3654
3655         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3656                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3657
3658         dw_mci_init_pinctrl(host);
3659         ret = mmc_add_host(mmc);
3660         if (ret)
3661                 goto err_setup_bus;
3662
3663 #if defined(CONFIG_DEBUG_FS)
3664         dw_mci_init_debugfs(slot);
3665 #endif
3666
3667         /* Card initially undetected */
3668         slot->last_detect_state = 1;
3669
3670         return 0;
3671 err_pm_notifier:
3672         unregister_pm_notifier(&mmc->pm_notify);
3673
3674 err_setup_bus:
3675         if (gpio_is_valid(slot->cd_gpio))
3676                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3677         mmc_free_host(mmc);
3678         return -EINVAL;
3679 }
3680
3681 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3682 {
3683         /* Shutdown detect IRQ */
3684         if (slot->host->pdata->exit)
3685                 slot->host->pdata->exit(id);
3686
3687         /* Debugfs stuff is cleaned up by mmc core */
3688         mmc_remove_host(slot->mmc);
3689         slot->host->slot[id] = NULL;
3690         mmc_free_host(slot->mmc);
3691 }
3692
3693 static void dw_mci_init_dma(struct dw_mci *host)
3694 {
3695         /* Alloc memory for sg translation */
3696         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3697                                           &host->sg_dma, GFP_KERNEL);
3698         if (!host->sg_cpu) {
3699                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3700                         __func__);
3701                 goto no_dma;
3702         }
3703         #ifdef CONFIG_ARM64
3704         memset(host->sg_cpu, 0, PAGE_SIZE);
3705         #endif
3706
3707         /* Determine which DMA interface to use */
3708 #if defined(CONFIG_MMC_DW_IDMAC)
3709         if(cpu_is_rk3036() || cpu_is_rk312x()){
3710                 host->dma_ops = &dw_mci_edmac_ops;
3711                 dev_info(host->dev, "Using external DMA controller.\n");
3712         }else{
3713                 host->dma_ops = &dw_mci_idmac_ops;
3714                 dev_info(host->dev, "Using internal DMA controller.\n");
3715         }
3716 #endif
3717
3718         if (!host->dma_ops)
3719                 goto no_dma;
3720
3721         if (host->dma_ops->init && host->dma_ops->start &&
3722             host->dma_ops->stop && host->dma_ops->cleanup) {
3723                 if (host->dma_ops->init(host)) {
3724                         dev_err(host->dev, "%s: Unable to initialize "
3725                                 "DMA Controller.\n", __func__);
3726                         goto no_dma;
3727                 }
3728         } else {
3729                 dev_err(host->dev, "DMA initialization not found.\n");
3730                 goto no_dma;
3731         }
3732
3733         host->use_dma = 1;
3734         return;
3735
3736 no_dma:
3737         dev_info(host->dev, "Using PIO mode.\n");
3738         host->use_dma = 0;
3739         return;
3740 }
3741
3742 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3743 {
3744         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3745         u32 ctrl;
3746
3747         ctrl = mci_readl(host, CTRL);
3748         ctrl |= reset;
3749         mci_writel(host, CTRL, ctrl);
3750
3751         /* wait till resets clear */
3752         do {
3753                 ctrl = mci_readl(host, CTRL);
3754                 if (!(ctrl & reset))
3755                         return true;
3756         } while (time_before(jiffies, timeout));
3757
3758         dev_err(host->dev,
3759                 "Timeout resetting block (ctrl reset %#x)\n",
3760                 ctrl & reset);
3761
3762         return false;
3763 }
3764
3765 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3766 {
3767         /*
3768          * Reseting generates a block interrupt, hence setting
3769          * the scatter-gather pointer to NULL.
3770          */
3771         if (host->sg) {
3772                 sg_miter_stop(&host->sg_miter);
3773                 host->sg = NULL;
3774         }
3775
3776         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3777 }
3778
3779 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3780 {
3781         return dw_mci_ctrl_reset(host,
3782                                  SDMMC_CTRL_FIFO_RESET |
3783                                  SDMMC_CTRL_RESET |
3784                                  SDMMC_CTRL_DMA_RESET);
3785 }
3786
3787 #ifdef CONFIG_OF
3788 /*
3789 static struct dw_mci_of_quirks {
3790         char *quirk;
3791         int id;
3792 } of_quirks[] = {
3793         {
3794                 .quirk  = "broken-cd",
3795                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3796         },
3797 };
3798 */
3799 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3800 {
3801         struct dw_mci_board *pdata;
3802         struct device *dev = host->dev;
3803         struct device_node *np = dev->of_node;
3804         const struct dw_mci_drv_data *drv_data = host->drv_data;
3805         int  ret;
3806         u32 clock_frequency;
3807
3808         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3809         if (!pdata) {
3810                 dev_err(dev, "could not allocate memory for pdata\n");
3811                 return ERR_PTR(-ENOMEM);
3812         }
3813
3814         /* find out number of slots supported */
3815         if (of_property_read_u32(dev->of_node, "num-slots",
3816                                 &pdata->num_slots)) {
3817                 dev_info(dev, "num-slots property not found, "
3818                                 "assuming 1 slot is available\n");
3819                 pdata->num_slots = 1;
3820         }
3821 #if 0
3822         /* get quirks */
3823         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3824                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3825                         pdata->quirks |= of_quirks[idx].id;
3826 #endif
3827
3828         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3829                 dev_info(dev, "fifo-depth property not found, using "
3830                                 "value of FIFOTH register as default\n");
3831
3832         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3833
3834         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3835                 pdata->bus_hz = clock_frequency;
3836
3837         if (drv_data && drv_data->parse_dt) {
3838                 ret = drv_data->parse_dt(host);
3839                 if (ret)
3840                         return ERR_PTR(ret);
3841         }
3842
3843         if (of_find_property(np, "keep-power-in-suspend", NULL))
3844                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3845
3846         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3847                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3848
3849         if (of_find_property(np, "supports-highspeed", NULL))
3850                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3851
3852     if (of_find_property(np, "supports-UHS_SDR104", NULL))
3853                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3854
3855     if (of_find_property(np, "supports-DDR_MODE", NULL))
3856                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3857
3858     if (of_find_property(np, "caps2-mmc-hs200", NULL))
3859                 pdata->caps2 |= MMC_CAP2_HS200;
3860
3861         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3862                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3863
3864         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3865                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3866
3867         if (of_get_property(np, "cd-inverted", NULL))
3868                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3869         if (of_get_property(np, "bootpart-no-access", NULL))
3870                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3871
3872         return pdata;
3873 }
3874
3875 #else /* CONFIG_OF */
3876 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3877 {
3878         return ERR_PTR(-EINVAL);
3879 }
3880 #endif /* CONFIG_OF */
3881
3882 int dw_mci_probe(struct dw_mci *host)
3883 {
3884         const struct dw_mci_drv_data *drv_data = host->drv_data;
3885         int width, i, ret = 0;
3886         u32 fifo_size;
3887         int init_slots = 0;
3888         u32 regs;
3889
3890         if (!host->pdata) {
3891                 host->pdata = dw_mci_parse_dt(host);
3892                 if (IS_ERR(host->pdata)) {
3893                         dev_err(host->dev, "platform data not available\n");
3894                         return -EINVAL;
3895                 }
3896         }
3897
3898         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3899                 dev_err(host->dev,
3900                         "Platform data must supply select_slot function\n");
3901                 return -ENODEV;
3902         }
3903
3904         /*
3905          * In 2.40a spec, Data offset is changed.
3906          * Need to check the version-id and set data-offset for DATA register.
3907          */
3908         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3909         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3910
3911         if (host->verid < DW_MMC_240A)
3912                 host->data_offset = DATA_OFFSET;
3913         else
3914                 host->data_offset = DATA_240A_OFFSET;
3915
3916         //hpclk enable
3917         host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
3918         if (IS_ERR(host->hpclk_mmc)) {
3919                 dev_err(host->dev, "failed to get hpclk_mmc\n");
3920         } else {
3921                 clk_prepare_enable(host->hpclk_mmc);
3922         }
3923
3924         //hclk enable
3925         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3926         if (IS_ERR(host->hclk_mmc)) {
3927                 dev_err(host->dev, "failed to get hclk_mmc\n");
3928                 ret = PTR_ERR(host->hclk_mmc);
3929                 goto err_hclk_mmc;
3930         }
3931
3932         clk_prepare_enable(host->hclk_mmc);
3933
3934         //mmc clk enable
3935         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3936         if (IS_ERR(host->clk_mmc)) {
3937                 dev_err(host->dev, "failed to get clk mmc_per\n");
3938                 ret = PTR_ERR(host->clk_mmc);
3939                 goto err_clk_mmc;
3940         }
3941
3942         host->bus_hz = host->pdata->bus_hz;
3943         if (!host->bus_hz) {
3944                 dev_err(host->dev,"Platform data must supply bus speed\n");
3945                 ret = -ENODEV;
3946                 goto err_clk_mmc;
3947         }
3948
3949         if (host->verid < DW_MMC_240A)
3950                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
3951         else
3952                 //rockchip: fix divider 2 in clksum before controlller
3953                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
3954
3955         if(ret < 0) {
3956             dev_err(host->dev, "failed to set clk mmc\n");
3957             goto err_clk_mmc;
3958         }
3959         clk_prepare_enable(host->clk_mmc);
3960
3961         if (drv_data && drv_data->setup_clock) {
3962         ret = drv_data->setup_clock(host);
3963         if (ret) {
3964             dev_err(host->dev,
3965                 "implementation specific clock setup failed\n");
3966             goto err_clk_mmc;
3967         }
3968     }
3969
3970         host->quirks = host->pdata->quirks;
3971         host->irq_state = true;
3972         host->set_speed = 0;
3973         host->set_div = 0;
3974         host->svi_flags = 0;
3975
3976         spin_lock_init(&host->lock);
3977         spin_lock_init(&host->slock);
3978
3979         INIT_LIST_HEAD(&host->queue);
3980         /*
3981          * Get the host data width - this assumes that HCON has been set with
3982          * the correct values.
3983          */
3984         i = (mci_readl(host, HCON) >> 7) & 0x7;
3985         if (!i) {
3986                 host->push_data = dw_mci_push_data16;
3987                 host->pull_data = dw_mci_pull_data16;
3988                 width = 16;
3989                 host->data_shift = 1;
3990         } else if (i == 2) {
3991                 host->push_data = dw_mci_push_data64;
3992                 host->pull_data = dw_mci_pull_data64;
3993                 width = 64;
3994                 host->data_shift = 3;
3995         } else {
3996                 /* Check for a reserved value, and warn if it is */
3997                 WARN((i != 1),
3998                      "HCON reports a reserved host data width!\n"
3999                      "Defaulting to 32-bit access.\n");
4000                 host->push_data = dw_mci_push_data32;
4001                 host->pull_data = dw_mci_pull_data32;
4002                 width = 32;
4003                 host->data_shift = 2;
4004         }
4005
4006         /* Reset all blocks */
4007         if (!dw_mci_ctrl_all_reset(host))
4008                 return -ENODEV;
4009
4010         host->dma_ops = host->pdata->dma_ops;
4011         dw_mci_init_dma(host);
4012
4013         /* Clear the interrupts for the host controller */
4014         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4015         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4016
4017         /* Put in max timeout */
4018         mci_writel(host, TMOUT, 0xFFFFFFFF);
4019
4020         /*
4021          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
4022          *                          Tx Mark = fifo_size / 2 DMA Size = 8
4023          */
4024         if (!host->pdata->fifo_depth) {
4025                 /*
4026                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4027                  * have been overwritten by the bootloader, just like we're
4028                  * about to do, so if you know the value for your hardware, you
4029                  * should put it in the platform data.
4030                  */
4031                 fifo_size = mci_readl(host, FIFOTH);
4032                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4033         } else {
4034                 fifo_size = host->pdata->fifo_depth;
4035         }
4036         host->fifo_depth = fifo_size;
4037         host->fifoth_val =
4038                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4039         mci_writel(host, FIFOTH, host->fifoth_val);
4040
4041         /* disable clock to CIU */
4042         mci_writel(host, CLKENA, 0);
4043         mci_writel(host, CLKSRC, 0);
4044
4045         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4046         host->card_workqueue = alloc_workqueue("dw-mci-card",
4047                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4048         if (!host->card_workqueue) {
4049                 ret = -ENOMEM;
4050                 goto err_dmaunmap;
4051         }
4052         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4053         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4054                                host->irq_flags, "dw-mci", host);
4055         if (ret)
4056                 goto err_workqueue;
4057
4058         if (host->pdata->num_slots)
4059                 host->num_slots = host->pdata->num_slots;
4060         else
4061                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4062
4063         /* We need at least one slot to succeed */
4064         for (i = 0; i < host->num_slots; i++) {
4065                 ret = dw_mci_init_slot(host, i);
4066                 if (ret)
4067                         dev_dbg(host->dev, "slot %d init failed\n", i);
4068                 else
4069                         init_slots++;
4070         }
4071
4072         /*
4073          * Enable interrupts for command done, data over, data empty, card det,
4074          * receive ready and error such as transmit, receive timeout, crc error
4075          */
4076         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4077         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
4078                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4079         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
4080             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4081             regs |= SDMMC_INT_CD;
4082
4083         mci_writel(host, INTMASK, regs);
4084
4085         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4086
4087         dev_info(host->dev, "DW MMC controller at irq %d, "
4088                  "%d bit host data width, "
4089                  "%u deep fifo\n",
4090                  host->irq, width, fifo_size);
4091
4092         if (init_slots) {
4093                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4094         } else {
4095                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4096                                         "but failed on all\n", host->num_slots);
4097                 goto err_workqueue;
4098         }
4099
4100
4101         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4102                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4103
4104         return 0;
4105
4106 err_workqueue:
4107         destroy_workqueue(host->card_workqueue);
4108
4109 err_dmaunmap:
4110         if (host->use_dma && host->dma_ops->exit)
4111                 host->dma_ops->exit(host);
4112
4113         if (host->vmmc){
4114                 regulator_disable(host->vmmc);
4115                 regulator_put(host->vmmc);
4116         }
4117
4118 err_clk_mmc:
4119         if (!IS_ERR(host->clk_mmc))
4120                 clk_disable_unprepare(host->clk_mmc);
4121 err_hclk_mmc:
4122         if (!IS_ERR(host->hclk_mmc))
4123                 clk_disable_unprepare(host->hclk_mmc);
4124         return ret;
4125 }
4126 EXPORT_SYMBOL(dw_mci_probe);
4127
4128 void dw_mci_remove(struct dw_mci *host)
4129 {
4130         struct mmc_host *mmc = host->mmc;
4131         struct dw_mci_slot *slot = mmc_priv(mmc);
4132         int i;
4133
4134         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4135         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4136
4137         for(i = 0; i < host->num_slots; i++){
4138                 dev_dbg(host->dev, "remove slot %d\n", i);
4139                 if(host->slot[i])
4140                         dw_mci_cleanup_slot(host->slot[i], i);
4141         }
4142
4143         /* disable clock to CIU */
4144         mci_writel(host, CLKENA, 0);
4145         mci_writel(host, CLKSRC, 0);
4146
4147         destroy_workqueue(host->card_workqueue);
4148         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4149                 unregister_pm_notifier(&host->mmc->pm_notify);
4150
4151         if (host->use_dma && host->dma_ops->exit)
4152                 host->dma_ops->exit(host);
4153
4154         if (gpio_is_valid(slot->cd_gpio))
4155                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4156
4157         if (host->vmmc){
4158                 regulator_disable(host->vmmc);
4159                 regulator_put(host->vmmc);
4160         }
4161         if (!IS_ERR(host->clk_mmc))
4162                 clk_disable_unprepare(host->clk_mmc);
4163
4164         if (!IS_ERR(host->hclk_mmc))
4165                 clk_disable_unprepare(host->hclk_mmc);
4166         if (!IS_ERR(host->hpclk_mmc))
4167                 clk_disable_unprepare(host->hpclk_mmc);
4168 }
4169 EXPORT_SYMBOL(dw_mci_remove);
4170
4171
4172
4173 #ifdef CONFIG_PM_SLEEP
4174 /*
4175  * TODO: we should probably disable the clock to the card in the suspend path.
4176  */
4177 extern int get_wifi_chip_type(void);
4178 int dw_mci_suspend(struct dw_mci *host)
4179 {
4180         int present = dw_mci_get_cd(host->mmc);
4181
4182         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4183                 (get_wifi_chip_type() == WIFI_ESP8089 || get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4184                 return 0;
4185
4186         if(host->vmmc)
4187                 regulator_disable(host->vmmc);
4188
4189         /*only for sdmmc controller*/
4190         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4191                 disable_irq(host->irq);
4192                 if (present) {
4193                         if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4194                                 MMC_DBG_ERR_FUNC(host->mmc,
4195                                         "Idle pinctrl setting failed! [%s]",
4196                                         mmc_hostname(host->mmc));
4197                 }
4198
4199                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4200                 mci_writel(host, INTMASK, 0x00);
4201                 mci_writel(host, CTRL, 0x00);
4202
4203                 /* Soc rk3126/3036 already in gpio_cd mode */
4204                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4205                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4206                         enable_irq_wake(host->mmc->slot.cd_irq);
4207                 }
4208         }
4209         return 0;
4210 }
4211 EXPORT_SYMBOL(dw_mci_suspend);
4212
4213 int dw_mci_resume(struct dw_mci *host)
4214 {
4215         int i, ret;
4216         u32 regs;
4217         struct dw_mci_slot *slot;
4218         int present = dw_mci_get_cd(host->mmc);
4219
4220         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4221                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4222                         get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4223                 return 0;
4224
4225         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4226                 slot = mmc_priv(host->mmc);
4227                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4228                         return 0;
4229         }
4230
4231         /*only for sdmmc controller*/
4232         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4233                 /* Soc rk3126/3036 already in gpio_cd mode */
4234                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4235                         disable_irq_wake(host->mmc->slot.cd_irq);
4236                         mmc_gpio_free_cd(host->mmc);
4237                 }
4238
4239                 if (!present) {
4240                         if (!IS_ERR(host->pins_udbg)) {
4241                                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4242                                         MMC_DBG_ERR_FUNC(host->mmc,
4243                                                 "Idle pinctrl setting failed! [%s]",
4244                                                 mmc_hostname(host->mmc));
4245                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4246                                         MMC_DBG_ERR_FUNC(host->mmc,
4247                                                 "%s: Udbg pinctrl setting failed! [%s]",
4248                                                 mmc_hostname(host->mmc));
4249                         } else {
4250                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4251                                         MMC_DBG_ERR_FUNC(host->mmc,
4252                                                 "Default pinctrl setting failed! [%s]",
4253                                                 mmc_hostname(host->mmc));
4254                         }
4255                 } else {
4256                         if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4257                                 MMC_DBG_ERR_FUNC(host->mmc,
4258                                         "Default pinctrl setting failed! [%s]",
4259                                         mmc_hostname(host->mmc));
4260                 }
4261
4262                 /* Disable jtag*/
4263                 if(cpu_is_rk3288())
4264                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4265                 else if(cpu_is_rk3036())
4266                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4267                 else if(cpu_is_rk312x())
4268                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4269                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4270         }
4271         if(host->vmmc){
4272                 ret = regulator_enable(host->vmmc);
4273                 if (ret){
4274                         dev_err(host->dev,
4275                                 "failed to enable regulator: %d\n", ret);
4276                         return ret;
4277                 }
4278         }
4279
4280         if(!dw_mci_ctrl_all_reset(host)){
4281                 ret = -ENODEV;
4282                 return ret;
4283         }
4284
4285         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
4286                 if(host->use_dma && host->dma_ops->init)
4287                         host->dma_ops->init(host);
4288
4289         /*
4290          * Restore the initial value at FIFOTH register
4291          * And Invalidate the prev_blksz with zero
4292          */
4293         mci_writel(host, FIFOTH, host->fifoth_val);
4294         host->prev_blksz = 0;
4295         /* Put in max timeout */
4296         mci_writel(host, TMOUT, 0xFFFFFFFF);
4297
4298         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4299         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
4300                    DW_MCI_ERROR_FLAGS;
4301         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4302             regs |= SDMMC_INT_CD;
4303         mci_writel(host, INTMASK, regs);
4304         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4305         /*only for sdmmc controller*/
4306         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)){
4307                 enable_irq(host->irq);
4308         }
4309
4310         for(i = 0; i < host->num_slots; i++){
4311                 struct dw_mci_slot *slot = host->slot[i];
4312                 if(!slot)
4313                         continue;
4314                 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4315                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4316                         dw_mci_setup_bus(slot, true);
4317                 }
4318         }
4319
4320         return 0;
4321 }
4322 EXPORT_SYMBOL(dw_mci_resume);
4323 #endif /* CONFIG_PM_SLEEP */
4324
4325 static int __init dw_mci_init(void)
4326 {
4327         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4328         return 0;
4329 }
4330
4331 static void __exit dw_mci_exit(void)
4332 {
4333 }
4334
4335 module_init(dw_mci_init);
4336 module_exit(dw_mci_exit);
4337
4338 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4339 MODULE_AUTHOR("NXP Semiconductor VietNam");
4340 MODULE_AUTHOR("Imagination Technologies Ltd");
4341 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4342 MODULE_AUTHOR("Bangwang Xie <xbw@rock-chips.com>");
4343 MODULE_LICENSE("GPL v2");