drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  * Copyright (C) 2014 - 2015 Fuzhou Rockchip Electronics Co.Ltd.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/blkdev.h>
  16 #include <linux/clk.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/suspend.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/card.h>
  37 #include <linux/mmc/sdio.h>
  38 #include <linux/mmc/rk_mmc.h>
  39 #include <linux/bitops.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/of.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/mmc/slot-gpio.h>
  45 #include <linux/clk-private.h>
  46 #include <linux/rockchip/cpu.h>
  47 #include <linux/rfkill-wlan.h>
  48 #include <linux/mfd/syscon.h>
  49 #include <linux/regmap.h>
  50 #include <linux/log2.h>
  51 #include <asm-generic/dma-mapping-common.h>
  52 #include "rk_sdmmc.h"
  53 #include "rk_sdmmc_dbg.h"
  54 #include <linux/regulator/rockchip_io_vol_domain.h>
  55 #include "../../clk/rockchip/clk-ops.h"
  56
  57 #define RK_SDMMC_DRIVER_VERSION "Ver 2.00 2015-06-10"
  58
  59 /* Common flag combinations */
  60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  61                                  SDMMC_INT_SBE  | \
  62                                  SDMMC_INT_EBE)
  63 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  64                                  SDMMC_INT_RESP_ERR)
  65 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  66                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  67 #define DW_MCI_SEND_STATUS      1
  68 #define DW_MCI_RECV_STATUS      2
  69 #define DW_MCI_DMA_THRESHOLD    16
  70 #define DW_MCI_FREQ_MAX         50000000        /* unit: HZ */
  71 #define DW_MCI_FREQ_MIN         300000          /* unit: HZ */
  72
  73 /* Max is 250ms showed in Spec */
  74 #define SDMMC_DATA_TIMEOUT_SD   500
  75 #define SDMMC_DATA_TIMEOUT_SDIO 250
  76 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  77 #define SDMMC_CMD_RTO_MAX_HOLD  200
  78 #define SDMMC_WAIT_FOR_UNBUSY   2500
  79
  80 #define DW_REGS_SIZE    (0x0098 + 4)
  81 #define DW_REGS_NUM     (0x0098 / 4)
  82
  83 #ifdef CONFIG_MMC_DW_IDMAC
  84 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  85                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  86                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  87                                  SDMMC_IDMAC_INT_TI)
  88
  89 struct idmac_desc {
  90         u32             des0;   /* Control Descriptor */
  91 #define IDMAC_DES0_DIC  BIT(1)
  92 #define IDMAC_DES0_LD   BIT(2)
  93 #define IDMAC_DES0_FD   BIT(3)
  94 #define IDMAC_DES0_CH   BIT(4)
  95 #define IDMAC_DES0_ER   BIT(5)
  96 #define IDMAC_DES0_CES  BIT(30)
  97 #define IDMAC_DES0_OWN  BIT(31)
  98
  99         u32             des1;   /* Buffer sizes */
 100 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 101         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 102
 103         u32             des2;   /* buffer 1 physical address */
 104
 105         u32             des3;   /* buffer 2 physical address */
 106 };
 107 #endif /* CONFIG_MMC_DW_IDMAC */
 108
 109
 110 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 111 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 112 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 113 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 114 extern void rk_send_wakeup_key(void);
 115
 116 #if defined(CONFIG_DEBUG_FS)
 117 static int dw_mci_req_show(struct seq_file *s, void *v)
 118 {
 119         struct dw_mci_slot *slot = s->private;
 120         struct mmc_request *mrq;
 121         struct mmc_command *cmd;
 122         struct mmc_command *stop;
 123         struct mmc_data *data;
 124
 125         /* Make sure we get a consistent snapshot */
 126         spin_lock_bh(&slot->host->lock);
 127         mrq = slot->mrq;
 128
 129         if (mrq) {
 130                 cmd = mrq->cmd;
 131                 data = mrq->data;
 132                 stop = mrq->stop;
 133
 134                 if (cmd)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    cmd->opcode, cmd->arg, cmd->flags,
 138                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 139                                    cmd->resp[2], cmd->error);
 140                 if (data)
 141                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 142                                    data->bytes_xfered, data->blocks,
 143                                    data->blksz, data->flags, data->error);
 144                 if (stop)
 145                         seq_printf(s,
 146                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 147                                    stop->opcode, stop->arg, stop->flags,
 148                                    stop->resp[0], stop->resp[1], stop->resp[2],
 149                                    stop->resp[2], stop->error);
 150         }
 151
 152         spin_unlock_bh(&slot->host->lock);
 153
 154         return 0;
 155 }
 156
 157 static int dw_mci_req_open(struct inode *inode, struct file *file)
 158 {
 159         return single_open(file, dw_mci_req_show, inode->i_private);
 160 }
 161
 162 static const struct file_operations dw_mci_req_fops = {
 163         .owner          = THIS_MODULE,
 164         .open           = dw_mci_req_open,
 165         .read           = seq_read,
 166         .llseek         = seq_lseek,
 167         .release        = single_release,
 168 };
 169
 170 static int dw_mci_regs_show(struct seq_file *s, void *v)
 171 {
 172         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 173         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 174         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 175         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 176         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 177         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 178
 179         return 0;
 180 }
 181
 182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 183 {
 184         return single_open(file, dw_mci_regs_show, inode->i_private);
 185 }
 186
 187 static const struct file_operations dw_mci_regs_fops = {
 188         .owner          = THIS_MODULE,
 189         .open           = dw_mci_regs_open,
 190         .read           = seq_read,
 191         .llseek         = seq_lseek,
 192         .release        = single_release,
 193 };
 194
 195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 196 {
 197         struct mmc_host *mmc = slot->mmc;
 198         struct dw_mci *host = slot->host;
 199         struct dentry *root;
 200         struct dentry *node;
 201
 202         root = mmc->debugfs_root;
 203         if (!root)
 204                 return;
 205
 206         node = debugfs_create_file("regs", S_IRUSR, root, host,
 207                                    &dw_mci_regs_fops);
 208         if (!node)
 209                 goto err;
 210
 211         node = debugfs_create_file("req", S_IRUSR, root, slot,
 212                                    &dw_mci_req_fops);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 217         if (!node)
 218                 goto err;
 219
 220         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 221                                   (u32 *)&host->pending_events);
 222         if (!node)
 223                 goto err;
 224
 225         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 226                                   (u32 *)&host->completed_events);
 227         if (!node)
 228                 goto err;
 229
 230         return;
 231
 232 err:
 233         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 234 }
 235 #endif /* defined(CONFIG_DEBUG_FS) */
 236
 237 static void dw_mci_set_timeout(struct dw_mci *host)
 238 {
 239         /* timeout (maximum) */
 240         mci_writel(host, TMOUT, 0xffffffff);
 241 }
 242
 243 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 244 {
 245         struct mmc_data *data;
 246         struct dw_mci_slot *slot = mmc_priv(mmc);
 247         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 248         u32 cmdr;
 249         cmd->error = -EINPROGRESS;
 250
 251         cmdr = cmd->opcode;
 252
 253         if (cmdr == MMC_STOP_TRANSMISSION)
 254                 cmdr |= SDMMC_CMD_STOP;
 255         else
 256                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 257
 258         if (cmd->flags & MMC_RSP_PRESENT) {
 259                 /* We expect a response, so set this bit */
 260                 cmdr |= SDMMC_CMD_RESP_EXP;
 261                 if (cmd->flags & MMC_RSP_136)
 262                         cmdr |= SDMMC_CMD_RESP_LONG;
 263         }
 264
 265         if (cmd->flags & MMC_RSP_CRC)
 266                 cmdr |= SDMMC_CMD_RESP_CRC;
 267
 268         data = cmd->data;
 269         if (data) {
 270                 cmdr |= SDMMC_CMD_DAT_EXP;
 271                 if (data->flags & MMC_DATA_STREAM)
 272                         cmdr |= SDMMC_CMD_STRM_MODE;
 273                 if (data->flags & MMC_DATA_WRITE)
 274                         cmdr |= SDMMC_CMD_DAT_WR;
 275         }
 276
 277         if (drv_data && drv_data->prepare_command)
 278                 drv_data->prepare_command(slot->host, &cmdr);
 279
 280         return cmdr;
 281 }
 282
 283 static void dw_mci_start_command(struct dw_mci *host,
 284                                  struct mmc_command *cmd, u32 cmd_flags)
 285 {
 286         struct dw_mci_slot *slot = host->slot[0];
 287
 288         host->pre_cmd = host->cmd;
 289         host->cmd = cmd;
 290         dev_vdbg(host->dev,
 291                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 292                 cmd->arg, cmd_flags);
 293
 294         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 295                 /*confirm non-low-power mode*/
 296                 mci_writel(host, CMDARG, 0);
 297                 dw_mci_disable_low_power(slot);
 298
 299                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 300                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 301
 302                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 303         }
 304
 305         mci_writel(host, CMDARG, cmd->arg);
 306         wmb();
 307
 308         /* Fix the value to 1 in current soc */
 309         if(host->mmc->hold_reg_flag)
 310                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 311
 312         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 313         wmb();
 314 }
 315
 316 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 317 {
 318         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 319 }
 320
 321 /* DMA interface functions */
 322 static void dw_mci_stop_dma(struct dw_mci *host)
 323 {
 324         if (host->using_dma) {
 325                 /* Fixme: No need to terminate edma, may cause flush op */
 326                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 327                         host->dma_ops->stop(host);
 328                 host->dma_ops->cleanup(host);
 329         }
 330
 331         /* Data transfer was stopped by the interrupt handler */
 332         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 333 }
 334
 335 static int dw_mci_get_dma_dir(struct mmc_data *data)
 336 {
 337         if (data->flags & MMC_DATA_WRITE)
 338                 return DMA_TO_DEVICE;
 339         else
 340                 return DMA_FROM_DEVICE;
 341 }
 342
 343 #ifdef CONFIG_MMC_DW_IDMAC
 344 static void dw_mci_dma_cleanup(struct dw_mci *host)
 345 {
 346         struct mmc_data *data = host->data;
 347
 348         if (data)
 349                 if (!data->host_cookie)
 350                         dma_unmap_sg(host->dev,
 351                                      data->sg,
 352                                      data->sg_len,
 353                                      dw_mci_get_dma_dir(data));
 354 }
 355
 356 static void dw_mci_idmac_reset(struct dw_mci *host)
 357 {
 358         u32 bmod = mci_readl(host, BMOD);
 359         /* Software reset of DMA */
 360         bmod |= SDMMC_IDMAC_SWRESET;
 361         mci_writel(host, BMOD, bmod);
 362 }
 363
 364 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 365 {
 366         u32 temp;
 367
 368         /* Disable and reset the IDMAC interface */
 369         temp = mci_readl(host, CTRL);
 370         temp &= ~SDMMC_CTRL_USE_IDMAC;
 371         temp |= SDMMC_CTRL_DMA_RESET;
 372         mci_writel(host, CTRL, temp);
 373
 374         /* Stop the IDMAC running */
 375         temp = mci_readl(host, BMOD);
 376         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 377         temp |= SDMMC_IDMAC_SWRESET;
 378         mci_writel(host, BMOD, temp);
 379 }
 380
 381 static void dw_mci_idmac_complete_dma(void *arg)
 382 {
 383         struct dw_mci *host = arg;
 384         struct mmc_data *data = host->data;
 385
 386         dev_vdbg(host->dev, "DMA complete\n");
 387
 388         host->dma_ops->cleanup(host);
 389
 390         /*
 391          * If the card was removed, data will be NULL. No point in trying to
 392          * send the stop command or waiting for NBUSY in this case.
 393          */
 394         if(data){
 395                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 396                 tasklet_schedule(&host->tasklet);
 397         }
 398 }
 399
 400 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 401                                     unsigned int sg_len)
 402 {
 403         int i;
 404         struct idmac_desc *desc = host->sg_cpu;
 405
 406         for (i = 0; i < sg_len; i++, desc++) {
 407                 unsigned int length = sg_dma_len(&data->sg[i]);
 408                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 409
 410                 /* Set the OWN bit and disable interrupts for this descriptor */
 411                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 412
 413                 /* Buffer length */
 414                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 415
 416                 /* Physical address to DMA to/from */
 417                 desc->des2 = mem_addr;
 418         }
 419
 420         /* Set first descriptor */
 421         desc = host->sg_cpu;
 422         desc->des0 |= IDMAC_DES0_FD;
 423
 424         /* Set last descriptor */
 425         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 426         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 427         desc->des0 |= IDMAC_DES0_LD;
 428
 429         wmb();
 430 }
 431
 432 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 433 {
 434         u32 temp;
 435
 436         dw_mci_translate_sglist(host, host->data, sg_len);
 437
 438         /* Select IDMAC interface */
 439         temp = mci_readl(host, CTRL);
 440         temp |= SDMMC_CTRL_USE_IDMAC;
 441         mci_writel(host, CTRL, temp);
 442
 443         wmb();
 444
 445         /* Enable the IDMAC */
 446         temp = mci_readl(host, BMOD);
 447         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 448         mci_writel(host, BMOD, temp);
 449
 450         /* Start it running */
 451         mci_writel(host, PLDMND, 1);
 452 }
 453
 454 static int dw_mci_idmac_init(struct dw_mci *host)
 455 {
 456         struct idmac_desc *p;
 457         int i;
 458
 459         /* Number of descriptors in the ring buffer */
 460         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 461
 462         /* Forward link the descriptor list */
 463         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
 464                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 465                 p->des1 = 0;
 466         }
 467         /* Set the last descriptor as the end-of-ring descriptor */
 468         p->des3 = host->sg_dma;
 469         p->des0 = IDMAC_DES0_ER;
 470
 471         dw_mci_idmac_reset(host);
 472
 473         /* Mask out interrupts - get Tx & Rx complete only */
 474         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 475         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 476                    SDMMC_IDMAC_INT_TI);
 477
 478         /* Set the descriptor base address */
 479         mci_writel(host, DBADDR, host->sg_dma);
 480         return 0;
 481 }
 482
 483 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 484         .init = dw_mci_idmac_init,
 485         .start = dw_mci_idmac_start_dma,
 486         .stop = dw_mci_idmac_stop_dma,
 487         .complete = dw_mci_idmac_complete_dma,
 488         .cleanup = dw_mci_dma_cleanup,
 489 };
 490
 491
 492 static void dw_mci_edma_cleanup(struct dw_mci *host)
 493 {
 494         struct mmc_data *data = host->data;
 495
 496         if (data)
 497                 if (!data->host_cookie)
 498                         dma_unmap_sg(host->dev,
 499                                         data->sg, data->sg_len,
 500                                         dw_mci_get_dma_dir(data));
 501 }
 502
 503 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 504 {
 505         dmaengine_terminate_all(host->dms->ch);
 506 }
 507
 508 static void dw_mci_edmac_complete_dma(void *arg)
 509 {
 510         struct dw_mci *host = arg;
 511         struct mmc_data *data = host->data;
 512
 513         dev_vdbg(host->dev, "DMA complete\n");
 514
 515         if(data)
 516                 if(data->flags & MMC_DATA_READ)
 517                         /* Invalidate cache after read */
 518                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 519                                 data->sg_len, DMA_FROM_DEVICE);
 520
 521         host->dma_ops->cleanup(host);
 522
 523         /*
 524          * If the card was removed, data will be NULL. No point in trying to
 525          * send the stop command or waiting for NBUSY in this case.
 526          */
 527         if (data) {
 528                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 529                 tasklet_schedule(&host->tasklet);
 530         }
 531 }
 532
 533 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 534 {
 535         struct dma_slave_config slave_config;
 536         struct dma_async_tx_descriptor *desc = NULL;
 537         struct scatterlist *sgl = host->data->sg;
 538         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 539         u32 sg_elems = host->data->sg_len;
 540         u32 fifoth_val, mburst;
 541         u32 burst_limit = 0;
 542         u32 idx, rx_wmark, tx_wmark;
 543         int ret = 0;
 544
 545         /* Set external dma config: burst size, burst width*/
 546         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 547         slave_config.src_addr = slave_config.dst_addr;
 548         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 549         slave_config.src_addr_width = slave_config.dst_addr_width;
 550
 551         /* Match FIFO dma burst MSIZE with external dma config*/
 552         fifoth_val = mci_readl(host, FIFOTH);
 553         mburst = mszs[(fifoth_val >> 28) & 0x7];
 554
 555         /* Edmac limit burst to 16, but work around for rk3036 to 8 */
 556         if (unlikely(cpu_is_rk3036()))
 557                 burst_limit = 8;
 558         else
 559                 burst_limit = 16;
 560
 561         if (mburst > burst_limit) {
 562                 mburst = burst_limit;
 563                 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
 564
 565                 rx_wmark = mszs[idx] - 1;
 566                 tx_wmark = (host->fifo_depth) / 2;
 567                 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
 568
 569                 mci_writel(host, FIFOTH, fifoth_val);
 570         }
 571
 572         slave_config.dst_maxburst = mburst;
 573         slave_config.src_maxburst = slave_config.dst_maxburst;
 574
 575         if(host->data->flags & MMC_DATA_WRITE){
 576                 slave_config.direction = DMA_MEM_TO_DEV;
 577                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 578                 if(ret){
 579                         dev_err(host->dev,
 580                                 "Error in dw_mci edmac write configuration.\n");
 581                         return;
 582                 }
 583
 584                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 585                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 586                 if (!desc) {
 587                         dev_err(host->dev,
 588                                 "Cannot prepare slave write sg the dw_mci edmac!\n");
 589                         return;
 590                 }
 591
 592                 /* Set dw_mci_edmac_complete_dma as callback */
 593                 desc->callback = dw_mci_edmac_complete_dma;
 594                 desc->callback_param = (void *)host;
 595                 dmaengine_submit(desc);
 596
 597                 /* Flush cache before write */
 598                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 599                                 sg_elems, DMA_TO_DEVICE);
 600                 dma_async_issue_pending(host->dms->ch);
 601         } else {
 602                 /* MMC_DATA_READ*/
 603                 slave_config.direction = DMA_DEV_TO_MEM;
 604                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 605                 if (ret) {
 606                         dev_err(host->dev,
 607                                 "Error in dw_mci edmac read configuration.\n");
 608                         return;
 609                 }
 610                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 611                                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 612                 if (!desc) {
 613                         dev_err(host->dev,
 614                                 "Cannot prepare slave read sg for the dw_mci edmac!\n");
 615                         return;
 616                 }
 617                 /* set dw_mci_edmac_complete_dma as callback */
 618                 desc->callback = dw_mci_edmac_complete_dma;
 619                 desc->callback_param = (void *)host;
 620                 dmaengine_submit(desc);
 621                 dma_async_issue_pending(host->dms->ch);
 622         }
 623 }
 624
 625 static int dw_mci_edmac_init(struct dw_mci *host)
 626 {
 627         int ret = 0;
 628
 629         /* Request external dma channel, SHOULD decide chn in dts */
 630         host->dms = NULL;
 631         host->dms = (struct dw_mci_dma_slave *)kzalloc
 632                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 633         if (NULL == host->dms) {
 634                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 635                 return -ENOMEM;
 636         }
 637
 638         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 639         if (!host->dms->ch) {
 640                 dev_err(host->dev,
 641                         "Failed to get external DMA channel %d\n",
 642                         host->dms->ch->chan_id);
 643                 kfree(host->dms);
 644                 host->dms = NULL;
 645                 return -ENXIO;
 646         }
 647
 648         return ret;
 649 }
 650
 651 static void dw_mci_edmac_exit(struct dw_mci *host)
 652 {
 653         if (NULL != host->dms) {
 654                 if (NULL != host->dms->ch) {
 655                         dma_release_channel(host->dms->ch);
 656                         host->dms->ch = NULL;
 657                 }
 658                 kfree(host->dms);
 659                 host->dms = NULL;
 660         }
 661 }
 662
 663 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 664         .init = dw_mci_edmac_init,
 665         .exit = dw_mci_edmac_exit,
 666         .start = dw_mci_edmac_start_dma,
 667         .stop = dw_mci_edmac_stop_dma,
 668         .complete = dw_mci_edmac_complete_dma,
 669         .cleanup = dw_mci_edma_cleanup,
 670 };
 671 #endif /* CONFIG_MMC_DW_IDMAC */
 672
 673 static struct dma_attrs dw_mci_direct_attrs;
 674
 675 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 676                                    struct mmc_data *data,
 677                                    bool next)
 678 {
 679         struct scatterlist *sg;
 680         unsigned int i, sg_len;
 681 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
 682         struct dma_attrs *attrs;
 683 #endif
 684
 685         if (!next && data->host_cookie)
 686                 return data->host_cookie;
 687
 688         /*
 689          * We don't do DMA on "complex" transfers, i.e. with
 690          * non-word-aligned buffers or lengths. Also, we don't bother
 691          * with all the DMA setup overhead for short transfers.
 692          */
 693         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 694                 return -EINVAL;
 695
 696         if (data->blksz & 3)
 697                 return -EINVAL;
 698
 699         for_each_sg(data->sg, sg, data->sg_len, i) {
 700                 if (sg->offset & 3 || sg->length & 3)
 701                         return -EINVAL;
 702         }
 703 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
 704         attrs = (data->flags & MMC_DATA_DIRECT) ? &dw_mci_direct_attrs : NULL;
 705         sg_len = dma_map_sg_attrs(host->dev,
 706                                  data->sg,
 707                                  data->sg_len,
 708                                  dw_mci_get_dma_dir(data), attrs);
 709 #else
 710
 711         sg_len = dma_map_sg(host->dev,
 712                             data->sg,
 713                             data->sg_len,
 714                             dw_mci_get_dma_dir(data));
 715 #endif
 716         if (sg_len == 0)
 717                 return -EINVAL;
 718
 719         if (next)
 720                 data->host_cookie = sg_len;
 721
 722         return sg_len;
 723 }
 724
 725 static void dw_mci_pre_req(struct mmc_host *mmc,
 726                            struct mmc_request *mrq,
 727                            bool is_first_req)
 728 {
 729         struct dw_mci_slot *slot = mmc_priv(mmc);
 730         struct mmc_data *data = mrq->data;
 731
 732         if (!slot->host->use_dma || !data)
 733                 return;
 734
 735         if (data->host_cookie) {
 736                 data->host_cookie = 0;
 737                 return;
 738         }
 739
 740         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 741                 data->host_cookie = 0;
 742 }
 743
 744 static void dw_mci_post_req(struct mmc_host *mmc,
 745                             struct mmc_request *mrq,
 746                             int err)
 747 {
 748         struct dw_mci_slot *slot = mmc_priv(mmc);
 749         struct mmc_data *data = mrq->data;
 750
 751         if (!slot->host->use_dma || !data)
 752                 return;
 753
 754         if (data->host_cookie)
 755                 dma_unmap_sg(slot->host->dev,
 756                              data->sg,
 757                              data->sg_len,
 758                              dw_mci_get_dma_dir(data));
 759         data->host_cookie = 0;
 760 }
 761
 762 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 763 {
 764 #ifdef CONFIG_MMC_DW_IDMAC
 765         unsigned int blksz = data->blksz;
 766         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 767         u32 fifo_width = 1 << host->data_shift;
 768         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 769         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 770         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 771
 772         tx_wmark = (host->fifo_depth) / 2;
 773         tx_wmark_invers = host->fifo_depth - tx_wmark;
 774
 775         /*
 776          * MSIZE is '1',
 777          * if blksz is not a multiple of the FIFO width
 778          */
 779         if (blksz % fifo_width) {
 780                 msize = 0;
 781                 rx_wmark = 1;
 782                 goto done;
 783         }
 784
 785         do {
 786                 if (!((blksz_depth % mszs[idx]) ||
 787                      (tx_wmark_invers % mszs[idx]))) {
 788                         msize = idx;
 789                         rx_wmark = mszs[idx] - 1;
 790                         break;
 791                 }
 792         } while (--idx > 0);
 793         /*
 794          * If idx is '0', it won't be tried
 795          * Thus, initial values are uesed
 796          */
 797 done:
 798         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 799         mci_writel(host, FIFOTH, fifoth_val);
 800
 801 #endif
 802 }
 803
 804 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 805 {
 806         unsigned int blksz = data->blksz;
 807         u32 blksz_depth, fifo_depth;
 808         u16 thld_size;
 809
 810         WARN_ON(!(data->flags & MMC_DATA_READ));
 811
 812         if (host->timing != MMC_TIMING_MMC_HS200 &&
 813             host->timing != MMC_TIMING_UHS_SDR104)
 814                 goto disable;
 815
 816         blksz_depth = blksz / (1 << host->data_shift);
 817         fifo_depth = host->fifo_depth;
 818
 819         if (blksz_depth > fifo_depth)
 820                 goto disable;
 821
 822         /*
 823          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 824          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 825          * Currently just choose blksz.
 826          */
 827         thld_size = blksz;
 828         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 829         return;
 830
 831 disable:
 832         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 833 }
 834
 835 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 836 {
 837         int sg_len;
 838         unsigned long flags;
 839         u32 temp;
 840
 841         host->using_dma = 0;
 842
 843         /* If we don't have a channel, we can't do DMA */
 844         if (!host->use_dma)
 845                 return -ENODEV;
 846
 847         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 848         if (sg_len < 0) {
 849                 /* Fixme: No need terminate edma, may cause flush op */
 850                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 851                         host->dma_ops->stop(host);
 852                 return sg_len;
 853         }
 854
 855         host->using_dma = 1;
 856
 857         dev_vdbg(host->dev,
 858                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 859                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 860                  sg_len);
 861
 862         /*
 863          * Decide the MSIZE and RX/TX Watermark.
 864          * If current block size is same with previous size,
 865          * no need to update fifoth.
 866          */
 867         if (host->prev_blksz != data->blksz)
 868                 dw_mci_adjust_fifoth(host, data);
 869
 870         /* Reset DMA FIFO*/
 871         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 872
 873         /* Enable the DMA interface */
 874         temp = mci_readl(host, CTRL);
 875         temp |= SDMMC_CTRL_DMA_ENABLE;
 876         mci_writel(host, CTRL, temp);
 877
 878         /* Disable RX/TX IRQs, let DMA handle it */
 879         spin_lock_irqsave(&host->slock, flags);
 880         temp = mci_readl(host, INTMASK);
 881         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 882         mci_writel(host, INTMASK, temp);
 883         spin_unlock_irqrestore(&host->slock, flags);
 884
 885         host->dma_ops->start(host, sg_len);
 886
 887         return 0;
 888 }
 889
 890 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 891 {
 892         u32 temp;
 893         unsigned long flag;
 894
 895         data->error = -EINPROGRESS;
 896
 897         //WARN_ON(host->data);
 898         host->sg = NULL;
 899         host->data = data;
 900
 901         /* Reset FIFO*/
 902         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 903
 904         if (data->flags & MMC_DATA_READ) {
 905                 host->dir_status = DW_MCI_RECV_STATUS;
 906                 dw_mci_ctrl_rd_thld(host, data);
 907         } else {
 908                 host->dir_status = DW_MCI_SEND_STATUS;
 909         }
 910
 911         MMC_DBG_INFO_FUNC(host->mmc,
 912                         "Dw_mci_submit_data, blocks = %d, blksz = %d [%s]",
 913                         data->blocks, data->blksz, mmc_hostname(host->mmc));
 914
 915         if (dw_mci_submit_data_dma(host, data)) {
 916                 int flags = SG_MITER_ATOMIC;
 917                 if (host->data->flags & MMC_DATA_READ)
 918                         flags |= SG_MITER_TO_SG;
 919                 else
 920                         flags |= SG_MITER_FROM_SG;
 921
 922                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 923                 host->sg = data->sg;
 924                 host->part_buf_start = 0;
 925                 host->part_buf_count = 0;
 926
 927                 spin_lock_irqsave(&host->slock, flag);
 928                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 929                 temp = mci_readl(host, INTMASK);
 930                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 931                 mci_writel(host, INTMASK, temp);
 932                 spin_unlock_irqrestore(&host->slock, flag);
 933
 934                 temp = mci_readl(host, CTRL);
 935                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 936                 mci_writel(host, CTRL, temp);
 937
 938                 /*
 939                  * Use the initial fifoth_val for PIO mode.
 940                  * If next issued data may be transfered by DMA mode,
 941                  * prev_blksz should be invalidated.
 942                  */
 943                 mci_writel(host, FIFOTH, host->fifoth_val);
 944                 host->prev_blksz = 0;
 945         } else {
 946                 /*
 947                  * Keep the current block size.
 948                  * It will be used to decide whether to update
 949                  * fifoth register next time.
 950                  */
 951                 host->prev_blksz = data->blksz;
 952         }
 953 }
 954
 955 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 956 {
 957         struct dw_mci *host = slot->host;
 958         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 959         unsigned int cmd_status = 0;
 960
 961 #ifdef SDMMC_WAIT_FOR_UNBUSY
 962         bool ret = true;
 963         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
 964
 965         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 966                 while (ret) {
 967                         ret =  time_before(jiffies, timeout);
 968                         cmd_status = mci_readl(host, STATUS);
 969                         if (!(cmd_status &
 970                                 (SDMMC_STAUTS_DATA_BUSY |
 971                                 SDMMC_STAUTS_MC_BUSY)))
 972                                 break;
 973                 };
 974
 975                 if(false == ret)
 976                         MMC_DBG_ERR_FUNC(host->mmc,
 977                                 "mci_send_cmd: wait for unbusy timeout! [%s]",
 978                                 mmc_hostname(host->mmc));
 979         }
 980 #endif
 981
 982         mci_writel(host, CMDARG, arg);
 983         wmb();
 984         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 985         if(cmd & SDMMC_CMD_UPD_CLK)
 986                 timeout = jiffies + msecs_to_jiffies(50);
 987         else
 988                 timeout = jiffies + msecs_to_jiffies(500);
 989
 990         while (time_before(jiffies, timeout)) {
 991                 cmd_status = mci_readl(host, CMD);
 992                 if (!(cmd_status & SDMMC_CMD_START))
 993                         return;
 994         }
 995
 996         dev_err(&slot->mmc->class_dev,
 997                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 998                 cmd, arg, cmd_status);
 999 }
1000
1001 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1002 {
1003         struct dw_mci *host = slot->host;
1004         unsigned int tempck,clock = slot->clock;
1005         u32 div;
1006         u32 clk_en_a;
1007         u32 sdio_int;
1008
1009         MMC_DBG_INFO_FUNC(host->mmc,
1010                         "%s: clock=%d, current_speed=%d, bus_hz=%d, forc=%d[%s]\n",
1011                         __FUNCTION__, clock, host->current_speed, host->bus_hz,
1012                         force_clkinit, mmc_hostname(host->mmc));
1013
1014         if (!clock) {
1015                 mci_writel(host, CLKENA, 0);
1016                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1017                 if(host->svi_flags == 0)
1018                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1019                 #else
1020                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1021                 #endif
1022         } else if (clock != host->current_speed || force_clkinit) {
1023                 div = host->bus_hz / clock;
1024                 if (host->bus_hz % clock && host->bus_hz > clock)
1025                         /*
1026                          * move the + 1 after the divide to prevent
1027                          * over-clocking the card.
1028                          */
1029                         div += 1;
1030
1031                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1032
1033                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1034                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1035                         dev_info(&slot->mmc->class_dev,
1036                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1037                                  slot->id, host->bus_hz, clock,
1038                                  tempck, div);
1039
1040                         host->set_speed = tempck;
1041                         host->set_div = div;
1042                 }
1043
1044                 /* disable clock */
1045                 mci_writel(host, CLKENA, 0);
1046                 mci_writel(host, CLKSRC, 0);
1047
1048                 /* inform CIU */
1049                 mci_send_cmd(slot,
1050                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1051
1052                 if(clock <= 400*1000){
1053                         MMC_DBG_BOOT_FUNC(host->mmc,
1054                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1055                                 clock * 2, mmc_hostname(host->mmc));
1056                         /* clk_mmc will change parents to 24MHz xtal*/
1057                         clk_set_rate(host->clk_mmc, clock * 2);
1058
1059                         div = 0;
1060                         host->set_div = div;
1061                 }
1062                 else
1063                 {
1064                         MMC_DBG_BOOT_FUNC(host->mmc,
1065                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1066                                 mmc_hostname(host->mmc));
1067                         if(div > 1)
1068                         {
1069                                 MMC_DBG_ERR_FUNC(host->mmc,
1070                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1071                                         mmc_hostname(host->mmc));
1072                                  div = 1;
1073                                  host->set_div = div;
1074                                  host->bus_hz = host->set_speed * 2;
1075                                  MMC_DBG_BOOT_FUNC(host->mmc,
1076                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1077                                         div, host->bus_hz, mmc_hostname(host->mmc));
1078                         }
1079                         /* BUG may be here, come on,  Linux BSP engineer looks!
1080                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1081                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1082                            some oops happened like that:
1083                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1084                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1085                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1086                            mmc0: new high speed DDR MMC card at address 0001
1087                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1088                            ....
1089                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1090                            mmcblk0: retrying using single block read
1091                            mmcblk0: error -110 sending status command, retrying
1092
1093                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1094                          */
1095                         if ((div == 0) &&
1096                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1097                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1098                                 /*  Fixup DDR MMC */
1099                                 div = 1;
1100                                 host->set_div = div;
1101                                 host->bus_hz = host->set_speed * 2;
1102                                 MMC_DBG_BOOT_FUNC(host->mmc,
1103                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1104                                         div, host->bus_hz, mmc_hostname(host->mmc));
1105                         }
1106
1107                         if (host->verid < DW_MMC_240A)
1108                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1109                         else
1110                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1111
1112
1113
1114                 }
1115
1116                 /* set clock to desired speed */
1117                 mci_writel(host, CLKDIV, div);
1118
1119                 /* inform CIU */
1120                 mci_send_cmd(slot,
1121                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1122
1123                 /* enable clock; only low power if no SDIO */
1124                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1125
1126                 if (host->verid < DW_MMC_240A)
1127                     sdio_int = SDMMC_INT_SDIO(slot->id);
1128                 else
1129                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1130
1131                 if (!(mci_readl(host, INTMASK) & sdio_int))
1132                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1133                 mci_writel(host, CLKENA, clk_en_a);
1134
1135                 /* inform CIU */
1136                 mci_send_cmd(slot,
1137                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1138                 /* keep the clock with reflecting clock dividor */
1139                 slot->__clk_old = clock << div;
1140         }
1141
1142         host->current_speed = clock;
1143
1144         if(slot->ctype != slot->pre_ctype)
1145                 MMC_DBG_BOOT_FUNC(host->mmc,
1146                                 "Bus speed=%dHz,Bus width=%s.[%s]",
1147                                 host->set_speed,
1148                                 (slot->ctype == SDMMC_CTYPE_4BIT) ? "4bits" : "8bits",
1149                                 mmc_hostname(host->mmc));
1150
1151         slot->pre_ctype = slot->ctype;
1152
1153         /* Set the current slot bus width */
1154         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1155 }
1156
1157 extern struct mmc_card *this_card;
1158 static void dw_mci_wait_unbusy(struct dw_mci *host)
1159 {
1160         unsigned int timeout = SDMMC_DATA_TIMEOUT_SDIO;
1161         unsigned long time_loop;
1162         unsigned int status;
1163         unsigned int tmo = 300000;
1164         /* Secure erase flag */
1165         u32 se_flag = 0;
1166
1167         MMC_DBG_INFO_FUNC(host->mmc,
1168                 "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1169
1170         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1171                 if (host->cmd && (host->cmd->opcode == MMC_ERASE) && this_card) {
1172                 /* Special care for (secure)erase timeout calculation */
1173                         if ((host->cmd->arg & (0x1 << 31)) == 1)
1174                                 se_flag = 0x1;
1175
1176                         if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1177                                 se_flag ?
1178                                 (timeout = (this_card->ext_csd.hc_erase_timeout) *
1179                                 tmo * (this_card->ext_csd.sec_erase_mult)) :
1180                                 (timeout = (this_card->ext_csd.hc_erase_timeout) * tmo);
1181                 }
1182
1183                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1184                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1185         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1186                 timeout = SDMMC_DATA_TIMEOUT_SD;
1187         }
1188
1189         time_loop = jiffies + msecs_to_jiffies(timeout);
1190         do {
1191                 status = mci_readl(host, STATUS);
1192                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1193                         break;
1194         } while (time_before(jiffies, time_loop));
1195 }
1196
1197 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1198 /*
1199 *   result:
1200 *   0--status is busy.
1201 *   1--status is unbusy.
1202 */
1203 int dw_mci_card_busy(struct mmc_host *mmc)
1204 {
1205         struct dw_mci_slot *slot = mmc_priv(mmc);
1206         struct dw_mci *host = slot->host;
1207
1208         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1209                                 host->svi_flags, mmc_hostname(host->mmc));
1210
1211         /* svi toggle*/
1212         if(host->svi_flags == 0){
1213                 /*first svi*/
1214                 host->svi_flags = 1;
1215                 return host->svi_flags;
1216
1217         }else{
1218                 host->svi_flags = 0;
1219                 return host->svi_flags;
1220         }
1221
1222
1223 }
1224 #endif
1225 static void __dw_mci_start_request(struct dw_mci *host,
1226                                    struct dw_mci_slot *slot,
1227                                    struct mmc_command *cmd)
1228 {
1229         struct mmc_request *mrq;
1230         struct mmc_data *data;
1231         u32 cmdflags;
1232
1233         mrq = slot->mrq;
1234         if (host->pdata->select_slot)
1235                 host->pdata->select_slot(slot->id);
1236
1237         host->cur_slot = slot;
1238         host->mrq = mrq;
1239
1240         dw_mci_wait_unbusy(host);
1241
1242         host->pending_events = 0;
1243         host->completed_events = 0;
1244         host->data_status = 0;
1245         host->cmd_status = 0;
1246
1247         data = cmd->data;
1248         if (data) {
1249                 dw_mci_set_timeout(host);
1250                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1251                 mci_writel(host, BLKSIZ, data->blksz);
1252         }
1253
1254         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1255
1256         /* this is the first command, send the initialization clock */
1257         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1258                 cmdflags |= SDMMC_CMD_INIT;
1259
1260         if (data) {
1261                 dw_mci_submit_data(host, data);
1262                 wmb();
1263         }
1264
1265         dw_mci_start_command(host, cmd, cmdflags);
1266
1267         if (mrq->stop)
1268                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1269 }
1270
1271 static void dw_mci_start_request(struct dw_mci *host,
1272                                  struct dw_mci_slot *slot)
1273 {
1274         struct mmc_request *mrq = slot->mrq;
1275         struct mmc_command *cmd;
1276
1277         MMC_DBG_INFO_FUNC(host->mmc,
1278                 " Begin to start the new request. cmd=%d(arg=0x%x)[%s]",
1279                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1280
1281         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1282         __dw_mci_start_request(host, slot, cmd);
1283 }
1284
1285 /* must be called with host->lock held */
1286 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1287                                  struct mmc_request *mrq)
1288 {
1289         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1290                  host->state);
1291
1292         slot->mrq = mrq;
1293
1294         if (host->state == STATE_IDLE) {
1295                 host->state = STATE_SENDING_CMD;
1296                 dw_mci_start_request(host, slot);
1297         } else {
1298                 list_add_tail(&slot->queue_node, &host->queue);
1299         }
1300 }
1301
1302 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1303 {
1304         struct dw_mci_slot *slot = mmc_priv(mmc);
1305         struct dw_mci *host = slot->host;
1306
1307         WARN_ON(slot->mrq);
1308
1309         /*
1310          * The check for card presence and queueing of the request must be
1311          * atomic, otherwise the card could be removed in between and the
1312          * request wouldn't fail until another card was inserted.
1313          */
1314         spin_lock_bh(&host->lock);
1315
1316         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1317                 spin_unlock_bh(&host->lock);
1318                 mrq->cmd->error = -ENOMEDIUM;
1319                 MMC_DBG_CMD_FUNC(host->mmc, "%s: no card,so reqeuest done, cmd=%d [%s]",
1320                                 __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1321
1322                 mmc_request_done(mmc, mrq);
1323                 return;
1324         }
1325
1326         MMC_DBG_CMD_FUNC(host->mmc,
1327                 "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]",
1328                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1329
1330         dw_mci_queue_request(host, slot, mrq);
1331
1332         spin_unlock_bh(&host->lock);
1333 }
1334
1335 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1336 {
1337         struct dw_mci_slot *slot = mmc_priv(mmc);
1338         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1339         struct dw_mci *host = slot->host;
1340         #endif
1341         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1342         u32 regs;
1343
1344         #ifdef SDMMC_WAIT_FOR_UNBUSY
1345         unsigned long   time_loop;
1346         bool ret = true;
1347
1348         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1349         if(host->svi_flags == 1)
1350                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1351         else
1352                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1353         #else
1354                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1355         #endif
1356
1357         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1358                 printk("%d..%s:  no card. [%s]\n", \
1359                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1360                 goto EXIT_POWER;
1361         }
1362
1363         while (ret) {
1364                 ret = time_before(jiffies, time_loop);
1365                 regs = mci_readl(slot->host, STATUS);
1366                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY |
1367                         SDMMC_STAUTS_MC_BUSY)))
1368                         break;
1369         };
1370
1371         if(false == ret)
1372         {
1373                 printk("slot->flags = %lu ", slot->flags);
1374                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1375                 if(host->svi_flags != 1)
1376                 #endif
1377                         dump_stack();
1378                 printk("%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n",
1379                          __FUNCTION__, regs, mmc_hostname(mmc));
1380         }
1381         #endif
1382
1383         switch (ios->bus_width) {
1384         case MMC_BUS_WIDTH_4:
1385                 slot->ctype = SDMMC_CTYPE_4BIT;
1386                 break;
1387         case MMC_BUS_WIDTH_8:
1388                 slot->ctype = SDMMC_CTYPE_8BIT;
1389                 break;
1390         default:
1391                 /* set default 1 bit mode */
1392                 slot->ctype = SDMMC_CTYPE_1BIT;
1393                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1394         }
1395
1396         regs = mci_readl(slot->host, UHS_REG);
1397
1398         /* DDR mode set */
1399         if (ios->timing == MMC_TIMING_UHS_DDR50)
1400                 regs |= ((0x1 << slot->id) << 16);
1401         else
1402                 regs &= ~((0x1 << slot->id) << 16);
1403
1404         mci_writel(slot->host, UHS_REG, regs);
1405         slot->host->timing = ios->timing;
1406
1407         /*
1408          * Use mirror of ios->clock to prevent race with mmc
1409          * core ios update when finding the minimum.
1410          */
1411         slot->clock = ios->clock;
1412
1413         if (drv_data && drv_data->set_ios)
1414                 drv_data->set_ios(slot->host, ios);
1415
1416         /* Slot specific timing and width adjustment */
1417         dw_mci_setup_bus(slot, false);
1418                 //return -EAGAIN;
1419
1420 EXIT_POWER:
1421         switch (ios->power_mode) {
1422         case MMC_POWER_UP:
1423         /* Power up slot */
1424                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1425                 if (slot->host->pdata->setpower)
1426                         slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1427                 regs = mci_readl(slot->host, PWREN);
1428                 regs |= (1 << slot->id);
1429                 mci_writel(slot->host, PWREN, regs);
1430                 break;
1431         case MMC_POWER_OFF:
1432         /* Power down slot */
1433                 if(slot->host->pdata->setpower)
1434                         slot->host->pdata->setpower(slot->id, 0);
1435                 regs = mci_readl(slot->host, PWREN);
1436                 regs &= ~(1 << slot->id);
1437                 mci_writel(slot->host, PWREN, regs);
1438                 break;
1439         default:
1440                 break;
1441         }
1442 }
1443
1444 static int dw_mci_get_ro(struct mmc_host *mmc)
1445 {
1446         int read_only;
1447         struct dw_mci_slot *slot = mmc_priv(mmc);
1448         struct dw_mci_board *brd = slot->host->pdata;
1449
1450         /* Use platform get_ro function, else try on board write protect */
1451         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1452                 read_only = 0;
1453         else if(brd->get_ro)
1454                 read_only = brd->get_ro(slot->id);
1455         else if(gpio_is_valid(slot->wp_gpio))
1456                 read_only = gpio_get_value(slot->wp_gpio);
1457         else
1458                 read_only =
1459                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1460
1461         dev_dbg(&mmc->class_dev, "card is %s\n",
1462                 read_only ? "read-only" : "read-write");
1463
1464         return read_only;
1465 }
1466
1467 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1468 {
1469         struct dw_mci_slot *slot = mmc_priv(mmc);
1470         struct dw_mci *host = slot->host;
1471
1472         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1473                 return 0;
1474
1475         spin_lock_bh(&host->lock);
1476
1477         if(val)
1478                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1479         else
1480                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1481
1482         spin_unlock_bh(&host->lock);
1483
1484         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1485                 if (__clk_is_enabled(host->hclk_mmc) == false)
1486                         clk_prepare_enable(host->hclk_mmc);
1487                 if (__clk_is_enabled(host->clk_mmc) == false)
1488                         clk_prepare_enable(host->clk_mmc);
1489         } else {
1490                 if (__clk_is_enabled(host->clk_mmc) == true)
1491                         clk_disable_unprepare(slot->host->clk_mmc);
1492                 if (__clk_is_enabled(host->hclk_mmc) == true)
1493                         clk_disable_unprepare(slot->host->hclk_mmc);
1494         }
1495
1496         mmc_detect_change(slot->mmc, 20);
1497         return 0;
1498 }
1499
1500
1501
1502 static int dw_mci_get_cd(struct mmc_host *mmc)
1503 {
1504         int present;
1505         struct dw_mci_slot *slot = mmc_priv(mmc);
1506         struct dw_mci_board *brd = slot->host->pdata;
1507         struct dw_mci *host = slot->host;
1508         int gpio_cd = mmc_gpio_get_cd(mmc);
1509         int force_jtag_bit, force_jtag_reg;
1510         int gpio_val;
1511         int irq;
1512
1513         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1514                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1515                 gpio_cd = slot->cd_gpio;
1516                 irq = gpio_to_irq(gpio_cd);
1517                 if (gpio_is_valid(gpio_cd)) {
1518                         gpio_val = gpio_get_value(gpio_cd);
1519                         if (soc_is_rk3036()) {
1520                                 force_jtag_bit = 11;
1521                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1522                         } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1523                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1524                                 force_jtag_bit = 8;
1525                         }
1526                         msleep(10);
1527                         if (gpio_val == gpio_get_value(gpio_cd)) {
1528                                 gpio_cd = (gpio_val == 0 ? 1 : 0);
1529                                 if (gpio_cd == 0) {
1530                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1531                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1532                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1533                                                         force_jtag_reg);
1534                                         dw_mci_ctrl_all_reset(host);
1535                                 } else {
1536                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1537                                         /* Really card detected: SHOULD disable force_jtag */
1538                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1539                                                         force_jtag_reg);
1540                                 }
1541                         } else {
1542                                 /* Jitter */
1543                                 gpio_val = gpio_get_value(gpio_cd);
1544                                 (gpio_val == 0) ?
1545                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
1546                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW  | IRQF_ONESHOT);
1547                                 return slot->last_detect_state;
1548                         }
1549                 } else {
1550                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1551                 }
1552         }
1553
1554         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1555                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1556
1557         /* Use platform get_cd function, else try onboard card detect */
1558         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1559                 present = 1;
1560         else if (brd->get_cd)
1561                 present = !brd->get_cd(slot->id);
1562         else if (!IS_ERR_VALUE(gpio_cd))
1563                 present = gpio_cd;
1564         else
1565                 present = ((mci_readl(slot->host, CDETECT) & (1 << slot->id))
1566                         == 0) ? 1 : 0;
1567
1568         spin_lock_bh(&host->lock);
1569         if (present) {
1570                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1571                 dev_dbg(&mmc->class_dev, "card is present\n");
1572         } else {
1573                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1574                 dev_dbg(&mmc->class_dev, "card is not present\n");
1575         }
1576         spin_unlock_bh(&host->lock);
1577
1578         return present;
1579 }
1580
1581
1582 /*
1583  * Dts Should caps emmc controller with poll-hw-reset
1584  */
1585 static void dw_mci_hw_reset(struct mmc_host *mmc)
1586 {
1587         struct dw_mci_slot *slot = mmc_priv(mmc);
1588         struct dw_mci *host = slot->host;
1589         u32 regs;
1590
1591         #if 0
1592         u32 cmd_flags;
1593         unsigned long timeout;
1594         bool ret = true;
1595
1596         /* (1) CMD12 to end any transfer in process */
1597         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1598                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1599
1600         if(host->mmc->hold_reg_flag)
1601                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1602         mci_writel(host, CMDARG, 0);
1603         wmb();
1604         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1605         wmb();
1606         timeout = jiffies + msecs_to_jiffies(500);
1607         while(ret){
1608                 ret = time_before(jiffies, timeout);
1609                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1610                         break;
1611         }
1612
1613         if(false == ret)
1614                 MMC_DBG_ERR_FUNC(host->mmc,
1615                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1616                         __func__, mmc_hostname(host->mmc));
1617
1618         /* (2) wait DTO, even if no response is sent back by card */
1619         ret = true;
1620         timeout = jiffies + msecs_to_jiffies(5);
1621         while(ret){
1622                 ret = time_before(jiffies, timeout);
1623                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1624                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1625                         break;
1626                 }
1627         }
1628         #endif
1629
1630         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1631
1632         /* Software reset - BMOD[0] for IDMA only */
1633         regs = mci_readl(host, BMOD);
1634         regs |= SDMMC_IDMAC_SWRESET;
1635         mci_writel(host, BMOD, regs);
1636         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1637         regs = mci_readl(host, BMOD);
1638         if(regs & SDMMC_IDMAC_SWRESET)
1639                 MMC_DBG_WARN_FUNC(host->mmc,
1640                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1641                         __func__, mmc_hostname(host->mmc));
1642
1643         /* DMA reset - CTRL[2] */
1644         regs = mci_readl(host, CTRL);
1645         regs |= SDMMC_CTRL_DMA_RESET;
1646         mci_writel(host, CTRL, regs);
1647         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1648         regs = mci_readl(host, CTRL);
1649         if(regs & SDMMC_CTRL_DMA_RESET)
1650                 MMC_DBG_WARN_FUNC(host->mmc,
1651                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1652                         __func__, mmc_hostname(host->mmc));
1653
1654         /* FIFO reset - CTRL[1] */
1655         regs = mci_readl(host, CTRL);
1656         regs |= SDMMC_CTRL_FIFO_RESET;
1657         mci_writel(host, CTRL, regs);
1658         mdelay(1); /* no timing limited, 1ms is random value */
1659         regs = mci_readl(host, CTRL);
1660         if(regs & SDMMC_CTRL_FIFO_RESET)
1661                 MMC_DBG_WARN_FUNC(host->mmc,
1662                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1663                         __func__, mmc_hostname(host->mmc));
1664
1665         /* (4) CARD_RESET
1666         According to eMMC spec
1667         tRstW >= 1us ;   RST_n pulse width
1668         tRSCA >= 200us ; RST_n to Command time
1669         tRSTH >= 1us ;   RST_n high period
1670         */
1671         mci_writel(slot->host, PWREN, 0x0);
1672         mci_writel(slot->host, RST_N, 0x0);
1673         dsb(sy);
1674         udelay(10); /* 10us for bad quality eMMc. */
1675
1676         mci_writel(slot->host, PWREN, 0x1);
1677         mci_writel(slot->host, RST_N, 0x1);
1678         dsb(sy);
1679         usleep_range(500, 1000); /* at least 500(> 200us) */
1680 }
1681
1682 /*
1683  * Disable lower power mode.
1684  *
1685  * Low power mode will stop the card clock when idle.  According to the
1686  * description of the CLKENA register we should disable low power mode
1687  * for SDIO cards if we need SDIO interrupts to work.
1688  *
1689  * This function is fast if low power mode is already disabled.
1690  */
1691 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1692 {
1693         struct dw_mci *host = slot->host;
1694         u32 clk_en_a;
1695         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1696
1697         clk_en_a = mci_readl(host, CLKENA);
1698
1699         if (clk_en_a & clken_low_pwr) {
1700                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1701                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1702                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1703         }
1704 }
1705
1706 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1707 {
1708         struct dw_mci_slot *slot = mmc_priv(mmc);
1709         struct dw_mci *host = slot->host;
1710         unsigned long flags;
1711         u32 int_mask;
1712         u32 sdio_int;
1713
1714         spin_lock_irqsave(&host->slock, flags);
1715
1716         /* Enable/disable Slot Specific SDIO interrupt */
1717         int_mask = mci_readl(host, INTMASK);
1718
1719         if (host->verid < DW_MMC_240A)
1720                 sdio_int = SDMMC_INT_SDIO(slot->id);
1721         else
1722                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1723
1724         if (enb) {
1725                 /*
1726                  * Turn off low power mode if it was enabled.  This is a bit of
1727                  * a heavy operation and we disable / enable IRQs a lot, so
1728                  * we'll leave low power mode disabled and it will get
1729                  * re-enabled again in dw_mci_setup_bus().
1730                  */
1731                 dw_mci_disable_low_power(slot);
1732
1733                 mci_writel(host, INTMASK,
1734                            (int_mask | sdio_int));
1735         } else {
1736                 mci_writel(host, INTMASK,
1737                            (int_mask & ~sdio_int));
1738         }
1739
1740         spin_unlock_irqrestore(&host->slock, flags);
1741 }
1742
1743 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1744 enum{
1745         IO_DOMAIN_12 = 1200,
1746         IO_DOMAIN_18 = 1800,
1747         IO_DOMAIN_33 = 3300,
1748 };
1749 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1750 {
1751         switch(voltage){
1752         case IO_DOMAIN_33:
1753                 voltage = 0;
1754                 break;
1755         case IO_DOMAIN_18:
1756                 voltage = 1;
1757                 break;
1758         case IO_DOMAIN_12:
1759                 MMC_DBG_ERR_FUNC(host->mmc,
1760                         "%s : Not support io domain voltage [%s]\n",
1761                         __FUNCTION__, mmc_hostname(host->mmc));
1762                 break;
1763         default:
1764                 MMC_DBG_ERR_FUNC(host->mmc,
1765                         "%s : Err io domain voltage [%s]\n",
1766                         __FUNCTION__, mmc_hostname(host->mmc));
1767                 break;
1768         }
1769
1770         if (cpu_is_rk3288()) {
1771                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1772                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1773                 else
1774                         return ;
1775         } else if (host->cid == DW_MCI_TYPE_RK3368) {
1776                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1777                          regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1778                 else
1779                         return;
1780         } else {
1781                 MMC_DBG_ERR_FUNC(host->mmc,
1782                         "%s : unknown chip [%s]\n",
1783                         __FUNCTION__, mmc_hostname(host->mmc));
1784         }
1785 }
1786
1787 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1788                                                 struct mmc_ios *ios)
1789 {
1790         int ret;
1791         unsigned int value,uhs_reg;
1792
1793         /*
1794          * Signal Voltage Switching is only applicable for Host Controllers
1795          * v3.00 and above.
1796          */
1797         if (host->verid < DW_MMC_240A)
1798                 return 0;
1799
1800         uhs_reg = mci_readl(host, UHS_REG);
1801         MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: vol=%d.[%s]\n",
1802                  __FUNCTION__, ios->signal_voltage, mmc_hostname(host->mmc));
1803
1804         switch (ios->signal_voltage) {
1805         case MMC_SIGNAL_VOLTAGE_330:
1806         /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1807                 if (host->vmmc) {
1808                         if (cpu_is_rk3288())
1809                                 ret = io_domain_regulator_set_voltage(
1810                                                 host->vmmc, 3300000, 3300000);
1811                         else
1812                                 ret = regulator_set_voltage(host->vmmc,
1813                                                         3300000, 3300000);
1814
1815                         /* regulator_put(host->vmmc); */
1816                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s =%dmV set 3.3 end, ret = %d\n",
1817                                 __func__, regulator_get_voltage(host->vmmc), ret);
1818                         if (ret) {
1819                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1820                                         "%s: Switching to 3.3V signalling voltage "
1821                                         " failed\n", mmc_hostname(host->mmc));
1822                                 return -EIO;
1823                         }
1824                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1825                 }
1826
1827                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: [%s]\n",
1828                                 __FUNCTION__, mmc_hostname(host->mmc));
1829
1830                 /* set High-power mode */
1831                 value = mci_readl(host, CLKENA);
1832                 value &= ~SDMMC_CLKEN_LOW_PWR;
1833                 mci_writel(host,CLKENA , value);
1834                 /* SDMMC_UHS_REG */
1835                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1836                 mci_writel(host,UHS_REG , uhs_reg);
1837
1838                 /* Wait for 5ms */
1839                 usleep_range(5000, 5500);
1840
1841                 /* 3.3V regulator output should be stable within 5 ms */
1842                 uhs_reg = mci_readl(host, UHS_REG);
1843                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1844                         return 0;
1845
1846                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1847                         "%s: 3.3V regulator output did not became stable\n",
1848                         mmc_hostname(host->mmc));
1849
1850                 return -EAGAIN;
1851         case MMC_SIGNAL_VOLTAGE_180:
1852                 if (host->vmmc) {
1853                         if (cpu_is_rk3288())
1854                                 ret = io_domain_regulator_set_voltage(
1855                                         host->vmmc, 1800000, 1800000);
1856                         else
1857                                 ret = regulator_set_voltage(
1858                                                 host->vmmc, 1800000, 1800000);
1859                         /* regulator_put(host->vmmc); */
1860                         MMC_DBG_SW_VOL_FUNC(host->mmc,
1861                                         "%s   =%dmV  set 1.8end, ret=%d . \n",
1862                                         __func__, regulator_get_voltage(host->vmmc), ret);
1863                         if (ret) {
1864                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1865                                         "%s: Switching to 1.8V signalling voltage "
1866                                         " failed\n", mmc_hostname(host->mmc));
1867                                 return -EIO;
1868                         }
1869                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1870                 }
1871
1872                 /*
1873                 * Enable 1.8V Signal Enable in the Host Control2
1874                 * register
1875                 */
1876                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1877
1878                 /* Wait for 5ms */
1879                 usleep_range(5000, 5500);
1880                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%d..%s: .[%s]\n",__LINE__,
1881                                 __FUNCTION__, mmc_hostname(host->mmc));
1882
1883                 /* 1.8V regulator output should be stable within 5 ms */
1884                 uhs_reg = mci_readl(host, UHS_REG);
1885                 if (uhs_reg & SDMMC_UHS_VOLT_REG_18)
1886                         return 0;
1887
1888                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1889                         "%s: 1.8V regulator output did not became stable\n",
1890                         mmc_hostname(host->mmc));
1891
1892                 return -EAGAIN;
1893         case MMC_SIGNAL_VOLTAGE_120:
1894                 if (host->vmmc) {
1895                         if (cpu_is_rk3288())
1896                                 ret = io_domain_regulator_set_voltage(
1897                                         host->vmmc, 1200000, 1200000);
1898                         else
1899                                 ret = regulator_set_voltage(host->vmmc,
1900                                         1200000, 1200000);
1901                         if (ret) {
1902                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1903                                         "%s: Switching to 1.2V signalling voltage "
1904                                         " failed\n", mmc_hostname(host->mmc));
1905                                 return -EIO;
1906                         }
1907                 }
1908                 return 0;
1909         default:
1910                 /* No signal voltage switch required */
1911                 return 0;
1912         }
1913 }
1914
1915
1916 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1917         struct mmc_ios *ios)
1918 {
1919         struct dw_mci_slot *slot = mmc_priv(mmc);
1920         struct dw_mci *host = slot->host;
1921         int err;
1922
1923         if (host->verid < DW_MMC_240A)
1924                 return 0;
1925
1926         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1927         return err;
1928 }
1929
1930 #endif
1931
1932 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1933 {
1934         struct dw_mci_slot *slot = mmc_priv(mmc);
1935         struct dw_mci *host = slot->host;
1936         const struct dw_mci_drv_data *drv_data = host->drv_data;
1937         struct dw_mci_tuning_data tuning_data;
1938         int err = -ENOSYS;
1939
1940         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1941         if(cpu_is_rk3036() || cpu_is_rk312x())
1942                 return err;
1943
1944         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1945                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1946                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1947                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1948                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1949                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1950                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1951                 } else {
1952                         return -EINVAL;
1953                 }
1954         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1955                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1956                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1957         } else {
1958                 dev_err(host->dev,
1959                         "Undefined command(%d) for tuning\n", opcode);
1960                 return -EINVAL;
1961         }
1962
1963         if (drv_data && drv_data->execute_tuning)
1964                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1965
1966         return err;
1967 }
1968
1969 static void dw_mci_post_tmo(struct mmc_host *mmc)
1970 {
1971         struct dw_mci_slot *slot = mmc_priv(mmc);
1972         struct dw_mci *host = slot->host;
1973         u32 i, regs, cmd_flags;
1974         u32 sdio_int;
1975         unsigned long timeout = 0;
1976         bool ret_timeout = true, is_retry = false;
1977         u32 opcode, offset;
1978
1979         if (host->cur_slot->mrq->data)
1980                 dw_mci_stop_dma(host);
1981
1982         offset = host->cru_reset_offset;
1983         opcode = host->mrq->cmd->opcode;
1984         host->cur_slot->mrq = NULL;
1985         host->mrq = NULL;
1986         host->state = STATE_IDLE;
1987         host->data = NULL;
1988
1989         if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
1990             (opcode == MMC_SEND_TUNING_BLOCK))
1991                 return;
1992
1993         printk("[%s] -- Timeout recovery procedure start --\n",
1994                 mmc_hostname(host->mmc));
1995
1996         /* unmask irq */
1997         mci_writel(host, INTMASK, 0x0);
1998
1999 retry_stop:
2000         /* send stop cmd */
2001         mci_writel(host, CMDARG, 0);
2002         wmb();
2003         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2004                         SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2005
2006         if (host->mmc->hold_reg_flag)
2007                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2008
2009         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2010         wmb();
2011         timeout = jiffies + msecs_to_jiffies(10);
2012
2013         while(ret_timeout) {
2014                 ret_timeout = time_before(jiffies, timeout);
2015                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2016                         break;
2017         }
2018
2019         if (false == ret_timeout) {
2020                 MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
2021                                  mmc_hostname(host->mmc));
2022                 if (host->cid == DW_MCI_TYPE_RK3368) {
2023                         /* pd_peri mmc AHB bus software reset request */
2024                         regmap_write(host->cru, host->cru_regsbase,
2025                                         (0x1<<offset)<<16 | (0x1 << offset));
2026                         mdelay(1);
2027                         regmap_write(host->cru, host->cru_regsbase,
2028                                         (0x1<<offset)<<16 | (0x0 << offset));
2029                 } else {
2030                         /* pd_peri mmc AHB bus software reset request */
2031                         cru_writel(((0x1<<offset)<<16) | (0x1 << offset),
2032                                         host->cru_regsbase);
2033                         mdelay(1);
2034                         cru_writel(((0x1<<offset)<<16) | (0x0 << offset),
2035                                         host->cru_regsbase);
2036                 }
2037         } else {
2038                 if (!dw_mci_ctrl_all_reset(host))
2039                         return;
2040                 if (is_retry == true)
2041                         goto recovery_end;
2042         }
2043
2044 #ifdef CONFIG_MMC_DW_IDMAC
2045         if (!(cpu_is_rk3036() || cpu_is_rk312x()))
2046                 if (host->use_dma && host->dma_ops->init)
2047                         host->dma_ops->init(host);
2048 #endif
2049
2050         /*
2051          * Restore the initial value at FIFOTH register
2052          * And Invalidate the prev_blksz with zero
2053          */
2054         mci_writel(host, FIFOTH, host->fifoth_val);
2055         host->prev_blksz = 0;
2056         mci_writel(host, TMOUT, 0xFFFFFFFF);
2057         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2058         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2059                 SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
2060                 DW_MCI_ERROR_FLAGS;
2061         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2062                 regs |= SDMMC_INT_CD;
2063
2064         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2065                 if (host->verid < DW_MMC_240A)
2066                         sdio_int = SDMMC_INT_SDIO(0);
2067                 else
2068                         sdio_int = SDMMC_INT_SDIO(8);
2069
2070                 if (mci_readl(host, INTMASK) & sdio_int)
2071                         regs |= sdio_int;
2072         }
2073
2074         mci_writel(host, INTMASK, regs);
2075         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2076         for (i = 0; i < host->num_slots; i++) {
2077                 struct dw_mci_slot *slot = host->slot[i];
2078                 if (!slot)
2079                         continue;
2080                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2081                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2082                         dw_mci_setup_bus(slot, true);
2083                 }
2084         }
2085         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2086         if (ret_timeout == false) {
2087                 ret_timeout = true;
2088                 is_retry = true;
2089                 goto retry_stop;
2090         }
2091
2092 recovery_end:
2093         printk("[%s] -- Timeout recovery procedure finished --\n",
2094                 mmc_hostname(host->mmc));
2095 }
2096
2097 static const struct mmc_host_ops dw_mci_ops = {
2098         .request                = dw_mci_request,
2099         .pre_req                = dw_mci_pre_req,
2100         .post_req               = dw_mci_post_req,
2101         .set_ios                = dw_mci_set_ios,
2102         .get_ro                 = dw_mci_get_ro,
2103         .get_cd                 = dw_mci_get_cd,
2104         .set_sdio_status        = dw_mci_set_sdio_status,
2105         .hw_reset               = dw_mci_hw_reset,
2106         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
2107         .execute_tuning         = dw_mci_execute_tuning,
2108         .post_tmo               = dw_mci_post_tmo,
2109         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2110         .start_signal_voltage_switch
2111                                 = dw_mci_start_signal_voltage_switch,
2112         .card_busy              = dw_mci_card_busy,
2113         #endif
2114 };
2115
2116 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2117         __releases(&host->lock)
2118         __acquires(&host->lock)
2119 {
2120         if (DW_MCI_SEND_STATUS == host->dir_status){
2121                 dw_mci_wait_unbusy(host);
2122         }
2123 }
2124
2125 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2126         __releases(&host->lock)
2127         __acquires(&host->lock)
2128 {
2129         struct dw_mci_slot *slot;
2130         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2131
2132         //WARN_ON(host->cmd || host->data);
2133
2134         dw_mci_deal_data_end(host, mrq);
2135
2136         if(mrq->cmd)
2137                 MMC_DBG_CMD_FUNC(host->mmc,
2138                         " reqeust end--reqeuest done, cmd=%d, "
2139                         "cmderr=%d, host->state=%d [%s]",
2140                         mrq->cmd->opcode, mrq->cmd->error,
2141                         host->state,mmc_hostname(host->mmc));
2142         if(mrq->data)
2143                 MMC_DBG_CMD_FUNC(host->mmc,
2144                         " reqeust end--reqeuest done, cmd=%d, "
2145                         "dataerr=%d, host->state=%d [%s]",
2146                         mrq->cmd->opcode,mrq->data->error,
2147                         host->state, mmc_hostname(host->mmc));
2148
2149         host->cur_slot->mrq = NULL;
2150         host->mrq = NULL;
2151         if (!list_empty(&host->queue)) {
2152                 slot = list_entry(host->queue.next,
2153                                   struct dw_mci_slot, queue_node);
2154                 list_del(&slot->queue_node);
2155                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2156                          mmc_hostname(slot->mmc));
2157                 host->state = STATE_SENDING_CMD;
2158                 MMC_DBG_CMD_FUNC(host->mmc,
2159                         " list is not empty. run the request in list. [%s]",
2160                         mmc_hostname(host->mmc));
2161                 dw_mci_start_request(host, slot);
2162         } else {
2163                 dev_vdbg(host->dev, "list empty\n");
2164                 host->state = STATE_IDLE;
2165         }
2166
2167         spin_unlock(&host->lock);
2168         mmc_request_done(prev_mmc, mrq);
2169         spin_lock(&host->lock);
2170 }
2171
2172 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2173 {
2174         u32 status = host->cmd_status;
2175
2176         host->cmd_status = 0;
2177
2178         /* Read the response from the card (up to 16 bytes) */
2179         if (cmd->flags & MMC_RSP_PRESENT) {
2180                 if (cmd->flags & MMC_RSP_136) {
2181                         cmd->resp[3] = mci_readl(host, RESP0);
2182                         cmd->resp[2] = mci_readl(host, RESP1);
2183                         cmd->resp[1] = mci_readl(host, RESP2);
2184                         cmd->resp[0] = mci_readl(host, RESP3);
2185
2186             MMC_DBG_INFO_FUNC(host->mmc,
2187                 "Command complete cmd=%d, "
2188                 "resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]",
2189                 cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0],
2190                 mmc_hostname(host->mmc));
2191         } else {
2192                 cmd->resp[0] = mci_readl(host, RESP0);
2193                 cmd->resp[1] = 0;
2194                 cmd->resp[2] = 0;
2195                 cmd->resp[3] = 0;
2196                 MMC_DBG_INFO_FUNC(host->mmc,
2197                         "Command complete cmd=%d,resp[0]=0x%x. [%s]",
2198                         cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2199                 }
2200         }
2201
2202         if (status & SDMMC_INT_RTO)
2203         {
2204                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2205                         host->cmd_rto += 1;
2206
2207                 cmd->error = -ETIMEDOUT;
2208         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2209                 cmd->error = -EILSEQ;
2210         }else if (status & SDMMC_INT_RESP_ERR){
2211                 cmd->error = -EIO;
2212         }else{
2213                 cmd->error = 0;
2214         }
2215
2216         MMC_DBG_CMD_FUNC(host->mmc,
2217                         "Command complete, cmd=%d,cmdError=%d [%s]",
2218                         cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2219
2220         if (cmd->error) {
2221                 if(MMC_SEND_STATUS != cmd->opcode)
2222                         if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2223                                 MMC_DBG_CMD_FUNC(host->mmc,
2224                                         "Command complete, cmd=%d,cmdError=%d [%s]",
2225                                         cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2226                                 host->cmd_rto = 0;
2227                         }
2228
2229                 /* newer ip versions need a delay between retries */
2230                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2231                         mdelay(20);
2232         }
2233 }
2234
2235 static void dw_mci_tasklet_func(unsigned long priv)
2236 {
2237         struct dw_mci *host = (struct dw_mci *)priv;
2238         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2239         struct mmc_data *data;
2240         struct mmc_command *cmd;
2241         enum dw_mci_state state;
2242         enum dw_mci_state prev_state;
2243         u32 status, cmd_flags;
2244         unsigned long timeout = 0;
2245         bool ret = true;
2246
2247         spin_lock(&host->lock);
2248
2249         state = host->state;
2250         data = host->data;
2251
2252         do {
2253                 prev_state = state;
2254
2255                 switch (state) {
2256                 case STATE_IDLE:
2257                         break;
2258
2259                 case STATE_SENDING_CMD:
2260                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2261                                                 &host->pending_events))
2262                                 break;
2263
2264                         cmd = host->cmd;
2265                         host->cmd = NULL;
2266                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2267                         dw_mci_command_complete(host, cmd);
2268                         if (cmd == host->mrq->sbc && !cmd->error) {
2269                                 prev_state = state = STATE_SENDING_CMD;
2270                                 __dw_mci_start_request(host, host->cur_slot,
2271                                                        host->mrq->cmd);
2272                                 goto unlock;
2273                         }
2274
2275                         if (cmd->data && cmd->error) {
2276                                 dw_mci_stop_dma(host);
2277                                 #if 1
2278                                 if (data->stop) {
2279                                         send_stop_cmd(host, data);
2280                                         state = STATE_SENDING_STOP;
2281                                         break;
2282                                 }else{
2283                                        /*  host->data = NULL; */
2284                                 }
2285                                 #else
2286                                 send_stop_abort(host, data);
2287                                 state = STATE_SENDING_STOP;
2288                                 break;
2289                                 #endif
2290                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2291                         }
2292
2293                         if (!host->mrq->data || cmd->error) {
2294                                 dw_mci_request_end(host, host->mrq);
2295                                 goto unlock;
2296                         }
2297
2298                         prev_state = state = STATE_SENDING_DATA;
2299                         /* fall through */
2300
2301                 case STATE_SENDING_DATA:
2302                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2303                                 &host->pending_events)) {
2304                                 dw_mci_stop_dma(host);
2305                                 #if 1
2306                                 if (data->stop){
2307                                         send_stop_cmd(host, data);
2308                                 }else{
2309                                         /*single block read/write, send stop cmd
2310                                         manually to prevent host controller halt*/
2311                                         MMC_DBG_INFO_FUNC(host->mmc,
2312                                                 "%s status 1 0x%08x [%s]\n",
2313                                                 __func__, mci_readl(host, STATUS),
2314                                                 mmc_hostname(host->mmc));
2315
2316                                         mci_writel(host, CMDARG, 0);
2317                                         wmb();
2318                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2319                                                 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2320
2321                                         if(host->mmc->hold_reg_flag)
2322                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2323
2324                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2325                                         wmb();
2326                                         timeout = jiffies + msecs_to_jiffies(500);
2327
2328                                         while(ret) {
2329                                                 ret = time_before(jiffies, timeout);
2330                                                 if (!(mci_readl(host, CMD) & SDMMC_CMD_START))
2331                                                         break;
2332                                         }
2333                                         if(false == ret)
2334                                                 MMC_DBG_ERR_FUNC(host->mmc,
2335                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2336                                                         __func__, mmc_hostname(host->mmc));
2337                                 }
2338                                 #else
2339                                 send_stop_abort(host, data);
2340                                 #endif
2341                                 state = STATE_DATA_ERROR;
2342                                 break;
2343                         }
2344
2345                         MMC_DBG_CMD_FUNC(host->mmc,
2346                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2347                                 "wait for EVENT_XFER_COMPLETE.[%s]",
2348                                 prev_state, state, mmc_hostname(host->mmc));
2349
2350                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2351                                 &host->pending_events))
2352                                 break;
2353                         MMC_DBG_INFO_FUNC(host->mmc,
2354                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2355                                 "wait for EVENT_DATA_COMPLETE. [%s]",
2356                                 prev_state, state, mmc_hostname(host->mmc));
2357
2358                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2359                         prev_state = state = STATE_DATA_BUSY;
2360                         /* fall through */
2361
2362                 case STATE_DATA_BUSY:
2363                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2364                                                 &host->pending_events))
2365                                 break;
2366
2367                         dw_mci_deal_data_end(host, host->mrq);
2368                         MMC_DBG_INFO_FUNC(host->mmc,
2369                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, "
2370                                 "after EVENT_DATA_COMPLETE. [%s]",
2371                                 prev_state, state, mmc_hostname(host->mmc));
2372
2373                         /* host->data = NULL; */
2374                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2375                         status = host->data_status;
2376
2377                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2378                                 if((SDMMC_CTYPE_1BIT != slot->ctype) &&
2379                                         (MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2380                                         MMC_DBG_ERR_FUNC(host->mmc,
2381                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,"
2382                                         "datastatus=0x%x [%s]",
2383                                         prev_state, state, status, mmc_hostname(host->mmc));
2384
2385                         if (status & SDMMC_INT_DRTO) {
2386                                         data->error = -ETIMEDOUT;
2387                                 } else if (status & SDMMC_INT_DCRC) {
2388                                         data->error = -EILSEQ;
2389                                 } else if (status & SDMMC_INT_EBE &&
2390                                 host->dir_status == DW_MCI_SEND_STATUS){
2391                                         /*
2392                                          * No data CRC status was returned.
2393                                          * The number of bytes transferred will
2394                                          * be exaggerated in PIO mode.
2395                                          */
2396                                         data->bytes_xfered = 0;
2397                                         data->error = -ETIMEDOUT;
2398                                 } else {
2399                                         dev_err(host->dev,
2400                                                 "data FIFO error "
2401                                                 "(status=%08x)\n",
2402                                                 status);
2403                                         data->error = -EIO;
2404                                 }
2405                                 /*
2406                                  * After an error, there may be data lingering
2407                                  * in the FIFO, so reset it - doing so
2408                                  * generates a block interrupt, hence setting
2409                                  * the scatter-gather pointer to NULL.
2410                                  */
2411                                 dw_mci_fifo_reset(host);
2412                         } else {
2413                                 data->bytes_xfered = data->blocks * data->blksz;
2414                                 data->error = 0;
2415                         }
2416
2417                         if (!data->stop) {
2418                                 MMC_DBG_CMD_FUNC(host->mmc,
2419                                         "Pre-state[%d]-->NowState[%d]: "
2420                                         "no stop and no dataerr, exit [%s]",
2421                                         prev_state, state, mmc_hostname(host->mmc));
2422                                 dw_mci_request_end(host, host->mrq);
2423                                 goto unlock;
2424                         }
2425                         MMC_DBG_CMD_FUNC(host->mmc,
2426                                 "Pre-state[%d]-->NowState[%d]: begin to stop [%s]",
2427                                 prev_state, state, mmc_hostname(host->mmc));
2428
2429                         if (host->mrq->sbc && !data->error) {
2430                                 data->stop->error = 0;
2431
2432                                 MMC_DBG_CMD_FUNC(host->mmc,
2433                                         "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit [%s]",
2434                                         prev_state,state,mmc_hostname(host->mmc));
2435
2436                                 dw_mci_request_end(host, host->mrq);
2437                                 goto unlock;
2438                         }
2439
2440                         prev_state = state = STATE_SENDING_STOP;
2441                         if (!data->error)
2442                                 send_stop_cmd(host, data);
2443                         /* fall through */
2444                         MMC_DBG_CMD_FUNC(host->mmc,
2445                                 "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP [%s]",
2446                                 prev_state, state, mmc_hostname(host->mmc));
2447
2448                 case STATE_SENDING_STOP:
2449                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2450                                 &host->pending_events))
2451                                 break;
2452
2453                         MMC_DBG_CMD_FUNC(host->mmc,
2454                                 "Pre-state[%d]-->NowState[%d]: begin to send cmd12 [%s]",
2455                                 prev_state, state, mmc_hostname(host->mmc));
2456
2457                         /* CMD error in data command */
2458                         if (host->mrq->cmd->error && host->mrq->data) {
2459                                 dw_mci_fifo_reset(host);
2460                         }
2461
2462                         /*
2463                         host->cmd = NULL;
2464                         host->data = NULL;
2465                         */
2466                         #if 1
2467                         dw_mci_command_complete(host, host->mrq->stop);
2468                         #else
2469                         if (host->mrq->stop)
2470                                 dw_mci_command_complete(host, host->mrq->stop);
2471                         else
2472                                 host->cmd_status = 0;
2473                         #endif
2474
2475                         dw_mci_request_end(host, host->mrq);
2476                         goto unlock;
2477
2478                 case STATE_DATA_ERROR:
2479                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2480                                                 &host->pending_events))
2481                                 break;
2482
2483                         state = STATE_DATA_BUSY;
2484                         break;
2485                 }
2486         } while (state != prev_state);
2487
2488         host->state = state;
2489 unlock:
2490         spin_unlock(&host->lock);
2491 }
2492
2493 /* push final bytes to part_buf, only use during push */
2494 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2495 {
2496         memcpy((void *)&host->part_buf, buf, cnt);
2497         host->part_buf_count = cnt;
2498 }
2499
2500 /* append bytes to part_buf, only use during push */
2501 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2502 {
2503         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2504         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2505         host->part_buf_count += cnt;
2506         return cnt;
2507 }
2508
2509 /* pull first bytes from part_buf, only use during pull */
2510 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2511 {
2512         cnt = min(cnt, (int)host->part_buf_count);
2513         if (cnt) {
2514                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2515                        cnt);
2516                 host->part_buf_count -= cnt;
2517                 host->part_buf_start += cnt;
2518         }
2519         return cnt;
2520 }
2521
2522 /* pull final bytes from the part_buf, assuming it's just been filled */
2523 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2524 {
2525         memcpy(buf, &host->part_buf, cnt);
2526         host->part_buf_start = cnt;
2527         host->part_buf_count = (1 << host->data_shift) - cnt;
2528 }
2529
2530 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2531 {
2532         struct mmc_data *data = host->data;
2533         int init_cnt = cnt;
2534
2535         /* try and push anything in the part_buf */
2536         if (unlikely(host->part_buf_count)) {
2537                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2538                 buf += len;
2539                 cnt -= len;
2540                 if (host->part_buf_count == 2) {
2541                         mci_writew(host, DATA(host->data_offset),
2542                                         host->part_buf16);
2543                         host->part_buf_count = 0;
2544                 }
2545         }
2546 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2547         if (unlikely((unsigned long)buf & 0x1)) {
2548                 while (cnt >= 2) {
2549                         u16 aligned_buf[64];
2550                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2551                         int items = len >> 1;
2552                         int i;
2553                         /* memcpy from input buffer into aligned buffer */
2554                         memcpy(aligned_buf, buf, len);
2555                         buf += len;
2556                         cnt -= len;
2557                         /* push data from aligned buffer into fifo */
2558                         for (i = 0; i < items; ++i)
2559                                 mci_writew(host, DATA(host->data_offset),
2560                                                 aligned_buf[i]);
2561                 }
2562         } else
2563 #endif
2564         {
2565                 u16 *pdata = buf;
2566                 for (; cnt >= 2; cnt -= 2)
2567                         mci_writew(host, DATA(host->data_offset), *pdata++);
2568                 buf = pdata;
2569         }
2570         /* put anything remaining in the part_buf */
2571         if (cnt) {
2572                 dw_mci_set_part_bytes(host, buf, cnt);
2573                  /* Push data if we have reached the expected data length */
2574                 if ((data->bytes_xfered + init_cnt) ==
2575                     (data->blksz * data->blocks))
2576                         mci_writew(host, DATA(host->data_offset),
2577                                    host->part_buf16);
2578         }
2579 }
2580
2581 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2582 {
2583 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2584         if (unlikely((unsigned long)buf & 0x1)) {
2585                 while (cnt >= 2) {
2586                         /* pull data from fifo into aligned buffer */
2587                         u16 aligned_buf[64];
2588                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2589                         int items = len >> 1;
2590                         int i;
2591                         for (i = 0; i < items; ++i)
2592                                 aligned_buf[i] = mci_readw(host,
2593                                                 DATA(host->data_offset));
2594                         /* memcpy from aligned buffer into output buffer */
2595                         memcpy(buf, aligned_buf, len);
2596                         buf += len;
2597                         cnt -= len;
2598                 }
2599         } else
2600 #endif
2601         {
2602                 u16 *pdata = buf;
2603                 for (; cnt >= 2; cnt -= 2)
2604                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2605                 buf = pdata;
2606         }
2607         if (cnt) {
2608                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2609                 dw_mci_pull_final_bytes(host, buf, cnt);
2610         }
2611 }
2612
2613 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2614 {
2615         struct mmc_data *data = host->data;
2616         int init_cnt = cnt;
2617
2618         /* try and push anything in the part_buf */
2619         if (unlikely(host->part_buf_count)) {
2620                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2621                 buf += len;
2622                 cnt -= len;
2623                 if (host->part_buf_count == 4) {
2624                         mci_writel(host, DATA(host->data_offset),
2625                                         host->part_buf32);
2626                         host->part_buf_count = 0;
2627                 }
2628         }
2629 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2630         if (unlikely((unsigned long)buf & 0x3)) {
2631                 while (cnt >= 4) {
2632                         u32 aligned_buf[32];
2633                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2634                         int items = len >> 2;
2635                         int i;
2636                         /* memcpy from input buffer into aligned buffer */
2637                         memcpy(aligned_buf, buf, len);
2638                         buf += len;
2639                         cnt -= len;
2640                         /* push data from aligned buffer into fifo */
2641                         for (i = 0; i < items; ++i)
2642                                 mci_writel(host, DATA(host->data_offset),
2643                                                 aligned_buf[i]);
2644                 }
2645         } else
2646 #endif
2647         {
2648                 u32 *pdata = buf;
2649                 for (; cnt >= 4; cnt -= 4)
2650                         mci_writel(host, DATA(host->data_offset), *pdata++);
2651                 buf = pdata;
2652         }
2653         /* put anything remaining in the part_buf */
2654         if (cnt) {
2655                 dw_mci_set_part_bytes(host, buf, cnt);
2656                  /* Push data if we have reached the expected data length */
2657                 if ((data->bytes_xfered + init_cnt) ==
2658                     (data->blksz * data->blocks))
2659                         mci_writel(host, DATA(host->data_offset),
2660                                    host->part_buf32);
2661         }
2662 }
2663
2664 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2665 {
2666 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2667         if (unlikely((unsigned long)buf & 0x3)) {
2668                 while (cnt >= 4) {
2669                         /* pull data from fifo into aligned buffer */
2670                         u32 aligned_buf[32];
2671                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2672                         int items = len >> 2;
2673                         int i;
2674                         for (i = 0; i < items; ++i)
2675                                 aligned_buf[i] = mci_readl(host,
2676                                                 DATA(host->data_offset));
2677                         /* memcpy from aligned buffer into output buffer */
2678                         memcpy(buf, aligned_buf, len);
2679                         buf += len;
2680                         cnt -= len;
2681                 }
2682         } else
2683 #endif
2684         {
2685                 u32 *pdata = buf;
2686                 for (; cnt >= 4; cnt -= 4)
2687                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2688                 buf = pdata;
2689         }
2690         if (cnt) {
2691                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2692                 dw_mci_pull_final_bytes(host, buf, cnt);
2693         }
2694 }
2695
2696 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2697 {
2698         struct mmc_data *data = host->data;
2699         int init_cnt = cnt;
2700
2701         /* try and push anything in the part_buf */
2702         if (unlikely(host->part_buf_count)) {
2703                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2704                 buf += len;
2705                 cnt -= len;
2706
2707                 if (host->part_buf_count == 8) {
2708                         mci_writeq(host, DATA(host->data_offset),
2709                                         host->part_buf);
2710                         host->part_buf_count = 0;
2711                 }
2712         }
2713 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2714         if (unlikely((unsigned long)buf & 0x7)) {
2715                 while (cnt >= 8) {
2716                         u64 aligned_buf[16];
2717                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2718                         int items = len >> 3;
2719                         int i;
2720                         /* memcpy from input buffer into aligned buffer */
2721                         memcpy(aligned_buf, buf, len);
2722                         buf += len;
2723                         cnt -= len;
2724                         /* push data from aligned buffer into fifo */
2725                         for (i = 0; i < items; ++i)
2726                                 mci_writeq(host, DATA(host->data_offset),
2727                                                 aligned_buf[i]);
2728                 }
2729         } else
2730 #endif
2731         {
2732                 u64 *pdata = buf;
2733                 for (; cnt >= 8; cnt -= 8)
2734                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2735                 buf = pdata;
2736         }
2737         /* put anything remaining in the part_buf */
2738         if (cnt) {
2739                 dw_mci_set_part_bytes(host, buf, cnt);
2740                 /* Push data if we have reached the expected data length */
2741                 if ((data->bytes_xfered + init_cnt) ==
2742                     (data->blksz * data->blocks))
2743                         mci_writeq(host, DATA(host->data_offset),
2744                                    host->part_buf);
2745         }
2746 }
2747
2748 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2749 {
2750 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2751         if (unlikely((unsigned long)buf & 0x7)) {
2752                 while (cnt >= 8) {
2753                         /* pull data from fifo into aligned buffer */
2754                         u64 aligned_buf[16];
2755                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2756                         int items = len >> 3;
2757                         int i;
2758                         for (i = 0; i < items; ++i)
2759                                 aligned_buf[i] = mci_readq(host,
2760                                                 DATA(host->data_offset));
2761                         /* memcpy from aligned buffer into output buffer */
2762                         memcpy(buf, aligned_buf, len);
2763                         buf += len;
2764                         cnt -= len;
2765                 }
2766         } else
2767 #endif
2768         {
2769                 u64 *pdata = buf;
2770                 for (; cnt >= 8; cnt -= 8)
2771                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2772                 buf = pdata;
2773         }
2774         if (cnt) {
2775                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2776                 dw_mci_pull_final_bytes(host, buf, cnt);
2777         }
2778 }
2779
2780 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2781 {
2782         int len;
2783
2784         /* get remaining partial bytes */
2785         len = dw_mci_pull_part_bytes(host, buf, cnt);
2786         if (unlikely(len == cnt))
2787                 return;
2788         buf += len;
2789         cnt -= len;
2790
2791         /* get the rest of the data */
2792         host->pull_data(host, buf, cnt);
2793 }
2794
2795 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2796 {
2797         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2798         void *buf;
2799         unsigned int offset;
2800         struct mmc_data *data = host->data;
2801         int shift = host->data_shift;
2802         u32 status;
2803         unsigned int len;
2804         unsigned int remain, fcnt;
2805
2806         if(!host->mmc->bus_refs){
2807                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2808                 goto host_put;
2809         }
2810         do {
2811                 if (!sg_miter_next(sg_miter))
2812                         goto done;
2813
2814                 host->sg = sg_miter->piter.sg;
2815                 buf = sg_miter->addr;
2816                 remain = sg_miter->length;
2817                 offset = 0;
2818
2819                 do {
2820                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2821                                         << shift) + host->part_buf_count;
2822                         len = min(remain, fcnt);
2823                         if (!len)
2824                                 break;
2825                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2826                         data->bytes_xfered += len;
2827                         offset += len;
2828                         remain -= len;
2829                 } while (remain);
2830
2831                 sg_miter->consumed = offset;
2832                 status = mci_readl(host, MINTSTS);
2833                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2834         /* if the RXDR is ready read again */
2835         } while ((status & SDMMC_INT_RXDR) ||
2836                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2837
2838         if (!remain) {
2839                 if (!sg_miter_next(sg_miter))
2840                         goto done;
2841                 sg_miter->consumed = 0;
2842         }
2843         sg_miter_stop(sg_miter);
2844         return;
2845
2846 done:
2847         sg_miter_stop(sg_miter);
2848 host_put:
2849         host->sg = NULL;
2850         smp_wmb();
2851         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2852 }
2853
2854 static void dw_mci_write_data_pio(struct dw_mci *host)
2855 {
2856         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2857         void *buf;
2858         unsigned int offset;
2859         struct mmc_data *data = host->data;
2860         int shift = host->data_shift;
2861         u32 status;
2862         unsigned int len;
2863         unsigned int fifo_depth = host->fifo_depth;
2864         unsigned int remain, fcnt;
2865
2866         if (!host->mmc->bus_refs){
2867                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2868                 goto host_put;
2869         }
2870
2871         do {
2872                 if (!sg_miter_next(sg_miter))
2873                         goto done;
2874
2875                 host->sg = sg_miter->piter.sg;
2876                 buf = sg_miter->addr;
2877                 remain = sg_miter->length;
2878                 offset = 0;
2879
2880                 do {
2881                         fcnt = ((fifo_depth -
2882                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2883                                         << shift) - host->part_buf_count;
2884                         len = min(remain, fcnt);
2885                         if (!len)
2886                                 break;
2887                         host->push_data(host, (void *)(buf + offset), len);
2888                         data->bytes_xfered += len;
2889                         offset += len;
2890                         remain -= len;
2891                 } while (remain);
2892
2893                 sg_miter->consumed = offset;
2894                 status = mci_readl(host, MINTSTS);
2895                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2896         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2897
2898         if (!remain) {
2899                 if (!sg_miter_next(sg_miter))
2900                         goto done;
2901                 sg_miter->consumed = 0;
2902         }
2903         sg_miter_stop(sg_miter);
2904         return;
2905
2906 done:
2907         sg_miter_stop(sg_miter);
2908 host_put:
2909         host->sg = NULL;
2910         smp_wmb();
2911         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2912 }
2913
2914 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2915 {
2916         if (!host->cmd_status)
2917             host->cmd_status = status;
2918
2919         if (!host->cmd)
2920                 goto cmd_exit;
2921
2922 cmd_exit:
2923         smp_wmb();
2924         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2925         tasklet_schedule(&host->tasklet);
2926 }
2927
2928 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2929 {
2930         struct dw_mci *host = dev_id;
2931         u32 pending, sdio_int;
2932         int i;
2933
2934         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2935
2936         /*
2937         * DTO fix - version 2.10a and below, and only if internal DMA
2938         * is configured.
2939         */
2940         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2941                         if (!pending &&
2942                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2943                                 pending |= SDMMC_INT_DATA_OVER;
2944         }
2945
2946         if (pending) {
2947                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2948                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2949                         host->cmd_status = pending;
2950                         smp_wmb();
2951                         MMC_DBG_INFO_FUNC(host->mmc,
2952                                 "%s cmd_status INT=0x%x,[%s]",
2953                                 __FUNCTION__, host->cmd_status,
2954                                 mmc_hostname(host->mmc));
2955
2956                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2957                 }
2958
2959                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2960                         /* if there is an error report DATA_ERROR */
2961                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2962                         host->data_status = pending;
2963                         smp_wmb();
2964                         printk(KERN_ERR "[%s] Data transmission error !!!!  MINTSTS: [0x%08x]\n",
2965                                mmc_hostname(host->mmc), pending);
2966                         mmc_retune_needed(host->mmc);
2967                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2968
2969                         MMC_DBG_INFO_FUNC(host->mmc,
2970                                 "%s data_status INT=0x%x,[%s]",
2971                                  __FUNCTION__, host->data_status,
2972                                  mmc_hostname(host->mmc));
2973                         tasklet_schedule(&host->tasklet);
2974                 }
2975
2976                 if (pending & SDMMC_INT_DATA_OVER) {
2977                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2978                         MMC_DBG_CMD_FUNC(host->mmc,
2979                                 "SDMMC_INT_DATA_OVER, INT-pending=0x%x [%s]",
2980                                 pending, mmc_hostname(host->mmc));
2981                         if (!host->data_status)
2982                                 host->data_status = pending;
2983                         smp_wmb();
2984                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2985                                 if (host->sg != NULL)
2986                                         dw_mci_read_data_pio(host, true);
2987                         }
2988                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2989                         tasklet_schedule(&host->tasklet);
2990                 }
2991
2992                 if (pending & SDMMC_INT_RXDR) {
2993                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2994                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2995                                 dw_mci_read_data_pio(host, false);
2996                 }
2997
2998                 if (pending & SDMMC_INT_TXDR) {
2999                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
3000                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
3001                                 dw_mci_write_data_pio(host);
3002                 }
3003
3004                 if (pending & SDMMC_INT_VSI) {
3005                         MMC_DBG_SW_VOL_FUNC(host->mmc,
3006                                 "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",
3007                                 pending, mmc_hostname(host->mmc));
3008                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
3009                         dw_mci_cmd_interrupt(host, pending);
3010                 }
3011
3012                 if (pending & SDMMC_INT_CMD_DONE) {
3013                         MMC_DBG_CMD_FUNC(host->mmc,
3014                                 "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",
3015                                 mci_readl(host, CMD), pending, mmc_hostname(host->mmc));
3016                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
3017                         dw_mci_cmd_interrupt(host, pending);
3018                 }
3019
3020                 if (pending & SDMMC_INT_CD) {
3021                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
3022                         MMC_DBG_INFO_FUNC(host->mmc,
3023                                 "SDMMC_INT_CD, INT-pending=0x%x. [%s]",
3024                                 pending, mmc_hostname(host->mmc));
3025                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
3026                         queue_work(host->card_workqueue, &host->card_work);
3027                 }
3028
3029                 if (pending & SDMMC_INT_HLE) {
3030                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
3031                         MMC_DBG_CMD_FUNC(host->mmc,
3032                                 "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",
3033                                 pending, mmc_hostname(host->mmc));
3034
3035                 }
3036
3037                 /* Handle SDIO Interrupts */
3038                 for (i = 0; i < host->num_slots; i++) {
3039                         struct dw_mci_slot *slot = host->slot[i];
3040
3041                         if (host->verid < DW_MMC_240A)
3042                                 sdio_int = SDMMC_INT_SDIO(i);
3043                         else
3044                                 sdio_int = SDMMC_INT_SDIO(i + 8);
3045
3046                         if (pending & sdio_int) {
3047                                 mci_writel(host, RINTSTS, sdio_int);
3048                                 mmc_signal_sdio_irq(slot->mmc);
3049                         }
3050                 }
3051
3052         }
3053
3054 #ifdef CONFIG_MMC_DW_IDMAC
3055         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3056         if (!(cpu_is_rk3036() || cpu_is_rk312x())){
3057                 /* Handle DMA interrupts */
3058                 pending = mci_readl(host, IDSTS);
3059                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3060                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3061                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3062                         host->dma_ops->complete((void *)host);
3063                 }
3064         }
3065 #endif
3066
3067         return IRQ_HANDLED;
3068 }
3069
3070 static void dw_mci_work_routine_card(struct work_struct *work)
3071 {
3072         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3073         int i;
3074
3075         for (i = 0; i < host->num_slots; i++) {
3076                 struct dw_mci_slot *slot = host->slot[i];
3077                 struct mmc_host *mmc = slot->mmc;
3078                 struct mmc_request *mrq;
3079                 int present;
3080
3081                 present = dw_mci_get_cd(mmc);
3082
3083                 /* Card insert, switch data line to uart function, and vice verse.
3084                 ONLY audi chip need switched by software, using udbg tag in dts!
3085                 */
3086                 if (!(IS_ERR(host->pins_udbg)) &&
3087                         !(IS_ERR(host->pins_default))) {
3088                         if (present) {
3089                                 if (pinctrl_select_state(host->pinctrl,
3090                                         host->pins_default) < 0)
3091                                         dev_err(host->dev,
3092                                                 "%s: Default pinctrl setting failed!\n",
3093                                                 mmc_hostname(host->mmc));
3094                         } else {
3095                                 if (pinctrl_select_state(host->pinctrl,
3096                                         host->pins_udbg) < 0)
3097                                         dev_err(host->dev,
3098                                                 "%s: Udbg pinctrl setting failed!\n",
3099                                                 mmc_hostname(host->mmc));
3100                         }
3101                 }
3102
3103                 while (present != slot->last_detect_state) {
3104                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
3105                                 present ? "inserted" : "removed");
3106                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
3107                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
3108
3109                         dw_mci_ctrl_all_reset(host);
3110                         /* Stop edma when rountine card triggered */
3111                         if(cpu_is_rk3036() || cpu_is_rk312x())
3112                                 if(host->dma_ops && host->dma_ops->stop)
3113                                         host->dma_ops->stop(host);
3114                         rk_send_wakeup_key();//wake up system
3115                         spin_lock_bh(&host->lock);
3116
3117                         /* Card change detected */
3118                         slot->last_detect_state = present;
3119
3120                         /* Clean up queue if present */
3121                         mrq = slot->mrq;
3122                         if (mrq) {
3123                                 if (mrq == host->mrq) {
3124                                         host->data = NULL;
3125                                         host->cmd = NULL;
3126
3127                                         switch (host->state) {
3128                                         case STATE_IDLE:
3129                                                 break;
3130                                         case STATE_SENDING_CMD:
3131                                                 mrq->cmd->error = -ENOMEDIUM;
3132                                                 if (!mrq->data)
3133                                                         break;
3134                                                 /* fall through */
3135                                         case STATE_SENDING_DATA:
3136                                                 mrq->data->error = -ENOMEDIUM;
3137                                                 dw_mci_stop_dma(host);
3138                                                 break;
3139                                         case STATE_DATA_BUSY:
3140                                         case STATE_DATA_ERROR:
3141                                                 if (mrq->data->error == -EINPROGRESS)
3142                                                         mrq->data->error = -ENOMEDIUM;
3143                                                 if (!mrq->stop)
3144                                                         break;
3145                                                 /* fall through */
3146                                         case STATE_SENDING_STOP:
3147                                                 mrq->stop->error = -ENOMEDIUM;
3148                                                 break;
3149                                         }
3150
3151                                         dw_mci_request_end(host, mrq);
3152                                 } else {
3153                                         list_del(&slot->queue_node);
3154                                         mrq->cmd->error = -ENOMEDIUM;
3155                                         if (mrq->data)
3156                                                 mrq->data->error = -ENOMEDIUM;
3157                                         if (mrq->stop)
3158                                                 mrq->stop->error = -ENOMEDIUM;
3159
3160                                         MMC_DBG_CMD_FUNC(host->mmc,
3161                                                 "dw_mci_work--reqeuest done, cmd=%d [%s]",
3162                                                 mrq->cmd->opcode, mmc_hostname(mmc));
3163
3164                                         spin_unlock(&host->lock);
3165                                         mmc_request_done(slot->mmc, mrq);
3166                                         spin_lock(&host->lock);
3167                                 }
3168                         }
3169
3170                         /* Power down slot */
3171                         if (present == 0) {
3172                                 /* Clear down the FIFO */
3173                                 dw_mci_fifo_reset(host);
3174 #ifdef CONFIG_MMC_DW_IDMAC
3175                                 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
3176                                         dw_mci_idmac_reset(host);
3177 #endif
3178                         }
3179
3180                         spin_unlock_bh(&host->lock);
3181
3182                         present = dw_mci_get_cd(mmc);
3183                 }
3184
3185                 mmc_detect_change(slot->mmc,
3186                         msecs_to_jiffies(host->pdata->detect_delay_ms));
3187         }
3188 }
3189
3190 #ifdef CONFIG_OF
3191 /* given a slot id, find out the device node representing that slot */
3192 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3193 {
3194         struct device_node *np;
3195         const __be32 *addr;
3196         int len;
3197
3198         if (!dev || !dev->of_node)
3199                 return NULL;
3200
3201         for_each_child_of_node(dev->of_node, np) {
3202                 addr = of_get_property(np, "reg", &len);
3203                 if (!addr || (len < sizeof(int)))
3204                         continue;
3205                 if (be32_to_cpup(addr) == slot)
3206                         return np;
3207         }
3208         return NULL;
3209 }
3210
3211 static struct dw_mci_of_slot_quirks {
3212         char *quirk;
3213         int id;
3214 } of_slot_quirks[] = {
3215         {
3216                 .quirk  = "disable-wp",
3217                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3218         },
3219 };
3220
3221 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3222 {
3223         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3224         int quirks = 0;
3225         int idx;
3226
3227         /* get quirks */
3228         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3229                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3230                         quirks |= of_slot_quirks[idx].id;
3231
3232         return quirks;
3233 }
3234
3235 /* find out bus-width for a given slot */
3236 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3237 {
3238         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3239         u32 bus_wd = 1;
3240
3241         if (!np)
3242                 return 1;
3243
3244         if (of_property_read_u32(np, "bus-width", &bus_wd))
3245                 dev_err(dev, "bus-width property not found, assuming width"
3246                                " as 1\n");
3247         return bus_wd;
3248 }
3249
3250
3251 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3252 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3253 {
3254         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3255         int gpio;
3256
3257         if (!np)
3258                 return -EINVAL;
3259
3260         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3261
3262         /* Having a missing entry is valid; return silently */
3263         if (!gpio_is_valid(gpio))
3264                 return -EINVAL;
3265
3266         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3267                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3268                 return -EINVAL;
3269         }
3270
3271     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3272
3273         return gpio;
3274 }
3275
3276
3277 /* find the write protect gpio for a given slot; or -1 if none specified */
3278 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3279 {
3280         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3281         int gpio;
3282
3283         if (!np)
3284                 return -EINVAL;
3285
3286         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3287
3288         /* Having a missing entry is valid; return silently */
3289         if (!gpio_is_valid(gpio))
3290                 return -EINVAL;
3291
3292         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3293                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3294                 return -EINVAL;
3295         }
3296
3297         return gpio;
3298 }
3299
3300 /* find the cd gpio for a given slot */
3301 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3302                                         struct mmc_host *mmc)
3303 {
3304         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3305         int gpio;
3306
3307         if (!np)
3308                 return;
3309
3310         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3311
3312         /* Having a missing entry is valid; return silently */
3313         if (!gpio_is_valid(gpio))
3314                 return;
3315
3316         if (mmc_gpio_request_cd(mmc, gpio, 0))
3317                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3318 }
3319
3320 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3321 {
3322         struct mmc_host *mmc = dev_id;
3323         struct dw_mci_slot *slot = mmc_priv(mmc);
3324         struct dw_mci *host = slot->host;
3325         int gpio_cd = slot->cd_gpio;
3326
3327         (gpio_get_value(gpio_cd)  == 0) ?
3328                 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
3329                 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3330
3331         /* wakeup system whether gpio debounce or not */
3332         rk_send_wakeup_key();
3333
3334         /* no need to trigger detect flow when rescan is disabled.
3335            This case happended in dpm, that we just wakeup system and
3336            let suspend_post notify callback handle it.
3337          */
3338         if(mmc->rescan_disable == 0)
3339                 queue_work(host->card_workqueue, &host->card_work);
3340         else
3341                 printk("%s: rescan been disabled!\n", __FUNCTION__);
3342
3343         return IRQ_HANDLED;
3344 }
3345
3346 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3347                                         struct mmc_host *mmc)
3348 {
3349         struct dw_mci_slot *slot = mmc_priv(mmc);
3350         struct dw_mci *host = slot->host;
3351         int irq;
3352         int ret;
3353
3354         /* Having a missing entry is valid; return silently */
3355         if (!gpio_is_valid(gpio))
3356                 return;
3357
3358         irq = gpio_to_irq(gpio);
3359         if (irq >= 0) {
3360                 ret = devm_request_threaded_irq(
3361                                         &mmc->class_dev, irq,
3362                                         NULL, dw_mci_gpio_cd_irqt,
3363                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3364                                         "dw_mci_cd", mmc);
3365                 if (ret < 0) {
3366                         irq = ret;
3367                         dev_err(host->dev,
3368                                 "Request cd-gpio %d interrupt error!\n", gpio);
3369                 } else{
3370                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3371                         enable_irq_wake(irq);
3372                 }
3373         } else {
3374                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3375         }
3376 }
3377
3378 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3379                                         struct mmc_host *mmc)
3380 {
3381         if (!gpio_is_valid(gpio))
3382                 return;
3383
3384         if (gpio_to_irq(gpio) >= 0) {
3385                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3386                 devm_gpio_free(&mmc->class_dev, gpio);
3387         }
3388 }
3389 #else /* CONFIG_OF */
3390 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3391 {
3392         return 0;
3393 }
3394 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3395 {
3396         return 1;
3397 }
3398 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3399 {
3400         return NULL;
3401 }
3402 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3403 {
3404         return -EINVAL;
3405 }
3406 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3407                                         struct mmc_host *mmc)
3408 {
3409         return;
3410 }
3411 #endif /* CONFIG_OF */
3412
3413 /* @host: dw_mci host prvdata
3414  * Init pinctrl for each platform. Usually we assign
3415  * "defalut" tag for functional usage, "idle" tag for gpio
3416  * state and "udbg" tag for uart_dbg if any.
3417  */
3418 static void dw_mci_init_pinctrl(struct dw_mci *host)
3419 {
3420         /* Fixme: DON'T TOUCH EMMC SETTING! */
3421         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3422                 return;
3423
3424         /* Get pinctrl for DTS */
3425         host->pinctrl = devm_pinctrl_get(host->dev);
3426         if (IS_ERR(host->pinctrl)) {
3427                 dev_err(host->dev, "%s: No pinctrl used!\n",
3428                                 mmc_hostname(host->mmc));
3429                 return;
3430         }
3431
3432         /* Lookup idle state */
3433         host->pins_idle =
3434                 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_IDLE);
3435         if (IS_ERR(host->pins_idle)) {
3436                 dev_err(host->dev, "%s: No idle tag found!\n",
3437                                 mmc_hostname(host->mmc));
3438         } else {
3439                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3440                         dev_err(host->dev,
3441                                 "%s: Idle pinctrl setting failed!\n",
3442                                 mmc_hostname(host->mmc));
3443         }
3444
3445         /* Lookup default state */
3446         host->pins_default =
3447                 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_DEFAULT);
3448         if (IS_ERR(host->pins_default)) {
3449                 dev_err(host->dev, "%s: No default pinctrl found!\n",
3450                 mmc_hostname(host->mmc));
3451         } else {
3452                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3453                         dev_err(host->dev,
3454                                 "%s:  Default pinctrl setting failed!\n",
3455                                 mmc_hostname(host->mmc));
3456         }
3457
3458         /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3459         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3460                 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3461                 if (IS_ERR(host->pins_udbg)) {
3462                         dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3463                                 mmc_hostname(host->mmc));
3464                 } else {
3465                         if (!dw_mci_get_cd(host->mmc))
3466                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3467                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3468                                                 mmc_hostname(host->mmc));
3469                 }
3470         }
3471 }
3472
3473 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3474                                         unsigned long mode, void *unused)
3475 {
3476         struct mmc_host *host = container_of(
3477                 notify_block, struct mmc_host, pm_notify);
3478         unsigned long flags;
3479
3480         switch (mode) {
3481         case PM_HIBERNATION_PREPARE:
3482         case PM_SUSPEND_PREPARE:
3483                 dev_err(host->parent,
3484                         "dw_mci_pm_notify:  suspend prepare\n");
3485                 spin_lock_irqsave(&host->lock, flags);
3486                 host->rescan_disable = 1;
3487                 spin_unlock_irqrestore(&host->lock, flags);
3488                 if (cancel_delayed_work(&host->detect))
3489                         wake_unlock(&host->detect_wake_lock);
3490                 break;
3491
3492         case PM_POST_SUSPEND:
3493         case PM_POST_HIBERNATION:
3494         case PM_POST_RESTORE:
3495                 dev_err(host->parent,
3496                         "dw_mci_pm_notify:  post suspend\n");
3497                 spin_lock_irqsave(&host->lock, flags);
3498                 host->rescan_disable = 0;
3499                 spin_unlock_irqrestore(&host->lock, flags);
3500                 mmc_detect_change(host, 10);
3501         }
3502
3503         return 0;
3504 }
3505
3506 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3507 {
3508         struct mmc_host *mmc;
3509         struct dw_mci_slot *slot;
3510         const struct dw_mci_drv_data *drv_data = host->drv_data;
3511         int ctrl_id, ret;
3512         u32 freq[2];
3513         u8 bus_width;
3514
3515         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3516         if (!mmc)
3517                 return -ENOMEM;
3518
3519         slot = mmc_priv(mmc);
3520         slot->id = id;
3521         slot->mmc = mmc;
3522         slot->host = host;
3523         host->slot[id] = slot;
3524         host->mmc = mmc;
3525
3526         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3527
3528         mmc->ops = &dw_mci_ops;
3529
3530         if (of_property_read_u32_array(host->dev->of_node,
3531                                        "clock-freq-min-max", freq, 2)) {
3532                 mmc->f_min = DW_MCI_FREQ_MIN;
3533                 mmc->f_max = DW_MCI_FREQ_MAX;
3534
3535                 printk("%s: fmin=%d, fmax=%d [%s]\n",
3536                          __FUNCTION__, mmc->f_min,
3537                          mmc->f_max, mmc_hostname(mmc));
3538         } else {
3539                 mmc->f_min = freq[0];
3540                 mmc->f_max = freq[1];
3541
3542                 printk("%s: fmin=%d, fmax=%d [%s]\n",
3543                          __FUNCTION__, mmc->f_min,
3544                          mmc->f_max, mmc_hostname(mmc));
3545         }
3546
3547         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3548                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3549         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3550                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3551         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3552                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3553
3554         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3555                 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3556                 if (register_pm_notifier(&mmc->pm_notify)) {
3557                         pr_err("dw_mci: register_pm_notifier failed\n");
3558                         goto err_pm_notifier;
3559                 }
3560         }
3561
3562         if (host->cid == DW_MCI_TYPE_RK3368) {
3563                 if (IS_ERR(host->grf))
3564                         pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3565                 else
3566                         /* Disable force_jtag */
3567                         regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3568         } else if (cpu_is_rk3288()) {
3569                 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3570         }
3571
3572         /* We assume only low-level chip use gpio_cd */
3573         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3574                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3575                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3576                 if (gpio_is_valid(slot->cd_gpio)) {
3577                         /* Request gpio int for card detection */
3578                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3579                 } else {
3580                         slot->cd_gpio = -ENODEV;
3581                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3582                 }
3583         }
3584
3585         if (host->pdata->get_ocr)
3586                 mmc->ocr_avail = host->pdata->get_ocr(id);
3587         else
3588         {
3589                 mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
3590                                 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33|
3591                                 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36 |
3592                                 MMC_VDD_26_27 | MMC_VDD_25_26 | MMC_VDD_24_25 |
3593                                 MMC_VDD_23_24 | MMC_VDD_22_23 | MMC_VDD_21_22 |
3594                                 MMC_VDD_20_21 | MMC_VDD_165_195;
3595         }
3596
3597         /*
3598          * Start with slot power disabled, it will be enabled when a card
3599          * is detected.
3600          */
3601         if (host->pdata->setpower)
3602                 host->pdata->setpower(id, 0);
3603
3604         if (host->pdata->caps)
3605                 mmc->caps = host->pdata->caps;
3606
3607         if (host->pdata->pm_caps)
3608                 mmc->pm_caps = host->pdata->pm_caps;
3609
3610         if (host->dev->of_node) {
3611                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3612                 if (ctrl_id < 0)
3613                         ctrl_id = 0;
3614         } else {
3615                 ctrl_id = to_platform_device(host->dev)->id;
3616         }
3617         if (drv_data && drv_data->caps)
3618                 mmc->caps |= drv_data->caps[ctrl_id];
3619         if (drv_data && drv_data->hold_reg_flag)
3620                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3621
3622         /* set the compatibility of driver. */
3623         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3624                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3625
3626         if (host->pdata->caps2)
3627                 mmc->caps2 = host->pdata->caps2;
3628
3629         if (host->pdata->get_bus_wd)
3630                 bus_width = host->pdata->get_bus_wd(slot->id);
3631         else if (host->dev->of_node)
3632                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3633         else
3634                 bus_width = 1;
3635
3636         switch (bus_width) {
3637                 case 8:
3638                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3639                 case 4:
3640                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3641         }
3642
3643         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3644                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3645         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3646                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3647         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3648                 mmc->caps |= MMC_CAP_HW_RESET;
3649         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3650                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3651         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3652                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3653         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3654                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3655         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3656                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3657
3658         /*Assign pm_caps pass to pm_flags*/
3659         mmc->pm_flags = mmc->pm_caps;
3660
3661         if (host->pdata->blk_settings) {
3662                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3663                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3664                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3665                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3666                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3667         } else {
3668                 /* Useful defaults if platform data is unset. */
3669 #ifdef CONFIG_MMC_DW_IDMAC
3670                 mmc->max_segs = host->ring_size;
3671                 mmc->max_blk_size = 65536;
3672                 mmc->max_blk_count = host->ring_size;
3673                 mmc->max_seg_size = 0x1000;
3674                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3675                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3676                         /* fixup for external dmac setting */
3677                         mmc->max_segs = 64;
3678                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3679                         mmc->max_blk_count = 65535;
3680                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3681                         mmc->max_seg_size = mmc->max_req_size;
3682                 }
3683 #else
3684                 mmc->max_segs = 64;
3685                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3686                 mmc->max_blk_count = 512;
3687                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3688                 mmc->max_seg_size = mmc->max_req_size;
3689 #endif /* CONFIG_MMC_DW_IDMAC */
3690
3691         }
3692         /* pwr_en */
3693         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3694
3695         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3696         {
3697                 host->vmmc = NULL;
3698         }else{
3699
3700                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3701                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3702                 else
3703                         host->vmmc = NULL;
3704
3705                 if (IS_ERR(host->vmmc)) {
3706                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3707                         host->vmmc = NULL;
3708                 }else{
3709                         ret = regulator_enable(host->vmmc);
3710                         if (ret) {
3711                                 dev_err(host->dev,
3712                                         "failed to enable regulator: %d\n", ret);
3713                                 host->vmmc = NULL;
3714                                 goto err_setup_bus;
3715                         }
3716                 }
3717         }
3718
3719         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3720
3721         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3722                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3723
3724         dw_mci_init_pinctrl(host);
3725         ret = mmc_add_host(mmc);
3726         if (ret)
3727                 goto err_setup_bus;
3728
3729 #if defined(CONFIG_DEBUG_FS)
3730         dw_mci_init_debugfs(slot);
3731 #endif
3732
3733         /* Card initially undetected */
3734         slot->last_detect_state = 1;
3735
3736         return 0;
3737 err_pm_notifier:
3738         unregister_pm_notifier(&mmc->pm_notify);
3739
3740 err_setup_bus:
3741         if (gpio_is_valid(slot->cd_gpio))
3742                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3743         mmc_free_host(mmc);
3744         return -EINVAL;
3745 }
3746
3747 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3748 {
3749         /* Shutdown detect IRQ */
3750         if (slot->host->pdata->exit)
3751                 slot->host->pdata->exit(id);
3752
3753         /* Debugfs stuff is cleaned up by mmc core */
3754         mmc_remove_host(slot->mmc);
3755         slot->host->slot[id] = NULL;
3756         mmc_free_host(slot->mmc);
3757 }
3758
3759 static void dw_mci_init_dma(struct dw_mci *host)
3760 {
3761         /* Alloc memory for sg translation */
3762         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3763                                           &host->sg_dma, GFP_KERNEL);
3764         if (!host->sg_cpu) {
3765                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3766                         __func__);
3767                 goto no_dma;
3768         }
3769
3770         /* Determine which DMA interface to use */
3771 #if defined(CONFIG_MMC_DW_IDMAC)
3772         if(cpu_is_rk3036() || cpu_is_rk312x()){
3773                 host->dma_ops = &dw_mci_edmac_ops;
3774                 dev_info(host->dev, "Using external DMA controller.\n");
3775         }else{
3776                 host->dma_ops = &dw_mci_idmac_ops;
3777                 dev_info(host->dev, "Using internal DMA controller.\n");
3778         }
3779 #endif
3780
3781         if (!host->dma_ops)
3782                 goto no_dma;
3783
3784         if (host->dma_ops->init && host->dma_ops->start &&
3785             host->dma_ops->stop && host->dma_ops->cleanup) {
3786                 if (host->dma_ops->init(host)) {
3787                         dev_err(host->dev, "%s: Unable to initialize "
3788                                 "DMA Controller.\n", __func__);
3789                         goto no_dma;
3790                 }
3791         } else {
3792                 dev_err(host->dev, "DMA initialization not found.\n");
3793                 goto no_dma;
3794         }
3795
3796         host->use_dma = 1;
3797         return;
3798
3799 no_dma:
3800         dev_info(host->dev, "Using PIO mode.\n");
3801         host->use_dma = 0;
3802         return;
3803 }
3804
3805 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3806 {
3807         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3808         u32 ctrl;
3809
3810         ctrl = mci_readl(host, CTRL);
3811         ctrl |= reset;
3812         mci_writel(host, CTRL, ctrl);
3813
3814         /* wait till resets clear */
3815         do {
3816                 ctrl = mci_readl(host, CTRL);
3817                 if (!(ctrl & reset))
3818                         return true;
3819         } while (time_before(jiffies, timeout));
3820
3821         dev_err(host->dev,
3822                 "Timeout resetting block (ctrl reset %#x)\n",
3823                 ctrl & reset);
3824
3825         return false;
3826 }
3827
3828 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3829 {
3830         /*
3831          * Reseting generates a block interrupt, hence setting
3832          * the scatter-gather pointer to NULL.
3833          */
3834         if (host->sg) {
3835                 sg_miter_stop(&host->sg_miter);
3836                 host->sg = NULL;
3837         }
3838
3839         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3840 }
3841
3842 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3843 {
3844         return dw_mci_ctrl_reset(host,
3845                                  SDMMC_CTRL_FIFO_RESET |
3846                                  SDMMC_CTRL_RESET |
3847                                  SDMMC_CTRL_DMA_RESET);
3848 }
3849
3850 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3851 {
3852         u32 index;
3853         u32 *buffer;
3854
3855         buffer = host->regs_buffer;
3856
3857         for (index = 0; index < DW_REGS_NUM ; index++){
3858                 *buffer = mci_readreg(host, index*4);
3859                 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3860                         dw_mci_regs[index].name, *buffer);
3861                 buffer++;
3862         }
3863
3864         *buffer = mci_readl(host,CDTHRCTL);
3865         MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3866 }
3867
3868 static void dw_mci_rst_post_resume(struct dw_mci *host)
3869 {
3870         u32 index;
3871         u32 *buffer;
3872
3873         buffer = host->regs_buffer;
3874
3875         for (index = 0; index < DW_REGS_NUM; index++){
3876                 mci_writereg(host, index*4, *buffer);
3877                 buffer++;
3878         }
3879         mci_writel(host, CDTHRCTL, *buffer);
3880 }
3881
3882 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3883         .pre_suspend = dw_mci_rst_pre_suspend,
3884         .post_resume = dw_mci_rst_post_resume,
3885 };
3886
3887 #ifdef CONFIG_OF
3888 /*
3889 static struct dw_mci_of_quirks {
3890         char *quirk;
3891         int id;
3892 } of_quirks[] = {
3893         {
3894                 .quirk  = "broken-cd",
3895                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3896         },
3897 };
3898 */
3899 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3900 {
3901         struct dw_mci_board *pdata;
3902         struct device *dev = host->dev;
3903         struct device_node *np = dev->of_node;
3904         const struct dw_mci_drv_data *drv_data = host->drv_data;
3905         int  ret;
3906         u32 clock_frequency;
3907
3908         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3909         if (!pdata) {
3910                 dev_err(dev, "could not allocate memory for pdata\n");
3911                 return ERR_PTR(-ENOMEM);
3912         }
3913
3914         /* find out number of slots supported */
3915         if (of_property_read_u32(dev->of_node, "num-slots",
3916                                 &pdata->num_slots)) {
3917                 dev_info(dev, "num-slots property not found, "
3918                                 "assuming 1 slot is available\n");
3919                 pdata->num_slots = 1;
3920         }
3921
3922         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3923                 dev_info(dev, "fifo-depth property not found, using "
3924                                 "value of FIFOTH register as default\n");
3925
3926         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3927
3928         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3929                 pdata->bus_hz = clock_frequency;
3930
3931         if (drv_data && drv_data->parse_dt) {
3932                 ret = drv_data->parse_dt(host);
3933                 if (ret)
3934                         return ERR_PTR(ret);
3935         }
3936
3937         if (of_find_property(np, "keep-power-in-suspend", NULL))
3938                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3939
3940         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3941                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3942
3943         if (of_find_property(np, "supports-highspeed", NULL))
3944                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3945
3946         if (of_find_property(np, "supports-UHS_SDR104", NULL))
3947                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3948
3949         if (of_find_property(np, "supports-DDR_MODE", NULL))
3950                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3951
3952         if (of_find_property(np, "caps2-mmc-hs200", NULL))
3953                 pdata->caps2 |= MMC_CAP2_HS200;
3954
3955         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3956                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3957
3958         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3959                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3960
3961         if (of_get_property(np, "cd-inverted", NULL))
3962                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3963
3964         if (of_get_property(np, "bootpart-no-access", NULL))
3965                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3966
3967         if (of_get_property(np, "controller-power-down", NULL)) {
3968                 host->regs_buffer =
3969                         (u32 *)devm_kzalloc(host->dev,
3970                                             DW_REGS_SIZE, GFP_KERNEL);
3971                 if (!host->regs_buffer) {
3972                         dev_err(host->dev,
3973                                 "could not allocate memory for regs_buffer\n");
3974                         return ERR_PTR(-ENOMEM);
3975                 }
3976
3977                 host->rst_ops = &dw_mci_pdrst_ops;
3978         }
3979
3980         if (of_get_property(np, "assume_removable", NULL))
3981                 mmc_assume_removable = 0;
3982
3983         if (!of_property_read_u32(np, "cru_regsbase", &host->cru_regsbase)) {
3984                 printk("dw cru_regsbase addr 0x%03x.\n", host->cru_regsbase);
3985         } else {
3986                 pr_err("dw cru_regsbase addr is missing!\n");
3987                 return ERR_PTR(-1);
3988         }
3989
3990         if (!of_property_read_u32(np, "cru_reset_offset", &host->cru_reset_offset)) {
3991                 printk("dw cru_reset_offset val %d.\n", host->cru_reset_offset);
3992         } else {
3993                 pr_err("dw cru_reset_offset val is missing!\n");
3994                 return ERR_PTR(-1);
3995         }
3996
3997         return pdata;
3998 }
3999
4000 #else /* CONFIG_OF */
4001 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
4002 {
4003         return ERR_PTR(-EINVAL);
4004 }
4005 #endif /* CONFIG_OF */
4006
4007 int dw_mci_probe(struct dw_mci *host)
4008 {
4009         const struct dw_mci_drv_data *drv_data = host->drv_data;
4010         int width, i, ret = 0;
4011         u32 fifo_size;
4012         int init_slots = 0;
4013         u32 regs;
4014
4015         if (!host->pdata) {
4016                 host->pdata = dw_mci_parse_dt(host);
4017                 if (IS_ERR(host->pdata)) {
4018                         dev_err(host->dev, "platform data not available\n");
4019                         return -EINVAL;
4020                 }
4021         }
4022
4023         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4024                 dev_err(host->dev,
4025                         "Platform data must supply select_slot function\n");
4026                 return -ENODEV;
4027         }
4028
4029         /*
4030          * In 2.40a spec, Data offset is changed.
4031          * Need to check the version-id and set data-offset for DATA register.
4032          */
4033         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4034         dev_info(host->dev, "Version ID is %04x\n", host->verid);
4035
4036         if (host->verid < DW_MMC_240A)
4037                 host->data_offset = DATA_OFFSET;
4038         else
4039                 host->data_offset = DATA_240A_OFFSET;
4040
4041         //hpclk enable
4042         host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
4043         if (IS_ERR(host->hpclk_mmc)) {
4044                 dev_err(host->dev, "failed to get hpclk_mmc\n");
4045         } else {
4046                 clk_prepare_enable(host->hpclk_mmc);
4047         }
4048
4049         //hclk enable
4050         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
4051         if (IS_ERR(host->hclk_mmc)) {
4052                 dev_err(host->dev, "failed to get hclk_mmc\n");
4053                 ret = PTR_ERR(host->hclk_mmc);
4054                 goto err_hclk_mmc;
4055         }
4056
4057         clk_prepare_enable(host->hclk_mmc);
4058
4059         //mmc clk enable
4060         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
4061         if (IS_ERR(host->clk_mmc)) {
4062                 dev_err(host->dev, "failed to get clk mmc_per\n");
4063                 ret = PTR_ERR(host->clk_mmc);
4064                 goto err_clk_mmc;
4065         }
4066
4067         host->bus_hz = host->pdata->bus_hz;
4068         if (!host->bus_hz) {
4069                 dev_err(host->dev, "Platform data must supply bus speed\n");
4070                 ret = -ENODEV;
4071                 goto err_clk_mmc;
4072         }
4073
4074         if (host->verid < DW_MMC_240A)
4075                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4076         else
4077                 //rockchip: fix divider 2 in clksum before controlller
4078                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4079
4080         if(ret < 0) {
4081                 dev_err(host->dev, "failed to set clk mmc\n");
4082                 goto err_clk_mmc;
4083         }
4084         clk_prepare_enable(host->clk_mmc);
4085
4086         if (drv_data && drv_data->setup_clock) {
4087                 ret = drv_data->setup_clock(host);
4088                 if (ret) {
4089                         dev_err(host->dev,
4090                         "implementation specific clock setup failed\n");
4091                         goto err_clk_mmc;
4092                 }
4093         }
4094
4095         host->quirks = host->pdata->quirks;
4096         host->irq_state = true;
4097         host->set_speed = 0;
4098         host->set_div = 0;
4099         host->svi_flags = 0;
4100
4101         spin_lock_init(&host->lock);
4102         spin_lock_init(&host->slock);
4103
4104         INIT_LIST_HEAD(&host->queue);
4105         /*
4106          * Get the host data width - this assumes that HCON has been set with
4107          * the correct values.
4108          */
4109         i = (mci_readl(host, HCON) >> 7) & 0x7;
4110         if (!i) {
4111                 host->push_data = dw_mci_push_data16;
4112                 host->pull_data = dw_mci_pull_data16;
4113                 width = 16;
4114                 host->data_shift = 1;
4115         } else if (i == 2) {
4116                 host->push_data = dw_mci_push_data64;
4117                 host->pull_data = dw_mci_pull_data64;
4118                 width = 64;
4119                 host->data_shift = 3;
4120         } else {
4121                 /* Check for a reserved value, and warn if it is */
4122                 WARN((i != 1),
4123                      "HCON reports a reserved host data width!\n"
4124                      "Defaulting to 32-bit access.\n");
4125                 host->push_data = dw_mci_push_data32;
4126                 host->pull_data = dw_mci_pull_data32;
4127                 width = 32;
4128                 host->data_shift = 2;
4129         }
4130
4131         /* Reset all blocks */
4132         if (!dw_mci_ctrl_all_reset(host))
4133                 return -ENODEV;
4134
4135         init_dma_attrs(&dw_mci_direct_attrs);
4136         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &dw_mci_direct_attrs);
4137
4138         host->dma_ops = host->pdata->dma_ops;
4139         dw_mci_init_dma(host);
4140
4141         /* Clear the interrupts for the host controller */
4142         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4143         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4144
4145         /* Put in max timeout */
4146         mci_writel(host, TMOUT, 0xFFFFFFFF);
4147
4148         /*
4149          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
4150          *                          Tx Mark = fifo_size / 2 DMA Size = 8
4151          */
4152         if (!host->pdata->fifo_depth) {
4153                 /*
4154                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4155                  * have been overwritten by the bootloader, just like we're
4156                  * about to do, so if you know the value for your hardware, you
4157                  * should put it in the platform data.
4158                  */
4159                 fifo_size = mci_readl(host, FIFOTH);
4160                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4161         } else {
4162                 fifo_size = host->pdata->fifo_depth;
4163         }
4164         host->fifo_depth = fifo_size;
4165         host->fifoth_val =
4166                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4167         mci_writel(host, FIFOTH, host->fifoth_val);
4168
4169         /* disable clock to CIU */
4170         mci_writel(host, CLKENA, 0);
4171         mci_writel(host, CLKSRC, 0);
4172
4173         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4174         host->card_workqueue = alloc_workqueue("dw-mci-card",
4175                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4176         if (!host->card_workqueue) {
4177                 ret = -ENOMEM;
4178                 goto err_dmaunmap;
4179         }
4180         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4181         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4182                                host->irq_flags, "dw-mci", host);
4183         if (ret)
4184                 goto err_workqueue;
4185
4186         if (host->pdata->num_slots)
4187                 host->num_slots = host->pdata->num_slots;
4188         else
4189                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4190
4191         /* We need at least one slot to succeed */
4192         for (i = 0; i < host->num_slots; i++) {
4193                 ret = dw_mci_init_slot(host, i);
4194                 if (ret)
4195                         dev_dbg(host->dev, "slot %d init failed\n", i);
4196                 else
4197                         init_slots++;
4198         }
4199
4200         /*
4201          * Enable interrupts for command done, data over, data empty, card det,
4202          * receive ready and error such as transmit, receive timeout, crc error
4203          */
4204         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4205         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4206                 SDMMC_INT_VSI | SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4207         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4208                 !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4209                 regs |= SDMMC_INT_CD;
4210
4211         mci_writel(host, INTMASK, regs);
4212
4213         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4214
4215         dev_info(host->dev, "DW MMC controller at irq %d, "
4216                  "%d bit host data width, "
4217                  "%u deep fifo\n",
4218                  host->irq, width, fifo_size);
4219
4220         if (init_slots) {
4221                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4222         } else {
4223                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4224                                         "but failed on all\n", host->num_slots);
4225                 goto err_workqueue;
4226         }
4227
4228
4229         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4230                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4231
4232         return 0;
4233
4234 err_workqueue:
4235         destroy_workqueue(host->card_workqueue);
4236
4237 err_dmaunmap:
4238         if (host->use_dma && host->dma_ops->exit)
4239                 host->dma_ops->exit(host);
4240
4241         if (host->vmmc){
4242                 regulator_disable(host->vmmc);
4243                 regulator_put(host->vmmc);
4244         }
4245
4246 err_clk_mmc:
4247         if (!IS_ERR(host->clk_mmc))
4248                 clk_disable_unprepare(host->clk_mmc);
4249 err_hclk_mmc:
4250         if (!IS_ERR(host->hclk_mmc))
4251                 clk_disable_unprepare(host->hclk_mmc);
4252         return ret;
4253 }
4254 EXPORT_SYMBOL(dw_mci_probe);
4255
4256 void dw_mci_remove(struct dw_mci *host)
4257 {
4258         struct mmc_host *mmc = host->mmc;
4259         struct dw_mci_slot *slot = mmc_priv(mmc);
4260         int i;
4261
4262         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4263         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4264
4265         for(i = 0; i < host->num_slots; i++){
4266                 dev_dbg(host->dev, "remove slot %d\n", i);
4267                 if(host->slot[i])
4268                         dw_mci_cleanup_slot(host->slot[i], i);
4269         }
4270
4271         /* disable clock to CIU */
4272         mci_writel(host, CLKENA, 0);
4273         mci_writel(host, CLKSRC, 0);
4274
4275         destroy_workqueue(host->card_workqueue);
4276         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4277                 unregister_pm_notifier(&host->mmc->pm_notify);
4278
4279         if (host->use_dma && host->dma_ops->exit)
4280                 host->dma_ops->exit(host);
4281
4282         if (gpio_is_valid(slot->cd_gpio))
4283                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4284
4285         if (host->vmmc){
4286                 regulator_disable(host->vmmc);
4287                 regulator_put(host->vmmc);
4288         }
4289         if (!IS_ERR(host->clk_mmc))
4290                 clk_disable_unprepare(host->clk_mmc);
4291
4292         if (!IS_ERR(host->hclk_mmc))
4293                 clk_disable_unprepare(host->hclk_mmc);
4294         if (!IS_ERR(host->hpclk_mmc))
4295                 clk_disable_unprepare(host->hpclk_mmc);
4296 }
4297 EXPORT_SYMBOL(dw_mci_remove);
4298
4299
4300
4301 #ifdef CONFIG_PM_SLEEP
4302 /*
4303  * TODO: we should probably disable the clock to the card in the suspend path.
4304  */
4305 extern int get_wifi_chip_type(void);
4306 int dw_mci_suspend(struct dw_mci *host)
4307 {
4308         int present = dw_mci_get_cd(host->mmc);
4309
4310         if((host->mmc->restrict_caps &
4311                 RESTRICT_CARD_TYPE_SDIO) &&
4312                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4313                 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4314                 return 0;
4315
4316         if(host->vmmc)
4317                 regulator_disable(host->vmmc);
4318
4319         /* Only for sdmmc controller */
4320         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4321                 disable_irq(host->irq);
4322                 if (present) {
4323                         if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4324                                 MMC_DBG_ERR_FUNC(host->mmc,
4325                                         "Idle pinctrl setting failed! [%s]",
4326                                         mmc_hostname(host->mmc));
4327                 }
4328
4329                 /* Soc rk3126/3036 already in gpio_cd mode */
4330                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4331                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4332                         enable_irq_wake(host->mmc->slot.cd_irq);
4333                 }
4334         }
4335
4336         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4337         mci_writel(host, INTMASK, 0x00);
4338         mci_writel(host, CTRL, 0x00);
4339
4340         if (host->rst_ops &&
4341                 host->rst_ops->pre_suspend)
4342                 host->rst_ops->pre_suspend(host);
4343
4344         return 0;
4345 }
4346 EXPORT_SYMBOL(dw_mci_suspend);
4347
4348 int dw_mci_resume(struct dw_mci *host)
4349 {
4350         int i, ret;
4351         u32 regs;
4352         struct dw_mci_slot *slot;
4353         int present = dw_mci_get_cd(host->mmc);
4354
4355         if (host->rst_ops &&
4356                 host->rst_ops->post_resume)
4357                 host->rst_ops->post_resume(host);
4358
4359
4360         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4361                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4362                         get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4363                 return 0;
4364
4365         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4366                 slot = mmc_priv(host->mmc);
4367                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4368                         return 0;
4369         }
4370
4371         /*only for sdmmc controller*/
4372         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4373                 /* Soc rk3126/3036 already in gpio_cd mode */
4374                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4375                         disable_irq_wake(host->mmc->slot.cd_irq);
4376                         mmc_gpio_free_cd(host->mmc);
4377                 }
4378
4379                 if (!present) {
4380                         if (!IS_ERR(host->pins_udbg)) {
4381                                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4382                                         MMC_DBG_ERR_FUNC(host->mmc,
4383                                                 "Idle pinctrl setting failed! [%s]",
4384                                                 mmc_hostname(host->mmc));
4385                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4386                                         MMC_DBG_ERR_FUNC(host->mmc,
4387                                                 "Udbg pinctrl setting failed! [%s]",
4388                                                 mmc_hostname(host->mmc));
4389                         } else {
4390                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4391                                         MMC_DBG_ERR_FUNC(host->mmc,
4392                                                 "Default pinctrl setting failed! [%s]",
4393                                                 mmc_hostname(host->mmc));
4394                         }
4395                 } else {
4396                         if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4397                                 MMC_DBG_ERR_FUNC(host->mmc,
4398                                         "Default pinctrl setting failed! [%s]",
4399                                         mmc_hostname(host->mmc));
4400                 }
4401
4402                 /* Disable jtag*/
4403                 if (cpu_is_rk3288())
4404                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4405                 else if (cpu_is_rk3036())
4406                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4407                 else if (cpu_is_rk312x())
4408                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4409                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4410         }
4411         if (host->vmmc){
4412                 ret = regulator_enable(host->vmmc);
4413                 if (ret){
4414                         dev_err(host->dev,
4415                                 "failed to enable regulator: %d\n", ret);
4416                         return ret;
4417                 }
4418         }
4419
4420         if (!dw_mci_ctrl_all_reset(host)){
4421                 ret = -ENODEV;
4422                 return ret;
4423         }
4424
4425         if (!(cpu_is_rk3036() || cpu_is_rk312x()))
4426                 if(host->use_dma && host->dma_ops->init)
4427                         host->dma_ops->init(host);
4428
4429         /*
4430          * Restore the initial value at FIFOTH register
4431          * And Invalidate the prev_blksz with zero
4432          */
4433         mci_writel(host, FIFOTH, host->fifoth_val);
4434         host->prev_blksz = 0;
4435         /* Put in max timeout */
4436         mci_writel(host, TMOUT, 0xFFFFFFFF);
4437
4438         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4439         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4440                 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4441
4442         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4443             regs |= SDMMC_INT_CD;
4444
4445         mci_writel(host, INTMASK, regs);
4446         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4447
4448         /* Only for sdmmc controller */
4449         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
4450                 enable_irq(host->irq);
4451
4452         for (i = 0; i < host->num_slots; i++){
4453                 struct dw_mci_slot *slot = host->slot[i];
4454                 if (!slot)
4455                         continue;
4456                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4457                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4458                         dw_mci_setup_bus(slot, true);
4459                 }
4460         }
4461
4462         return 0;
4463 }
4464 EXPORT_SYMBOL(dw_mci_resume);
4465 #endif /* CONFIG_PM_SLEEP */
4466
4467 static int __init dw_mci_init(void)
4468 {
4469         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4470         pr_info("MHSC version = %s\n", RK_SDMMC_DRIVER_VERSION);
4471         return 0;
4472 }
4473
4474 static void __exit dw_mci_exit(void)
4475 {
4476 }
4477
4478 module_init(dw_mci_init);
4479 module_exit(dw_mci_exit);
4480
4481 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4482 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4483 MODULE_LICENSE("GPL v2");