drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/suspend.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/mmc.h>
  36 #include <linux/mmc/sd.h>
  37 #include <linux/mmc/card.h>
  38 #include <linux/mmc/sdio.h>
  39 #include <linux/mmc/rk_mmc.h>
  40 #include <linux/bitops.h>
  41 #include <linux/regulator/consumer.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/of.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/mmc/slot-gpio.h>
  46 #include <linux/clk-private.h>
  47 #include <linux/rockchip/cpu.h>
  48 #include <linux/rfkill-wlan.h>
  49 #include "rk_sdmmc.h"
  50 #include "rk_sdmmc_dbg.h"
  51 #include <linux/regulator/rockchip_io_vol_domain.h>
  52 #include "../../clk/rockchip/clk-ops.h"
  53
  54 #define RK_SDMMC_DRIVER_VERSION "Ver 1.13 2014-09-05"
  55
  56 /* Common flag combinations */
  57 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  58                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  59                                  SDMMC_INT_EBE)
  60 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  61                                  SDMMC_INT_RESP_ERR)
  62 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  63                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  64 #define DW_MCI_SEND_STATUS      1
  65 #define DW_MCI_RECV_STATUS      2
  66 #define DW_MCI_DMA_THRESHOLD    16
  67
  68 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  69 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  70
  71 /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  72 #define SDMMC_DATA_TIMEOUT_SD   500
  73 #define SDMMC_DATA_TIMEOUT_SDIO 250
  74 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  75
  76 #define SDMMC_CMD_RTO_MAX_HOLD  200
  77 #define SDMMC_WAIT_FOR_UNBUSY   2500
  78
  79 #ifdef CONFIG_MMC_DW_IDMAC
  80 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  81                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  82                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  83                                  SDMMC_IDMAC_INT_TI)
  84
  85 struct idmac_desc {
  86         u32             des0;   /* Control Descriptor */
  87 #define IDMAC_DES0_DIC  BIT(1)
  88 #define IDMAC_DES0_LD   BIT(2)
  89 #define IDMAC_DES0_FD   BIT(3)
  90 #define IDMAC_DES0_CH   BIT(4)
  91 #define IDMAC_DES0_ER   BIT(5)
  92 #define IDMAC_DES0_CES  BIT(30)
  93 #define IDMAC_DES0_OWN  BIT(31)
  94
  95         u32             des1;   /* Buffer sizes */
  96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  97         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  98
  99         u32             des2;   /* buffer 1 physical address */
 100
 101         u32             des3;   /* buffer 2 physical address */
 102 };
 103 #endif /* CONFIG_MMC_DW_IDMAC */
 104
 105 static const u8 tuning_blk_pattern_4bit[] = {
 106         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 107         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 108         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 109         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 110         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 111         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 112         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 113         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 114 };
 115
 116 static const u8 tuning_blk_pattern_8bit[] = {
 117         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 118         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 119         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 120         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 121         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 122         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 123         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 124         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 125         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 126         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 127         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 128         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 129         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 130         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 131         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 132         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 133 };
 134
 135 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 136 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 137 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 138 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 139
 140 /*printk the all register of current host*/
 141 #if 0
 142 static int dw_mci_regs_printk(struct dw_mci *host)
 143 {
 144     struct sdmmc_reg *regs = dw_mci_regs;
 145
 146     while( regs->name != 0 ){
 147         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 148         regs++;
 149     }
 150     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 151     return 0;
 152 }
 153 #endif
 154
 155 #if defined(CONFIG_DEBUG_FS)
 156 static int dw_mci_req_show(struct seq_file *s, void *v)
 157 {
 158         struct dw_mci_slot *slot = s->private;
 159         struct mmc_request *mrq;
 160         struct mmc_command *cmd;
 161         struct mmc_command *stop;
 162         struct mmc_data *data;
 163
 164         /* Make sure we get a consistent snapshot */
 165         spin_lock_bh(&slot->host->lock);
 166         mrq = slot->mrq;
 167
 168         if (mrq) {
 169                 cmd = mrq->cmd;
 170                 data = mrq->data;
 171                 stop = mrq->stop;
 172
 173                 if (cmd)
 174                         seq_printf(s,
 175                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 176                                    cmd->opcode, cmd->arg, cmd->flags,
 177                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 178                                    cmd->resp[2], cmd->error);
 179                 if (data)
 180                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 181                                    data->bytes_xfered, data->blocks,
 182                                    data->blksz, data->flags, data->error);
 183                 if (stop)
 184                         seq_printf(s,
 185                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 186                                    stop->opcode, stop->arg, stop->flags,
 187                                    stop->resp[0], stop->resp[1], stop->resp[2],
 188                                    stop->resp[2], stop->error);
 189         }
 190
 191         spin_unlock_bh(&slot->host->lock);
 192
 193         return 0;
 194 }
 195
 196 static int dw_mci_req_open(struct inode *inode, struct file *file)
 197 {
 198         return single_open(file, dw_mci_req_show, inode->i_private);
 199 }
 200
 201 static const struct file_operations dw_mci_req_fops = {
 202         .owner          = THIS_MODULE,
 203         .open           = dw_mci_req_open,
 204         .read           = seq_read,
 205         .llseek         = seq_lseek,
 206         .release        = single_release,
 207 };
 208
 209 static int dw_mci_regs_show(struct seq_file *s, void *v)
 210 {
 211         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 212         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 213         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 214         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 215         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 216         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 217
 218         return 0;
 219 }
 220
 221 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 222 {
 223         return single_open(file, dw_mci_regs_show, inode->i_private);
 224 }
 225
 226 static const struct file_operations dw_mci_regs_fops = {
 227         .owner          = THIS_MODULE,
 228         .open           = dw_mci_regs_open,
 229         .read           = seq_read,
 230         .llseek         = seq_lseek,
 231         .release        = single_release,
 232 };
 233
 234 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 235 {
 236         struct mmc_host *mmc = slot->mmc;
 237         struct dw_mci *host = slot->host;
 238         struct dentry *root;
 239         struct dentry *node;
 240
 241         root = mmc->debugfs_root;
 242         if (!root)
 243                 return;
 244
 245         node = debugfs_create_file("regs", S_IRUSR, root, host,
 246                                    &dw_mci_regs_fops);
 247         if (!node)
 248                 goto err;
 249
 250         node = debugfs_create_file("req", S_IRUSR, root, slot,
 251                                    &dw_mci_req_fops);
 252         if (!node)
 253                 goto err;
 254
 255         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 256         if (!node)
 257                 goto err;
 258
 259         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 260                                   (u32 *)&host->pending_events);
 261         if (!node)
 262                 goto err;
 263
 264         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 265                                   (u32 *)&host->completed_events);
 266         if (!node)
 267                 goto err;
 268
 269         return;
 270
 271 err:
 272         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 273 }
 274 #endif /* defined(CONFIG_DEBUG_FS) */
 275
 276 static void dw_mci_set_timeout(struct dw_mci *host)
 277 {
 278         /* timeout (maximum) */
 279         mci_writel(host, TMOUT, 0xffffffff);
 280 }
 281
 282 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 283 {
 284         struct mmc_data *data;
 285         struct dw_mci_slot *slot = mmc_priv(mmc);
 286         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 287         u32 cmdr;
 288         cmd->error = -EINPROGRESS;
 289
 290         cmdr = cmd->opcode;
 291
 292         if (cmdr == MMC_STOP_TRANSMISSION)
 293                 cmdr |= SDMMC_CMD_STOP;
 294         else
 295                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 296
 297         if (cmd->flags & MMC_RSP_PRESENT) {
 298                 /* We expect a response, so set this bit */
 299                 cmdr |= SDMMC_CMD_RESP_EXP;
 300                 if (cmd->flags & MMC_RSP_136)
 301                         cmdr |= SDMMC_CMD_RESP_LONG;
 302         }
 303
 304         if (cmd->flags & MMC_RSP_CRC)
 305                 cmdr |= SDMMC_CMD_RESP_CRC;
 306
 307         data = cmd->data;
 308         if (data) {
 309                 cmdr |= SDMMC_CMD_DAT_EXP;
 310                 if (data->flags & MMC_DATA_STREAM)
 311                         cmdr |= SDMMC_CMD_STRM_MODE;
 312                 if (data->flags & MMC_DATA_WRITE)
 313                         cmdr |= SDMMC_CMD_DAT_WR;
 314         }
 315
 316         if (drv_data && drv_data->prepare_command)
 317                 drv_data->prepare_command(slot->host, &cmdr);
 318
 319         return cmdr;
 320 }
 321
 322 #if 0
 323 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 324 {
 325         struct mmc_command *stop;
 326         u32 cmdr;
 327
 328         if (!cmd->data)
 329                 return 0;
 330
 331         stop = &host->stop_abort;
 332         cmdr = cmd->opcode;
 333         memset(stop, 0, sizeof(struct mmc_command));
 334
 335         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 336             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 337             cmdr == MMC_WRITE_BLOCK ||
 338             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 339                 stop->opcode = MMC_STOP_TRANSMISSION;
 340                 stop->arg = 0;
 341                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 342         } else if (cmdr == SD_IO_RW_EXTENDED) {
 343                 stop->opcode = SD_IO_RW_DIRECT;
 344                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 345                              ((cmd->arg >> 28) & 0x7);
 346                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 347         } else {
 348                 return 0;
 349         }
 350
 351         cmdr = stop->opcode | SDMMC_CMD_STOP |
 352                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 353
 354         return cmdr;
 355 }
 356 #endif
 357 static void dw_mci_start_command(struct dw_mci *host,
 358                                  struct mmc_command *cmd, u32 cmd_flags)
 359 {
 360         struct dw_mci_slot *slot = host->slot[0];
 361         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 362
 363         host->pre_cmd = host->cmd;
 364         host->cmd = cmd;
 365         dev_vdbg(host->dev,
 366                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 367                 cmd->arg, cmd_flags);
 368
 369         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 370                 /*confirm non-low-power mode*/
 371                 mci_writel(host, CMDARG, 0);
 372                 dw_mci_disable_low_power(slot);
 373
 374                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 375                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 376
 377                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 378         }
 379
 380         mci_writel(host, CMDARG, cmd->arg);
 381         wmb();
 382
 383         /* fix the value to 1 in some Soc,for example RK3188. */
 384         if(host->mmc->hold_reg_flag)
 385                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 386
 387         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 388         wmb();
 389 }
 390
 391 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 392 {
 393         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 394 }
 395
 396 /* DMA interface functions */
 397 static void dw_mci_stop_dma(struct dw_mci *host)
 398 {
 399         if (host->using_dma) {
 400                 /* Fixme: No need to terminate edma, may cause flush op */
 401                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 402                         host->dma_ops->stop(host);
 403                 host->dma_ops->cleanup(host);
 404         }
 405
 406         /* Data transfer was stopped by the interrupt handler */
 407         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 408 }
 409
 410 static int dw_mci_get_dma_dir(struct mmc_data *data)
 411 {
 412         if (data->flags & MMC_DATA_WRITE)
 413                 return DMA_TO_DEVICE;
 414         else
 415                 return DMA_FROM_DEVICE;
 416 }
 417
 418 #ifdef CONFIG_MMC_DW_IDMAC
 419 static void dw_mci_dma_cleanup(struct dw_mci *host)
 420 {
 421         struct mmc_data *data = host->data;
 422
 423         if (data)
 424                 if (!data->host_cookie)
 425                         dma_unmap_sg(host->dev,
 426                                      data->sg,
 427                                      data->sg_len,
 428                                      dw_mci_get_dma_dir(data));
 429 }
 430
 431 static void dw_mci_idmac_reset(struct dw_mci *host)
 432 {
 433         u32 bmod = mci_readl(host, BMOD);
 434         /* Software reset of DMA */
 435         bmod |= SDMMC_IDMAC_SWRESET;
 436         mci_writel(host, BMOD, bmod);
 437 }
 438
 439 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 440 {
 441         u32 temp;
 442
 443         /* Disable and reset the IDMAC interface */
 444         temp = mci_readl(host, CTRL);
 445         temp &= ~SDMMC_CTRL_USE_IDMAC;
 446         temp |= SDMMC_CTRL_DMA_RESET;
 447         mci_writel(host, CTRL, temp);
 448
 449         /* Stop the IDMAC running */
 450         temp = mci_readl(host, BMOD);
 451         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 452         temp |= SDMMC_IDMAC_SWRESET;
 453         mci_writel(host, BMOD, temp);
 454 }
 455
 456 static void dw_mci_idmac_complete_dma(void *arg)
 457 {
 458         struct dw_mci *host = arg;
 459         struct mmc_data *data = host->data;
 460
 461         dev_vdbg(host->dev, "DMA complete\n");
 462
 463         /*
 464         MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 465                 host->mrq->cmd->opcode,host->mrq->cmd->arg,
 466                 data->blocks,data->blksz,mmc_hostname(host->mmc));
 467         */
 468
 469         host->dma_ops->cleanup(host);
 470
 471         /*
 472          * If the card was removed, data will be NULL. No point in trying to
 473          * send the stop command or waiting for NBUSY in this case.
 474          */
 475         if(data){
 476                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 477                 tasklet_schedule(&host->tasklet);
 478         }
 479 }
 480
 481 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 482                                     unsigned int sg_len)
 483 {
 484         int i;
 485         struct idmac_desc *desc = host->sg_cpu;
 486
 487         for (i = 0; i < sg_len; i++, desc++) {
 488                 unsigned int length = sg_dma_len(&data->sg[i]);
 489                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 490
 491                 /* Set the OWN bit and disable interrupts for this descriptor */
 492                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 493
 494                 /* Buffer length */
 495                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 496
 497                 /* Physical address to DMA to/from */
 498                 desc->des2 = mem_addr;
 499         }
 500
 501         /* Set first descriptor */
 502         desc = host->sg_cpu;
 503         desc->des0 |= IDMAC_DES0_FD;
 504
 505         /* Set last descriptor */
 506         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 507         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 508         desc->des0 |= IDMAC_DES0_LD;
 509
 510         wmb();
 511 }
 512
 513 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 514 {
 515         u32 temp;
 516
 517         dw_mci_translate_sglist(host, host->data, sg_len);
 518
 519         /* Select IDMAC interface */
 520         temp = mci_readl(host, CTRL);
 521         temp |= SDMMC_CTRL_USE_IDMAC;
 522         mci_writel(host, CTRL, temp);
 523
 524         wmb();
 525
 526         /* Enable the IDMAC */
 527         temp = mci_readl(host, BMOD);
 528         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 529         mci_writel(host, BMOD, temp);
 530
 531         /* Start it running */
 532         mci_writel(host, PLDMND, 1);
 533 }
 534
 535 static int dw_mci_idmac_init(struct dw_mci *host)
 536 {
 537         struct idmac_desc *p;
 538         int i;
 539
 540         /* Number of descriptors in the ring buffer */
 541         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 542
 543         /* Forward link the descriptor list */
 544         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 545                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 546
 547         /* Set the last descriptor as the end-of-ring descriptor */
 548         p->des3 = host->sg_dma;
 549         p->des0 = IDMAC_DES0_ER;
 550
 551         dw_mci_idmac_reset(host);
 552
 553         /* Mask out interrupts - get Tx & Rx complete only */
 554         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 555         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 556                    SDMMC_IDMAC_INT_TI);
 557
 558         /* Set the descriptor base address */
 559         mci_writel(host, DBADDR, host->sg_dma);
 560         return 0;
 561 }
 562
 563 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 564         .init = dw_mci_idmac_init,
 565         .start = dw_mci_idmac_start_dma,
 566         .stop = dw_mci_idmac_stop_dma,
 567         .complete = dw_mci_idmac_complete_dma,
 568         .cleanup = dw_mci_dma_cleanup,
 569 };
 570
 571
 572 static void dw_mci_edma_cleanup(struct dw_mci *host)
 573 {
 574         struct mmc_data *data = host->data;
 575
 576         if (data)
 577                 if (!data->host_cookie)
 578                         dma_unmap_sg(host->dev,
 579                                         data->sg, data->sg_len,
 580                                         dw_mci_get_dma_dir(data));
 581 }
 582
 583 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 584 {
 585         dmaengine_terminate_all(host->dms->ch);
 586 }
 587
 588 static void dw_mci_edmac_complete_dma(void *arg)
 589 {
 590         struct dw_mci *host = arg;
 591         struct mmc_data *data = host->data;
 592
 593         dev_vdbg(host->dev, "DMA complete\n");
 594
 595         if(data)
 596                 if(data->flags & MMC_DATA_READ)
 597                         /* Invalidate cache after read */
 598                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 599                                 data->sg_len, DMA_FROM_DEVICE);
 600
 601         host->dma_ops->cleanup(host);
 602
 603         /*
 604          * If the card was removed, data will be NULL. No point in trying to
 605          * send the stop command or waiting for NBUSY in this case.
 606          */
 607         if (data) {
 608                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 609                 tasklet_schedule(&host->tasklet);
 610         }
 611 }
 612
 613 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 614 {
 615         struct dma_slave_config slave_config;
 616         struct dma_async_tx_descriptor *desc = NULL;
 617         struct scatterlist *sgl = host->data->sg;
 618         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 619         u32 sg_elems = host->data->sg_len;
 620         u32 fifoth_val, mburst;
 621         int ret = 0;
 622
 623         /* Set external dma config: burst size, burst width*/
 624         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 625         slave_config.src_addr = slave_config.dst_addr;
 626         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 627         slave_config.src_addr_width = slave_config.dst_addr_width;
 628
 629         /* Match FIFO dma burst MSIZE with external dma config*/
 630         fifoth_val = mci_readl(host, FIFOTH);
 631         mburst = mszs[(fifoth_val >> 28) & 0x7];
 632
 633         /* edmac limit burst to 16 */
 634         slave_config.dst_maxburst = (mburst > 16) ? 16 : mburst;
 635         slave_config.src_maxburst = slave_config.dst_maxburst;
 636
 637         if(host->data->flags & MMC_DATA_WRITE){
 638                 slave_config.direction = DMA_MEM_TO_DEV;
 639                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 640                 if(ret){
 641                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 642                         return;
 643                 }
 644
 645                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 646                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 647                 if(!desc){
 648                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 649                         return;
 650                 }
 651                 /* Set dw_mci_edmac_complete_dma as callback */
 652                 desc->callback = dw_mci_edmac_complete_dma;
 653                 desc->callback_param = (void *)host;
 654                 dmaengine_submit(desc);
 655
 656                 /* Flush cache before write */
 657                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 658                                         sg_elems, DMA_TO_DEVICE);
 659                 dma_async_issue_pending(host->dms->ch);
 660         }else{
 661                 /* MMC_DATA_READ*/
 662                 slave_config.direction = DMA_DEV_TO_MEM;
 663                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 664                 if(ret){
 665                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 666                         return;
 667                 }
 668                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 669                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 670                 if(!desc){
 671                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 672                         return;
 673                 }
 674                 /* set dw_mci_edmac_complete_dma as callback */
 675                 desc->callback = dw_mci_edmac_complete_dma;
 676                 desc->callback_param = (void *)host;
 677                 dmaengine_submit(desc);
 678                 dma_async_issue_pending(host->dms->ch);
 679         }
 680 }
 681
 682 static int dw_mci_edmac_init(struct dw_mci *host)
 683 {
 684         /* Request external dma channel, SHOULD decide chn in dts */
 685         host->dms = NULL;
 686         host->dms = (struct dw_mci_dma_slave *)kmalloc
 687                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 688         if (NULL == host->dms) {
 689                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 690                 goto err_exit;
 691         }
 692
 693         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 694         if (!host->dms->ch) {
 695                 dev_err(host->dev, "Failed to get external DMA channel: channel id = %d\n",
 696                                 host->dms->ch->chan_id);
 697                 goto err_exit;
 698         }
 699
 700         return 0;
 701
 702 err_exit:
 703         if (NULL != host->dms) {
 704                 kfree(host->dms);
 705                 host->dms = NULL;
 706         }
 707         return -ENXIO;
 708
 709 }
 710
 711 static void dw_mci_edmac_exit(struct dw_mci *host)
 712 {
 713         if (NULL != host->dms) {
 714                 if (NULL != host->dms->ch) {
 715                         dma_release_channel(host->dms->ch);
 716                         host->dms->ch = NULL;
 717                 }
 718                 kfree(host->dms);
 719                 host->dms = NULL;
 720         }
 721 }
 722
 723 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 724         .init = dw_mci_edmac_init,
 725         .exit = dw_mci_edmac_exit,
 726         .start = dw_mci_edmac_start_dma,
 727         .stop = dw_mci_edmac_stop_dma,
 728         .complete = dw_mci_edmac_complete_dma,
 729         .cleanup = dw_mci_edma_cleanup,
 730 };
 731 #endif /* CONFIG_MMC_DW_IDMAC */
 732
 733 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 734                                    struct mmc_data *data,
 735                                    bool next)
 736 {
 737         struct scatterlist *sg;
 738         unsigned int i, sg_len;
 739
 740         if (!next && data->host_cookie)
 741                 return data->host_cookie;
 742
 743         /*
 744          * We don't do DMA on "complex" transfers, i.e. with
 745          * non-word-aligned buffers or lengths. Also, we don't bother
 746          * with all the DMA setup overhead for short transfers.
 747          */
 748         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 749                 return -EINVAL;
 750
 751         if (data->blksz & 3)
 752                 return -EINVAL;
 753
 754         for_each_sg(data->sg, sg, data->sg_len, i) {
 755                 if (sg->offset & 3 || sg->length & 3)
 756                         return -EINVAL;
 757         }
 758
 759         sg_len = dma_map_sg(host->dev,
 760                             data->sg,
 761                             data->sg_len,
 762                             dw_mci_get_dma_dir(data));
 763         if (sg_len == 0)
 764                 return -EINVAL;
 765
 766         if (next)
 767                 data->host_cookie = sg_len;
 768
 769         return sg_len;
 770 }
 771
 772 static void dw_mci_pre_req(struct mmc_host *mmc,
 773                            struct mmc_request *mrq,
 774                            bool is_first_req)
 775 {
 776         struct dw_mci_slot *slot = mmc_priv(mmc);
 777         struct mmc_data *data = mrq->data;
 778
 779         if (!slot->host->use_dma || !data)
 780                 return;
 781
 782         if (data->host_cookie) {
 783                 data->host_cookie = 0;
 784                 return;
 785         }
 786
 787         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 788                 data->host_cookie = 0;
 789 }
 790
 791 static void dw_mci_post_req(struct mmc_host *mmc,
 792                             struct mmc_request *mrq,
 793                             int err)
 794 {
 795         struct dw_mci_slot *slot = mmc_priv(mmc);
 796         struct mmc_data *data = mrq->data;
 797
 798         if (!slot->host->use_dma || !data)
 799                 return;
 800
 801         if (data->host_cookie)
 802                 dma_unmap_sg(slot->host->dev,
 803                              data->sg,
 804                              data->sg_len,
 805                              dw_mci_get_dma_dir(data));
 806         data->host_cookie = 0;
 807 }
 808
 809 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 810 {
 811 #ifdef CONFIG_MMC_DW_IDMAC
 812         unsigned int blksz = data->blksz;
 813         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 814         u32 fifo_width = 1 << host->data_shift;
 815         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 816         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 817         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 818
 819         tx_wmark = (host->fifo_depth) / 2;
 820         tx_wmark_invers = host->fifo_depth - tx_wmark;
 821
 822         /*
 823          * MSIZE is '1',
 824          * if blksz is not a multiple of the FIFO width
 825          */
 826         if (blksz % fifo_width) {
 827                 msize = 0;
 828                 rx_wmark = 1;
 829                 goto done;
 830         }
 831
 832         do {
 833                 if (!((blksz_depth % mszs[idx]) ||
 834                      (tx_wmark_invers % mszs[idx]))) {
 835                         msize = idx;
 836                         rx_wmark = mszs[idx] - 1;
 837                         break;
 838                 }
 839         } while (--idx > 0);
 840         /*
 841          * If idx is '0', it won't be tried
 842          * Thus, initial values are uesed
 843          */
 844 done:
 845         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 846         mci_writel(host, FIFOTH, fifoth_val);
 847
 848 #endif
 849 }
 850
 851 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 852 {
 853         unsigned int blksz = data->blksz;
 854         u32 blksz_depth, fifo_depth;
 855         u16 thld_size;
 856
 857         WARN_ON(!(data->flags & MMC_DATA_READ));
 858
 859         if (host->timing != MMC_TIMING_MMC_HS200 &&
 860             host->timing != MMC_TIMING_UHS_SDR104)
 861                 goto disable;
 862
 863         blksz_depth = blksz / (1 << host->data_shift);
 864         fifo_depth = host->fifo_depth;
 865
 866         if (blksz_depth > fifo_depth)
 867                 goto disable;
 868
 869         /*
 870          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 871          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 872          * Currently just choose blksz.
 873          */
 874         thld_size = blksz;
 875         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 876         return;
 877
 878 disable:
 879         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 880 }
 881
 882 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 883 {
 884         int sg_len;
 885         unsigned long flags;
 886         u32 temp;
 887
 888         host->using_dma = 0;
 889
 890         /* If we don't have a channel, we can't do DMA */
 891         if (!host->use_dma)
 892                 return -ENODEV;
 893
 894         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 895         if (sg_len < 0) {
 896                 /* Fixme: No need terminate edma, may cause flush op */
 897                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 898                         host->dma_ops->stop(host);
 899                 return sg_len;
 900         }
 901
 902         host->using_dma = 1;
 903
 904         dev_vdbg(host->dev,
 905                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 906                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 907                  sg_len);
 908
 909         /*
 910          * Decide the MSIZE and RX/TX Watermark.
 911          * If current block size is same with previous size,
 912          * no need to update fifoth.
 913          */
 914         if (host->prev_blksz != data->blksz)
 915                 dw_mci_adjust_fifoth(host, data);
 916
 917         /* Reset DMA FIFO*/
 918         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 919
 920         /* Enable the DMA interface */
 921         temp = mci_readl(host, CTRL);
 922         temp |= SDMMC_CTRL_DMA_ENABLE;
 923         mci_writel(host, CTRL, temp);
 924
 925         /* Disable RX/TX IRQs, let DMA handle it */
 926         spin_lock_irqsave(&host->slock, flags);
 927         temp = mci_readl(host, INTMASK);
 928         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 929         mci_writel(host, INTMASK, temp);
 930         spin_unlock_irqrestore(&host->slock, flags);
 931
 932         host->dma_ops->start(host, sg_len);
 933
 934         return 0;
 935 }
 936
 937 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 938 {
 939         u32 temp;
 940         unsigned long flag;
 941
 942         data->error = -EINPROGRESS;
 943
 944         WARN_ON(host->data);
 945         host->sg = NULL;
 946         host->data = data;
 947
 948         /* Reset FIFO*/
 949         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
 950
 951         if (data->flags & MMC_DATA_READ) {
 952                 host->dir_status = DW_MCI_RECV_STATUS;
 953                 dw_mci_ctrl_rd_thld(host, data);
 954         } else {
 955                 host->dir_status = DW_MCI_SEND_STATUS;
 956         }
 957
 958     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
 959          data->blocks, data->blksz, mmc_hostname(host->mmc));
 960
 961         if (dw_mci_submit_data_dma(host, data)) {
 962                 int flags = SG_MITER_ATOMIC;
 963                 if (host->data->flags & MMC_DATA_READ)
 964                         flags |= SG_MITER_TO_SG;
 965                 else
 966                         flags |= SG_MITER_FROM_SG;
 967
 968                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 969                 host->sg = data->sg;
 970                 host->part_buf_start = 0;
 971                 host->part_buf_count = 0;
 972
 973                 spin_lock_irqsave(&host->slock, flag);
 974                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 975                 temp = mci_readl(host, INTMASK);
 976                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 977                 mci_writel(host, INTMASK, temp);
 978                 spin_unlock_irqrestore(&host->slock, flag);
 979
 980                 temp = mci_readl(host, CTRL);
 981                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 982                 mci_writel(host, CTRL, temp);
 983
 984                 /*
 985                  * Use the initial fifoth_val for PIO mode.
 986                  * If next issued data may be transfered by DMA mode,
 987                  * prev_blksz should be invalidated.
 988                  */
 989                 mci_writel(host, FIFOTH, host->fifoth_val);
 990                 host->prev_blksz = 0;
 991         } else {
 992                 /*
 993                  * Keep the current block size.
 994                  * It will be used to decide whether to update
 995                  * fifoth register next time.
 996                  */
 997                 host->prev_blksz = data->blksz;
 998         }
 999 }
1000
1001 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1002 {
1003         struct dw_mci *host = slot->host;
1004         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
1005         unsigned int cmd_status = 0;
1006 #ifdef SDMMC_WAIT_FOR_UNBUSY
1007         bool ret = true;
1008         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1009
1010     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1011         while (ret) {
1012                 ret =  time_before(jiffies, timeout);
1013                 cmd_status = mci_readl(host, STATUS);
1014                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1015                         break;
1016         } ;
1017         if(false == ret)
1018             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
1019                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
1020     }
1021 #endif
1022         mci_writel(host, CMDARG, arg);
1023         wmb();
1024         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1025         if(cmd & SDMMC_CMD_UPD_CLK)
1026                 timeout = jiffies + msecs_to_jiffies(50);
1027         else
1028                 timeout = jiffies + msecs_to_jiffies(500);
1029         while (time_before(jiffies, timeout)) {
1030                 cmd_status = mci_readl(host, CMD);
1031                 if (!(cmd_status & SDMMC_CMD_START))
1032                         return ;
1033         }
1034         dev_err(&slot->mmc->class_dev,
1035                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1036                 cmd, arg, cmd_status);
1037 }
1038
1039 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1040 {
1041         struct dw_mci *host = slot->host;
1042         unsigned int tempck,clock = slot->clock;
1043         u32 div;
1044         u32 clk_en_a;
1045         u32 sdio_int;
1046
1047         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
1048                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
1049
1050         if (!clock) {
1051                 mci_writel(host, CLKENA, 0);
1052                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1053                 if(host->svi_flags == 0)
1054                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1055                 #else
1056                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1057                 #endif
1058         } else if (clock != host->current_speed || force_clkinit) {
1059                 div = host->bus_hz / clock;
1060                 if (host->bus_hz % clock && host->bus_hz > clock)
1061                         /*
1062                          * move the + 1 after the divide to prevent
1063                          * over-clocking the card.
1064                          */
1065                         div += 1;
1066
1067                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1068
1069                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1070                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1071                         dev_info(&slot->mmc->class_dev,
1072                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1073                                  slot->id, host->bus_hz, clock,
1074                                  tempck, div);
1075
1076                         host->set_speed = tempck;
1077                         host->set_div = div;
1078                 }
1079
1080                 /* disable clock */
1081                 mci_writel(host, CLKENA, 0);
1082                 mci_writel(host, CLKSRC, 0);
1083
1084                 /* inform CIU */
1085                 mci_send_cmd(slot,
1086                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1087
1088                 if(clock <= 400*1000){
1089                         MMC_DBG_BOOT_FUNC(host->mmc,
1090                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1091                                 clock * 2, mmc_hostname(host->mmc));
1092                         /* clk_mmc will change parents to 24MHz xtal*/
1093                         clk_set_rate(host->clk_mmc, clock * 2);
1094
1095                         div = 0;
1096                         host->set_div = div;
1097                 }
1098                 else
1099                 {
1100                         MMC_DBG_BOOT_FUNC(host->mmc,
1101                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1102                                 mmc_hostname(host->mmc));
1103                         if(div > 1)
1104                         {
1105                                 MMC_DBG_ERR_FUNC(host->mmc,
1106                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1107                                         mmc_hostname(host->mmc));
1108                                  div = 1;
1109                                  host->set_div = div;
1110                                  host->bus_hz = host->set_speed * 2;
1111                                  MMC_DBG_BOOT_FUNC(host->mmc,
1112                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1113                                         div, host->bus_hz, mmc_hostname(host->mmc));
1114                         }
1115                         /* BUG may be here, come on,  Linux BSP engineer looks!
1116                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1117                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1118                            some oops happened like that:
1119                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1120                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1121                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1122                            mmc0: new high speed DDR MMC card at address 0001
1123                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1124                            ....
1125                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1126                            mmcblk0: retrying using single block read
1127                            mmcblk0: error -110 sending status command, retrying
1128
1129                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1130                          */
1131                         if ((div == 0) &&
1132                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1133                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1134                                 /*  Fixup DDR MMC */
1135                                 div = 1;
1136                                 host->set_div = div;
1137                                 host->bus_hz = host->set_speed * 2;
1138                                 MMC_DBG_BOOT_FUNC(host->mmc,
1139                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1140                                         div, host->bus_hz, mmc_hostname(host->mmc));
1141                         }
1142
1143                         if (host->verid < DW_MMC_240A)
1144                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1145                         else
1146                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1147
1148
1149
1150                 }
1151
1152                 /* set clock to desired speed */
1153                 mci_writel(host, CLKDIV, div);
1154
1155                 /* inform CIU */
1156                 mci_send_cmd(slot,
1157                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1158
1159                 /* enable clock; only low power if no SDIO */
1160                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1161
1162                 if (host->verid < DW_MMC_240A)
1163                     sdio_int = SDMMC_INT_SDIO(slot->id);
1164                 else
1165                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1166
1167                 if (!(mci_readl(host, INTMASK) & sdio_int))
1168                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1169                 mci_writel(host, CLKENA, clk_en_a);
1170
1171                 /* inform CIU */
1172                 mci_send_cmd(slot,
1173                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1174                 /* keep the clock with reflecting clock dividor */
1175                 slot->__clk_old = clock << div;
1176         }
1177
1178         host->current_speed = clock;
1179
1180     if(slot->ctype != slot->pre_ctype)
1181         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
1182             host->set_speed,
1183             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
1184             mmc_hostname(host->mmc));
1185     slot->pre_ctype = slot->ctype;
1186
1187         /* Set the current slot bus width */
1188         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1189 }
1190
1191 extern struct mmc_card *this_card;
1192 static void dw_mci_wait_unbusy(struct dw_mci *host)
1193 {
1194
1195         unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1196         unsigned long   time_loop;
1197         unsigned int    status;
1198         u32 se_flag = 0;
1199
1200         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1201
1202         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1203                 if (host->cmd && (host->cmd->opcode == MMC_ERASE)) {
1204                 /* Special care for (secure)erase timeout calculation */
1205                         if(this_card){
1206                                 if((host->cmd->arg & (0x1 << 31)) == 1) /* secure erase */
1207                                         se_flag = 0x1;
1208
1209                                 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1210                                         se_flag ? (timeout = (this_card->ext_csd.hc_erase_timeout) *
1211                                                         300000 * (this_card->ext_csd.sec_erase_mult)) :
1212                                                         (timeout = (this_card->ext_csd.hc_erase_timeout) * 300000);
1213                         }
1214                 }
1215
1216                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1217                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1218         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1219                 timeout = SDMMC_DATA_TIMEOUT_SD;
1220         }
1221
1222         time_loop = jiffies + msecs_to_jiffies(timeout);
1223         do {
1224                 status = mci_readl(host, STATUS);
1225                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1226                         break;
1227         } while (time_before(jiffies, time_loop));
1228 }
1229
1230
1231
1232 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1233 /*
1234 *   result:
1235 *   0--status is busy.
1236 *   1--status is unbusy.
1237 */
1238 int dw_mci_card_busy(struct mmc_host *mmc)
1239 {
1240         struct dw_mci_slot *slot = mmc_priv(mmc);
1241         struct dw_mci *host = slot->host;
1242
1243         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1244                                 host->svi_flags, mmc_hostname(host->mmc));
1245
1246         /* svi toggle*/
1247         if(host->svi_flags == 0){
1248                 /*first svi*/
1249                 host->svi_flags = 1;
1250                 return host->svi_flags;
1251
1252         }else{
1253                 host->svi_flags = 0;
1254                 return host->svi_flags;
1255         }
1256
1257
1258 }
1259 #endif
1260 static void __dw_mci_start_request(struct dw_mci *host,
1261                                    struct dw_mci_slot *slot,
1262                                    struct mmc_command *cmd)
1263 {
1264         struct mmc_request *mrq;
1265         struct mmc_data *data;
1266         u32 cmdflags;
1267
1268         mrq = slot->mrq;
1269         if (host->pdata->select_slot)
1270                 host->pdata->select_slot(slot->id);
1271
1272         host->cur_slot = slot;
1273         host->mrq = mrq;
1274
1275         dw_mci_wait_unbusy(host);
1276
1277         host->pending_events = 0;
1278         host->completed_events = 0;
1279         host->data_status = 0;
1280
1281         data = cmd->data;
1282         if (data) {
1283                 dw_mci_set_timeout(host);
1284                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1285                 mci_writel(host, BLKSIZ, data->blksz);
1286         }
1287
1288         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1289
1290         /* this is the first command, send the initialization clock */
1291         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1292                 cmdflags |= SDMMC_CMD_INIT;
1293
1294         if (data) {
1295                 dw_mci_submit_data(host, data);
1296                 wmb();
1297         }
1298
1299         dw_mci_start_command(host, cmd, cmdflags);
1300
1301         if (mrq->stop)
1302                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1303 }
1304
1305 static void dw_mci_start_request(struct dw_mci *host,
1306                                  struct dw_mci_slot *slot)
1307 {
1308         struct mmc_request *mrq = slot->mrq;
1309         struct mmc_command *cmd;
1310
1311         MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1312                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1313
1314         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1315         __dw_mci_start_request(host, slot, cmd);
1316 }
1317
1318 /* must be called with host->lock held */
1319 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1320                                  struct mmc_request *mrq)
1321 {
1322         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1323                  host->state);
1324
1325         slot->mrq = mrq;
1326
1327         if (host->state == STATE_IDLE) {
1328                 host->state = STATE_SENDING_CMD;
1329                 dw_mci_start_request(host, slot);
1330         } else {
1331                 list_add_tail(&slot->queue_node, &host->queue);
1332         }
1333 }
1334
1335 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1336 {
1337         struct dw_mci_slot *slot = mmc_priv(mmc);
1338         struct dw_mci *host = slot->host;
1339
1340         WARN_ON(slot->mrq);
1341
1342         /*
1343          * The check for card presence and queueing of the request must be
1344          * atomic, otherwise the card could be removed in between and the
1345          * request wouldn't fail until another card was inserted.
1346          */
1347         spin_lock_bh(&host->lock);
1348
1349         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1350                 spin_unlock_bh(&host->lock);
1351                 mrq->cmd->error = -ENOMEDIUM;
1352                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1353                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1354
1355                 mmc_request_done(mmc, mrq);
1356                 return;
1357         }
1358
1359         MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1360                                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1361
1362         dw_mci_queue_request(host, slot, mrq);
1363
1364         spin_unlock_bh(&host->lock);
1365 }
1366
1367 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1368 {
1369         struct dw_mci_slot *slot = mmc_priv(mmc);
1370         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1371         struct dw_mci *host = slot->host;
1372         #endif
1373         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1374         u32 regs;
1375
1376         #ifdef SDMMC_WAIT_FOR_UNBUSY
1377         unsigned long   time_loop;
1378         bool ret = true;
1379
1380         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1381         if(host->svi_flags == 1)
1382                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1383         else
1384                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1385         #else
1386                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1387         #endif
1388
1389         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1390                 printk("%d..%s:  no card. [%s]\n", \
1391                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1392                 goto EXIT_POWER;
1393         }
1394
1395         while (ret) {
1396                 ret = time_before(jiffies, time_loop);
1397                 regs = mci_readl(slot->host, STATUS);
1398                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1399                         break;
1400         };
1401
1402         if(false == ret)
1403         {
1404                 printk("slot->flags = %lu ", slot->flags);
1405                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1406                 if(host->svi_flags != 1)
1407                 #endif
1408                         dump_stack();
1409                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1410                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1411         }
1412         #endif
1413
1414         switch (ios->bus_width) {
1415         case MMC_BUS_WIDTH_4:
1416                 slot->ctype = SDMMC_CTYPE_4BIT;
1417                 break;
1418         case MMC_BUS_WIDTH_8:
1419                 slot->ctype = SDMMC_CTYPE_8BIT;
1420                 break;
1421         default:
1422                 /* set default 1 bit mode */
1423                 slot->ctype = SDMMC_CTYPE_1BIT;
1424                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1425         }
1426
1427         regs = mci_readl(slot->host, UHS_REG);
1428
1429         /* DDR mode set */
1430         if (ios->timing == MMC_TIMING_UHS_DDR50)
1431                 regs |= ((0x1 << slot->id) << 16);
1432         else
1433                 regs &= ~((0x1 << slot->id) << 16);
1434
1435         mci_writel(slot->host, UHS_REG, regs);
1436         slot->host->timing = ios->timing;
1437
1438         /*
1439          * Use mirror of ios->clock to prevent race with mmc
1440          * core ios update when finding the minimum.
1441          */
1442         slot->clock = ios->clock;
1443
1444         if (drv_data && drv_data->set_ios)
1445                 drv_data->set_ios(slot->host, ios);
1446
1447         /* Slot specific timing and width adjustment */
1448         dw_mci_setup_bus(slot, false);
1449                 //return -EAGAIN;
1450
1451 EXIT_POWER:
1452         switch (ios->power_mode) {
1453                 case MMC_POWER_UP:
1454                         set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1455                         /* Power up slot */
1456                         if (slot->host->pdata->setpower)
1457                                 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1458                         regs = mci_readl(slot->host, PWREN);
1459                         regs |= (1 << slot->id);
1460                         mci_writel(slot->host, PWREN, regs);
1461                         break;
1462                 case MMC_POWER_OFF:
1463                         /* Power down slot */
1464                         if(slot->host->pdata->setpower)
1465                                 slot->host->pdata->setpower(slot->id, 0);
1466                         regs = mci_readl(slot->host, PWREN);
1467                         regs &= ~(1 << slot->id);
1468                         mci_writel(slot->host, PWREN, regs);
1469                         break;
1470                 default:
1471                         break;
1472         }
1473 }
1474
1475 static int dw_mci_get_ro(struct mmc_host *mmc)
1476 {
1477         int read_only;
1478         struct dw_mci_slot *slot = mmc_priv(mmc);
1479         struct dw_mci_board *brd = slot->host->pdata;
1480
1481         /* Use platform get_ro function, else try on board write protect */
1482         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1483                 read_only = 0;
1484         else if(brd->get_ro)
1485                 read_only = brd->get_ro(slot->id);
1486         else if(gpio_is_valid(slot->wp_gpio))
1487                 read_only = gpio_get_value(slot->wp_gpio);
1488         else
1489                 read_only =
1490                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1491
1492         dev_dbg(&mmc->class_dev, "card is %s\n",
1493                 read_only ? "read-only" : "read-write");
1494
1495         return read_only;
1496 }
1497
1498 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1499 {
1500         struct dw_mci_slot *slot = mmc_priv(mmc);
1501         struct dw_mci *host = slot->host;
1502         /*struct dw_mci_board *brd = slot->host->pdata;*/
1503
1504         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1505                 return 0;
1506
1507         spin_lock_bh(&host->lock);
1508
1509         if(val)
1510                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1511         else
1512                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1513
1514         spin_unlock_bh(&host->lock);
1515
1516         if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1517                 if(__clk_is_enabled(host->hclk_mmc) == false)
1518                         clk_prepare_enable(host->hclk_mmc);
1519                 if(__clk_is_enabled(host->clk_mmc) == false)
1520                         clk_prepare_enable(host->clk_mmc);
1521         }else{
1522                 if(__clk_is_enabled(host->clk_mmc) == true)
1523                         clk_disable_unprepare(slot->host->clk_mmc);
1524                 if(__clk_is_enabled(host->hclk_mmc) == true)
1525                         clk_disable_unprepare(slot->host->hclk_mmc);
1526         }
1527
1528         mmc_detect_change(slot->mmc, 20);
1529         return 0;
1530 }
1531
1532
1533
1534 static int dw_mci_get_cd(struct mmc_host *mmc)
1535 {
1536         int present;
1537         struct dw_mci_slot *slot = mmc_priv(mmc);
1538         struct dw_mci_board *brd = slot->host->pdata;
1539         struct dw_mci *host = slot->host;
1540         int gpio_cd = mmc_gpio_get_cd(mmc);
1541         int gpio_val;
1542
1543         if ((soc_is_rk3126() || soc_is_rk3126b()) &&
1544                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1545                 gpio_cd = slot->cd_gpio;
1546                 if (gpio_is_valid(gpio_cd)) {
1547                         gpio_val = gpio_get_value(gpio_cd);
1548                         msleep(10);
1549                         if (gpio_val == gpio_get_value(gpio_cd)) {
1550                                 gpio_cd = (gpio_val == 0 ? 1 : 0);
1551                                 if (gpio_cd == 0) {
1552                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1553                                         grf_writel((0x1 << 24) | (1 << 8), RK312X_GRF_SOC_CON0);
1554                                         dw_mci_ctrl_all_reset(host);
1555                                 } else {
1556                                         /* Really card detected: SHOULD disable force_jtag */
1557                                         grf_writel((0x1 << 24) | (0 << 8), RK312X_GRF_SOC_CON0);
1558                                 }
1559                         } else {
1560                                 /* Jitter */
1561                                 return slot->last_detect_state;
1562                         }
1563                 } else {
1564                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1565                 }
1566         }
1567
1568         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1569                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1570
1571         /* Use platform get_cd function, else try onboard card detect */
1572         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1573                 present = 1;
1574         else if (brd->get_cd)
1575                 present = !brd->get_cd(slot->id);
1576         else if (!IS_ERR_VALUE(gpio_cd))
1577                 present = gpio_cd;
1578         else
1579                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1580                         == 0 ? 1 : 0;
1581
1582         spin_lock_bh(&host->lock);
1583         if (present) {
1584                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1585                 dev_dbg(&mmc->class_dev, "card is present\n");
1586         } else {
1587                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1588                 dev_dbg(&mmc->class_dev, "card is not present\n");
1589         }
1590         spin_unlock_bh(&host->lock);
1591
1592         return present;
1593 }
1594
1595
1596 /*
1597  * Dts Should caps emmc controller with poll-hw-reset
1598  */
1599 static void dw_mci_hw_reset(struct mmc_host *mmc)
1600 {
1601         struct dw_mci_slot *slot = mmc_priv(mmc);
1602         struct dw_mci *host = slot->host;
1603         u32 regs;
1604
1605         #if 0
1606         u32 cmd_flags;
1607         unsigned long timeout;
1608         bool ret = true;
1609
1610         /* (1) CMD12 to end any transfer in process */
1611         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1612                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1613
1614         if(host->mmc->hold_reg_flag)
1615                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1616         mci_writel(host, CMDARG, 0);
1617         wmb();
1618         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1619         wmb();
1620         timeout = jiffies + msecs_to_jiffies(500);
1621         while(ret){
1622                 ret = time_before(jiffies, timeout);
1623                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1624                         break;
1625         }
1626
1627         if(false == ret)
1628                 MMC_DBG_ERR_FUNC(host->mmc,
1629                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1630                         __func__, mmc_hostname(host->mmc));
1631
1632         /* (2) wait DTO, even if no response is sent back by card */
1633         ret = true;
1634         timeout = jiffies + msecs_to_jiffies(5);
1635         while(ret){
1636                 ret = time_before(jiffies, timeout);
1637                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1638                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1639                         break;
1640                 }
1641         }
1642         #endif
1643
1644         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1645
1646         /* Software reset - BMOD[0] for IDMA only */
1647         regs = mci_readl(host, BMOD);
1648         regs |= SDMMC_IDMAC_SWRESET;
1649         mci_writel(host, BMOD, regs);
1650         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1651         regs = mci_readl(host, BMOD);
1652         if(regs & SDMMC_IDMAC_SWRESET)
1653                 MMC_DBG_WARN_FUNC(host->mmc,
1654                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1655                         __func__, mmc_hostname(host->mmc));
1656
1657         /* DMA reset - CTRL[2] */
1658         regs = mci_readl(host, CTRL);
1659         regs |= SDMMC_CTRL_DMA_RESET;
1660         mci_writel(host, CTRL, regs);
1661         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1662         regs = mci_readl(host, CTRL);
1663         if(regs & SDMMC_CTRL_DMA_RESET)
1664                 MMC_DBG_WARN_FUNC(host->mmc,
1665                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1666                         __func__, mmc_hostname(host->mmc));
1667
1668         /* FIFO reset - CTRL[1] */
1669         regs = mci_readl(host, CTRL);
1670         regs |= SDMMC_CTRL_FIFO_RESET;
1671         mci_writel(host, CTRL, regs);
1672         mdelay(1); /* no timing limited, 1ms is random value */
1673         regs = mci_readl(host, CTRL);
1674         if(regs & SDMMC_CTRL_FIFO_RESET)
1675                 MMC_DBG_WARN_FUNC(host->mmc,
1676                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1677                         __func__, mmc_hostname(host->mmc));
1678
1679         /* (4) CARD_RESET
1680         According to eMMC spec
1681         tRstW >= 1us ;   RST_n pulse width
1682         tRSCA >= 200us ; RST_n to Command time
1683         tRSTH >= 1us ;   RST_n high period
1684         */
1685         mci_writel(slot->host, PWREN, 0x0);
1686         mci_writel(slot->host, RST_N, 0x0);
1687         dsb(sy);
1688         udelay(10); /* 10us for bad quality eMMc. */
1689
1690         mci_writel(slot->host, PWREN, 0x1);
1691         mci_writel(slot->host, RST_N, 0x1);
1692         dsb(sy);
1693         usleep_range(500, 1000); /* at least 500(> 200us) */
1694 }
1695
1696 /*
1697  * Disable lower power mode.
1698  *
1699  * Low power mode will stop the card clock when idle.  According to the
1700  * description of the CLKENA register we should disable low power mode
1701  * for SDIO cards if we need SDIO interrupts to work.
1702  *
1703  * This function is fast if low power mode is already disabled.
1704  */
1705 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1706 {
1707         struct dw_mci *host = slot->host;
1708         u32 clk_en_a;
1709         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1710
1711         clk_en_a = mci_readl(host, CLKENA);
1712
1713         if (clk_en_a & clken_low_pwr) {
1714                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1715                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1716                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1717         }
1718 }
1719
1720 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1721 {
1722         struct dw_mci_slot *slot = mmc_priv(mmc);
1723         struct dw_mci *host = slot->host;
1724         unsigned long flags;
1725         u32 int_mask;
1726         u32 sdio_int;
1727
1728         spin_lock_irqsave(&host->slock, flags);
1729
1730         /* Enable/disable Slot Specific SDIO interrupt */
1731         int_mask = mci_readl(host, INTMASK);
1732
1733         if (host->verid < DW_MMC_240A)
1734                 sdio_int = SDMMC_INT_SDIO(slot->id);
1735         else
1736                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1737
1738         if (enb) {
1739                 /*
1740                  * Turn off low power mode if it was enabled.  This is a bit of
1741                  * a heavy operation and we disable / enable IRQs a lot, so
1742                  * we'll leave low power mode disabled and it will get
1743                  * re-enabled again in dw_mci_setup_bus().
1744                  */
1745                 dw_mci_disable_low_power(slot);
1746
1747                 mci_writel(host, INTMASK,
1748                            (int_mask | sdio_int));
1749         } else {
1750                 mci_writel(host, INTMASK,
1751                            (int_mask & ~sdio_int));
1752         }
1753
1754         spin_unlock_irqrestore(&host->slock, flags);
1755 }
1756
1757 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1758 enum{
1759         IO_DOMAIN_12 = 1200,
1760         IO_DOMAIN_18 = 1800,
1761         IO_DOMAIN_33 = 3300,
1762 };
1763 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1764 {
1765         switch(voltage){
1766                 case IO_DOMAIN_33:
1767                         voltage = 0;
1768                         break;
1769                 case IO_DOMAIN_18:
1770                         voltage = 1;
1771                         break;
1772                 case IO_DOMAIN_12:
1773                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Not support io domain voltage [%s]\n",
1774                                                         __FUNCTION__, mmc_hostname(host->mmc));
1775                         break;
1776                 default:
1777                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Err io domain voltage [%s]\n",
1778                                                         __FUNCTION__, mmc_hostname(host->mmc));
1779                         break;
1780         }
1781
1782         if(cpu_is_rk3288()){
1783                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1784                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1785                 else
1786                         return ;
1787         }else{
1788                 MMC_DBG_ERR_FUNC(host->mmc,"%s : unknown chip [%s]\n",
1789                                         __FUNCTION__, mmc_hostname(host->mmc));
1790         }
1791 }
1792
1793 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1794                                                 struct mmc_ios *ios)
1795 {
1796         int ret;
1797         unsigned int value,uhs_reg;
1798
1799         /*
1800          * Signal Voltage Switching is only applicable for Host Controllers
1801          * v3.00 and above.
1802          */
1803         if (host->verid < DW_MMC_240A)
1804                 return 0;
1805
1806         uhs_reg = mci_readl(host, UHS_REG);
1807         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1808                 __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1809
1810         switch (ios->signal_voltage) {
1811         case MMC_SIGNAL_VOLTAGE_330:
1812                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1813                 if (host->vmmc) {
1814                         ret = io_domain_regulator_set_voltage(host->vmmc, 3300000, 3300000);
1815                         /* regulator_put(host->vmmc); //to be done in remove function. */
1816
1817                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1818                             __func__, regulator_get_voltage(host->vmmc), ret);
1819                         if (ret) {
1820                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 3.3V signalling voltage "
1821                                                 " failed\n", mmc_hostname(host->mmc));
1822                                 return -EIO;
1823                         }
1824                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1825                 }
1826                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__,
1827                                         __FUNCTION__, mmc_hostname(host->mmc));
1828
1829                 /* set High-power mode */
1830                 value = mci_readl(host, CLKENA);
1831                 value &= ~SDMMC_CLKEN_LOW_PWR;
1832                 mci_writel(host,CLKENA , value);
1833                 /* SDMMC_UHS_REG */
1834                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1835                 mci_writel(host,UHS_REG , uhs_reg);
1836
1837                 /* Wait for 5ms */
1838                 usleep_range(5000, 5500);
1839
1840                 /* 3.3V regulator output should be stable within 5 ms */
1841                 uhs_reg = mci_readl(host, UHS_REG);
1842                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1843                         return 0;
1844
1845                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 3.3V regulator output did not became stable\n",
1846                                 mmc_hostname(host->mmc));
1847
1848                 return -EAGAIN;
1849         case MMC_SIGNAL_VOLTAGE_180:
1850                 if (host->vmmc) {
1851                         ret = io_domain_regulator_set_voltage(host->vmmc,1800000, 1800000);
1852                         /* regulator_put(host->vmmc);//to be done in remove function. */
1853
1854                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1855                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1856                         if (ret) {
1857                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.8V signalling voltage "
1858                                                 " failed\n", mmc_hostname(host->mmc));
1859                                 return -EIO;
1860                         }
1861                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1862                 }
1863
1864                 /*
1865                  * Enable 1.8V Signal Enable in the Host Control2
1866                  * register
1867                  */
1868                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1869
1870                 /* Wait for 5ms */
1871                 usleep_range(5000, 5500);
1872                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__,
1873                                         __FUNCTION__,mmc_hostname(host->mmc));
1874
1875                 /* 1.8V regulator output should be stable within 5 ms */
1876                 uhs_reg = mci_readl(host, UHS_REG);
1877                 if(uhs_reg & SDMMC_UHS_VOLT_REG_18)
1878                         return 0;
1879
1880                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 1.8V regulator output did not became stable\n",
1881                                 mmc_hostname(host->mmc));
1882
1883                 return -EAGAIN;
1884         case MMC_SIGNAL_VOLTAGE_120:
1885                 if (host->vmmc) {
1886                         ret = io_domain_regulator_set_voltage(host->vmmc, 1200000, 1200000);
1887                         if (ret) {
1888                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.2V signalling voltage "
1889                                                 " failed\n", mmc_hostname(host->mmc));
1890                                 return -EIO;
1891                         }
1892                 }
1893                 return 0;
1894         default:
1895                 /* No signal voltage switch required */
1896                 return 0;
1897         }
1898 }
1899
1900
1901 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1902         struct mmc_ios *ios)
1903 {
1904         struct dw_mci_slot *slot = mmc_priv(mmc);
1905         struct dw_mci *host = slot->host;
1906         int err;
1907
1908         if (host->verid < DW_MMC_240A)
1909                 return 0;
1910
1911         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1912         return err;
1913 }
1914
1915 #endif
1916
1917 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1918 {
1919         struct dw_mci_slot *slot = mmc_priv(mmc);
1920         struct dw_mci *host = slot->host;
1921         const struct dw_mci_drv_data *drv_data = host->drv_data;
1922         struct dw_mci_tuning_data tuning_data;
1923         int err = -ENOSYS;
1924
1925         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1926         if(cpu_is_rk3036() || cpu_is_rk312x())
1927                 return err;
1928
1929         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1930                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1931                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1932                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1933                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1934                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1935                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1936                 } else {
1937                         return -EINVAL;
1938                 }
1939         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1940                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1941                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1942         } else {
1943                 dev_err(host->dev,
1944                         "Undefined command(%d) for tuning\n", opcode);
1945                 return -EINVAL;
1946         }
1947
1948
1949         /* Recommend sample phase and delayline
1950            Fixme: Mix-use these three controllers will cause
1951            con_id mismatch.
1952          */
1953         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1954             tuning_data.con_id = 3;
1955         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1956             tuning_data.con_id = 1;
1957         else
1958             tuning_data.con_id = 0;
1959
1960         /* 0: driver, from host->devices
1961            1: sample, from devices->host
1962          */
1963         tuning_data.tuning_type = 1;
1964
1965         if (drv_data && drv_data->execute_tuning)
1966                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1967
1968         return err;
1969 }
1970
1971 static const struct mmc_host_ops dw_mci_ops = {
1972         .request                = dw_mci_request,
1973         .pre_req                = dw_mci_pre_req,
1974         .post_req               = dw_mci_post_req,
1975         .set_ios                = dw_mci_set_ios,
1976         .get_ro                 = dw_mci_get_ro,
1977         .get_cd                 = dw_mci_get_cd,
1978         .set_sdio_status    = dw_mci_set_sdio_status,
1979         .hw_reset       = dw_mci_hw_reset,
1980         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1981         .execute_tuning         = dw_mci_execute_tuning,
1982         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1983         .start_signal_voltage_switch    = dw_mci_start_signal_voltage_switch,
1984         .card_busy  = dw_mci_card_busy,
1985         #endif
1986 };
1987
1988 #if 0
1989 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
1990 {
1991         unsigned long flags;
1992
1993     if(!host)
1994         return;
1995
1996         local_irq_save(flags);
1997         if(host->irq_state != irqflag)
1998         {
1999             host->irq_state = irqflag;
2000             if(irqflag)
2001             {
2002                 enable_irq(host->irq);
2003             }
2004             else
2005             {
2006                 disable_irq(host->irq);
2007             }
2008         }
2009         local_irq_restore(flags);
2010 }
2011 #endif
2012
2013 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2014         __releases(&host->lock)
2015         __acquires(&host->lock)
2016 {
2017         if(DW_MCI_SEND_STATUS == host->dir_status){
2018             #if 0
2019             if( MMC_BUS_TEST_W != host->cmd->opcode){
2020                 if(host->data_status & SDMMC_INT_DCRC)
2021                     host->data->error = -EILSEQ;
2022                 else if(host->data_status & SDMMC_INT_EBE)
2023                     host->data->error = -ETIMEDOUT;
2024             } else {
2025                 dw_mci_wait_unbusy(host);
2026             }
2027             #else
2028             dw_mci_wait_unbusy(host);
2029             #endif
2030         }
2031 }
2032
2033 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2034         __releases(&host->lock)
2035         __acquires(&host->lock)
2036 {
2037         struct dw_mci_slot *slot;
2038         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2039
2040         WARN_ON(host->cmd || host->data);
2041
2042         del_timer_sync(&host->dto_timer);
2043         dw_mci_deal_data_end(host, mrq);
2044
2045         if(mrq->cmd)
2046                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
2047                         mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
2048         if(mrq->data)
2049                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
2050                         mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
2051
2052         host->cur_slot->mrq = NULL;
2053         host->mrq = NULL;
2054         if (!list_empty(&host->queue)) {
2055                 slot = list_entry(host->queue.next,
2056                                   struct dw_mci_slot, queue_node);
2057                 list_del(&slot->queue_node);
2058                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2059                          mmc_hostname(slot->mmc));
2060                 host->state = STATE_SENDING_CMD;
2061                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
2062                 dw_mci_start_request(host, slot);
2063         } else {
2064                 dev_vdbg(host->dev, "list empty\n");
2065                 host->state = STATE_IDLE;
2066         }
2067
2068         spin_unlock(&host->lock);
2069         mmc_request_done(prev_mmc, mrq);
2070         spin_lock(&host->lock);
2071 }
2072
2073 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2074 {
2075         u32 status = host->cmd_status;
2076
2077         host->cmd_status = 0;
2078
2079         /* Read the response from the card (up to 16 bytes) */
2080         if (cmd->flags & MMC_RSP_PRESENT) {
2081                 if (cmd->flags & MMC_RSP_136) {
2082                         cmd->resp[3] = mci_readl(host, RESP0);
2083                         cmd->resp[2] = mci_readl(host, RESP1);
2084                         cmd->resp[1] = mci_readl(host, RESP2);
2085                         cmd->resp[0] = mci_readl(host, RESP3);
2086
2087             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
2088                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
2089                 } else {
2090                         cmd->resp[0] = mci_readl(host, RESP0);
2091                         cmd->resp[1] = 0;
2092                         cmd->resp[2] = 0;
2093                         cmd->resp[3] = 0;
2094             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
2095                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2096                 }
2097         }
2098
2099         if (status & SDMMC_INT_RTO)
2100         {
2101             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2102                 host->cmd_rto += 1;
2103
2104                 cmd->error = -ETIMEDOUT;
2105                 del_timer_sync(&host->dto_timer);
2106         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2107                 del_timer_sync(&host->dto_timer);
2108                 cmd->error = -EILSEQ;
2109         }else if (status & SDMMC_INT_RESP_ERR){
2110                 del_timer_sync(&host->dto_timer);
2111                 cmd->error = -EIO;
2112         }else{
2113                 cmd->error = 0;
2114         }
2115         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",
2116                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2117
2118         if (cmd->error) {
2119                 del_timer_sync(&host->dto_timer);
2120             if(MMC_SEND_STATUS != cmd->opcode)
2121                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2122                         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
2123                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2124                         host->cmd_rto = 0;
2125                 }
2126
2127                 /* newer ip versions need a delay between retries */
2128                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2129                         mdelay(20);
2130         }
2131
2132 }
2133
2134 static void dw_mci_tasklet_func(unsigned long priv)
2135 {
2136         struct dw_mci *host = (struct dw_mci *)priv;
2137         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2138         struct mmc_data *data;
2139         struct mmc_command *cmd;
2140         enum dw_mci_state state;
2141         enum dw_mci_state prev_state;
2142         u32 status, cmd_flags;
2143         unsigned long timeout = 0;
2144         bool ret = true;
2145
2146         spin_lock(&host->lock);
2147
2148         state = host->state;
2149         data = host->data;
2150
2151         do {
2152                 prev_state = state;
2153
2154                 switch (state) {
2155                 case STATE_IDLE:
2156                         break;
2157
2158                 case STATE_SENDING_CMD:
2159                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2160                                                 &host->pending_events))
2161                                 break;
2162
2163                         cmd = host->cmd;
2164                         host->cmd = NULL;
2165                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2166                         dw_mci_command_complete(host, cmd);
2167                         if (cmd == host->mrq->sbc && !cmd->error) {
2168                                 prev_state = state = STATE_SENDING_CMD;
2169                                 __dw_mci_start_request(host, host->cur_slot,
2170                                                        host->mrq->cmd);
2171                                 goto unlock;
2172                         }
2173
2174                         if (cmd->data && cmd->error) {
2175                                 del_timer_sync(&host->dto_timer); /* delete the timer for INT_DTO */
2176                                 dw_mci_stop_dma(host);
2177                                 #if 1
2178                                 if (data->stop) {
2179                                         send_stop_cmd(host, data);
2180                                         state = STATE_SENDING_STOP;
2181                                         break;
2182                                 }else{
2183                                         host->data = NULL;
2184                                 }
2185                                 #else
2186                                 send_stop_abort(host, data);
2187                                 state = STATE_SENDING_STOP;
2188                                 break;
2189                                 #endif
2190                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2191                         }
2192
2193                         if (!host->mrq->data || cmd->error) {
2194                                 dw_mci_request_end(host, host->mrq);
2195                                 goto unlock;
2196                         }
2197
2198                         prev_state = state = STATE_SENDING_DATA;
2199                         /* fall through */
2200
2201                 case STATE_SENDING_DATA:
2202                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
2203                                 dw_mci_stop_dma(host);
2204                                 #if 1
2205                                 if (data->stop){
2206                                         send_stop_cmd(host, data);
2207                                 }else{
2208                                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
2209                                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
2210                                                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
2211
2212                                         mci_writel(host, CMDARG, 0);
2213                                         wmb();
2214                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
2215                                                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2216
2217                                         if(host->mmc->hold_reg_flag)
2218                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2219
2220                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2221                                         wmb();
2222                                         timeout = jiffies + msecs_to_jiffies(500);
2223
2224                                         while(ret){
2225                                                 ret = time_before(jiffies, timeout);
2226                                                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2227                                                         break;
2228                                         }
2229                                         if(false == ret)
2230                                                 MMC_DBG_ERR_FUNC(host->mmc,
2231                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2232                                                         __func__, mmc_hostname(host->mmc));
2233                                 }
2234                                 #else
2235                                 send_stop_abort(host, data);
2236                                 #endif
2237                                 state = STATE_DATA_ERROR;
2238                                 break;
2239                         }
2240
2241                         MMC_DBG_CMD_FUNC(host->mmc,
2242                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
2243                         prev_state,state, mmc_hostname(host->mmc));
2244
2245                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2246                                                 &host->pending_events))
2247                                 break;
2248                         MMC_DBG_INFO_FUNC(host->mmc,
2249                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
2250                                           prev_state,state,mmc_hostname(host->mmc));
2251
2252                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2253                         prev_state = state = STATE_DATA_BUSY;
2254                         /* fall through */
2255
2256                 case STATE_DATA_BUSY:
2257                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2258                                                 &host->pending_events))
2259                                 break;
2260
2261                         dw_mci_deal_data_end(host, host->mrq);
2262                         del_timer_sync(&host->dto_timer); //delete the timer for INT_DTO
2263                         MMC_DBG_INFO_FUNC(host->mmc,
2264                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
2265                                           prev_state,state,mmc_hostname(host->mmc));
2266
2267                         host->data = NULL;
2268                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2269                         status = host->data_status;
2270
2271                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2272                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2273                                 MMC_DBG_ERR_FUNC(host->mmc,
2274                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
2275                             prev_state,state, status, mmc_hostname(host->mmc));
2276
2277                         if (status & SDMMC_INT_DRTO) {
2278                                         data->error = -ETIMEDOUT;
2279                                 } else if (status & SDMMC_INT_DCRC) {
2280                                         data->error = -EILSEQ;
2281                                 } else if (status & SDMMC_INT_EBE &&
2282                                 host->dir_status == DW_MCI_SEND_STATUS){
2283                                         /*
2284                                          * No data CRC status was returned.
2285                                          * The number of bytes transferred will
2286                                          * be exaggerated in PIO mode.
2287                                          */
2288                                         data->bytes_xfered = 0;
2289                                         data->error = -ETIMEDOUT;
2290                                 } else {
2291                                         dev_err(host->dev,
2292                                                 "data FIFO error "
2293                                                 "(status=%08x)\n",
2294                                                 status);
2295                                         data->error = -EIO;
2296                                 }
2297                                 /*
2298                                  * After an error, there may be data lingering
2299                                  * in the FIFO, so reset it - doing so
2300                                  * generates a block interrupt, hence setting
2301                                  * the scatter-gather pointer to NULL.
2302                                  */
2303                                 dw_mci_fifo_reset(host);
2304                         } else {
2305                                 data->bytes_xfered = data->blocks * data->blksz;
2306                                 data->error = 0;
2307                         }
2308
2309                         if (!data->stop) {
2310                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2311                                       prev_state,state,mmc_hostname(host->mmc));
2312                                 dw_mci_request_end(host, host->mrq);
2313                                 goto unlock;
2314                         }
2315                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2316                                                 prev_state,state,mmc_hostname(host->mmc));
2317
2318                         if (host->mrq->sbc && !data->error) {
2319                                 data->stop->error = 0;
2320
2321                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2322                                                 prev_state,state,mmc_hostname(host->mmc));
2323
2324                                 dw_mci_request_end(host, host->mrq);
2325                                 goto unlock;
2326                         }
2327
2328                         prev_state = state = STATE_SENDING_STOP;
2329                         if (!data->error)
2330                             send_stop_cmd(host, data);
2331                         #if 0
2332                         if (data->stop && !data->error) {
2333                                 /* stop command for open-ended transfer*/
2334
2335                                 send_stop_abort(host, data);
2336                         }
2337                         #endif
2338                         /* fall through */
2339                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2340                                                 prev_state,state,mmc_hostname(host->mmc));
2341
2342                 case STATE_SENDING_STOP:
2343                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2344                                 break;
2345
2346                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2347                                                 prev_state, state, mmc_hostname(host->mmc));
2348
2349                         /* CMD error in data command */
2350                         if (host->mrq->cmd->error && host->mrq->data) {
2351                                 dw_mci_fifo_reset(host);
2352                         }
2353
2354                         host->cmd = NULL;
2355                         host->data = NULL;
2356                         #if 1
2357                         dw_mci_command_complete(host, host->mrq->stop);
2358                         #else
2359                         if (host->mrq->stop)
2360                                 dw_mci_command_complete(host, host->mrq->stop);
2361                         else
2362                                 host->cmd_status = 0;
2363                         #endif
2364
2365                         dw_mci_request_end(host, host->mrq);
2366                         goto unlock;
2367
2368                 case STATE_DATA_ERROR:
2369                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2370                                                 &host->pending_events))
2371                                 break;
2372
2373                         state = STATE_DATA_BUSY;
2374                         break;
2375                 }
2376         } while (state != prev_state);
2377
2378         host->state = state;
2379 unlock:
2380         spin_unlock(&host->lock);
2381
2382 }
2383
2384 /* push final bytes to part_buf, only use during push */
2385 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2386 {
2387         memcpy((void *)&host->part_buf, buf, cnt);
2388         host->part_buf_count = cnt;
2389 }
2390
2391 /* append bytes to part_buf, only use during push */
2392 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2393 {
2394         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2395         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2396         host->part_buf_count += cnt;
2397         return cnt;
2398 }
2399
2400 /* pull first bytes from part_buf, only use during pull */
2401 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2402 {
2403         cnt = min(cnt, (int)host->part_buf_count);
2404         if (cnt) {
2405                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2406                        cnt);
2407                 host->part_buf_count -= cnt;
2408                 host->part_buf_start += cnt;
2409         }
2410         return cnt;
2411 }
2412
2413 /* pull final bytes from the part_buf, assuming it's just been filled */
2414 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2415 {
2416         memcpy(buf, &host->part_buf, cnt);
2417         host->part_buf_start = cnt;
2418         host->part_buf_count = (1 << host->data_shift) - cnt;
2419 }
2420
2421 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2422 {
2423         struct mmc_data *data = host->data;
2424         int init_cnt = cnt;
2425
2426         /* try and push anything in the part_buf */
2427         if (unlikely(host->part_buf_count)) {
2428                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2429                 buf += len;
2430                 cnt -= len;
2431                 if (host->part_buf_count == 2) {
2432                         mci_writew(host, DATA(host->data_offset),
2433                                         host->part_buf16);
2434                         host->part_buf_count = 0;
2435                 }
2436         }
2437 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2438         if (unlikely((unsigned long)buf & 0x1)) {
2439                 while (cnt >= 2) {
2440                         u16 aligned_buf[64];
2441                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2442                         int items = len >> 1;
2443                         int i;
2444                         /* memcpy from input buffer into aligned buffer */
2445                         memcpy(aligned_buf, buf, len);
2446                         buf += len;
2447                         cnt -= len;
2448                         /* push data from aligned buffer into fifo */
2449                         for (i = 0; i < items; ++i)
2450                                 mci_writew(host, DATA(host->data_offset),
2451                                                 aligned_buf[i]);
2452                 }
2453         } else
2454 #endif
2455         {
2456                 u16 *pdata = buf;
2457                 for (; cnt >= 2; cnt -= 2)
2458                         mci_writew(host, DATA(host->data_offset), *pdata++);
2459                 buf = pdata;
2460         }
2461         /* put anything remaining in the part_buf */
2462         if (cnt) {
2463                 dw_mci_set_part_bytes(host, buf, cnt);
2464                  /* Push data if we have reached the expected data length */
2465                 if ((data->bytes_xfered + init_cnt) ==
2466                     (data->blksz * data->blocks))
2467                         mci_writew(host, DATA(host->data_offset),
2468                                    host->part_buf16);
2469         }
2470 }
2471
2472 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2473 {
2474 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2475         if (unlikely((unsigned long)buf & 0x1)) {
2476                 while (cnt >= 2) {
2477                         /* pull data from fifo into aligned buffer */
2478                         u16 aligned_buf[64];
2479                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2480                         int items = len >> 1;
2481                         int i;
2482                         for (i = 0; i < items; ++i)
2483                                 aligned_buf[i] = mci_readw(host,
2484                                                 DATA(host->data_offset));
2485                         /* memcpy from aligned buffer into output buffer */
2486                         memcpy(buf, aligned_buf, len);
2487                         buf += len;
2488                         cnt -= len;
2489                 }
2490         } else
2491 #endif
2492         {
2493                 u16 *pdata = buf;
2494                 for (; cnt >= 2; cnt -= 2)
2495                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2496                 buf = pdata;
2497         }
2498         if (cnt) {
2499                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2500                 dw_mci_pull_final_bytes(host, buf, cnt);
2501         }
2502 }
2503
2504 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2505 {
2506         struct mmc_data *data = host->data;
2507         int init_cnt = cnt;
2508
2509         /* try and push anything in the part_buf */
2510         if (unlikely(host->part_buf_count)) {
2511                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2512                 buf += len;
2513                 cnt -= len;
2514                 if (host->part_buf_count == 4) {
2515                         mci_writel(host, DATA(host->data_offset),
2516                                         host->part_buf32);
2517                         host->part_buf_count = 0;
2518                 }
2519         }
2520 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2521         if (unlikely((unsigned long)buf & 0x3)) {
2522                 while (cnt >= 4) {
2523                         u32 aligned_buf[32];
2524                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2525                         int items = len >> 2;
2526                         int i;
2527                         /* memcpy from input buffer into aligned buffer */
2528                         memcpy(aligned_buf, buf, len);
2529                         buf += len;
2530                         cnt -= len;
2531                         /* push data from aligned buffer into fifo */
2532                         for (i = 0; i < items; ++i)
2533                                 mci_writel(host, DATA(host->data_offset),
2534                                                 aligned_buf[i]);
2535                 }
2536         } else
2537 #endif
2538         {
2539                 u32 *pdata = buf;
2540                 for (; cnt >= 4; cnt -= 4)
2541                         mci_writel(host, DATA(host->data_offset), *pdata++);
2542                 buf = pdata;
2543         }
2544         /* put anything remaining in the part_buf */
2545         if (cnt) {
2546                 dw_mci_set_part_bytes(host, buf, cnt);
2547                  /* Push data if we have reached the expected data length */
2548                 if ((data->bytes_xfered + init_cnt) ==
2549                     (data->blksz * data->blocks))
2550                         mci_writel(host, DATA(host->data_offset),
2551                                    host->part_buf32);
2552         }
2553 }
2554
2555 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2556 {
2557 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2558         if (unlikely((unsigned long)buf & 0x3)) {
2559                 while (cnt >= 4) {
2560                         /* pull data from fifo into aligned buffer */
2561                         u32 aligned_buf[32];
2562                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2563                         int items = len >> 2;
2564                         int i;
2565                         for (i = 0; i < items; ++i)
2566                                 aligned_buf[i] = mci_readl(host,
2567                                                 DATA(host->data_offset));
2568                         /* memcpy from aligned buffer into output buffer */
2569                         memcpy(buf, aligned_buf, len);
2570                         buf += len;
2571                         cnt -= len;
2572                 }
2573         } else
2574 #endif
2575         {
2576                 u32 *pdata = buf;
2577                 for (; cnt >= 4; cnt -= 4)
2578                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2579                 buf = pdata;
2580         }
2581         if (cnt) {
2582                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2583                 dw_mci_pull_final_bytes(host, buf, cnt);
2584         }
2585 }
2586
2587 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2588 {
2589         struct mmc_data *data = host->data;
2590         int init_cnt = cnt;
2591
2592         /* try and push anything in the part_buf */
2593         if (unlikely(host->part_buf_count)) {
2594                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2595                 buf += len;
2596                 cnt -= len;
2597
2598                 if (host->part_buf_count == 8) {
2599                         mci_writeq(host, DATA(host->data_offset),
2600                                         host->part_buf);
2601                         host->part_buf_count = 0;
2602                 }
2603         }
2604 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2605         if (unlikely((unsigned long)buf & 0x7)) {
2606                 while (cnt >= 8) {
2607                         u64 aligned_buf[16];
2608                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2609                         int items = len >> 3;
2610                         int i;
2611                         /* memcpy from input buffer into aligned buffer */
2612                         memcpy(aligned_buf, buf, len);
2613                         buf += len;
2614                         cnt -= len;
2615                         /* push data from aligned buffer into fifo */
2616                         for (i = 0; i < items; ++i)
2617                                 mci_writeq(host, DATA(host->data_offset),
2618                                                 aligned_buf[i]);
2619                 }
2620         } else
2621 #endif
2622         {
2623                 u64 *pdata = buf;
2624                 for (; cnt >= 8; cnt -= 8)
2625                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2626                 buf = pdata;
2627         }
2628         /* put anything remaining in the part_buf */
2629         if (cnt) {
2630                 dw_mci_set_part_bytes(host, buf, cnt);
2631                 /* Push data if we have reached the expected data length */
2632                 if ((data->bytes_xfered + init_cnt) ==
2633                     (data->blksz * data->blocks))
2634                         mci_writeq(host, DATA(host->data_offset),
2635                                    host->part_buf);
2636         }
2637 }
2638
2639 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2640 {
2641 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2642         if (unlikely((unsigned long)buf & 0x7)) {
2643                 while (cnt >= 8) {
2644                         /* pull data from fifo into aligned buffer */
2645                         u64 aligned_buf[16];
2646                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2647                         int items = len >> 3;
2648                         int i;
2649                         for (i = 0; i < items; ++i)
2650                                 aligned_buf[i] = mci_readq(host,
2651                                                 DATA(host->data_offset));
2652                         /* memcpy from aligned buffer into output buffer */
2653                         memcpy(buf, aligned_buf, len);
2654                         buf += len;
2655                         cnt -= len;
2656                 }
2657         } else
2658 #endif
2659         {
2660                 u64 *pdata = buf;
2661                 for (; cnt >= 8; cnt -= 8)
2662                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2663                 buf = pdata;
2664         }
2665         if (cnt) {
2666                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2667                 dw_mci_pull_final_bytes(host, buf, cnt);
2668         }
2669 }
2670
2671 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2672 {
2673         int len;
2674
2675         /* get remaining partial bytes */
2676         len = dw_mci_pull_part_bytes(host, buf, cnt);
2677         if (unlikely(len == cnt))
2678                 return;
2679         buf += len;
2680         cnt -= len;
2681
2682         /* get the rest of the data */
2683         host->pull_data(host, buf, cnt);
2684 }
2685
2686 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2687 {
2688         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2689         void *buf;
2690         unsigned int offset;
2691         struct mmc_data *data = host->data;
2692         int shift = host->data_shift;
2693         u32 status;
2694         unsigned int len;
2695         unsigned int remain, fcnt;
2696
2697         if(!host->mmc->bus_refs){
2698                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2699                 goto host_put;
2700         }
2701         do {
2702                 if (!sg_miter_next(sg_miter))
2703                         goto done;
2704
2705                 host->sg = sg_miter->piter.sg;
2706                 buf = sg_miter->addr;
2707                 remain = sg_miter->length;
2708                 offset = 0;
2709
2710                 do {
2711                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2712                                         << shift) + host->part_buf_count;
2713                         len = min(remain, fcnt);
2714                         if (!len)
2715                                 break;
2716                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2717                         data->bytes_xfered += len;
2718                         offset += len;
2719                         remain -= len;
2720                 } while (remain);
2721
2722                 sg_miter->consumed = offset;
2723                 status = mci_readl(host, MINTSTS);
2724                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2725         /* if the RXDR is ready read again */
2726         } while ((status & SDMMC_INT_RXDR) ||
2727                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2728
2729         if (!remain) {
2730                 if (!sg_miter_next(sg_miter))
2731                         goto done;
2732                 sg_miter->consumed = 0;
2733         }
2734         sg_miter_stop(sg_miter);
2735         return;
2736
2737 done:
2738         sg_miter_stop(sg_miter);
2739 host_put:
2740         host->sg = NULL;
2741         smp_wmb();
2742         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2743 }
2744
2745 static void dw_mci_write_data_pio(struct dw_mci *host)
2746 {
2747         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2748         void *buf;
2749         unsigned int offset;
2750         struct mmc_data *data = host->data;
2751         int shift = host->data_shift;
2752         u32 status;
2753         unsigned int len;
2754         unsigned int fifo_depth = host->fifo_depth;
2755         unsigned int remain, fcnt;
2756
2757         if(!host->mmc->bus_refs){
2758                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2759                 goto host_put;
2760         }
2761
2762         do {
2763                 if (!sg_miter_next(sg_miter))
2764                         goto done;
2765
2766                 host->sg = sg_miter->piter.sg;
2767                 buf = sg_miter->addr;
2768                 remain = sg_miter->length;
2769                 offset = 0;
2770
2771                 do {
2772                         fcnt = ((fifo_depth -
2773                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2774                                         << shift) - host->part_buf_count;
2775                         len = min(remain, fcnt);
2776                         if (!len)
2777                                 break;
2778                         host->push_data(host, (void *)(buf + offset), len);
2779                         data->bytes_xfered += len;
2780                         offset += len;
2781                         remain -= len;
2782                 } while (remain);
2783
2784                 sg_miter->consumed = offset;
2785                 status = mci_readl(host, MINTSTS);
2786                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2787         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2788
2789         if (!remain) {
2790                 if (!sg_miter_next(sg_miter))
2791                         goto done;
2792                 sg_miter->consumed = 0;
2793         }
2794         sg_miter_stop(sg_miter);
2795         return;
2796
2797 done:
2798         sg_miter_stop(sg_miter);
2799 host_put:
2800         host->sg = NULL;
2801         smp_wmb();
2802         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2803 }
2804
2805 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2806 {
2807         u32 multi, unit = SZ_2M;
2808
2809         if (!host->cmd_status)
2810             host->cmd_status = status;
2811
2812         if (!host->cmd)
2813                 goto cmd_exit;
2814
2815         if ((MMC_STOP_TRANSMISSION != host->cmd->opcode)) {
2816                 multi = (mci_readl(host, BYTCNT) / unit) +
2817                         ((mci_readl(host, BYTCNT) % unit) ? 1 :0 ) +
2818                         ((host->cmd->retries > 2) ? 2 : host->cmd->retries);
2819                 /* Max limit time: 8s for dto */
2820                 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(4000 * multi));
2821         }
2822
2823 cmd_exit:
2824         smp_wmb();
2825         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2826         tasklet_schedule(&host->tasklet);
2827 }
2828
2829 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2830 {
2831         struct dw_mci *host = dev_id;
2832         u32 pending, sdio_int;
2833         int i;
2834
2835         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2836
2837         /*
2838         * DTO fix - version 2.10a and below, and only if internal DMA
2839         * is configured.
2840         */
2841         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2842                         if (!pending &&
2843                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2844                                 pending |= SDMMC_INT_DATA_OVER;
2845         }
2846
2847         if (pending) {
2848                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2849                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2850                         host->cmd_status = pending;
2851                         smp_wmb();
2852                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
2853                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
2854
2855                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2856                 }
2857
2858                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2859                         /* if there is an error report DATA_ERROR */
2860                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2861                         host->data_status = pending;
2862                         smp_wmb();
2863                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2864
2865                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
2866                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
2867                         tasklet_schedule(&host->tasklet);
2868                 }
2869
2870                 if (pending & SDMMC_INT_DATA_OVER) {
2871                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2872                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2873                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2874                         if (!host->data_status)
2875                                 host->data_status = pending;
2876                         smp_wmb();
2877                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2878                                 if (host->sg != NULL)
2879                                         dw_mci_read_data_pio(host, true);
2880                         }
2881                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2882                         tasklet_schedule(&host->tasklet);
2883                 }
2884
2885                 if (pending & SDMMC_INT_RXDR) {
2886                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2887                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2888                                 dw_mci_read_data_pio(host, false);
2889                 }
2890
2891                 if (pending & SDMMC_INT_TXDR) {
2892                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2893                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2894                                 dw_mci_write_data_pio(host);
2895                 }
2896
2897                 if (pending & SDMMC_INT_VSI) {
2898                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2899                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2900                         dw_mci_cmd_interrupt(host, pending);
2901                 }
2902
2903                 if (pending & SDMMC_INT_CMD_DONE) {
2904                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
2905                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2906                         dw_mci_cmd_interrupt(host, pending);
2907                 }
2908
2909                 if (pending & SDMMC_INT_CD) {
2910                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2911                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
2912                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2913                         queue_work(host->card_workqueue, &host->card_work);
2914                 }
2915
2916                 if (pending & SDMMC_INT_HLE) {
2917                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2918                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
2919
2920                 }
2921
2922                 /* Handle SDIO Interrupts */
2923                 for (i = 0; i < host->num_slots; i++) {
2924                         struct dw_mci_slot *slot = host->slot[i];
2925
2926                         if (host->verid < DW_MMC_240A)
2927                                 sdio_int = SDMMC_INT_SDIO(i);
2928                         else
2929                                 sdio_int = SDMMC_INT_SDIO(i + 8);
2930
2931                         if (pending & sdio_int) {
2932                                 mci_writel(host, RINTSTS, sdio_int);
2933                                 mmc_signal_sdio_irq(slot->mmc);
2934                         }
2935                 }
2936
2937         }
2938
2939 #ifdef CONFIG_MMC_DW_IDMAC
2940         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
2941         if(!(cpu_is_rk3036() || cpu_is_rk312x())){
2942                 /* Handle DMA interrupts */
2943                 pending = mci_readl(host, IDSTS);
2944                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2945                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2946                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2947                         host->dma_ops->complete((void *)host);
2948                 }
2949         }
2950 #endif
2951
2952         return IRQ_HANDLED;
2953 }
2954
2955 static void dw_mci_work_routine_card(struct work_struct *work)
2956 {
2957         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2958         int i;
2959
2960         for (i = 0; i < host->num_slots; i++) {
2961                 struct dw_mci_slot *slot = host->slot[i];
2962                 struct mmc_host *mmc = slot->mmc;
2963                 struct mmc_request *mrq;
2964                 int present;
2965
2966                 present = dw_mci_get_cd(mmc);
2967
2968                 /* Card insert, switch data line to uart function, and vice verse.
2969                  * ONLY audi chip need switched by software, using udbg tag in dts!
2970                  */
2971                 if (!(IS_ERR(host->pins_udbg)) && !(IS_ERR(host->pins_default))) {
2972                          if (present) {
2973                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
2974                                         dev_err(host->dev, "%s: Default pinctrl setting failed!\n",
2975                                                 mmc_hostname(host->mmc));
2976                          } else {
2977                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
2978                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
2979                                                 mmc_hostname(host->mmc));
2980                         }
2981                 }
2982
2983                 while (present != slot->last_detect_state) {
2984                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
2985                                 present ? "inserted" : "removed");
2986                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
2987                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
2988
2989                         dw_mci_ctrl_all_reset(host);
2990                         /* Stop edma when rountine card triggered */
2991                         if(cpu_is_rk3036() || cpu_is_rk312x())
2992                                 if(host->dma_ops && host->dma_ops->stop)
2993                                         host->dma_ops->stop(host);
2994                         rk_send_wakeup_key();//wake up system
2995                         spin_lock_bh(&host->lock);
2996
2997                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2998                         /* Card change detected */
2999                         slot->last_detect_state = present;
3000
3001                         /* Clean up queue if present */
3002                         mrq = slot->mrq;
3003                         if (mrq) {
3004                                 if (mrq == host->mrq) {
3005                                         host->data = NULL;
3006                                         host->cmd = NULL;
3007
3008                                         switch (host->state) {
3009                                         case STATE_IDLE:
3010                                                 break;
3011                                         case STATE_SENDING_CMD:
3012                                                 mrq->cmd->error = -ENOMEDIUM;
3013                                                 if (!mrq->data)
3014                                                         break;
3015                                                 /* fall through */
3016                                         case STATE_SENDING_DATA:
3017                                                 mrq->data->error = -ENOMEDIUM;
3018                                                 dw_mci_stop_dma(host);
3019                                                 break;
3020                                         case STATE_DATA_BUSY:
3021                                         case STATE_DATA_ERROR:
3022                                                 if (mrq->data->error == -EINPROGRESS)
3023                                                         mrq->data->error = -ENOMEDIUM;
3024                                                 if (!mrq->stop)
3025                                                         break;
3026                                                 /* fall through */
3027                                         case STATE_SENDING_STOP:
3028                                                 mrq->stop->error = -ENOMEDIUM;
3029                                                 break;
3030                                         }
3031
3032                                         dw_mci_request_end(host, mrq);
3033                                 } else {
3034                                         list_del(&slot->queue_node);
3035                                         mrq->cmd->error = -ENOMEDIUM;
3036                                         if (mrq->data)
3037                                                 mrq->data->error = -ENOMEDIUM;
3038                                         if (mrq->stop)
3039                                                 mrq->stop->error = -ENOMEDIUM;
3040
3041                                         MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",
3042                                                         mrq->cmd->opcode, mmc_hostname(mmc));
3043
3044                                         spin_unlock(&host->lock);
3045                                         mmc_request_done(slot->mmc, mrq);
3046                                         spin_lock(&host->lock);
3047                                 }
3048                         }
3049
3050                         /* Power down slot */
3051                         if (present == 0) {
3052                                 /* Clear down the FIFO */
3053                                 dw_mci_fifo_reset(host);
3054 #ifdef CONFIG_MMC_DW_IDMAC
3055                                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3056                                         dw_mci_idmac_reset(host);
3057 #endif
3058
3059                         }
3060
3061                         spin_unlock_bh(&host->lock);
3062
3063                         present = dw_mci_get_cd(mmc);
3064                 }
3065
3066                 mmc_detect_change(slot->mmc,
3067                 msecs_to_jiffies(host->pdata->detect_delay_ms));
3068         }
3069 }
3070
3071 #ifdef CONFIG_OF
3072 /* given a slot id, find out the device node representing that slot */
3073 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3074 {
3075         struct device_node *np;
3076         const __be32 *addr;
3077         int len;
3078
3079         if (!dev || !dev->of_node)
3080                 return NULL;
3081
3082         for_each_child_of_node(dev->of_node, np) {
3083                 addr = of_get_property(np, "reg", &len);
3084                 if (!addr || (len < sizeof(int)))
3085                         continue;
3086                 if (be32_to_cpup(addr) == slot)
3087                         return np;
3088         }
3089         return NULL;
3090 }
3091
3092 static struct dw_mci_of_slot_quirks {
3093         char *quirk;
3094         int id;
3095 } of_slot_quirks[] = {
3096         {
3097                 .quirk  = "disable-wp",
3098                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3099         },
3100 };
3101
3102 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3103 {
3104         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3105         int quirks = 0;
3106         int idx;
3107
3108         /* get quirks */
3109         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3110                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3111                         quirks |= of_slot_quirks[idx].id;
3112
3113         return quirks;
3114 }
3115
3116 /* find out bus-width for a given slot */
3117 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3118 {
3119         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3120         u32 bus_wd = 1;
3121
3122         if (!np)
3123                 return 1;
3124
3125         if (of_property_read_u32(np, "bus-width", &bus_wd))
3126                 dev_err(dev, "bus-width property not found, assuming width"
3127                                " as 1\n");
3128         return bus_wd;
3129 }
3130
3131
3132 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3133 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3134 {
3135         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3136         int gpio;
3137
3138         if (!np)
3139                 return -EINVAL;
3140
3141         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3142
3143         /* Having a missing entry is valid; return silently */
3144         if (!gpio_is_valid(gpio))
3145                 return -EINVAL;
3146
3147         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3148                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3149                 return -EINVAL;
3150         }
3151
3152     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3153
3154         return gpio;
3155 }
3156
3157
3158 /* find the write protect gpio for a given slot; or -1 if none specified */
3159 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3160 {
3161         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3162         int gpio;
3163
3164         if (!np)
3165                 return -EINVAL;
3166
3167         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3168
3169         /* Having a missing entry is valid; return silently */
3170         if (!gpio_is_valid(gpio))
3171                 return -EINVAL;
3172
3173         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3174                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3175                 return -EINVAL;
3176         }
3177
3178         return gpio;
3179 }
3180
3181 /* find the cd gpio for a given slot */
3182 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3183                                         struct mmc_host *mmc)
3184 {
3185         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3186         int gpio;
3187
3188         if (!np)
3189                 return;
3190
3191         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3192
3193         /* Having a missing entry is valid; return silently */
3194         if (!gpio_is_valid(gpio))
3195                 return;
3196
3197         if (mmc_gpio_request_cd(mmc, gpio, 0))
3198                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3199 }
3200
3201 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3202 {
3203         struct mmc_host *mmc = dev_id;
3204         struct dw_mci_slot *slot = mmc_priv(mmc);
3205         struct dw_mci *host = slot->host;
3206
3207         /* wakeup system whether gpio debounce or not */
3208         rk_send_wakeup_key();
3209
3210         /* no need to trigger detect flow when rescan is disabled.
3211            This case happended in dpm, that we just wakeup system and
3212            let suspend_post notify callback handle it.
3213          */
3214         if(mmc->rescan_disable == 0)
3215                 queue_work(host->card_workqueue, &host->card_work);
3216         else
3217                 printk("%s: rescan been disabled!\n", __FUNCTION__);
3218
3219         return IRQ_HANDLED;
3220 }
3221
3222 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3223                                         struct mmc_host *mmc)
3224 {
3225         struct dw_mci_slot *slot = mmc_priv(mmc);
3226         struct dw_mci *host = slot->host;
3227         int irq;
3228         int ret;
3229
3230         /* Having a missing entry is valid; return silently */
3231         if (!gpio_is_valid(gpio))
3232                 return;
3233
3234         irq = gpio_to_irq(gpio);
3235         if (irq >= 0) {
3236                 ret = devm_request_threaded_irq(&mmc->class_dev, irq,
3237                                                 NULL, dw_mci_gpio_cd_irqt,
3238                                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3239                                                 "dw_mci_cd", mmc);
3240                 if (ret < 0) {
3241                         irq = ret;
3242                         dev_err(host->dev, "Request cd-gpio %d interrupt error!\n", gpio);
3243                 } else{
3244                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3245                         enable_irq_wake(irq);
3246                 }
3247         } else {
3248                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3249         }
3250 }
3251
3252 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3253                                         struct mmc_host *mmc)
3254 {
3255         if (!gpio_is_valid(gpio))
3256                 return;
3257
3258         if (gpio_to_irq(gpio) >= 0) {
3259                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3260                 devm_gpio_free(&mmc->class_dev, gpio);
3261         }
3262 }
3263 #else /* CONFIG_OF */
3264 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3265 {
3266         return 0;
3267 }
3268 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3269 {
3270         return 1;
3271 }
3272 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3273 {
3274         return NULL;
3275 }
3276 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3277 {
3278         return -EINVAL;
3279 }
3280 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3281                                         struct mmc_host *mmc)
3282 {
3283         return;
3284 }
3285 #endif /* CONFIG_OF */
3286
3287 /* @host: dw_mci host prvdata
3288  * Init pinctrl for each platform. Usually we assign
3289  * "defalut" tag for functional usage, "idle" tag for gpio
3290  * state and "udbg" tag for uart_dbg if any.
3291  */
3292 static void dw_mci_init_pinctrl(struct dw_mci *host)
3293 {
3294         /* Fixme: DON'T TOUCH EMMC SETTING! */
3295         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3296                 return;
3297
3298         /* Get pinctrl for DTS */
3299         host->pinctrl = devm_pinctrl_get(host->dev);
3300         if (IS_ERR(host->pinctrl)) {
3301                 dev_err(host->dev, "%s: No pinctrl used!\n",
3302                         mmc_hostname(host->mmc));
3303                 return;
3304         }
3305
3306         /* Lookup idle state */
3307         host->pins_idle = pinctrl_lookup_state(host->pinctrl,
3308                                                 PINCTRL_STATE_IDLE);
3309         if (IS_ERR(host->pins_idle)) {
3310                 dev_err(host->dev, "%s: No idle tag found!\n",
3311                         mmc_hostname(host->mmc));
3312         } else {
3313                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3314                         dev_err(host->dev, "%s: Idle pinctrl setting failed!\n",
3315                                 mmc_hostname(host->mmc));
3316         }
3317
3318         /* Lookup default state */
3319         host->pins_default = pinctrl_lookup_state(host->pinctrl,
3320                                                         PINCTRL_STATE_DEFAULT);
3321         if (IS_ERR(host->pins_default)) {
3322                 dev_err(host->dev, "%s: No default pinctrl found!\n",
3323                         mmc_hostname(host->mmc));
3324         } else {
3325                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3326                         dev_err(host->dev, "%s:  Default pinctrl setting failed!\n",
3327                                 mmc_hostname(host->mmc));
3328         }
3329
3330         /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3331         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3332                 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3333                 if (IS_ERR(host->pins_udbg)) {
3334                         dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3335                                         mmc_hostname(host->mmc));
3336                 } else {
3337                         if (!dw_mci_get_cd(host->mmc))
3338                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3339                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3340                                                 mmc_hostname(host->mmc));
3341                 }
3342         }
3343 }
3344
3345 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3346                                         unsigned long mode, void *unused)
3347 {
3348         struct mmc_host *host = container_of(
3349                 notify_block, struct mmc_host, pm_notify);
3350         unsigned long flags;
3351
3352         switch (mode) {
3353         case PM_HIBERNATION_PREPARE:
3354         case PM_SUSPEND_PREPARE:
3355                 dev_err(host->parent, "dw_mci_pm_notify:  suspend prepare\n");
3356                 spin_lock_irqsave(&host->lock, flags);
3357                 host->rescan_disable = 1;
3358                 spin_unlock_irqrestore(&host->lock, flags);
3359                 if (cancel_delayed_work(&host->detect))
3360                         wake_unlock(&host->detect_wake_lock);
3361                 break;
3362
3363         case PM_POST_SUSPEND:
3364         case PM_POST_HIBERNATION:
3365         case PM_POST_RESTORE:
3366                 dev_err(host->parent, "dw_mci_pm_notify:  post suspend\n");
3367                 spin_lock_irqsave(&host->lock, flags);
3368                 host->rescan_disable = 0;
3369                 spin_unlock_irqrestore(&host->lock, flags);
3370                 mmc_detect_change(host, 10);
3371         }
3372
3373         return 0;
3374 }
3375
3376 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3377 {
3378         struct mmc_host *mmc;
3379         struct dw_mci_slot *slot;
3380         const struct dw_mci_drv_data *drv_data = host->drv_data;
3381         int ctrl_id, ret;
3382         u32 freq[2];
3383         u8 bus_width;
3384
3385         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3386         if (!mmc)
3387                 return -ENOMEM;
3388
3389         slot = mmc_priv(mmc);
3390         slot->id = id;
3391         slot->mmc = mmc;
3392         slot->host = host;
3393         host->slot[id] = slot;
3394         host->mmc = mmc;
3395
3396         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3397
3398         mmc->ops = &dw_mci_ops;
3399
3400         if (of_property_read_u32_array(host->dev->of_node,
3401                                        "clock-freq-min-max", freq, 2)) {
3402                 mmc->f_min = DW_MCI_FREQ_MIN;
3403                 mmc->f_max = DW_MCI_FREQ_MAX;
3404
3405                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3406                         mmc->f_min, mmc->f_max, mmc_hostname(mmc));
3407         } else {
3408                 mmc->f_min = freq[0];
3409                 mmc->f_max = freq[1];
3410
3411                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3412                         mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
3413         }
3414
3415         printk("%s : Rockchip specific MHSC: %s\n", mmc_hostname(mmc), RK_SDMMC_DRIVER_VERSION);
3416
3417         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3418                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3419         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3420                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3421         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3422                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3423         /* Fixup for tSD */
3424         if (of_find_property(host->dev->of_node, "supports-tSD", NULL))
3425                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_TSD;
3426
3427         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3428                 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3429                 if (register_pm_notifier(&mmc->pm_notify)) {
3430                         printk(KERN_ERR "dw_mci: register_pm_notifier failed\n");
3431                         goto err_pm_notifier;
3432                 }
3433         }
3434
3435         /* We assume only low-level chip use gpio_cd */
3436         if ((soc_is_rk3126() || soc_is_rk3126b()) &&
3437                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3438                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3439                 if (gpio_is_valid(slot->cd_gpio)) {
3440                         /* Request gpio int for card detection */
3441                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3442                 } else {
3443                         slot->cd_gpio = -ENODEV;
3444                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3445                 }
3446         }
3447
3448         if (host->pdata->get_ocr)
3449                 mmc->ocr_avail = host->pdata->get_ocr(id);
3450         else
3451         {
3452                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
3453                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
3454                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
3455                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
3456         }
3457
3458         /*
3459          * Start with slot power disabled, it will be enabled when a card
3460          * is detected.
3461          */
3462         if (host->pdata->setpower)
3463                 host->pdata->setpower(id, 0);
3464
3465         if (host->pdata->caps)
3466                 mmc->caps = host->pdata->caps;
3467
3468         if (host->pdata->pm_caps)
3469                 mmc->pm_caps = host->pdata->pm_caps;
3470
3471         if (host->dev->of_node) {
3472                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3473                 if (ctrl_id < 0)
3474                         ctrl_id = 0;
3475         } else {
3476                 ctrl_id = to_platform_device(host->dev)->id;
3477         }
3478         if (drv_data && drv_data->caps)
3479                 mmc->caps |= drv_data->caps[ctrl_id];
3480         if (drv_data && drv_data->hold_reg_flag)
3481                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3482
3483         /* set the compatibility of driver. */
3484         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3485                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3486
3487         if (host->pdata->caps2)
3488                 mmc->caps2 = host->pdata->caps2;
3489
3490         if (host->pdata->get_bus_wd)
3491                 bus_width = host->pdata->get_bus_wd(slot->id);
3492         else if (host->dev->of_node)
3493                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3494         else
3495                 bus_width = 1;
3496
3497         switch (bus_width) {
3498                 case 8:
3499                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3500                 case 4:
3501                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3502         }
3503
3504         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3505                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3506         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3507                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3508         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3509                 mmc->caps |= MMC_CAP_HW_RESET;
3510         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3511                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3512         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3513                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3514         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3515                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3516         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3517                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3518
3519         /*Assign pm_caps pass to pm_flags*/
3520         mmc->pm_flags = mmc->pm_caps;
3521
3522         if (host->pdata->blk_settings) {
3523                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3524                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3525                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3526                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3527                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3528         } else {
3529                 /* Useful defaults if platform data is unset. */
3530 #ifdef CONFIG_MMC_DW_IDMAC
3531                 mmc->max_segs = host->ring_size;
3532                 mmc->max_blk_size = 65536;
3533                 mmc->max_blk_count = host->ring_size;
3534                 mmc->max_seg_size = 0x1000;
3535                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3536                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3537                         /* fixup for external dmac setting */
3538                         mmc->max_segs = 64;
3539                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3540                         mmc->max_blk_count = 65535;
3541                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3542                         mmc->max_seg_size = mmc->max_req_size;
3543                 }
3544 #else
3545                 mmc->max_segs = 64;
3546                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3547                 mmc->max_blk_count = 512;
3548                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3549                 mmc->max_seg_size = mmc->max_req_size;
3550 #endif /* CONFIG_MMC_DW_IDMAC */
3551
3552         }
3553         /* pwr_en */
3554         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3555
3556         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3557         {
3558                 host->vmmc = NULL;
3559         }else{
3560
3561                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3562                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3563                 else
3564                         host->vmmc = NULL;
3565
3566                 if (IS_ERR(host->vmmc)) {
3567                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3568                         host->vmmc = NULL;
3569                 }else{
3570                         ret = regulator_enable(host->vmmc);
3571                         if (ret) {
3572                                 dev_err(host->dev,
3573                                         "failed to enable regulator: %d\n", ret);
3574                                 host->vmmc = NULL;
3575                                 goto err_setup_bus;
3576                         }
3577                 }
3578         }
3579
3580         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3581
3582         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3583                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3584
3585         dw_mci_init_pinctrl(host);
3586         ret = mmc_add_host(mmc);
3587         if (ret)
3588                 goto err_setup_bus;
3589
3590 #if defined(CONFIG_DEBUG_FS)
3591         dw_mci_init_debugfs(slot);
3592 #endif
3593
3594         /* Card initially undetected */
3595         slot->last_detect_state = 1;
3596
3597         return 0;
3598 err_pm_notifier:
3599         unregister_pm_notifier(&mmc->pm_notify);
3600
3601 err_setup_bus:
3602         if (gpio_is_valid(slot->cd_gpio))
3603                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3604         mmc_free_host(mmc);
3605         return -EINVAL;
3606 }
3607
3608 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3609 {
3610         /* Shutdown detect IRQ */
3611         if (slot->host->pdata->exit)
3612                 slot->host->pdata->exit(id);
3613
3614         /* Debugfs stuff is cleaned up by mmc core */
3615         mmc_remove_host(slot->mmc);
3616         slot->host->slot[id] = NULL;
3617         mmc_free_host(slot->mmc);
3618 }
3619
3620 static void dw_mci_init_dma(struct dw_mci *host)
3621 {
3622         /* Alloc memory for sg translation */
3623         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3624                                           &host->sg_dma, GFP_KERNEL);
3625         if (!host->sg_cpu) {
3626                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3627                         __func__);
3628                 goto no_dma;
3629         }
3630
3631         /* Determine which DMA interface to use */
3632 #if defined(CONFIG_MMC_DW_IDMAC)
3633         if(cpu_is_rk3036() || cpu_is_rk312x()){
3634                 host->dma_ops = &dw_mci_edmac_ops;
3635                 dev_info(host->dev, "Using external DMA controller.\n");
3636         }else{
3637                 host->dma_ops = &dw_mci_idmac_ops;
3638                 dev_info(host->dev, "Using internal DMA controller.\n");
3639         }
3640 #endif
3641
3642         if (!host->dma_ops)
3643                 goto no_dma;
3644
3645         if (host->dma_ops->init && host->dma_ops->start &&
3646             host->dma_ops->stop && host->dma_ops->cleanup) {
3647                 if (host->dma_ops->init(host)) {
3648                         dev_err(host->dev, "%s: Unable to initialize "
3649                                 "DMA Controller.\n", __func__);
3650                         goto no_dma;
3651                 }
3652         } else {
3653                 dev_err(host->dev, "DMA initialization not found.\n");
3654                 goto no_dma;
3655         }
3656
3657         host->use_dma = 1;
3658         return;
3659
3660 no_dma:
3661         dev_info(host->dev, "Using PIO mode.\n");
3662         host->use_dma = 0;
3663         return;
3664 }
3665
3666 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3667 {
3668         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3669         u32 ctrl;
3670
3671         ctrl = mci_readl(host, CTRL);
3672         ctrl |= reset;
3673         mci_writel(host, CTRL, ctrl);
3674
3675         /* wait till resets clear */
3676         do {
3677                 ctrl = mci_readl(host, CTRL);
3678                 if (!(ctrl & reset))
3679                         return true;
3680         } while (time_before(jiffies, timeout));
3681
3682         dev_err(host->dev,
3683                 "Timeout resetting block (ctrl reset %#x)\n",
3684                 ctrl & reset);
3685
3686         return false;
3687 }
3688
3689 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3690 {
3691         /*
3692          * Reseting generates a block interrupt, hence setting
3693          * the scatter-gather pointer to NULL.
3694          */
3695         if (host->sg) {
3696                 sg_miter_stop(&host->sg_miter);
3697                 host->sg = NULL;
3698         }
3699
3700         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3701 }
3702
3703 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3704 {
3705         return dw_mci_ctrl_reset(host,
3706                                  SDMMC_CTRL_FIFO_RESET |
3707                                  SDMMC_CTRL_RESET |
3708                                  SDMMC_CTRL_DMA_RESET);
3709 }
3710
3711 #ifdef CONFIG_OF
3712 /*
3713 static struct dw_mci_of_quirks {
3714         char *quirk;
3715         int id;
3716 } of_quirks[] = {
3717         {
3718                 .quirk  = "broken-cd",
3719                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3720         },
3721 };
3722 */
3723 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3724 {
3725         struct dw_mci_board *pdata;
3726         struct device *dev = host->dev;
3727         struct device_node *np = dev->of_node;
3728         const struct dw_mci_drv_data *drv_data = host->drv_data;
3729         int  ret;
3730         u32 clock_frequency;
3731
3732         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3733         if (!pdata) {
3734                 dev_err(dev, "could not allocate memory for pdata\n");
3735                 return ERR_PTR(-ENOMEM);
3736         }
3737
3738         /* find out number of slots supported */
3739         if (of_property_read_u32(dev->of_node, "num-slots",
3740                                 &pdata->num_slots)) {
3741                 dev_info(dev, "num-slots property not found, "
3742                                 "assuming 1 slot is available\n");
3743                 pdata->num_slots = 1;
3744         }
3745 #if 0
3746         /* get quirks */
3747         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3748                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3749                         pdata->quirks |= of_quirks[idx].id;
3750 #endif
3751
3752         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3753                 dev_info(dev, "fifo-depth property not found, using "
3754                                 "value of FIFOTH register as default\n");
3755
3756         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3757
3758         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3759                 pdata->bus_hz = clock_frequency;
3760
3761         if (drv_data && drv_data->parse_dt) {
3762                 ret = drv_data->parse_dt(host);
3763                 if (ret)
3764                         return ERR_PTR(ret);
3765         }
3766
3767         if (of_find_property(np, "keep-power-in-suspend", NULL))
3768                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3769
3770         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3771                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3772
3773         if (of_find_property(np, "supports-highspeed", NULL))
3774                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3775
3776     if (of_find_property(np, "supports-UHS_SDR104", NULL))
3777                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3778
3779     if (of_find_property(np, "supports-DDR_MODE", NULL))
3780                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3781
3782     if (of_find_property(np, "caps2-mmc-hs200", NULL))
3783                 pdata->caps2 |= MMC_CAP2_HS200;
3784
3785         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3786                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3787
3788         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3789                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3790
3791         if (of_get_property(np, "cd-inverted", NULL))
3792                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3793         if (of_get_property(np, "bootpart-no-access", NULL))
3794                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3795
3796         return pdata;
3797 }
3798
3799 #else /* CONFIG_OF */
3800 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3801 {
3802         return ERR_PTR(-EINVAL);
3803 }
3804 #endif /* CONFIG_OF */
3805
3806 static void dw_mci_dealwith_timeout(struct dw_mci *host)
3807 {
3808         u32 regs;
3809         u32 sdio_int;
3810
3811         dev_err(host->dev, "host->state = 0x%x\n", host->state);
3812         switch(host->state){
3813                 case STATE_IDLE:
3814                         break;
3815                 case STATE_SENDING_DATA:
3816                 case STATE_DATA_BUSY:
3817                         host->data_status |= (SDMMC_INT_DCRC|SDMMC_INT_EBE);
3818                         mci_writel(host, RINTSTS, SDMMC_INT_DRTO);  // clear interrupt
3819                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3820                         host->state = STATE_DATA_BUSY;
3821                         if (!dw_mci_ctrl_all_reset(host)) {
3822                                 dev_err(host->dev, "dto: ctrl_all_reset failed!\n");
3823                                 return ;
3824                         }
3825
3826                         /* NO requirement to reclaim slave chn using external dmac */
3827                         #ifdef CONFIG_MMC_DW_IDMAC
3828                         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3829                                 if (host->use_dma && host->dma_ops->init)
3830                                         host->dma_ops->init(host);
3831                         #endif
3832
3833                         /*
3834                          * Restore the initial value at FIFOTH register
3835                          * And Invalidate the prev_blksz with zero
3836                          */
3837                         mci_writel(host, FIFOTH, host->fifoth_val);
3838                         host->prev_blksz = 0;
3839                         mci_writel(host, TMOUT, 0xFFFFFFFF);
3840                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3841                         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
3842                                         | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
3843                         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
3844                                 regs |= SDMMC_INT_CD;
3845
3846                         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
3847                                 if (host->verid < DW_MMC_240A)
3848                                         sdio_int = SDMMC_INT_SDIO(0);
3849                                 else
3850                                         sdio_int = SDMMC_INT_SDIO(8);
3851
3852                                 if (mci_readl(host, INTMASK) & sdio_int)
3853                                         regs |= sdio_int;
3854                         }
3855
3856                         mci_writel(host, INTMASK, regs);
3857                         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3858                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3859                         tasklet_schedule(&host->tasklet);
3860                         break;
3861                 default:
3862                         break;
3863     }
3864 }
3865 static void dw_mci_dto_timeout(unsigned long host_data)
3866 {
3867         struct dw_mci *host = (struct dw_mci *) host_data;
3868
3869         disable_irq(host->irq);
3870
3871         dev_err(host->dev, "data_over interrupt timeout!\n");
3872         host->data_status = SDMMC_INT_EBE;
3873         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3874         dw_mci_dealwith_timeout(host);
3875
3876         enable_irq(host->irq);
3877 }
3878
3879 int dw_mci_probe(struct dw_mci *host)
3880 {
3881         const struct dw_mci_drv_data *drv_data = host->drv_data;
3882         int width, i, ret = 0;
3883         u32 fifo_size;
3884         int init_slots = 0;
3885         u32 regs;
3886
3887         if (!host->pdata) {
3888                 host->pdata = dw_mci_parse_dt(host);
3889                 if (IS_ERR(host->pdata)) {
3890                         dev_err(host->dev, "platform data not available\n");
3891                         return -EINVAL;
3892                 }
3893         }
3894
3895         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3896                 dev_err(host->dev,
3897                         "Platform data must supply select_slot function\n");
3898                 return -ENODEV;
3899         }
3900
3901         /*
3902          * In 2.40a spec, Data offset is changed.
3903          * Need to check the version-id and set data-offset for DATA register.
3904          */
3905         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3906         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3907
3908         if (host->verid < DW_MMC_240A)
3909                 host->data_offset = DATA_OFFSET;
3910         else
3911                 host->data_offset = DATA_240A_OFFSET;
3912
3913         //hclk enable
3914         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3915         if (IS_ERR(host->hclk_mmc)) {
3916                 dev_err(host->dev, "failed to get hclk_mmc\n");
3917                 ret = PTR_ERR(host->hclk_mmc);
3918                 goto err_hclk_mmc;
3919         }
3920
3921         clk_prepare_enable(host->hclk_mmc);
3922
3923         //mmc clk enable
3924         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3925         if (IS_ERR(host->clk_mmc)) {
3926                 dev_err(host->dev, "failed to get clk mmc_per\n");
3927                 ret = PTR_ERR(host->clk_mmc);
3928                 goto err_clk_mmc;
3929         }
3930
3931         host->bus_hz = host->pdata->bus_hz;
3932         if (!host->bus_hz) {
3933                 dev_err(host->dev,"Platform data must supply bus speed\n");
3934                 ret = -ENODEV;
3935                 goto err_clk_mmc;
3936         }
3937
3938         if (host->verid < DW_MMC_240A)
3939                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
3940         else
3941                 //rockchip: fix divider 2 in clksum before controlller
3942                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
3943
3944         if(ret < 0) {
3945             dev_err(host->dev, "failed to set clk mmc\n");
3946             goto err_clk_mmc;
3947         }
3948         clk_prepare_enable(host->clk_mmc);
3949
3950         if (drv_data && drv_data->setup_clock) {
3951         ret = drv_data->setup_clock(host);
3952         if (ret) {
3953             dev_err(host->dev,
3954                 "implementation specific clock setup failed\n");
3955             goto err_clk_mmc;
3956         }
3957     }
3958
3959         host->quirks = host->pdata->quirks;
3960         host->irq_state = true;
3961         host->set_speed = 0;
3962         host->set_div = 0;
3963         host->svi_flags = 0;
3964
3965         spin_lock_init(&host->lock);
3966         spin_lock_init(&host->slock);
3967
3968         INIT_LIST_HEAD(&host->queue);
3969         /*
3970          * Get the host data width - this assumes that HCON has been set with
3971          * the correct values.
3972          */
3973         i = (mci_readl(host, HCON) >> 7) & 0x7;
3974         if (!i) {
3975                 host->push_data = dw_mci_push_data16;
3976                 host->pull_data = dw_mci_pull_data16;
3977                 width = 16;
3978                 host->data_shift = 1;
3979         } else if (i == 2) {
3980                 host->push_data = dw_mci_push_data64;
3981                 host->pull_data = dw_mci_pull_data64;
3982                 width = 64;
3983                 host->data_shift = 3;
3984         } else {
3985                 /* Check for a reserved value, and warn if it is */
3986                 WARN((i != 1),
3987                      "HCON reports a reserved host data width!\n"
3988                      "Defaulting to 32-bit access.\n");
3989                 host->push_data = dw_mci_push_data32;
3990                 host->pull_data = dw_mci_pull_data32;
3991                 width = 32;
3992                 host->data_shift = 2;
3993         }
3994
3995         /* Reset all blocks */
3996         if (!dw_mci_ctrl_all_reset(host))
3997                 return -ENODEV;
3998
3999         host->dma_ops = host->pdata->dma_ops;
4000         dw_mci_init_dma(host);
4001
4002         /* Clear the interrupts for the host controller */
4003         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4004         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4005
4006         /* Put in max timeout */
4007         mci_writel(host, TMOUT, 0xFFFFFFFF);
4008
4009         /*
4010          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
4011          *                          Tx Mark = fifo_size / 2 DMA Size = 8
4012          */
4013         if (!host->pdata->fifo_depth) {
4014                 /*
4015                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4016                  * have been overwritten by the bootloader, just like we're
4017                  * about to do, so if you know the value for your hardware, you
4018                  * should put it in the platform data.
4019                  */
4020                 fifo_size = mci_readl(host, FIFOTH);
4021                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4022         } else {
4023                 fifo_size = host->pdata->fifo_depth;
4024         }
4025         host->fifo_depth = fifo_size;
4026         host->fifoth_val =
4027                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4028         mci_writel(host, FIFOTH, host->fifoth_val);
4029
4030         /* disable clock to CIU */
4031         mci_writel(host, CLKENA, 0);
4032         mci_writel(host, CLKSRC, 0);
4033
4034         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4035         host->card_workqueue = alloc_workqueue("dw-mci-card",
4036                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4037         if (!host->card_workqueue) {
4038                 ret = -ENOMEM;
4039                 goto err_dmaunmap;
4040         }
4041         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4042         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4043                                host->irq_flags, "dw-mci", host);
4044         if (ret)
4045                 goto err_workqueue;
4046
4047         if (host->pdata->num_slots)
4048                 host->num_slots = host->pdata->num_slots;
4049         else
4050                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4051
4052         setup_timer(&host->dto_timer, dw_mci_dto_timeout, (unsigned long)host);
4053         /* We need at least one slot to succeed */
4054         for (i = 0; i < host->num_slots; i++) {
4055                 ret = dw_mci_init_slot(host, i);
4056                 if (ret)
4057                         dev_dbg(host->dev, "slot %d init failed\n", i);
4058                 else
4059                         init_slots++;
4060         }
4061
4062         /*
4063          * Enable interrupts for command done, data over, data empty, card det,
4064          * receive ready and error such as transmit, receive timeout, crc error
4065          */
4066         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4067         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
4068                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4069         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
4070             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4071             regs |= SDMMC_INT_CD;
4072
4073         mci_writel(host, INTMASK, regs);
4074
4075         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4076
4077         dev_info(host->dev, "DW MMC controller at irq %d, "
4078                  "%d bit host data width, "
4079                  "%u deep fifo\n",
4080                  host->irq, width, fifo_size);
4081
4082         if (init_slots) {
4083                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4084         } else {
4085                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4086                                         "but failed on all\n", host->num_slots);
4087                 goto err_workqueue;
4088         }
4089
4090
4091         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4092                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4093
4094         return 0;
4095
4096 err_workqueue:
4097         destroy_workqueue(host->card_workqueue);
4098
4099 err_dmaunmap:
4100         if (host->use_dma && host->dma_ops->exit)
4101                 host->dma_ops->exit(host);
4102
4103         if (host->vmmc){
4104                 regulator_disable(host->vmmc);
4105                 regulator_put(host->vmmc);
4106         }
4107
4108 err_clk_mmc:
4109     if (!IS_ERR(host->clk_mmc))
4110                 clk_disable_unprepare(host->clk_mmc);
4111 err_hclk_mmc:
4112     if (!IS_ERR(host->hclk_mmc))
4113                 clk_disable_unprepare(host->hclk_mmc);
4114
4115         return ret;
4116 }
4117 EXPORT_SYMBOL(dw_mci_probe);
4118
4119 void dw_mci_remove(struct dw_mci *host)
4120 {
4121         struct mmc_host *mmc = host->mmc;
4122         struct dw_mci_slot *slot = mmc_priv(mmc);
4123         int i;
4124
4125         del_timer_sync(&host->dto_timer);
4126
4127         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4128         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4129
4130         for(i = 0; i < host->num_slots; i++){
4131                 dev_dbg(host->dev, "remove slot %d\n", i);
4132                 if(host->slot[i])
4133                         dw_mci_cleanup_slot(host->slot[i], i);
4134         }
4135
4136         /* disable clock to CIU */
4137         mci_writel(host, CLKENA, 0);
4138         mci_writel(host, CLKSRC, 0);
4139
4140         destroy_workqueue(host->card_workqueue);
4141         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4142                 unregister_pm_notifier(&host->mmc->pm_notify);
4143
4144         if(host->use_dma && host->dma_ops->exit)
4145                 host->dma_ops->exit(host);
4146
4147         if (gpio_is_valid(slot->cd_gpio))
4148                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4149
4150         if(host->vmmc){
4151                 regulator_disable(host->vmmc);
4152                 regulator_put(host->vmmc);
4153         }
4154         if(!IS_ERR(host->clk_mmc))
4155                 clk_disable_unprepare(host->clk_mmc);
4156
4157         if(!IS_ERR(host->hclk_mmc))
4158                 clk_disable_unprepare(host->hclk_mmc);
4159 }
4160 EXPORT_SYMBOL(dw_mci_remove);
4161
4162
4163
4164 #ifdef CONFIG_PM_SLEEP
4165 /*
4166  * TODO: we should probably disable the clock to the card in the suspend path.
4167  */
4168 extern int get_wifi_chip_type(void);
4169 int dw_mci_suspend(struct dw_mci *host)
4170 {
4171         struct dw_mci_slot *slot = mmc_priv(host->mmc);
4172
4173         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4174                 (get_wifi_chip_type() == WIFI_ESP8089))
4175                 return 0;
4176
4177         if(host->vmmc)
4178                 regulator_disable(host->vmmc);
4179
4180         /*only for sdmmc controller*/
4181         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4182                 disable_irq(host->irq);
4183                 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
4184                         if (!IS_ERR(host->pins_idle) &&
4185                                 pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4186                                 MMC_DBG_ERR_FUNC(host->mmc, "Idle pinctrl setting failed! [%s]",
4187                                                         mmc_hostname(host->mmc));
4188                 } else {
4189                         if (IS_ERR(host->pins_udbg) && !IS_ERR(host->pins_idle) &&
4190                                 pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4191                                 MMC_DBG_ERR_FUNC(host->mmc, "Idle pinctrl setting failed! [%s]",
4192                                                         mmc_hostname(host->mmc));
4193                 }
4194
4195                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4196                 mci_writel(host, INTMASK, 0x00);
4197                 mci_writel(host, CTRL, 0x00);
4198
4199                 /* Soc rk3126 already in gpio_cd mode */
4200                 if (!soc_is_rk3126() && !soc_is_rk3126b()) {
4201                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4202                         enable_irq_wake(host->mmc->slot.cd_irq);
4203                 }
4204         }
4205         return 0;
4206 }
4207 EXPORT_SYMBOL(dw_mci_suspend);
4208
4209 int dw_mci_resume(struct dw_mci *host)
4210 {
4211         int i, ret;
4212         u32 regs;
4213         struct dw_mci_slot *slot;
4214
4215         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4216                 (get_wifi_chip_type() == WIFI_ESP8089))
4217                 return 0;
4218
4219
4220
4221         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4222                 slot = mmc_priv(host->mmc);
4223                 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4224                         return 0;
4225         }
4226
4227         /*only for sdmmc controller*/
4228         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4229                 /* Soc rk3126 already in gpio_cd mode */
4230                 if (!soc_is_rk3126() && !soc_is_rk3126b()) {
4231                         disable_irq_wake(host->mmc->slot.cd_irq);
4232                         mmc_gpio_free_cd(host->mmc);
4233                 }
4234
4235                 if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
4236                         if (!IS_ERR(host->pins_default) &&
4237                                 pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4238                                 MMC_DBG_ERR_FUNC(host->mmc, "Default pinctrl setting failed! [%s]",
4239                                                 mmc_hostname(host->mmc));
4240                 } else {
4241                         if (IS_ERR(host->pins_udbg) && !IS_ERR(host->pins_default) &&
4242                                 pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4243                                 MMC_DBG_ERR_FUNC(host->mmc, "Default pinctrl setting failed! [%s]",
4244                                                 mmc_hostname(host->mmc));
4245                 }
4246
4247                 /* Disable jtag*/
4248                 if(cpu_is_rk3288())
4249                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4250                 else if(cpu_is_rk3036())
4251                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4252                 else if(cpu_is_rk312x())
4253                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4254                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4255         }
4256         if(host->vmmc){
4257                 ret = regulator_enable(host->vmmc);
4258                 if (ret){
4259                         dev_err(host->dev,
4260                                 "failed to enable regulator: %d\n", ret);
4261                         return ret;
4262                 }
4263         }
4264
4265         if(!dw_mci_ctrl_all_reset(host)){
4266                 ret = -ENODEV;
4267                 return ret;
4268         }
4269
4270         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
4271                 if(host->use_dma && host->dma_ops->init)
4272                         host->dma_ops->init(host);
4273
4274         /*
4275          * Restore the initial value at FIFOTH register
4276          * And Invalidate the prev_blksz with zero
4277          */
4278         mci_writel(host, FIFOTH, host->fifoth_val);
4279         host->prev_blksz = 0;
4280         /* Put in max timeout */
4281         mci_writel(host, TMOUT, 0xFFFFFFFF);
4282
4283         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4284         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
4285                    DW_MCI_ERROR_FLAGS;
4286         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4287             regs |= SDMMC_INT_CD;
4288         mci_writel(host, INTMASK, regs);
4289         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4290         /*only for sdmmc controller*/
4291         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)){
4292                 enable_irq(host->irq);
4293         }
4294
4295         for(i = 0; i < host->num_slots; i++){
4296                 struct dw_mci_slot *slot = host->slot[i];
4297                 if(!slot)
4298                         continue;
4299                 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4300                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4301                         dw_mci_setup_bus(slot, true);
4302                 }
4303         }
4304
4305         return 0;
4306 }
4307 EXPORT_SYMBOL(dw_mci_resume);
4308 #endif /* CONFIG_PM_SLEEP */
4309
4310 static int __init dw_mci_init(void)
4311 {
4312         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4313         return 0;
4314 }
4315
4316 static void __exit dw_mci_exit(void)
4317 {
4318 }
4319
4320 module_init(dw_mci_init);
4321 module_exit(dw_mci_exit);
4322
4323 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4324 MODULE_AUTHOR("NXP Semiconductor VietNam");
4325 MODULE_AUTHOR("Imagination Technologies Ltd");
4326 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4327 MODULE_AUTHOR("Bangwang Xie <xbw@rock-chips.com>");
4328 MODULE_LICENSE("GPL v2");