drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/mmc/host.h>
  33 #include <linux/mmc/mmc.h>
  34 #include <linux/mmc/dw_mmc.h>
  35 #include <linux/bitops.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40
  41 #include "rk_sdmmc.h"
  42
  43 /* Common flag combinations */
  44 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  45                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  46                                  SDMMC_INT_EBE)
  47 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  48                                  SDMMC_INT_RESP_ERR)
  49 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  50                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  51 #define DW_MCI_SEND_STATUS      1
  52 #define DW_MCI_RECV_STATUS      2
  53 #define DW_MCI_DMA_THRESHOLD    16
  54
  55 #ifdef CONFIG_MMC_DW_IDMAC
  56 struct idmac_desc {
  57         u32             des0;   /* Control Descriptor */
  58 #define IDMAC_DES0_DIC  BIT(1)
  59 #define IDMAC_DES0_LD   BIT(2)
  60 #define IDMAC_DES0_FD   BIT(3)
  61 #define IDMAC_DES0_CH   BIT(4)
  62 #define IDMAC_DES0_ER   BIT(5)
  63 #define IDMAC_DES0_CES  BIT(30)
  64 #define IDMAC_DES0_OWN  BIT(31)
  65
  66         u32             des1;   /* Buffer sizes */
  67 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  68         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  69
  70         u32             des2;   /* buffer 1 physical address */
  71
  72         u32             des3;   /* buffer 2 physical address */
  73 };
  74 #endif /* CONFIG_MMC_DW_IDMAC */
  75
  76 /**
  77  * struct dw_mci_slot - MMC slot state
  78  * @mmc: The mmc_host representing this slot.
  79  * @host: The MMC controller this slot is using.
  80  * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
  81  * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
  82  * @ctype: Card type for this slot.
  83  * @mrq: mmc_request currently being processed or waiting to be
  84  *      processed, or NULL when the slot is idle.
  85  * @queue_node: List node for placing this node in the @queue list of
  86  *      &struct dw_mci.
  87  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  88  * @flags: Random state bits associated with the slot.
  89  * @id: Number of this slot.
  90  * @last_detect_state: Most recently observed card detect state.
  91  */
  92 struct dw_mci_slot {
  93         struct mmc_host         *mmc;
  94         struct dw_mci           *host;
  95
  96         int                     quirks;
  97         int                     wp_gpio;
  98     int         pwr_en_gpio;
  99         u32                     ctype;
 100
 101         struct mmc_request      *mrq;
 102         struct list_head        queue_node;
 103
 104         unsigned int            clock;
 105         unsigned long           flags;
 106 #define DW_MMC_CARD_PRESENT     0
 107 #define DW_MMC_CARD_NEED_INIT   1
 108         int                     id;
 109         int                     last_detect_state;
 110 };
 111
 112 #if defined(CONFIG_DEBUG_FS)
 113 static int dw_mci_req_show(struct seq_file *s, void *v)
 114 {
 115         struct dw_mci_slot *slot = s->private;
 116         struct mmc_request *mrq;
 117         struct mmc_command *cmd;
 118         struct mmc_command *stop;
 119         struct mmc_data *data;
 120
 121         /* Make sure we get a consistent snapshot */
 122         spin_lock_bh(&slot->host->lock);
 123         mrq = slot->mrq;
 124
 125         if (mrq) {
 126                 cmd = mrq->cmd;
 127                 data = mrq->data;
 128                 stop = mrq->stop;
 129
 130                 if (cmd)
 131                         seq_printf(s,
 132                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 133                                    cmd->opcode, cmd->arg, cmd->flags,
 134                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 135                                    cmd->resp[2], cmd->error);
 136                 if (data)
 137                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 138                                    data->bytes_xfered, data->blocks,
 139                                    data->blksz, data->flags, data->error);
 140                 if (stop)
 141                         seq_printf(s,
 142                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 143                                    stop->opcode, stop->arg, stop->flags,
 144                                    stop->resp[0], stop->resp[1], stop->resp[2],
 145                                    stop->resp[2], stop->error);
 146         }
 147
 148         spin_unlock_bh(&slot->host->lock);
 149
 150         return 0;
 151 }
 152
 153 static int dw_mci_req_open(struct inode *inode, struct file *file)
 154 {
 155         return single_open(file, dw_mci_req_show, inode->i_private);
 156 }
 157
 158 static const struct file_operations dw_mci_req_fops = {
 159         .owner          = THIS_MODULE,
 160         .open           = dw_mci_req_open,
 161         .read           = seq_read,
 162         .llseek         = seq_lseek,
 163         .release        = single_release,
 164 };
 165
 166 static int dw_mci_regs_show(struct seq_file *s, void *v)
 167 {
 168         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 170         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 171         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 172         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 173         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static void dw_mci_set_timeout(struct dw_mci *host)
 234 {
 235         /* timeout (maximum) */
 236         mci_writel(host, TMOUT, 0xffffffff);
 237 }
 238
 239 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 240 {
 241         struct mmc_data *data;
 242         struct dw_mci_slot *slot = mmc_priv(mmc);
 243         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 244         u32 cmdr;
 245         cmd->error = -EINPROGRESS;
 246
 247         cmdr = cmd->opcode;
 248
 249         if (cmdr == MMC_STOP_TRANSMISSION)
 250                 cmdr |= SDMMC_CMD_STOP;
 251         else
 252                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 253
 254         if (cmd->flags & MMC_RSP_PRESENT) {
 255                 /* We expect a response, so set this bit */
 256                 cmdr |= SDMMC_CMD_RESP_EXP;
 257                 if (cmd->flags & MMC_RSP_136)
 258                         cmdr |= SDMMC_CMD_RESP_LONG;
 259         }
 260
 261         if (cmd->flags & MMC_RSP_CRC)
 262                 cmdr |= SDMMC_CMD_RESP_CRC;
 263
 264         data = cmd->data;
 265         if (data) {
 266                 cmdr |= SDMMC_CMD_DAT_EXP;
 267                 if (data->flags & MMC_DATA_STREAM)
 268                         cmdr |= SDMMC_CMD_STRM_MODE;
 269                 if (data->flags & MMC_DATA_WRITE)
 270                         cmdr |= SDMMC_CMD_DAT_WR;
 271         }
 272
 273         if (drv_data && drv_data->prepare_command)
 274                 drv_data->prepare_command(slot->host, &cmdr);
 275
 276         return cmdr;
 277 }
 278
 279 static void dw_mci_start_command(struct dw_mci *host,
 280                                  struct mmc_command *cmd, u32 cmd_flags)
 281 {
 282         host->cmd = cmd;
 283         dev_vdbg(host->dev,
 284                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 285                  cmd->arg, cmd_flags);
 286
 287         mci_writel(host, CMDARG, cmd->arg);
 288         wmb();
 289
 290         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 291 }
 292
 293 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 294 {
 295         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 296 }
 297
 298 /* DMA interface functions */
 299 static void dw_mci_stop_dma(struct dw_mci *host)
 300 {
 301         if (host->using_dma) {
 302                 host->dma_ops->stop(host);
 303                 host->dma_ops->cleanup(host);
 304         } else {
 305                 /* Data transfer was stopped by the interrupt handler */
 306                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 307         }
 308 }
 309
 310 static int dw_mci_get_dma_dir(struct mmc_data *data)
 311 {
 312         if (data->flags & MMC_DATA_WRITE)
 313                 return DMA_TO_DEVICE;
 314         else
 315                 return DMA_FROM_DEVICE;
 316 }
 317
 318 #ifdef CONFIG_MMC_DW_IDMAC
 319 static void dw_mci_dma_cleanup(struct dw_mci *host)
 320 {
 321         struct mmc_data *data = host->data;
 322
 323         if (data)
 324                 if (!data->host_cookie)
 325                         dma_unmap_sg(host->dev,
 326                                      data->sg,
 327                                      data->sg_len,
 328                                      dw_mci_get_dma_dir(data));
 329 }
 330
 331 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 332 {
 333         u32 temp;
 334
 335         /* Disable and reset the IDMAC interface */
 336         temp = mci_readl(host, CTRL);
 337         temp &= ~SDMMC_CTRL_USE_IDMAC;
 338         temp |= SDMMC_CTRL_DMA_RESET;
 339         mci_writel(host, CTRL, temp);
 340
 341         /* Stop the IDMAC running */
 342         temp = mci_readl(host, BMOD);
 343         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 344         mci_writel(host, BMOD, temp);
 345 }
 346
 347 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 348 {
 349         struct mmc_data *data = host->data;
 350
 351         dev_vdbg(host->dev, "DMA complete\n");
 352
 353         host->dma_ops->cleanup(host);
 354
 355         /*
 356          * If the card was removed, data will be NULL. No point in trying to
 357          * send the stop command or waiting for NBUSY in this case.
 358          */
 359         if (data) {
 360                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 361                 tasklet_schedule(&host->tasklet);
 362         }
 363 }
 364
 365 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 366                                     unsigned int sg_len)
 367 {
 368         int i;
 369         struct idmac_desc *desc = host->sg_cpu;
 370
 371         for (i = 0; i < sg_len; i++, desc++) {
 372                 unsigned int length = sg_dma_len(&data->sg[i]);
 373                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 374
 375                 /* Set the OWN bit and disable interrupts for this descriptor */
 376                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 377
 378                 /* Buffer length */
 379                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 380
 381                 /* Physical address to DMA to/from */
 382                 desc->des2 = mem_addr;
 383         }
 384
 385         /* Set first descriptor */
 386         desc = host->sg_cpu;
 387         desc->des0 |= IDMAC_DES0_FD;
 388
 389         /* Set last descriptor */
 390         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 391         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 392         desc->des0 |= IDMAC_DES0_LD;
 393
 394         wmb();
 395 }
 396
 397 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 398 {
 399         u32 temp;
 400
 401         dw_mci_translate_sglist(host, host->data, sg_len);
 402
 403         /* Select IDMAC interface */
 404         temp = mci_readl(host, CTRL);
 405         temp |= SDMMC_CTRL_USE_IDMAC;
 406         mci_writel(host, CTRL, temp);
 407
 408         wmb();
 409
 410         /* Enable the IDMAC */
 411         temp = mci_readl(host, BMOD);
 412         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 413         mci_writel(host, BMOD, temp);
 414
 415         /* Start it running */
 416         mci_writel(host, PLDMND, 1);
 417 }
 418
 419 static int dw_mci_idmac_init(struct dw_mci *host)
 420 {
 421         struct idmac_desc *p;
 422         int i;
 423
 424         /* Number of descriptors in the ring buffer */
 425         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 426
 427         /* Forward link the descriptor list */
 428         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 429                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 430
 431         /* Set the last descriptor as the end-of-ring descriptor */
 432         p->des3 = host->sg_dma;
 433         p->des0 = IDMAC_DES0_ER;
 434
 435         mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
 436
 437         /* Mask out interrupts - get Tx & Rx complete only */
 438         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 439                    SDMMC_IDMAC_INT_TI);
 440
 441         /* Set the descriptor base address */
 442         mci_writel(host, DBADDR, host->sg_dma);
 443         return 0;
 444 }
 445
 446 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 447         .init = dw_mci_idmac_init,
 448         .start = dw_mci_idmac_start_dma,
 449         .stop = dw_mci_idmac_stop_dma,
 450         .complete = dw_mci_idmac_complete_dma,
 451         .cleanup = dw_mci_dma_cleanup,
 452 };
 453 #endif /* CONFIG_MMC_DW_IDMAC */
 454
 455 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 456                                    struct mmc_data *data,
 457                                    bool next)
 458 {
 459         struct scatterlist *sg;
 460         unsigned int i, sg_len;
 461
 462         if (!next && data->host_cookie)
 463                 return data->host_cookie;
 464
 465         /*
 466          * We don't do DMA on "complex" transfers, i.e. with
 467          * non-word-aligned buffers or lengths. Also, we don't bother
 468          * with all the DMA setup overhead for short transfers.
 469          */
 470         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 471                 return -EINVAL;
 472
 473         if (data->blksz & 3)
 474                 return -EINVAL;
 475
 476         for_each_sg(data->sg, sg, data->sg_len, i) {
 477                 if (sg->offset & 3 || sg->length & 3)
 478                         return -EINVAL;
 479         }
 480
 481         sg_len = dma_map_sg(host->dev,
 482                             data->sg,
 483                             data->sg_len,
 484                             dw_mci_get_dma_dir(data));
 485         if (sg_len == 0)
 486                 return -EINVAL;
 487
 488         if (next)
 489                 data->host_cookie = sg_len;
 490
 491         return sg_len;
 492 }
 493
 494 static void dw_mci_pre_req(struct mmc_host *mmc,
 495                            struct mmc_request *mrq,
 496                            bool is_first_req)
 497 {
 498         struct dw_mci_slot *slot = mmc_priv(mmc);
 499         struct mmc_data *data = mrq->data;
 500
 501         if (!slot->host->use_dma || !data)
 502                 return;
 503
 504         if (data->host_cookie) {
 505                 data->host_cookie = 0;
 506                 return;
 507         }
 508
 509         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 510                 data->host_cookie = 0;
 511 }
 512
 513 static void dw_mci_post_req(struct mmc_host *mmc,
 514                             struct mmc_request *mrq,
 515                             int err)
 516 {
 517         struct dw_mci_slot *slot = mmc_priv(mmc);
 518         struct mmc_data *data = mrq->data;
 519
 520         if (!slot->host->use_dma || !data)
 521                 return;
 522
 523         if (data->host_cookie)
 524                 dma_unmap_sg(slot->host->dev,
 525                              data->sg,
 526                              data->sg_len,
 527                              dw_mci_get_dma_dir(data));
 528         data->host_cookie = 0;
 529 }
 530
 531 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 532 {
 533         int sg_len;
 534         u32 temp;
 535
 536         host->using_dma = 0;
 537
 538         /* If we don't have a channel, we can't do DMA */
 539         if (!host->use_dma)
 540                 return -ENODEV;
 541
 542         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 543         if (sg_len < 0) {
 544                 host->dma_ops->stop(host);
 545                 return sg_len;
 546         }
 547
 548         host->using_dma = 1;
 549
 550         dev_vdbg(host->dev,
 551                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 552                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 553                  sg_len);
 554
 555         /* Enable the DMA interface */
 556         temp = mci_readl(host, CTRL);
 557         temp |= SDMMC_CTRL_DMA_ENABLE;
 558         mci_writel(host, CTRL, temp);
 559
 560         /* Disable RX/TX IRQs, let DMA handle it */
 561         temp = mci_readl(host, INTMASK);
 562         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 563         mci_writel(host, INTMASK, temp);
 564
 565         host->dma_ops->start(host, sg_len);
 566
 567         return 0;
 568 }
 569
 570 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 571 {
 572         u32 temp;
 573
 574         data->error = -EINPROGRESS;
 575
 576         WARN_ON(host->data);
 577         host->sg = NULL;
 578         host->data = data;
 579
 580         if (data->flags & MMC_DATA_READ)
 581                 host->dir_status = DW_MCI_RECV_STATUS;
 582         else
 583                 host->dir_status = DW_MCI_SEND_STATUS;
 584
 585         if (dw_mci_submit_data_dma(host, data)) {
 586                 int flags = SG_MITER_ATOMIC;
 587                 if (host->data->flags & MMC_DATA_READ)
 588                         flags |= SG_MITER_TO_SG;
 589                 else
 590                         flags |= SG_MITER_FROM_SG;
 591
 592                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 593                 host->sg = data->sg;
 594                 host->part_buf_start = 0;
 595                 host->part_buf_count = 0;
 596
 597                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 598                 temp = mci_readl(host, INTMASK);
 599                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 600                 mci_writel(host, INTMASK, temp);
 601
 602                 temp = mci_readl(host, CTRL);
 603                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 604                 mci_writel(host, CTRL, temp);
 605         }
 606 }
 607
 608 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 609 {
 610         struct dw_mci *host = slot->host;
 611         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 612         unsigned int cmd_status = 0;
 613
 614         mci_writel(host, CMDARG, arg);
 615         wmb();
 616         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 617
 618         while (time_before(jiffies, timeout)) {
 619                 cmd_status = mci_readl(host, CMD);
 620                 if (!(cmd_status & SDMMC_CMD_START))
 621                         return;
 622         }
 623         dev_err(&slot->mmc->class_dev,
 624                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 625                 cmd, arg, cmd_status);
 626 }
 627
 628 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 629 {
 630         struct dw_mci *host = slot->host;
 631         u32 div;
 632         u32 clk_en_a;
 633
 634         if (slot->clock != host->current_speed || force_clkinit) {
 635                 div = host->bus_hz / slot->clock;
 636                 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
 637                         /*
 638                          * move the + 1 after the divide to prevent
 639                          * over-clocking the card.
 640                          */
 641                         div += 1;
 642
 643                 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 644
 645                 dev_info(&slot->mmc->class_dev,
 646                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 647                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 648                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 649
 650                 /* disable clock */
 651                 mci_writel(host, CLKENA, 0);
 652                 mci_writel(host, CLKSRC, 0);
 653
 654                 /* inform CIU */
 655                 mci_send_cmd(slot,
 656                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 657
 658                 /* set clock to desired speed */
 659                 mci_writel(host, CLKDIV, div);
 660
 661                 /* inform CIU */
 662                 mci_send_cmd(slot,
 663                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 664
 665                 /* enable clock; only low power if no SDIO */
 666                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 667                 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
 668                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 669                 mci_writel(host, CLKENA, clk_en_a);
 670
 671                 /* inform CIU */
 672                 mci_send_cmd(slot,
 673                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 674
 675                 host->current_speed = slot->clock;
 676         }
 677
 678         /* Set the current slot bus width */
 679         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 680 }
 681
 682 static void __dw_mci_start_request(struct dw_mci *host,
 683                                    struct dw_mci_slot *slot,
 684                                    struct mmc_command *cmd)
 685 {
 686         struct mmc_request *mrq;
 687         struct mmc_data *data;
 688         u32 cmdflags;
 689
 690         mrq = slot->mrq;
 691         if (host->pdata->select_slot)
 692                 host->pdata->select_slot(slot->id);
 693
 694         host->cur_slot = slot;
 695         host->mrq = mrq;
 696
 697         host->pending_events = 0;
 698         host->completed_events = 0;
 699         host->data_status = 0;
 700
 701         data = cmd->data;
 702         if (data) {
 703                 dw_mci_set_timeout(host);
 704                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 705                 mci_writel(host, BLKSIZ, data->blksz);
 706         }
 707
 708         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 709
 710         /* this is the first command, send the initialization clock */
 711         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 712                 cmdflags |= SDMMC_CMD_INIT;
 713
 714         if (data) {
 715                 dw_mci_submit_data(host, data);
 716                 wmb();
 717         }
 718
 719         dw_mci_start_command(host, cmd, cmdflags);
 720
 721         if (mrq->stop)
 722                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 723 }
 724
 725 static void dw_mci_start_request(struct dw_mci *host,
 726                                  struct dw_mci_slot *slot)
 727 {
 728         struct mmc_request *mrq = slot->mrq;
 729         struct mmc_command *cmd;
 730
 731         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 732         __dw_mci_start_request(host, slot, cmd);
 733 }
 734
 735 /* must be called with host->lock held */
 736 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 737                                  struct mmc_request *mrq)
 738 {
 739         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 740                  host->state);
 741
 742         slot->mrq = mrq;
 743
 744         if (host->state == STATE_IDLE) {
 745                 host->state = STATE_SENDING_CMD;
 746                 dw_mci_start_request(host, slot);
 747         } else {
 748                 list_add_tail(&slot->queue_node, &host->queue);
 749         }
 750 }
 751
 752 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 753 {
 754         struct dw_mci_slot *slot = mmc_priv(mmc);
 755         struct dw_mci *host = slot->host;
 756
 757         WARN_ON(slot->mrq);
 758
 759         /*
 760          * The check for card presence and queueing of the request must be
 761          * atomic, otherwise the card could be removed in between and the
 762          * request wouldn't fail until another card was inserted.
 763          */
 764         spin_lock_bh(&host->lock);
 765
 766         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 767                 spin_unlock_bh(&host->lock);
 768                 mrq->cmd->error = -ENOMEDIUM;
 769                 mmc_request_done(mmc, mrq);
 770                 return;
 771         }
 772
 773         dw_mci_queue_request(host, slot, mrq);
 774
 775         spin_unlock_bh(&host->lock);
 776 }
 777
 778 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 779 {
 780         struct dw_mci_slot *slot = mmc_priv(mmc);
 781         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 782         u32 regs;
 783
 784         switch (ios->bus_width) {
 785         case MMC_BUS_WIDTH_4:
 786                 slot->ctype = SDMMC_CTYPE_4BIT;
 787                 break;
 788         case MMC_BUS_WIDTH_8:
 789                 slot->ctype = SDMMC_CTYPE_8BIT;
 790                 break;
 791         default:
 792                 /* set default 1 bit mode */
 793                 slot->ctype = SDMMC_CTYPE_1BIT;
 794         }
 795
 796         regs = mci_readl(slot->host, UHS_REG);
 797
 798         /* DDR mode set */
 799         if (ios->timing == MMC_TIMING_UHS_DDR50)
 800                 regs |= ((0x1 << slot->id) << 16);
 801         else
 802                 regs &= ~((0x1 << slot->id) << 16);
 803
 804         mci_writel(slot->host, UHS_REG, regs);
 805
 806         if (ios->clock) {
 807                 /*
 808                  * Use mirror of ios->clock to prevent race with mmc
 809                  * core ios update when finding the minimum.
 810                  */
 811                 slot->clock = ios->clock;
 812         }
 813
 814         if (drv_data && drv_data->set_ios)
 815                 drv_data->set_ios(slot->host, ios);
 816
 817         /* Slot specific timing and width adjustment */
 818         dw_mci_setup_bus(slot, false);
 819
 820         switch (ios->power_mode) {
 821         case MMC_POWER_UP:
 822                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 823                 /* Power up slot */
 824                 if (slot->host->pdata->setpower)
 825                         slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
 826                 regs = mci_readl(slot->host, PWREN);
 827                 regs |= (1 << slot->id);
 828                 mci_writel(slot->host, PWREN, regs);
 829                 break;
 830         case MMC_POWER_OFF:
 831                 /* Power down slot */
 832                 if (slot->host->pdata->setpower)
 833                         slot->host->pdata->setpower(slot->id, 0);
 834                 regs = mci_readl(slot->host, PWREN);
 835                 regs &= ~(1 << slot->id);
 836                 mci_writel(slot->host, PWREN, regs);
 837                 break;
 838         default:
 839                 break;
 840         }
 841 }
 842
 843 static int dw_mci_get_ro(struct mmc_host *mmc)
 844 {
 845         int read_only;
 846         struct dw_mci_slot *slot = mmc_priv(mmc);
 847         struct dw_mci_board *brd = slot->host->pdata;
 848
 849         /* Use platform get_ro function, else try on board write protect */
 850         if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
 851                 read_only = 0;
 852         else if (brd->get_ro)
 853                 read_only = brd->get_ro(slot->id);
 854         else if (gpio_is_valid(slot->wp_gpio))
 855                 read_only = gpio_get_value(slot->wp_gpio);
 856         else
 857                 read_only =
 858                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 859
 860         dev_dbg(&mmc->class_dev, "card is %s\n",
 861                 read_only ? "read-only" : "read-write");
 862
 863         return read_only;
 864 }
 865
 866 static int dw_mci_get_cd(struct mmc_host *mmc)
 867 {
 868         int present;
 869         struct dw_mci_slot *slot = mmc_priv(mmc);
 870         struct dw_mci_board *brd = slot->host->pdata;
 871
 872         /* Use platform get_cd function, else try onboard card detect */
 873         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 874                 present = 1;
 875         else if (brd->get_cd)
 876                 present = !brd->get_cd(slot->id);
 877         else
 878                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 879                         == 0 ? 1 : 0;
 880
 881         if (present)
 882                 dev_dbg(&mmc->class_dev, "card is present\n");
 883         else
 884                 dev_dbg(&mmc->class_dev, "card is not present\n");
 885
 886         return present;
 887 }
 888
 889 /*
 890  * Disable lower power mode.
 891  *
 892  * Low power mode will stop the card clock when idle.  According to the
 893  * description of the CLKENA register we should disable low power mode
 894  * for SDIO cards if we need SDIO interrupts to work.
 895  *
 896  * This function is fast if low power mode is already disabled.
 897  */
 898 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
 899 {
 900         struct dw_mci *host = slot->host;
 901         u32 clk_en_a;
 902         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
 903
 904         clk_en_a = mci_readl(host, CLKENA);
 905
 906         if (clk_en_a & clken_low_pwr) {
 907                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
 908                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 909                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 910         }
 911 }
 912
 913 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 914 {
 915         struct dw_mci_slot *slot = mmc_priv(mmc);
 916         struct dw_mci *host = slot->host;
 917         u32 int_mask;
 918
 919         /* Enable/disable Slot Specific SDIO interrupt */
 920         int_mask = mci_readl(host, INTMASK);
 921         if (enb) {
 922                 /*
 923                  * Turn off low power mode if it was enabled.  This is a bit of
 924                  * a heavy operation and we disable / enable IRQs a lot, so
 925                  * we'll leave low power mode disabled and it will get
 926                  * re-enabled again in dw_mci_setup_bus().
 927                  */
 928                 dw_mci_disable_low_power(slot);
 929
 930                 mci_writel(host, INTMASK,
 931                            (int_mask | SDMMC_INT_SDIO(slot->id)));
 932         } else {
 933                 mci_writel(host, INTMASK,
 934                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 935         }
 936 }
 937
 938 static const struct mmc_host_ops dw_mci_ops = {
 939         .request                = dw_mci_request,
 940         .pre_req                = dw_mci_pre_req,
 941         .post_req               = dw_mci_post_req,
 942         .set_ios                = dw_mci_set_ios,
 943         .get_ro                 = dw_mci_get_ro,
 944         .get_cd                 = dw_mci_get_cd,
 945         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 946 };
 947
 948 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 949         __releases(&host->lock)
 950         __acquires(&host->lock)
 951 {
 952         struct dw_mci_slot *slot;
 953         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 954
 955         WARN_ON(host->cmd || host->data);
 956
 957         host->cur_slot->mrq = NULL;
 958         host->mrq = NULL;
 959         if (!list_empty(&host->queue)) {
 960                 slot = list_entry(host->queue.next,
 961                                   struct dw_mci_slot, queue_node);
 962                 list_del(&slot->queue_node);
 963                 dev_vdbg(host->dev, "list not empty: %s is next\n",
 964                          mmc_hostname(slot->mmc));
 965                 host->state = STATE_SENDING_CMD;
 966                 dw_mci_start_request(host, slot);
 967         } else {
 968                 dev_vdbg(host->dev, "list empty\n");
 969                 host->state = STATE_IDLE;
 970         }
 971
 972         spin_unlock(&host->lock);
 973         mmc_request_done(prev_mmc, mrq);
 974         spin_lock(&host->lock);
 975 }
 976
 977 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 978 {
 979         u32 status = host->cmd_status;
 980
 981         host->cmd_status = 0;
 982
 983         /* Read the response from the card (up to 16 bytes) */
 984         if (cmd->flags & MMC_RSP_PRESENT) {
 985                 if (cmd->flags & MMC_RSP_136) {
 986                         cmd->resp[3] = mci_readl(host, RESP0);
 987                         cmd->resp[2] = mci_readl(host, RESP1);
 988                         cmd->resp[1] = mci_readl(host, RESP2);
 989                         cmd->resp[0] = mci_readl(host, RESP3);
 990                 } else {
 991                         cmd->resp[0] = mci_readl(host, RESP0);
 992                         cmd->resp[1] = 0;
 993                         cmd->resp[2] = 0;
 994                         cmd->resp[3] = 0;
 995                 }
 996         }
 997
 998         if (status & SDMMC_INT_RTO)
 999                 cmd->error = -ETIMEDOUT;
1000         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1001                 cmd->error = -EILSEQ;
1002         else if (status & SDMMC_INT_RESP_ERR)
1003                 cmd->error = -EIO;
1004         else
1005                 cmd->error = 0;
1006
1007         if (cmd->error) {
1008                 /* newer ip versions need a delay between retries */
1009                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1010                         mdelay(20);
1011
1012                 if (cmd->data) {
1013                         dw_mci_stop_dma(host);
1014                         host->data = NULL;
1015                 }
1016         }
1017 }
1018
1019 static void dw_mci_tasklet_func(unsigned long priv)
1020 {
1021         struct dw_mci *host = (struct dw_mci *)priv;
1022         struct mmc_data *data;
1023         struct mmc_command *cmd;
1024         enum dw_mci_state state;
1025         enum dw_mci_state prev_state;
1026         u32 status, ctrl;
1027
1028         spin_lock(&host->lock);
1029
1030         state = host->state;
1031         data = host->data;
1032
1033         do {
1034                 prev_state = state;
1035
1036                 switch (state) {
1037                 case STATE_IDLE:
1038                         break;
1039
1040                 case STATE_SENDING_CMD:
1041                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1042                                                 &host->pending_events))
1043                                 break;
1044
1045                         cmd = host->cmd;
1046                         host->cmd = NULL;
1047                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1048                         dw_mci_command_complete(host, cmd);
1049                         if (cmd == host->mrq->sbc && !cmd->error) {
1050                                 prev_state = state = STATE_SENDING_CMD;
1051                                 __dw_mci_start_request(host, host->cur_slot,
1052                                                        host->mrq->cmd);
1053                                 goto unlock;
1054                         }
1055
1056                         if (!host->mrq->data || cmd->error) {
1057                                 dw_mci_request_end(host, host->mrq);
1058                                 goto unlock;
1059                         }
1060
1061                         prev_state = state = STATE_SENDING_DATA;
1062                         /* fall through */
1063
1064                 case STATE_SENDING_DATA:
1065                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1066                                                &host->pending_events)) {
1067                                 dw_mci_stop_dma(host);
1068                                 if (data->stop)
1069                                         send_stop_cmd(host, data);
1070                                 state = STATE_DATA_ERROR;
1071                                 break;
1072                         }
1073
1074                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1075                                                 &host->pending_events))
1076                                 break;
1077
1078                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1079                         prev_state = state = STATE_DATA_BUSY;
1080                         /* fall through */
1081
1082                 case STATE_DATA_BUSY:
1083                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1084                                                 &host->pending_events))
1085                                 break;
1086
1087                         host->data = NULL;
1088                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1089                         status = host->data_status;
1090
1091                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1092                                 if (status & SDMMC_INT_DTO) {
1093                                         data->error = -ETIMEDOUT;
1094                                 } else if (status & SDMMC_INT_DCRC) {
1095                                         data->error = -EILSEQ;
1096                                 } else if (status & SDMMC_INT_EBE &&
1097                                            host->dir_status ==
1098                                                         DW_MCI_SEND_STATUS) {
1099                                         /*
1100                                          * No data CRC status was returned.
1101                                          * The number of bytes transferred will
1102                                          * be exaggerated in PIO mode.
1103                                          */
1104                                         data->bytes_xfered = 0;
1105                                         data->error = -ETIMEDOUT;
1106                                 } else {
1107                                         dev_err(host->dev,
1108                                                 "data FIFO error "
1109                                                 "(status=%08x)\n",
1110                                                 status);
1111                                         data->error = -EIO;
1112                                 }
1113                                 /*
1114                                  * After an error, there may be data lingering
1115                                  * in the FIFO, so reset it - doing so
1116                                  * generates a block interrupt, hence setting
1117                                  * the scatter-gather pointer to NULL.
1118                                  */
1119                                 sg_miter_stop(&host->sg_miter);
1120                                 host->sg = NULL;
1121                                 ctrl = mci_readl(host, CTRL);
1122                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1123                                 mci_writel(host, CTRL, ctrl);
1124                         } else {
1125                                 data->bytes_xfered = data->blocks * data->blksz;
1126                                 data->error = 0;
1127                         }
1128
1129                         if (!data->stop) {
1130                                 dw_mci_request_end(host, host->mrq);
1131                                 goto unlock;
1132                         }
1133
1134                         if (host->mrq->sbc && !data->error) {
1135                                 data->stop->error = 0;
1136                                 dw_mci_request_end(host, host->mrq);
1137                                 goto unlock;
1138                         }
1139
1140                         prev_state = state = STATE_SENDING_STOP;
1141                         if (!data->error)
1142                                 send_stop_cmd(host, data);
1143                         /* fall through */
1144
1145                 case STATE_SENDING_STOP:
1146                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1147                                                 &host->pending_events))
1148                                 break;
1149
1150                         host->cmd = NULL;
1151                         dw_mci_command_complete(host, host->mrq->stop);
1152                         dw_mci_request_end(host, host->mrq);
1153                         goto unlock;
1154
1155                 case STATE_DATA_ERROR:
1156                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1157                                                 &host->pending_events))
1158                                 break;
1159
1160                         state = STATE_DATA_BUSY;
1161                         break;
1162                 }
1163         } while (state != prev_state);
1164
1165         host->state = state;
1166 unlock:
1167         spin_unlock(&host->lock);
1168
1169 }
1170
1171 /* push final bytes to part_buf, only use during push */
1172 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1173 {
1174         memcpy((void *)&host->part_buf, buf, cnt);
1175         host->part_buf_count = cnt;
1176 }
1177
1178 /* append bytes to part_buf, only use during push */
1179 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1180 {
1181         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1182         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1183         host->part_buf_count += cnt;
1184         return cnt;
1185 }
1186
1187 /* pull first bytes from part_buf, only use during pull */
1188 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1189 {
1190         cnt = min(cnt, (int)host->part_buf_count);
1191         if (cnt) {
1192                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1193                        cnt);
1194                 host->part_buf_count -= cnt;
1195                 host->part_buf_start += cnt;
1196         }
1197         return cnt;
1198 }
1199
1200 /* pull final bytes from the part_buf, assuming it's just been filled */
1201 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1202 {
1203         memcpy(buf, &host->part_buf, cnt);
1204         host->part_buf_start = cnt;
1205         host->part_buf_count = (1 << host->data_shift) - cnt;
1206 }
1207
1208 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1209 {
1210         struct mmc_data *data = host->data;
1211         int init_cnt = cnt;
1212
1213         /* try and push anything in the part_buf */
1214         if (unlikely(host->part_buf_count)) {
1215                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1216                 buf += len;
1217                 cnt -= len;
1218                 if (host->part_buf_count == 2) {
1219                         mci_writew(host, DATA(host->data_offset),
1220                                         host->part_buf16);
1221                         host->part_buf_count = 0;
1222                 }
1223         }
1224 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1225         if (unlikely((unsigned long)buf & 0x1)) {
1226                 while (cnt >= 2) {
1227                         u16 aligned_buf[64];
1228                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1229                         int items = len >> 1;
1230                         int i;
1231                         /* memcpy from input buffer into aligned buffer */
1232                         memcpy(aligned_buf, buf, len);
1233                         buf += len;
1234                         cnt -= len;
1235                         /* push data from aligned buffer into fifo */
1236                         for (i = 0; i < items; ++i)
1237                                 mci_writew(host, DATA(host->data_offset),
1238                                                 aligned_buf[i]);
1239                 }
1240         } else
1241 #endif
1242         {
1243                 u16 *pdata = buf;
1244                 for (; cnt >= 2; cnt -= 2)
1245                         mci_writew(host, DATA(host->data_offset), *pdata++);
1246                 buf = pdata;
1247         }
1248         /* put anything remaining in the part_buf */
1249         if (cnt) {
1250                 dw_mci_set_part_bytes(host, buf, cnt);
1251                  /* Push data if we have reached the expected data length */
1252                 if ((data->bytes_xfered + init_cnt) ==
1253                     (data->blksz * data->blocks))
1254                         mci_writew(host, DATA(host->data_offset),
1255                                    host->part_buf16);
1256         }
1257 }
1258
1259 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1260 {
1261 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1262         if (unlikely((unsigned long)buf & 0x1)) {
1263                 while (cnt >= 2) {
1264                         /* pull data from fifo into aligned buffer */
1265                         u16 aligned_buf[64];
1266                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1267                         int items = len >> 1;
1268                         int i;
1269                         for (i = 0; i < items; ++i)
1270                                 aligned_buf[i] = mci_readw(host,
1271                                                 DATA(host->data_offset));
1272                         /* memcpy from aligned buffer into output buffer */
1273                         memcpy(buf, aligned_buf, len);
1274                         buf += len;
1275                         cnt -= len;
1276                 }
1277         } else
1278 #endif
1279         {
1280                 u16 *pdata = buf;
1281                 for (; cnt >= 2; cnt -= 2)
1282                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1283                 buf = pdata;
1284         }
1285         if (cnt) {
1286                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1287                 dw_mci_pull_final_bytes(host, buf, cnt);
1288         }
1289 }
1290
1291 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1292 {
1293         struct mmc_data *data = host->data;
1294         int init_cnt = cnt;
1295
1296         /* try and push anything in the part_buf */
1297         if (unlikely(host->part_buf_count)) {
1298                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1299                 buf += len;
1300                 cnt -= len;
1301                 if (host->part_buf_count == 4) {
1302                         mci_writel(host, DATA(host->data_offset),
1303                                         host->part_buf32);
1304                         host->part_buf_count = 0;
1305                 }
1306         }
1307 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1308         if (unlikely((unsigned long)buf & 0x3)) {
1309                 while (cnt >= 4) {
1310                         u32 aligned_buf[32];
1311                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1312                         int items = len >> 2;
1313                         int i;
1314                         /* memcpy from input buffer into aligned buffer */
1315                         memcpy(aligned_buf, buf, len);
1316                         buf += len;
1317                         cnt -= len;
1318                         /* push data from aligned buffer into fifo */
1319                         for (i = 0; i < items; ++i)
1320                                 mci_writel(host, DATA(host->data_offset),
1321                                                 aligned_buf[i]);
1322                 }
1323         } else
1324 #endif
1325         {
1326                 u32 *pdata = buf;
1327                 for (; cnt >= 4; cnt -= 4)
1328                         mci_writel(host, DATA(host->data_offset), *pdata++);
1329                 buf = pdata;
1330         }
1331         /* put anything remaining in the part_buf */
1332         if (cnt) {
1333                 dw_mci_set_part_bytes(host, buf, cnt);
1334                  /* Push data if we have reached the expected data length */
1335                 if ((data->bytes_xfered + init_cnt) ==
1336                     (data->blksz * data->blocks))
1337                         mci_writel(host, DATA(host->data_offset),
1338                                    host->part_buf32);
1339         }
1340 }
1341
1342 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1343 {
1344 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1345         if (unlikely((unsigned long)buf & 0x3)) {
1346                 while (cnt >= 4) {
1347                         /* pull data from fifo into aligned buffer */
1348                         u32 aligned_buf[32];
1349                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1350                         int items = len >> 2;
1351                         int i;
1352                         for (i = 0; i < items; ++i)
1353                                 aligned_buf[i] = mci_readl(host,
1354                                                 DATA(host->data_offset));
1355                         /* memcpy from aligned buffer into output buffer */
1356                         memcpy(buf, aligned_buf, len);
1357                         buf += len;
1358                         cnt -= len;
1359                 }
1360         } else
1361 #endif
1362         {
1363                 u32 *pdata = buf;
1364                 for (; cnt >= 4; cnt -= 4)
1365                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1366                 buf = pdata;
1367         }
1368         if (cnt) {
1369                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1370                 dw_mci_pull_final_bytes(host, buf, cnt);
1371         }
1372 }
1373
1374 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1375 {
1376         struct mmc_data *data = host->data;
1377         int init_cnt = cnt;
1378
1379         /* try and push anything in the part_buf */
1380         if (unlikely(host->part_buf_count)) {
1381                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1382                 buf += len;
1383                 cnt -= len;
1384
1385                 if (host->part_buf_count == 8) {
1386                         mci_writeq(host, DATA(host->data_offset),
1387                                         host->part_buf);
1388                         host->part_buf_count = 0;
1389                 }
1390         }
1391 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1392         if (unlikely((unsigned long)buf & 0x7)) {
1393                 while (cnt >= 8) {
1394                         u64 aligned_buf[16];
1395                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1396                         int items = len >> 3;
1397                         int i;
1398                         /* memcpy from input buffer into aligned buffer */
1399                         memcpy(aligned_buf, buf, len);
1400                         buf += len;
1401                         cnt -= len;
1402                         /* push data from aligned buffer into fifo */
1403                         for (i = 0; i < items; ++i)
1404                                 mci_writeq(host, DATA(host->data_offset),
1405                                                 aligned_buf[i]);
1406                 }
1407         } else
1408 #endif
1409         {
1410                 u64 *pdata = buf;
1411                 for (; cnt >= 8; cnt -= 8)
1412                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1413                 buf = pdata;
1414         }
1415         /* put anything remaining in the part_buf */
1416         if (cnt) {
1417                 dw_mci_set_part_bytes(host, buf, cnt);
1418                 /* Push data if we have reached the expected data length */
1419                 if ((data->bytes_xfered + init_cnt) ==
1420                     (data->blksz * data->blocks))
1421                         mci_writeq(host, DATA(host->data_offset),
1422                                    host->part_buf);
1423         }
1424 }
1425
1426 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1427 {
1428 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1429         if (unlikely((unsigned long)buf & 0x7)) {
1430                 while (cnt >= 8) {
1431                         /* pull data from fifo into aligned buffer */
1432                         u64 aligned_buf[16];
1433                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1434                         int items = len >> 3;
1435                         int i;
1436                         for (i = 0; i < items; ++i)
1437                                 aligned_buf[i] = mci_readq(host,
1438                                                 DATA(host->data_offset));
1439                         /* memcpy from aligned buffer into output buffer */
1440                         memcpy(buf, aligned_buf, len);
1441                         buf += len;
1442                         cnt -= len;
1443                 }
1444         } else
1445 #endif
1446         {
1447                 u64 *pdata = buf;
1448                 for (; cnt >= 8; cnt -= 8)
1449                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1450                 buf = pdata;
1451         }
1452         if (cnt) {
1453                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1454                 dw_mci_pull_final_bytes(host, buf, cnt);
1455         }
1456 }
1457
1458 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1459 {
1460         int len;
1461
1462         /* get remaining partial bytes */
1463         len = dw_mci_pull_part_bytes(host, buf, cnt);
1464         if (unlikely(len == cnt))
1465                 return;
1466         buf += len;
1467         cnt -= len;
1468
1469         /* get the rest of the data */
1470         host->pull_data(host, buf, cnt);
1471 }
1472
1473 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1474 {
1475         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1476         void *buf;
1477         unsigned int offset;
1478         struct mmc_data *data = host->data;
1479         int shift = host->data_shift;
1480         u32 status;
1481         unsigned int len;
1482         unsigned int remain, fcnt;
1483
1484         do {
1485                 if (!sg_miter_next(sg_miter))
1486                         goto done;
1487
1488                 host->sg = sg_miter->piter.sg;
1489                 buf = sg_miter->addr;
1490                 remain = sg_miter->length;
1491                 offset = 0;
1492
1493                 do {
1494                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1495                                         << shift) + host->part_buf_count;
1496                         len = min(remain, fcnt);
1497                         if (!len)
1498                                 break;
1499                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1500                         data->bytes_xfered += len;
1501                         offset += len;
1502                         remain -= len;
1503                 } while (remain);
1504
1505                 sg_miter->consumed = offset;
1506                 status = mci_readl(host, MINTSTS);
1507                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1508         /* if the RXDR is ready read again */
1509         } while ((status & SDMMC_INT_RXDR) ||
1510                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1511
1512         if (!remain) {
1513                 if (!sg_miter_next(sg_miter))
1514                         goto done;
1515                 sg_miter->consumed = 0;
1516         }
1517         sg_miter_stop(sg_miter);
1518         return;
1519
1520 done:
1521         sg_miter_stop(sg_miter);
1522         host->sg = NULL;
1523         smp_wmb();
1524         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1525 }
1526
1527 static void dw_mci_write_data_pio(struct dw_mci *host)
1528 {
1529         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1530         void *buf;
1531         unsigned int offset;
1532         struct mmc_data *data = host->data;
1533         int shift = host->data_shift;
1534         u32 status;
1535         unsigned int len;
1536         unsigned int fifo_depth = host->fifo_depth;
1537         unsigned int remain, fcnt;
1538
1539         do {
1540                 if (!sg_miter_next(sg_miter))
1541                         goto done;
1542
1543                 host->sg = sg_miter->piter.sg;
1544                 buf = sg_miter->addr;
1545                 remain = sg_miter->length;
1546                 offset = 0;
1547
1548                 do {
1549                         fcnt = ((fifo_depth -
1550                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1551                                         << shift) - host->part_buf_count;
1552                         len = min(remain, fcnt);
1553                         if (!len)
1554                                 break;
1555                         host->push_data(host, (void *)(buf + offset), len);
1556                         data->bytes_xfered += len;
1557                         offset += len;
1558                         remain -= len;
1559                 } while (remain);
1560
1561                 sg_miter->consumed = offset;
1562                 status = mci_readl(host, MINTSTS);
1563                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1564         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1565
1566         if (!remain) {
1567                 if (!sg_miter_next(sg_miter))
1568                         goto done;
1569                 sg_miter->consumed = 0;
1570         }
1571         sg_miter_stop(sg_miter);
1572         return;
1573
1574 done:
1575         sg_miter_stop(sg_miter);
1576         host->sg = NULL;
1577         smp_wmb();
1578         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1579 }
1580
1581 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1582 {
1583         if (!host->cmd_status)
1584                 host->cmd_status = status;
1585
1586         smp_wmb();
1587
1588         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1589         tasklet_schedule(&host->tasklet);
1590 }
1591
1592 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1593 {
1594         struct dw_mci *host = dev_id;
1595         u32 pending;
1596         int i;
1597
1598         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1599
1600         if (pending) {
1601
1602                 /*
1603                  * DTO fix - version 2.10a and below, and only if internal DMA
1604                  * is configured.
1605                  */
1606                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1607                         if (!pending &&
1608                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1609                                 pending |= SDMMC_INT_DATA_OVER;
1610                 }
1611
1612                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1613                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1614                         host->cmd_status = pending;
1615                         smp_wmb();
1616                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1617                 }
1618
1619                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1620                         /* if there is an error report DATA_ERROR */
1621                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1622                         host->data_status = pending;
1623                         smp_wmb();
1624                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1625                         tasklet_schedule(&host->tasklet);
1626                 }
1627
1628                 if (pending & SDMMC_INT_DATA_OVER) {
1629                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1630                         if (!host->data_status)
1631                                 host->data_status = pending;
1632                         smp_wmb();
1633                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1634                                 if (host->sg != NULL)
1635                                         dw_mci_read_data_pio(host, true);
1636                         }
1637                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1638                         tasklet_schedule(&host->tasklet);
1639                 }
1640
1641                 if (pending & SDMMC_INT_RXDR) {
1642                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1643                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1644                                 dw_mci_read_data_pio(host, false);
1645                 }
1646
1647                 if (pending & SDMMC_INT_TXDR) {
1648                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1649                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1650                                 dw_mci_write_data_pio(host);
1651                 }
1652
1653                 if (pending & SDMMC_INT_CMD_DONE) {
1654                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1655                         dw_mci_cmd_interrupt(host, pending);
1656                 }
1657
1658                 if (pending & SDMMC_INT_CD) {
1659                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1660                         queue_work(host->card_workqueue, &host->card_work);
1661                 }
1662
1663                 /* Handle SDIO Interrupts */
1664                 for (i = 0; i < host->num_slots; i++) {
1665                         struct dw_mci_slot *slot = host->slot[i];
1666                         if (pending & SDMMC_INT_SDIO(i)) {
1667                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1668                                 mmc_signal_sdio_irq(slot->mmc);
1669                         }
1670                 }
1671
1672         }
1673
1674 #ifdef CONFIG_MMC_DW_IDMAC
1675         /* Handle DMA interrupts */
1676         pending = mci_readl(host, IDSTS);
1677         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1678                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1679                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1680                 host->dma_ops->complete(host);
1681         }
1682 #endif
1683
1684         return IRQ_HANDLED;
1685 }
1686
1687 static void dw_mci_work_routine_card(struct work_struct *work)
1688 {
1689         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1690         int i;
1691
1692         for (i = 0; i < host->num_slots; i++) {
1693                 struct dw_mci_slot *slot = host->slot[i];
1694                 struct mmc_host *mmc = slot->mmc;
1695                 struct mmc_request *mrq;
1696                 int present;
1697                 u32 ctrl;
1698
1699                 present = dw_mci_get_cd(mmc);
1700                 while (present != slot->last_detect_state) {
1701                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1702                                 present ? "inserted" : "removed");
1703
1704                         spin_lock_bh(&host->lock);
1705
1706                         /* Card change detected */
1707                         slot->last_detect_state = present;
1708
1709                         /* Mark card as present if applicable */
1710                         if (present != 0)
1711                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1712
1713                         /* Clean up queue if present */
1714                         mrq = slot->mrq;
1715                         if (mrq) {
1716                                 if (mrq == host->mrq) {
1717                                         host->data = NULL;
1718                                         host->cmd = NULL;
1719
1720                                         switch (host->state) {
1721                                         case STATE_IDLE:
1722                                                 break;
1723                                         case STATE_SENDING_CMD:
1724                                                 mrq->cmd->error = -ENOMEDIUM;
1725                                                 if (!mrq->data)
1726                                                         break;
1727                                                 /* fall through */
1728                                         case STATE_SENDING_DATA:
1729                                                 mrq->data->error = -ENOMEDIUM;
1730                                                 dw_mci_stop_dma(host);
1731                                                 break;
1732                                         case STATE_DATA_BUSY:
1733                                         case STATE_DATA_ERROR:
1734                                                 if (mrq->data->error == -EINPROGRESS)
1735                                                         mrq->data->error = -ENOMEDIUM;
1736                                                 if (!mrq->stop)
1737                                                         break;
1738                                                 /* fall through */
1739                                         case STATE_SENDING_STOP:
1740                                                 mrq->stop->error = -ENOMEDIUM;
1741                                                 break;
1742                                         }
1743
1744                                         dw_mci_request_end(host, mrq);
1745                                 } else {
1746                                         list_del(&slot->queue_node);
1747                                         mrq->cmd->error = -ENOMEDIUM;
1748                                         if (mrq->data)
1749                                                 mrq->data->error = -ENOMEDIUM;
1750                                         if (mrq->stop)
1751                                                 mrq->stop->error = -ENOMEDIUM;
1752
1753                                         spin_unlock(&host->lock);
1754                                         mmc_request_done(slot->mmc, mrq);
1755                                         spin_lock(&host->lock);
1756                                 }
1757                         }
1758
1759                         /* Power down slot */
1760                         if (present == 0) {
1761                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1762
1763                                 /*
1764                                  * Clear down the FIFO - doing so generates a
1765                                  * block interrupt, hence setting the
1766                                  * scatter-gather pointer to NULL.
1767                                  */
1768                                 sg_miter_stop(&host->sg_miter);
1769                                 host->sg = NULL;
1770
1771                                 ctrl = mci_readl(host, CTRL);
1772                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1773                                 mci_writel(host, CTRL, ctrl);
1774
1775 #ifdef CONFIG_MMC_DW_IDMAC
1776                                 ctrl = mci_readl(host, BMOD);
1777                                 /* Software reset of DMA */
1778                                 ctrl |= SDMMC_IDMAC_SWRESET;
1779                                 mci_writel(host, BMOD, ctrl);
1780 #endif
1781
1782                         }
1783
1784                         spin_unlock_bh(&host->lock);
1785
1786                         present = dw_mci_get_cd(mmc);
1787                 }
1788
1789                 mmc_detect_change(slot->mmc,
1790                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1791         }
1792 }
1793
1794 #ifdef CONFIG_OF
1795 /* given a slot id, find out the device node representing that slot */
1796 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1797 {
1798         struct device_node *np;
1799         const __be32 *addr;
1800         int len;
1801
1802         if (!dev || !dev->of_node)
1803                 return NULL;
1804
1805         for_each_child_of_node(dev->of_node, np) {
1806                 addr = of_get_property(np, "reg", &len);
1807                 if (!addr || (len < sizeof(int)))
1808                         continue;
1809                 if (be32_to_cpup(addr) == slot)
1810                         return np;
1811         }
1812         return NULL;
1813 }
1814
1815 static struct dw_mci_of_slot_quirks {
1816         char *quirk;
1817         int id;
1818 } of_slot_quirks[] = {
1819         {
1820                 .quirk  = "disable-wp",
1821                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
1822         },
1823 };
1824
1825 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1826 {
1827         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1828         int quirks = 0;
1829         int idx;
1830
1831         /* get quirks */
1832         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
1833                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
1834                         quirks |= of_slot_quirks[idx].id;
1835
1836         return quirks;
1837 }
1838
1839 /* find out bus-width for a given slot */
1840 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1841 {
1842         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1843         u32 bus_wd = 1;
1844
1845         if (!np)
1846                 return 1;
1847
1848         if (of_property_read_u32(np, "bus-width", &bus_wd))
1849                 dev_err(dev, "bus-width property not found, assuming width"
1850                                " as 1\n");
1851         return bus_wd;
1852 }
1853
1854
1855 /* find the pwr-en gpio for a given slot; or -1 if none specified */
1856 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
1857 {
1858         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
1859         int gpio;
1860
1861         if (!np)
1862                 return -EINVAL;
1863
1864         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
1865
1866         /* Having a missing entry is valid; return silently */
1867         if (!gpio_is_valid(gpio))
1868                 return -EINVAL;
1869
1870         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
1871                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
1872                 return -EINVAL;
1873         }
1874
1875     gpio_direction_output(gpio, 0);//set 0 to pwr-en
1876
1877         return gpio;
1878 }
1879
1880
1881 /* find the write protect gpio for a given slot; or -1 if none specified */
1882 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1883 {
1884         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1885         int gpio;
1886
1887         if (!np)
1888                 return -EINVAL;
1889
1890         gpio = of_get_named_gpio(np, "wp-gpios", 0);
1891
1892         /* Having a missing entry is valid; return silently */
1893         if (!gpio_is_valid(gpio))
1894                 return -EINVAL;
1895
1896         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
1897                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
1898                 return -EINVAL;
1899         }
1900
1901         return gpio;
1902 }
1903 #else /* CONFIG_OF */
1904 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1905 {
1906         return 0;
1907 }
1908 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1909 {
1910         return 1;
1911 }
1912 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1913 {
1914         return NULL;
1915 }
1916 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1917 {
1918         return -EINVAL;
1919 }
1920 #endif /* CONFIG_OF */
1921
1922 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1923 {
1924         struct mmc_host *mmc;
1925         struct dw_mci_slot *slot;
1926         const struct dw_mci_drv_data *drv_data = host->drv_data;
1927         int ctrl_id, ret;
1928         u8 bus_width;
1929
1930         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
1931         if (!mmc)
1932                 return -ENOMEM;
1933
1934         slot = mmc_priv(mmc);
1935         slot->id = id;
1936         slot->mmc = mmc;
1937         slot->host = host;
1938         host->slot[id] = slot;
1939
1940         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
1941
1942         mmc->ops = &dw_mci_ops;
1943         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1944         mmc->f_max = host->bus_hz;
1945
1946         if (host->pdata->get_ocr)
1947                 mmc->ocr_avail = host->pdata->get_ocr(id);
1948         else
1949                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1950
1951         /*
1952          * Start with slot power disabled, it will be enabled when a card
1953          * is detected.
1954          */
1955         if (host->pdata->setpower)
1956                 host->pdata->setpower(id, 0);
1957
1958         if (host->pdata->caps)
1959                 mmc->caps = host->pdata->caps;
1960
1961         if (host->pdata->pm_caps)
1962                 mmc->pm_caps = host->pdata->pm_caps;
1963
1964         if (host->dev->of_node) {
1965                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1966                 if (ctrl_id < 0)
1967                         ctrl_id = 0;
1968         } else {
1969                 ctrl_id = to_platform_device(host->dev)->id;
1970         }
1971         if (drv_data && drv_data->caps)
1972                 mmc->caps |= drv_data->caps[ctrl_id];
1973
1974         if (host->pdata->caps2)
1975                 mmc->caps2 = host->pdata->caps2;
1976
1977         if (host->pdata->get_bus_wd)
1978                 bus_width = host->pdata->get_bus_wd(slot->id);
1979         else if (host->dev->of_node)
1980                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1981         else
1982                 bus_width = 1;
1983
1984         switch (bus_width) {
1985         case 8:
1986                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1987         case 4:
1988                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1989         }
1990
1991         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1992                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1993
1994         if (host->pdata->blk_settings) {
1995                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1996                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1997                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1998                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1999                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2000         } else {
2001                 /* Useful defaults if platform data is unset. */
2002 #ifdef CONFIG_MMC_DW_IDMAC
2003                 mmc->max_segs = host->ring_size;
2004                 mmc->max_blk_size = 65536;
2005                 mmc->max_blk_count = host->ring_size;
2006                 mmc->max_seg_size = 0x1000;
2007                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
2008 #else
2009                 mmc->max_segs = 64;
2010                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2011                 mmc->max_blk_count = 512;
2012                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2013                 mmc->max_seg_size = mmc->max_req_size;
2014 #endif /* CONFIG_MMC_DW_IDMAC */
2015         }
2016     //pwr_en
2017     slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
2018
2019 if (gpio_is_valid(slot->pwr_en_gpio))
2020 {
2021     host->vmmc = NULL;
2022 }else{
2023
2024         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
2025         if (IS_ERR(host->vmmc)) {
2026                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2027                 host->vmmc = NULL;
2028         } else {
2029                 ret = regulator_enable(host->vmmc);
2030                 if (ret) {
2031                         dev_err(host->dev,
2032                                 "failed to enable regulator: %d\n", ret);
2033                         goto err_setup_bus;
2034                 }
2035         }
2036 }
2037         if (dw_mci_get_cd(mmc))
2038                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2039         else
2040                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2041
2042         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
2043
2044         ret = mmc_add_host(mmc);
2045         if (ret)
2046                 goto err_setup_bus;
2047
2048 #if defined(CONFIG_DEBUG_FS)
2049         dw_mci_init_debugfs(slot);
2050 #endif
2051
2052         /* Card initially undetected */
2053         slot->last_detect_state = 0;
2054
2055         /*
2056          * Card may have been plugged in prior to boot so we
2057          * need to run the detect tasklet
2058          */
2059         queue_work(host->card_workqueue, &host->card_work);
2060
2061         return 0;
2062
2063 err_setup_bus:
2064         mmc_free_host(mmc);
2065         return -EINVAL;
2066 }
2067
2068 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2069 {
2070         /* Shutdown detect IRQ */
2071         if (slot->host->pdata->exit)
2072                 slot->host->pdata->exit(id);
2073
2074         /* Debugfs stuff is cleaned up by mmc core */
2075         mmc_remove_host(slot->mmc);
2076         slot->host->slot[id] = NULL;
2077         mmc_free_host(slot->mmc);
2078 }
2079
2080 static void dw_mci_init_dma(struct dw_mci *host)
2081 {
2082         /* Alloc memory for sg translation */
2083         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2084                                           &host->sg_dma, GFP_KERNEL);
2085         if (!host->sg_cpu) {
2086                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2087                         __func__);
2088                 goto no_dma;
2089         }
2090
2091         /* Determine which DMA interface to use */
2092 #ifdef CONFIG_MMC_DW_IDMAC
2093         host->dma_ops = &dw_mci_idmac_ops;
2094         dev_info(host->dev, "Using internal DMA controller.\n");
2095 #endif
2096
2097         if (!host->dma_ops)
2098                 goto no_dma;
2099
2100         if (host->dma_ops->init && host->dma_ops->start &&
2101             host->dma_ops->stop && host->dma_ops->cleanup) {
2102                 if (host->dma_ops->init(host)) {
2103                         dev_err(host->dev, "%s: Unable to initialize "
2104                                 "DMA Controller.\n", __func__);
2105                         goto no_dma;
2106                 }
2107         } else {
2108                 dev_err(host->dev, "DMA initialization not found.\n");
2109                 goto no_dma;
2110         }
2111
2112         host->use_dma = 1;
2113         return;
2114
2115 no_dma:
2116         dev_info(host->dev, "Using PIO mode.\n");
2117         host->use_dma = 0;
2118         return;
2119 }
2120
2121 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2122 {
2123         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2124         unsigned int ctrl;
2125
2126         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2127                                 SDMMC_CTRL_DMA_RESET));
2128
2129         /* wait till resets clear */
2130         do {
2131                 ctrl = mci_readl(host, CTRL);
2132                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2133                               SDMMC_CTRL_DMA_RESET)))
2134                         return true;
2135         } while (time_before(jiffies, timeout));
2136
2137         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2138
2139         return false;
2140 }
2141
2142 #ifdef CONFIG_OF
2143 static struct dw_mci_of_quirks {
2144         char *quirk;
2145         int id;
2146 } of_quirks[] = {
2147         {
2148                 .quirk  = "supports-highspeed",
2149                 .id     = DW_MCI_QUIRK_HIGHSPEED,
2150         }, {
2151                 .quirk  = "broken-cd",
2152                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2153         },
2154 };
2155
2156 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2157 {
2158         struct dw_mci_board *pdata;
2159         struct device *dev = host->dev;
2160         struct device_node *np = dev->of_node;
2161         const struct dw_mci_drv_data *drv_data = host->drv_data;
2162         int idx, ret;
2163
2164         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2165         if (!pdata) {
2166                 dev_err(dev, "could not allocate memory for pdata\n");
2167                 return ERR_PTR(-ENOMEM);
2168         }
2169
2170         /* find out number of slots supported */
2171         if (of_property_read_u32(dev->of_node, "num-slots",
2172                                 &pdata->num_slots)) {
2173                 dev_info(dev, "num-slots property not found, "
2174                                 "assuming 1 slot is available\n");
2175                 pdata->num_slots = 1;
2176         }
2177
2178         /* get quirks */
2179         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2180                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2181                         pdata->quirks |= of_quirks[idx].id;
2182
2183         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2184                 dev_info(dev, "fifo-depth property not found, using "
2185                                 "value of FIFOTH register as default\n");
2186
2187         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2188
2189         if (drv_data && drv_data->parse_dt) {
2190                 ret = drv_data->parse_dt(host);
2191                 if (ret)
2192                         return ERR_PTR(ret);
2193         }
2194
2195         if (of_find_property(np, "keep-power-in-suspend", NULL))
2196                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2197
2198         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2199                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2200
2201         return pdata;
2202 }
2203
2204 #else /* CONFIG_OF */
2205 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2206 {
2207         return ERR_PTR(-EINVAL);
2208 }
2209 #endif /* CONFIG_OF */
2210
2211 int dw_mci_probe(struct dw_mci *host)
2212 {
2213         const struct dw_mci_drv_data *drv_data = host->drv_data;
2214         int width, i, ret = 0;
2215         u32 fifo_size;
2216         int init_slots = 0;
2217
2218         if (!host->pdata) {
2219                 host->pdata = dw_mci_parse_dt(host);
2220                 if (IS_ERR(host->pdata)) {
2221                         dev_err(host->dev, "platform data not available\n");
2222                         return -EINVAL;
2223                 }
2224         }
2225
2226         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
2227                 dev_err(host->dev,
2228                         "Platform data must supply select_slot function\n");
2229                 return -ENODEV;
2230         }
2231
2232         host->biu_clk = devm_clk_get(host->dev, "biu");
2233         if (IS_ERR(host->biu_clk)) {
2234                 dev_dbg(host->dev, "biu clock not available\n");
2235         } else {
2236                 ret = clk_prepare_enable(host->biu_clk);
2237                 if (ret) {
2238                         dev_err(host->dev, "failed to enable biu clock\n");
2239                         return ret;
2240                 }
2241         }
2242
2243         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2244         if (IS_ERR(host->ciu_clk)) {
2245                 dev_dbg(host->dev, "ciu clock not available\n");
2246         } else {
2247                 ret = clk_prepare_enable(host->ciu_clk);
2248                 if (ret) {
2249                         dev_err(host->dev, "failed to enable ciu clock\n");
2250                         goto err_clk_biu;
2251                 }
2252         }
2253
2254 #if 1
2255     //test, modify by xbw
2256     host->bus_hz = 50000000;
2257 #else
2258         if (IS_ERR(host->ciu_clk))
2259                 host->bus_hz = host->pdata->bus_hz;
2260         else
2261                 host->bus_hz = clk_get_rate(host->ciu_clk);
2262 #endif
2263         if (drv_data && drv_data->setup_clock) {
2264                 ret = drv_data->setup_clock(host);
2265                 if (ret) {
2266                         dev_err(host->dev,
2267                                 "implementation specific clock setup failed\n");
2268                         goto err_clk_ciu;
2269                 }
2270         }
2271
2272         if (!host->bus_hz) {
2273                 dev_err(host->dev,
2274                         "Platform data must supply bus speed\n");
2275                 ret = -ENODEV;
2276                 goto err_clk_ciu;
2277         }
2278
2279         host->quirks = host->pdata->quirks;
2280
2281         spin_lock_init(&host->lock);
2282         INIT_LIST_HEAD(&host->queue);
2283
2284         /*
2285          * Get the host data width - this assumes that HCON has been set with
2286          * the correct values.
2287          */
2288         i = (mci_readl(host, HCON) >> 7) & 0x7;
2289         if (!i) {
2290                 host->push_data = dw_mci_push_data16;
2291                 host->pull_data = dw_mci_pull_data16;
2292                 width = 16;
2293                 host->data_shift = 1;
2294         } else if (i == 2) {
2295                 host->push_data = dw_mci_push_data64;
2296                 host->pull_data = dw_mci_pull_data64;
2297                 width = 64;
2298                 host->data_shift = 3;
2299         } else {
2300                 /* Check for a reserved value, and warn if it is */
2301                 WARN((i != 1),
2302                      "HCON reports a reserved host data width!\n"
2303                      "Defaulting to 32-bit access.\n");
2304                 host->push_data = dw_mci_push_data32;
2305                 host->pull_data = dw_mci_pull_data32;
2306                 width = 32;
2307                 host->data_shift = 2;
2308         }
2309
2310         /* Reset all blocks */
2311         if (!mci_wait_reset(host->dev, host))
2312                 return -ENODEV;
2313
2314         host->dma_ops = host->pdata->dma_ops;
2315         dw_mci_init_dma(host);
2316
2317         /* Clear the interrupts for the host controller */
2318         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2319         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2320
2321         /* Put in max timeout */
2322         mci_writel(host, TMOUT, 0xFFFFFFFF);
2323
2324         /*
2325          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2326          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2327          */
2328         if (!host->pdata->fifo_depth) {
2329                 /*
2330                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2331                  * have been overwritten by the bootloader, just like we're
2332                  * about to do, so if you know the value for your hardware, you
2333                  * should put it in the platform data.
2334                  */
2335                 fifo_size = mci_readl(host, FIFOTH);
2336                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2337         } else {
2338                 fifo_size = host->pdata->fifo_depth;
2339         }
2340         host->fifo_depth = fifo_size;
2341         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2342                         ((fifo_size/2) << 0));
2343         mci_writel(host, FIFOTH, host->fifoth_val);
2344
2345         /* disable clock to CIU */
2346         mci_writel(host, CLKENA, 0);
2347         mci_writel(host, CLKSRC, 0);
2348
2349         /*
2350          * In 2.40a spec, Data offset is changed.
2351          * Need to check the version-id and set data-offset for DATA register.
2352          */
2353         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2354         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2355
2356         if (host->verid < DW_MMC_240A)
2357                 host->data_offset = DATA_OFFSET;
2358         else
2359                 host->data_offset = DATA_240A_OFFSET;
2360
2361         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2362         host->card_workqueue = alloc_workqueue("dw-mci-card",
2363                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2364         if (!host->card_workqueue)
2365                 goto err_dmaunmap;
2366         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2367         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2368                                host->irq_flags, "dw-mci", host);
2369         if (ret)
2370                 goto err_workqueue;
2371
2372         if (host->pdata->num_slots)
2373                 host->num_slots = host->pdata->num_slots;
2374         else
2375                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2376
2377         /*
2378          * Enable interrupts for command done, data over, data empty, card det,
2379          * receive ready and error such as transmit, receive timeout, crc error
2380          */
2381         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2382         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2383                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2384                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2385         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2386
2387         dev_info(host->dev, "DW MMC controller at irq %d, "
2388                  "%d bit host data width, "
2389                  "%u deep fifo\n",
2390                  host->irq, width, fifo_size);
2391
2392         /* We need at least one slot to succeed */
2393         for (i = 0; i < host->num_slots; i++) {
2394                 ret = dw_mci_init_slot(host, i);
2395                 if (ret)
2396                         dev_dbg(host->dev, "slot %d init failed\n", i);
2397                 else
2398                         init_slots++;
2399         }
2400
2401         if (init_slots) {
2402                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2403         } else {
2404                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2405                                         "but failed on all\n", host->num_slots);
2406                 goto err_workqueue;
2407         }
2408
2409         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2410                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2411
2412         return 0;
2413
2414 err_workqueue:
2415         destroy_workqueue(host->card_workqueue);
2416
2417 err_dmaunmap:
2418         if (host->use_dma && host->dma_ops->exit)
2419                 host->dma_ops->exit(host);
2420
2421         if (host->vmmc)
2422                 regulator_disable(host->vmmc);
2423
2424 err_clk_ciu:
2425         if (!IS_ERR(host->ciu_clk))
2426                 clk_disable_unprepare(host->ciu_clk);
2427
2428 err_clk_biu:
2429         if (!IS_ERR(host->biu_clk))
2430                 clk_disable_unprepare(host->biu_clk);
2431
2432         return ret;
2433 }
2434 EXPORT_SYMBOL(dw_mci_probe);
2435
2436 void dw_mci_remove(struct dw_mci *host)
2437 {
2438         int i;
2439
2440         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2441         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2442
2443         for (i = 0; i < host->num_slots; i++) {
2444                 dev_dbg(host->dev, "remove slot %d\n", i);
2445                 if (host->slot[i])
2446                         dw_mci_cleanup_slot(host->slot[i], i);
2447         }
2448
2449         /* disable clock to CIU */
2450         mci_writel(host, CLKENA, 0);
2451         mci_writel(host, CLKSRC, 0);
2452
2453         destroy_workqueue(host->card_workqueue);
2454
2455         if (host->use_dma && host->dma_ops->exit)
2456                 host->dma_ops->exit(host);
2457
2458         if (host->vmmc)
2459                 regulator_disable(host->vmmc);
2460
2461         if (!IS_ERR(host->ciu_clk))
2462                 clk_disable_unprepare(host->ciu_clk);
2463
2464         if (!IS_ERR(host->biu_clk))
2465                 clk_disable_unprepare(host->biu_clk);
2466 }
2467 EXPORT_SYMBOL(dw_mci_remove);
2468
2469
2470
2471 #ifdef CONFIG_PM_SLEEP
2472 /*
2473  * TODO: we should probably disable the clock to the card in the suspend path.
2474  */
2475 int dw_mci_suspend(struct dw_mci *host)
2476 {
2477         int i, ret = 0;
2478
2479         for (i = 0; i < host->num_slots; i++) {
2480                 struct dw_mci_slot *slot = host->slot[i];
2481                 if (!slot)
2482                         continue;
2483                 ret = mmc_suspend_host(slot->mmc);
2484                 if (ret < 0) {
2485                         while (--i >= 0) {
2486                                 slot = host->slot[i];
2487                                 if (slot)
2488                                         mmc_resume_host(host->slot[i]->mmc);
2489                         }
2490                         return ret;
2491                 }
2492         }
2493
2494         if (host->vmmc)
2495                 regulator_disable(host->vmmc);
2496
2497         return 0;
2498 }
2499 EXPORT_SYMBOL(dw_mci_suspend);
2500
2501 int dw_mci_resume(struct dw_mci *host)
2502 {
2503         int i, ret;
2504
2505         if (host->vmmc) {
2506                 ret = regulator_enable(host->vmmc);
2507                 if (ret) {
2508                         dev_err(host->dev,
2509                                 "failed to enable regulator: %d\n", ret);
2510                         return ret;
2511                 }
2512         }
2513
2514         if (!mci_wait_reset(host->dev, host)) {
2515                 ret = -ENODEV;
2516                 return ret;
2517         }
2518
2519         if (host->use_dma && host->dma_ops->init)
2520                 host->dma_ops->init(host);
2521
2522         /* Restore the old value at FIFOTH register */
2523         mci_writel(host, FIFOTH, host->fifoth_val);
2524
2525         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2526         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2527                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2528                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2529         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2530
2531         for (i = 0; i < host->num_slots; i++) {
2532                 struct dw_mci_slot *slot = host->slot[i];
2533                 if (!slot)
2534                         continue;
2535                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2536                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2537                         dw_mci_setup_bus(slot, true);
2538                 }
2539
2540                 ret = mmc_resume_host(host->slot[i]->mmc);
2541                 if (ret < 0)
2542                         return ret;
2543         }
2544         return 0;
2545 }
2546 EXPORT_SYMBOL(dw_mci_resume);
2547 #endif /* CONFIG_PM_SLEEP */
2548
2549 static int __init dw_mci_init(void)
2550 {
2551         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2552         return 0;
2553 }
2554
2555 static void __exit dw_mci_exit(void)
2556 {
2557 }
2558
2559 module_init(dw_mci_init);
2560 module_exit(dw_mci_exit);
2561
2562 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2563
2564 MODULE_AUTHOR("NXP Semiconductor VietNam");
2565 MODULE_AUTHOR("Imagination Technologies Ltd");
2566 MODULE_AUTHOR("Rockchip Electronics£¬Bangwang Xie < xbw@rock-chips.com> ");
2567
2568 MODULE_LICENSE("GPL v2");