drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/mmc/host.h>
  33 #include <linux/mmc/mmc.h>
  34 #include <linux/mmc/sd.h>
  35 #include <linux/mmc/sdio.h>
  36 #include <linux/mmc/rk_mmc.h>
  37 #include <linux/bitops.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/of.h>
  41 #include <linux/of_gpio.h>
  42 #include <linux/mmc/slot-gpio.h>
  43 #include <linux/clk-private.h>
  44 #include <linux/rockchip/cpu.h>
  45
  46 #include "rk_sdmmc.h"
  47 #include "rk_sdmmc_of.h"
  48 #include <linux/regulator/rockchip_io_vol_domain.h>
  49 #include "../../clk/rockchip/clk-ops.h"
  50
  51 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
  52
  53 #define RK_SDMMC_DRIVER_VERSION "Ver 1.11 2014-06-05"
  54
  55 /* Common flag combinations */
  56 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  57                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  58                                  SDMMC_INT_EBE)
  59 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  60                                  SDMMC_INT_RESP_ERR)
  61 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  62                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  63 #define DW_MCI_SEND_STATUS      1
  64 #define DW_MCI_RECV_STATUS      2
  65 #define DW_MCI_DMA_THRESHOLD    16
  66
  67 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  68 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  69
  70 #define SDMMC_DATA_TIMEOUT_SD   500; /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  71 #define SDMMC_DATA_TIMEOUT_SDIO 250
  72 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  73
  74 #define SDMMC_CMD_RTO_MAX_HOLD 200
  75 #define SDMMC_WAIT_FOR_UNBUSY   2500
  76
  77 #ifdef CONFIG_MMC_DW_IDMAC
  78 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  79                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  80                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  81                                  SDMMC_IDMAC_INT_TI)
  82
  83 struct idmac_desc {
  84         u32             des0;   /* Control Descriptor */
  85 #define IDMAC_DES0_DIC  BIT(1)
  86 #define IDMAC_DES0_LD   BIT(2)
  87 #define IDMAC_DES0_FD   BIT(3)
  88 #define IDMAC_DES0_CH   BIT(4)
  89 #define IDMAC_DES0_ER   BIT(5)
  90 #define IDMAC_DES0_CES  BIT(30)
  91 #define IDMAC_DES0_OWN  BIT(31)
  92
  93         u32             des1;   /* Buffer sizes */
  94 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  95         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  96
  97         u32             des2;   /* buffer 1 physical address */
  98
  99         u32             des3;   /* buffer 2 physical address */
 100 };
 101 #endif /* CONFIG_MMC_DW_IDMAC */
 102
 103 static const u8 tuning_blk_pattern_4bit[] = {
 104         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 105         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 106         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 107         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 108         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 109         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 110         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 111         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 112 };
 113
 114 static const u8 tuning_blk_pattern_8bit[] = {
 115         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 116         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 117         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 118         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 119         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 120         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 121         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 122         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 123         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 124         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 125         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 126         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 127         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 128         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 129         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 130         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 131 };
 132
 133 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 134 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 135 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 136 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 137
 138 /*printk the all register of current host*/
 139 #if 0
 140 static int dw_mci_regs_printk(struct dw_mci *host)
 141 {
 142     struct sdmmc_reg *regs = dw_mci_regs;
 143
 144     while( regs->name != 0 ){
 145         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 146         regs++;
 147     }
 148     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 149     return 0;
 150 }
 151 #endif
 152
 153 #if defined(CONFIG_DEBUG_FS)
 154 static int dw_mci_req_show(struct seq_file *s, void *v)
 155 {
 156         struct dw_mci_slot *slot = s->private;
 157         struct mmc_request *mrq;
 158         struct mmc_command *cmd;
 159         struct mmc_command *stop;
 160         struct mmc_data *data;
 161
 162         /* Make sure we get a consistent snapshot */
 163         spin_lock_bh(&slot->host->lock);
 164         mrq = slot->mrq;
 165
 166         if (mrq) {
 167                 cmd = mrq->cmd;
 168                 data = mrq->data;
 169                 stop = mrq->stop;
 170
 171                 if (cmd)
 172                         seq_printf(s,
 173                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 174                                    cmd->opcode, cmd->arg, cmd->flags,
 175                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 176                                    cmd->resp[2], cmd->error);
 177                 if (data)
 178                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 179                                    data->bytes_xfered, data->blocks,
 180                                    data->blksz, data->flags, data->error);
 181                 if (stop)
 182                         seq_printf(s,
 183                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 184                                    stop->opcode, stop->arg, stop->flags,
 185                                    stop->resp[0], stop->resp[1], stop->resp[2],
 186                                    stop->resp[2], stop->error);
 187         }
 188
 189         spin_unlock_bh(&slot->host->lock);
 190
 191         return 0;
 192 }
 193
 194 static int dw_mci_req_open(struct inode *inode, struct file *file)
 195 {
 196         return single_open(file, dw_mci_req_show, inode->i_private);
 197 }
 198
 199 static const struct file_operations dw_mci_req_fops = {
 200         .owner          = THIS_MODULE,
 201         .open           = dw_mci_req_open,
 202         .read           = seq_read,
 203         .llseek         = seq_lseek,
 204         .release        = single_release,
 205 };
 206
 207 static int dw_mci_regs_show(struct seq_file *s, void *v)
 208 {
 209         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 210         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 211         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 212         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 213         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 214         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 215
 216         return 0;
 217 }
 218
 219 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 220 {
 221         return single_open(file, dw_mci_regs_show, inode->i_private);
 222 }
 223
 224 static const struct file_operations dw_mci_regs_fops = {
 225         .owner          = THIS_MODULE,
 226         .open           = dw_mci_regs_open,
 227         .read           = seq_read,
 228         .llseek         = seq_lseek,
 229         .release        = single_release,
 230 };
 231
 232 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 233 {
 234         struct mmc_host *mmc = slot->mmc;
 235         struct dw_mci *host = slot->host;
 236         struct dentry *root;
 237         struct dentry *node;
 238
 239         root = mmc->debugfs_root;
 240         if (!root)
 241                 return;
 242
 243         node = debugfs_create_file("regs", S_IRUSR, root, host,
 244                                    &dw_mci_regs_fops);
 245         if (!node)
 246                 goto err;
 247
 248         node = debugfs_create_file("req", S_IRUSR, root, slot,
 249                                    &dw_mci_req_fops);
 250         if (!node)
 251                 goto err;
 252
 253         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 254         if (!node)
 255                 goto err;
 256
 257         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 258                                   (u32 *)&host->pending_events);
 259         if (!node)
 260                 goto err;
 261
 262         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 263                                   (u32 *)&host->completed_events);
 264         if (!node)
 265                 goto err;
 266
 267         return;
 268
 269 err:
 270         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 271 }
 272 #endif /* defined(CONFIG_DEBUG_FS) */
 273
 274 static void dw_mci_set_timeout(struct dw_mci *host)
 275 {
 276         /* timeout (maximum) */
 277         mci_writel(host, TMOUT, 0xffffffff);
 278 }
 279
 280 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 281 {
 282         struct mmc_data *data;
 283         struct dw_mci_slot *slot = mmc_priv(mmc);
 284         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 285         u32 cmdr;
 286         cmd->error = -EINPROGRESS;
 287
 288         cmdr = cmd->opcode;
 289
 290         if (cmdr == MMC_STOP_TRANSMISSION)
 291                 cmdr |= SDMMC_CMD_STOP;
 292         else
 293                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 294
 295         if (cmd->flags & MMC_RSP_PRESENT) {
 296                 /* We expect a response, so set this bit */
 297                 cmdr |= SDMMC_CMD_RESP_EXP;
 298                 if (cmd->flags & MMC_RSP_136)
 299                         cmdr |= SDMMC_CMD_RESP_LONG;
 300         }
 301
 302         if (cmd->flags & MMC_RSP_CRC)
 303                 cmdr |= SDMMC_CMD_RESP_CRC;
 304
 305         data = cmd->data;
 306         if (data) {
 307                 cmdr |= SDMMC_CMD_DAT_EXP;
 308                 if (data->flags & MMC_DATA_STREAM)
 309                         cmdr |= SDMMC_CMD_STRM_MODE;
 310                 if (data->flags & MMC_DATA_WRITE)
 311                         cmdr |= SDMMC_CMD_DAT_WR;
 312         }
 313
 314         if (drv_data && drv_data->prepare_command)
 315                 drv_data->prepare_command(slot->host, &cmdr);
 316
 317         return cmdr;
 318 }
 319
 320 #if 0
 321 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 322 {
 323         struct mmc_command *stop;
 324         u32 cmdr;
 325
 326         if (!cmd->data)
 327                 return 0;
 328
 329         stop = &host->stop_abort;
 330         cmdr = cmd->opcode;
 331         memset(stop, 0, sizeof(struct mmc_command));
 332
 333         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 334             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 335             cmdr == MMC_WRITE_BLOCK ||
 336             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 337                 stop->opcode = MMC_STOP_TRANSMISSION;
 338                 stop->arg = 0;
 339                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 340         } else if (cmdr == SD_IO_RW_EXTENDED) {
 341                 stop->opcode = SD_IO_RW_DIRECT;
 342                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 343                              ((cmd->arg >> 28) & 0x7);
 344                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 345         } else {
 346                 return 0;
 347         }
 348
 349         cmdr = stop->opcode | SDMMC_CMD_STOP |
 350                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 351
 352         return cmdr;
 353 }
 354 #endif
 355 static void dw_mci_start_command(struct dw_mci *host,
 356                                  struct mmc_command *cmd, u32 cmd_flags)
 357 {
 358         struct dw_mci_slot *slot = host->slot[0];
 359         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 360
 361         host->pre_cmd = host->cmd;
 362         host->cmd = cmd;
 363         dev_vdbg(host->dev,
 364                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 365                 cmd->arg, cmd_flags);
 366
 367         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 368                 /*confirm non-low-power mode*/
 369                 mci_writel(host, CMDARG, 0);
 370                 dw_mci_disable_low_power(slot);
 371
 372                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 373                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 374
 375                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 376         }
 377
 378         mci_writel(host, CMDARG, cmd->arg);
 379         wmb();
 380
 381         /* fix the value to 1 in some Soc,for example RK3188. */
 382         if(host->mmc->hold_reg_flag)
 383                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 384
 385         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 386         wmb();
 387 }
 388
 389 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 390 {
 391         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 392 }
 393
 394 /* DMA interface functions */
 395 static void dw_mci_stop_dma(struct dw_mci *host)
 396 {
 397         if (host->using_dma) {
 398                 host->dma_ops->stop(host);
 399                 host->dma_ops->cleanup(host);
 400         }
 401
 402         /* Data transfer was stopped by the interrupt handler */
 403         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 404 }
 405
 406 static int dw_mci_get_dma_dir(struct mmc_data *data)
 407 {
 408         if (data->flags & MMC_DATA_WRITE)
 409                 return DMA_TO_DEVICE;
 410         else
 411                 return DMA_FROM_DEVICE;
 412 }
 413
 414 #ifdef CONFIG_MMC_DW_IDMAC
 415 static void dw_mci_dma_cleanup(struct dw_mci *host)
 416 {
 417         struct mmc_data *data = host->data;
 418
 419         if (data)
 420                 if (!data->host_cookie)
 421                         dma_unmap_sg(host->dev,
 422                                      data->sg,
 423                                      data->sg_len,
 424                                      dw_mci_get_dma_dir(data));
 425 }
 426
 427 static void dw_mci_idmac_reset(struct dw_mci *host)
 428 {
 429         u32 bmod = mci_readl(host, BMOD);
 430         /* Software reset of DMA */
 431         bmod |= SDMMC_IDMAC_SWRESET;
 432         mci_writel(host, BMOD, bmod);
 433 }
 434
 435 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 436 {
 437         u32 temp;
 438
 439         /* Disable and reset the IDMAC interface */
 440         temp = mci_readl(host, CTRL);
 441         temp &= ~SDMMC_CTRL_USE_IDMAC;
 442         temp |= SDMMC_CTRL_DMA_RESET;
 443         mci_writel(host, CTRL, temp);
 444
 445         /* Stop the IDMAC running */
 446         temp = mci_readl(host, BMOD);
 447         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 448         temp |= SDMMC_IDMAC_SWRESET;
 449         mci_writel(host, BMOD, temp);
 450 }
 451
 452 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 453 {
 454         struct mmc_data *data = host->data;
 455
 456         dev_vdbg(host->dev, "DMA complete\n");
 457
 458     /*
 459     MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 460         host->mrq->cmd->opcode,host->mrq->cmd->arg,data->blocks,data->blksz,mmc_hostname(host->mmc));
 461     */
 462
 463         host->dma_ops->cleanup(host);
 464
 465         /*
 466          * If the card was removed, data will be NULL. No point in trying to
 467          * send the stop command or waiting for NBUSY in this case.
 468          */
 469         if (data) {
 470                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 471                 tasklet_schedule(&host->tasklet);
 472         }
 473 }
 474
 475 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 476                                     unsigned int sg_len)
 477 {
 478         int i;
 479         struct idmac_desc *desc = host->sg_cpu;
 480
 481         for (i = 0; i < sg_len; i++, desc++) {
 482                 unsigned int length = sg_dma_len(&data->sg[i]);
 483                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 484
 485                 /* Set the OWN bit and disable interrupts for this descriptor */
 486                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 487
 488                 /* Buffer length */
 489                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 490
 491                 /* Physical address to DMA to/from */
 492                 desc->des2 = mem_addr;
 493         }
 494
 495         /* Set first descriptor */
 496         desc = host->sg_cpu;
 497         desc->des0 |= IDMAC_DES0_FD;
 498
 499         /* Set last descriptor */
 500         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 501         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 502         desc->des0 |= IDMAC_DES0_LD;
 503
 504         wmb();
 505 }
 506
 507 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 508 {
 509         u32 temp;
 510
 511         dw_mci_translate_sglist(host, host->data, sg_len);
 512
 513         /* Select IDMAC interface */
 514         temp = mci_readl(host, CTRL);
 515         temp |= SDMMC_CTRL_USE_IDMAC;
 516         mci_writel(host, CTRL, temp);
 517
 518         wmb();
 519
 520         /* Enable the IDMAC */
 521         temp = mci_readl(host, BMOD);
 522         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 523         mci_writel(host, BMOD, temp);
 524
 525         /* Start it running */
 526         mci_writel(host, PLDMND, 1);
 527 }
 528
 529 static int dw_mci_idmac_init(struct dw_mci *host)
 530 {
 531         struct idmac_desc *p;
 532         int i;
 533
 534         /* Number of descriptors in the ring buffer */
 535         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 536
 537         /* Forward link the descriptor list */
 538         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 539                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 540
 541         /* Set the last descriptor as the end-of-ring descriptor */
 542         p->des3 = host->sg_dma;
 543         p->des0 = IDMAC_DES0_ER;
 544
 545         dw_mci_idmac_reset(host);
 546
 547         /* Mask out interrupts - get Tx & Rx complete only */
 548         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 549         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 550                    SDMMC_IDMAC_INT_TI);
 551
 552         /* Set the descriptor base address */
 553         mci_writel(host, DBADDR, host->sg_dma);
 554         return 0;
 555 }
 556
 557 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 558         .init = dw_mci_idmac_init,
 559         .start = dw_mci_idmac_start_dma,
 560         .stop = dw_mci_idmac_stop_dma,
 561         .complete = dw_mci_idmac_complete_dma,
 562         .cleanup = dw_mci_dma_cleanup,
 563 };
 564 #endif /* CONFIG_MMC_DW_IDMAC */
 565
 566 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 567                                    struct mmc_data *data,
 568                                    bool next)
 569 {
 570         struct scatterlist *sg;
 571         unsigned int i, sg_len;
 572
 573         if (!next && data->host_cookie)
 574                 return data->host_cookie;
 575
 576         /*
 577          * We don't do DMA on "complex" transfers, i.e. with
 578          * non-word-aligned buffers or lengths. Also, we don't bother
 579          * with all the DMA setup overhead for short transfers.
 580          */
 581         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 582                 return -EINVAL;
 583
 584         if (data->blksz & 3)
 585                 return -EINVAL;
 586
 587         for_each_sg(data->sg, sg, data->sg_len, i) {
 588                 if (sg->offset & 3 || sg->length & 3)
 589                         return -EINVAL;
 590         }
 591
 592         sg_len = dma_map_sg(host->dev,
 593                             data->sg,
 594                             data->sg_len,
 595                             dw_mci_get_dma_dir(data));
 596         if (sg_len == 0)
 597                 return -EINVAL;
 598
 599         if (next)
 600                 data->host_cookie = sg_len;
 601
 602         return sg_len;
 603 }
 604
 605 static void dw_mci_pre_req(struct mmc_host *mmc,
 606                            struct mmc_request *mrq,
 607                            bool is_first_req)
 608 {
 609         struct dw_mci_slot *slot = mmc_priv(mmc);
 610         struct mmc_data *data = mrq->data;
 611
 612         if (!slot->host->use_dma || !data)
 613                 return;
 614
 615         if (data->host_cookie) {
 616                 data->host_cookie = 0;
 617                 return;
 618         }
 619
 620         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 621                 data->host_cookie = 0;
 622 }
 623
 624 static void dw_mci_post_req(struct mmc_host *mmc,
 625                             struct mmc_request *mrq,
 626                             int err)
 627 {
 628         struct dw_mci_slot *slot = mmc_priv(mmc);
 629         struct mmc_data *data = mrq->data;
 630
 631         if (!slot->host->use_dma || !data)
 632                 return;
 633
 634         if (data->host_cookie)
 635                 dma_unmap_sg(slot->host->dev,
 636                              data->sg,
 637                              data->sg_len,
 638                              dw_mci_get_dma_dir(data));
 639         data->host_cookie = 0;
 640 }
 641
 642 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 643 {
 644 #ifdef CONFIG_MMC_DW_IDMAC
 645         unsigned int blksz = data->blksz;
 646         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 647         u32 fifo_width = 1 << host->data_shift;
 648         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 649         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 650         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 651
 652         tx_wmark = (host->fifo_depth) / 2;
 653         tx_wmark_invers = host->fifo_depth - tx_wmark;
 654
 655         /*
 656          * MSIZE is '1',
 657          * if blksz is not a multiple of the FIFO width
 658          */
 659         if (blksz % fifo_width) {
 660                 msize = 0;
 661                 rx_wmark = 1;
 662                 goto done;
 663         }
 664
 665         do {
 666                 if (!((blksz_depth % mszs[idx]) ||
 667                      (tx_wmark_invers % mszs[idx]))) {
 668                         msize = idx;
 669                         rx_wmark = mszs[idx] - 1;
 670                         break;
 671                 }
 672         } while (--idx > 0);
 673         /*
 674          * If idx is '0', it won't be tried
 675          * Thus, initial values are uesed
 676          */
 677 done:
 678         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 679         mci_writel(host, FIFOTH, fifoth_val);
 680 #endif
 681 }
 682
 683 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 684 {
 685         unsigned int blksz = data->blksz;
 686         u32 blksz_depth, fifo_depth;
 687         u16 thld_size;
 688
 689         WARN_ON(!(data->flags & MMC_DATA_READ));
 690
 691         if (host->timing != MMC_TIMING_MMC_HS200 &&
 692             host->timing != MMC_TIMING_UHS_SDR104)
 693                 goto disable;
 694
 695         blksz_depth = blksz / (1 << host->data_shift);
 696         fifo_depth = host->fifo_depth;
 697
 698         if (blksz_depth > fifo_depth)
 699                 goto disable;
 700
 701         /*
 702          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 703          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 704          * Currently just choose blksz.
 705          */
 706         thld_size = blksz;
 707         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 708         return;
 709
 710 disable:
 711         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 712 }
 713
 714 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 715 {
 716         int sg_len;
 717         u32 temp;
 718
 719         host->using_dma = 0;
 720
 721         /* If we don't have a channel, we can't do DMA */
 722         if (!host->use_dma)
 723                 return -ENODEV;
 724
 725         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 726         if (sg_len < 0) {
 727                 host->dma_ops->stop(host);
 728                 return sg_len;
 729         }
 730
 731         host->using_dma = 1;
 732
 733         dev_vdbg(host->dev,
 734                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 735                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 736                  sg_len);
 737
 738         /*
 739          * Decide the MSIZE and RX/TX Watermark.
 740          * If current block size is same with previous size,
 741          * no need to update fifoth.
 742          */
 743         if (host->prev_blksz != data->blksz)
 744                 dw_mci_adjust_fifoth(host, data);
 745
 746         /* Reset DMA FIFO*/
 747         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 748
 749         /* Enable the DMA interface */
 750         temp = mci_readl(host, CTRL);
 751         temp |= SDMMC_CTRL_DMA_ENABLE;
 752         mci_writel(host, CTRL, temp);
 753
 754         /* Disable RX/TX IRQs, let DMA handle it */
 755         temp = mci_readl(host, INTMASK);
 756         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 757         mci_writel(host, INTMASK, temp);
 758
 759         host->dma_ops->start(host, sg_len);
 760
 761         return 0;
 762 }
 763
 764 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 765 {
 766         u32 temp;
 767
 768         data->error = -EINPROGRESS;
 769
 770         WARN_ON(host->data);
 771         host->sg = NULL;
 772         host->data = data;
 773
 774         /* Reset FIFO*/
 775         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
 776
 777         if (data->flags & MMC_DATA_READ) {
 778                 host->dir_status = DW_MCI_RECV_STATUS;
 779                 dw_mci_ctrl_rd_thld(host, data);
 780         } else {
 781                 host->dir_status = DW_MCI_SEND_STATUS;
 782         }
 783
 784     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
 785          data->blocks, data->blksz, mmc_hostname(host->mmc));
 786
 787         if (dw_mci_submit_data_dma(host, data)) {
 788                 int flags = SG_MITER_ATOMIC;
 789                 if (host->data->flags & MMC_DATA_READ)
 790                         flags |= SG_MITER_TO_SG;
 791                 else
 792                         flags |= SG_MITER_FROM_SG;
 793
 794                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 795                 host->sg = data->sg;
 796                 host->part_buf_start = 0;
 797                 host->part_buf_count = 0;
 798
 799                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 800                 temp = mci_readl(host, INTMASK);
 801                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 802                 mci_writel(host, INTMASK, temp);
 803
 804                 temp = mci_readl(host, CTRL);
 805                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 806                 mci_writel(host, CTRL, temp);
 807
 808                 /*
 809                  * Use the initial fifoth_val for PIO mode.
 810                  * If next issued data may be transfered by DMA mode,
 811                  * prev_blksz should be invalidated.
 812                  */
 813                 mci_writel(host, FIFOTH, host->fifoth_val);
 814                 host->prev_blksz = 0;
 815         } else {
 816                 /*
 817                  * Keep the current block size.
 818                  * It will be used to decide whether to update
 819                  * fifoth register next time.
 820                  */
 821                 host->prev_blksz = data->blksz;
 822         }
 823 }
 824
 825 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 826 {
 827         struct dw_mci *host = slot->host;
 828         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
 829         unsigned int cmd_status = 0;
 830 #ifdef SDMMC_WAIT_FOR_UNBUSY
 831         bool ret = true;
 832         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
 833
 834     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 835         while (ret) {
 836                 ret =  time_before(jiffies, timeout);
 837                 cmd_status = mci_readl(host, STATUS);
 838                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
 839                         break;
 840         } ;
 841         if(false == ret)
 842             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
 843                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
 844     }
 845 #endif
 846         mci_writel(host, CMDARG, arg);
 847         wmb();
 848         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 849         if(cmd & SDMMC_CMD_UPD_CLK)
 850                 timeout = jiffies + msecs_to_jiffies(50);
 851         else
 852                 timeout = jiffies + msecs_to_jiffies(500);
 853         while (time_before(jiffies, timeout)) {
 854                 cmd_status = mci_readl(host, CMD);
 855                 if (!(cmd_status & SDMMC_CMD_START))
 856                         return ;
 857         }
 858         dev_err(&slot->mmc->class_dev,
 859                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 860                 cmd, arg, cmd_status);
 861 }
 862
 863 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 864 {
 865         struct dw_mci *host = slot->host;
 866         unsigned int tempck,clock = slot->clock;
 867         u32 div;
 868         u32 clk_en_a;
 869         u32 sdio_int;
 870
 871         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
 872                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
 873
 874         if (!clock) {
 875                 mci_writel(host, CLKENA, 0);
 876                 mci_send_cmd(slot,
 877                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 878
 879         } else if (clock != host->current_speed || force_clkinit) {
 880                 div = host->bus_hz / clock;
 881                 if (host->bus_hz % clock && host->bus_hz > clock)
 882                         /*
 883                          * move the + 1 after the divide to prevent
 884                          * over-clocking the card.
 885                          */
 886                         div += 1;
 887
 888                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
 889
 890                 if ((clock << div) != slot->__clk_old || force_clkinit) {
 891                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
 892                         dev_info(&slot->mmc->class_dev,
 893                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
 894                                  slot->id, host->bus_hz, clock,
 895                                  tempck, div);
 896
 897                         host->set_speed = tempck;
 898                         host->set_div = div;
 899                 }
 900
 901                 /* disable clock */
 902                 mci_writel(host, CLKENA, 0);
 903                 mci_writel(host, CLKSRC, 0);
 904
 905                 /* inform CIU */
 906                 mci_send_cmd(slot,
 907                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 908
 909                 if(clock <= 400*1000){
 910                         MMC_DBG_BOOT_FUNC(host->mmc,
 911                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
 912                                 clock * 2, mmc_hostname(host->mmc));
 913                         /* RK3288 clk_mmc will change parents to 24MHz xtal*/
 914                         clk_set_rate(host->clk_mmc, clock * 2);
 915
 916                         div = 0;
 917                         host->set_div = div;
 918                 }
 919                 else
 920                 {
 921                         MMC_DBG_BOOT_FUNC(host->mmc,
 922                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
 923                                 mmc_hostname(host->mmc));
 924                         if(div > 1)
 925                         {
 926                                 MMC_DBG_ERR_FUNC(host->mmc,
 927                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
 928                                         mmc_hostname(host->mmc));
 929                                  div = 1;
 930                                  host->set_div = div;
 931                                  host->bus_hz = host->set_speed * 2;
 932                                  MMC_DBG_BOOT_FUNC(host->mmc,
 933                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
 934                                         div, host->bus_hz, mmc_hostname(host->mmc));
 935                         }
 936                         /* BUG may be here, come on,  Linux BSP engineer looks!
 937                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
 938                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
 939                            some oops happened like that:
 940                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
 941                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
 942                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
 943                            mmc0: new high speed DDR MMC card at address 0001
 944                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
 945                            ....
 946                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
 947                            mmcblk0: retrying using single block read
 948                            mmcblk0: error -110 sending status command, retrying
 949
 950                            How to: If eMMC HW version < 4.51, or > 4.51 but no caps2-mmc-hs200 support in dts
 951                                    Please set dts emmc clk to 100M or 150M, I will workaround it!
 952                          */
 953
 954                         if (host->verid < DW_MMC_240A)
 955                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
 956                         else
 957                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
 958
 959
 960
 961                 }
 962
 963                 /* set clock to desired speed */
 964                 mci_writel(host, CLKDIV, div);
 965
 966                 /* inform CIU */
 967                 mci_send_cmd(slot,
 968                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 969
 970                 /* enable clock; only low power if no SDIO */
 971                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 972
 973                 if (host->verid < DW_MMC_240A)
 974                     sdio_int = SDMMC_INT_SDIO(slot->id);
 975                 else
 976                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
 977
 978                 if (!(mci_readl(host, INTMASK) & sdio_int))
 979                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 980                 mci_writel(host, CLKENA, clk_en_a);
 981
 982                 /* inform CIU */
 983                 mci_send_cmd(slot,
 984                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 985                 /* keep the clock with reflecting clock dividor */
 986                 slot->__clk_old = clock << div;
 987         }
 988
 989         host->current_speed = clock;
 990
 991     if(slot->ctype != slot->pre_ctype)
 992         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
 993             host->set_speed,
 994             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
 995             mmc_hostname(host->mmc));
 996     slot->pre_ctype = slot->ctype;
 997
 998         /* Set the current slot bus width */
 999         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1000 }
1001
1002 static void dw_mci_wait_unbusy(struct dw_mci *host)
1003 {
1004
1005     unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1006     unsigned long   time_loop;
1007     unsigned int    status;
1008
1009     MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1010
1011     if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1012         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1013     else if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1014         timeout = SDMMC_DATA_TIMEOUT_SD;
1015
1016     time_loop = jiffies + msecs_to_jiffies(timeout);
1017     do {
1018         status = mci_readl(host, STATUS);
1019         if (!(status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1020                 break;
1021         //MMC_DBG_INFO_FUNC("dw_mci_wait_unbusy, waiting for......");
1022     } while (time_before(jiffies, time_loop));
1023 }
1024
1025 /*
1026 *   result:
1027 *   0--status is busy.
1028 *   1--status is unbusy.
1029 */
1030 int dw_mci_card_busy(struct mmc_host *mmc)
1031 {
1032         struct dw_mci_slot *slot = mmc_priv(mmc);
1033         struct dw_mci *host = slot->host;
1034     unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1035     unsigned long   time_loop;
1036     unsigned int    status;
1037     int ret= 0;
1038
1039     if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1040         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1041     else if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1042         timeout = SDMMC_DATA_TIMEOUT_SD;
1043     timeout = 250*1000;//test
1044     time_loop = jiffies + msecs_to_jiffies(timeout);
1045
1046     MMC_DBG_INFO_FUNC(host->mmc, "line%d: dw_mci_wait_unbusy,timeloop=%lu, status=0x%x ",
1047         __LINE__, time_loop, mci_readl(host, STATUS));
1048     do {
1049         status = mci_readl(host, STATUS);
1050         if (!(status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY))){
1051             ret = 1;//card is unbusy.
1052                 break;
1053         }
1054         //MMC_DBG_INFO_FUNC("dw_mci_wait_unbusy, waiting for......");
1055     } while (time_before(jiffies, time_loop));
1056     MMC_DBG_INFO_FUNC(host->mmc, "line%d: dw_mci_wait_unbusy,ret=%d,  status=0x%x ",
1057         __LINE__,ret,mci_readl(host, STATUS));
1058
1059     return ret;
1060 }
1061
1062 static void __dw_mci_start_request(struct dw_mci *host,
1063                                    struct dw_mci_slot *slot,
1064                                    struct mmc_command *cmd)
1065 {
1066         struct mmc_request *mrq;
1067         struct mmc_data *data;
1068         u32 cmdflags;
1069
1070         mrq = slot->mrq;
1071         if (host->pdata->select_slot)
1072                 host->pdata->select_slot(slot->id);
1073
1074         host->cur_slot = slot;
1075         host->mrq = mrq;
1076 #if 0 //add by xbw,at 2014-03-12
1077         /*clean FIFO if it is a new request*/
1078     if(!(mrq->cmd->opcode & SDMMC_CMD_STOP)) {
1079         MMC_DBG_INFO_FUNC("%d..%s: reset the ctrl.", __LINE__, __FUNCTION__);
1080         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1081                                 SDMMC_CTRL_DMA_RESET));
1082     }
1083  #endif
1084     dw_mci_wait_unbusy(host);
1085
1086         host->pending_events = 0;
1087         host->completed_events = 0;
1088         host->data_status = 0;
1089
1090         data = cmd->data;
1091         if (data) {
1092                 dw_mci_set_timeout(host);
1093                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1094                 mci_writel(host, BLKSIZ, data->blksz);
1095         }
1096
1097         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1098
1099         /* this is the first command, send the initialization clock */
1100         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1101                 cmdflags |= SDMMC_CMD_INIT;
1102
1103         if (data) {
1104                 dw_mci_submit_data(host, data);
1105                 wmb();
1106         }
1107
1108         dw_mci_start_command(host, cmd, cmdflags);
1109
1110         if (mrq->stop)
1111                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1112 }
1113
1114 static void dw_mci_start_request(struct dw_mci *host,
1115                                  struct dw_mci_slot *slot)
1116 {
1117         struct mmc_request *mrq = slot->mrq;
1118         struct mmc_command *cmd;
1119
1120     MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1121         mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1122
1123         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1124         __dw_mci_start_request(host, slot, cmd);
1125 }
1126
1127 /* must be called with host->lock held */
1128 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1129                                  struct mmc_request *mrq)
1130 {
1131         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1132                  host->state);
1133
1134         slot->mrq = mrq;
1135
1136         if (host->state == STATE_IDLE) {
1137                 host->state = STATE_SENDING_CMD;
1138                 dw_mci_start_request(host, slot);
1139         } else {
1140                 list_add_tail(&slot->queue_node, &host->queue);
1141         }
1142 }
1143
1144 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1145 {
1146         struct dw_mci_slot *slot = mmc_priv(mmc);
1147         struct dw_mci *host = slot->host;
1148
1149         WARN_ON(slot->mrq);
1150
1151         /*
1152          * The check for card presence and queueing of the request must be
1153          * atomic, otherwise the card could be removed in between and the
1154          * request wouldn't fail until another card was inserted.
1155          */
1156         spin_lock_bh(&host->lock);
1157
1158         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1159                 spin_unlock_bh(&host->lock);
1160                 mrq->cmd->error = -ENOMEDIUM;
1161                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1162                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1163
1164                 mmc_request_done(mmc, mrq);
1165                 return;
1166         }
1167     MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1168         mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1169
1170         dw_mci_queue_request(host, slot, mrq);
1171
1172         spin_unlock_bh(&host->lock);
1173 }
1174
1175 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1176 {
1177         struct dw_mci_slot *slot = mmc_priv(mmc);
1178         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1179         u32 regs;
1180 #ifdef SDMMC_WAIT_FOR_UNBUSY
1181         unsigned long   time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1182         bool ret = true;
1183
1184         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1185                 printk("%d..%s:  no card. [%s]\n", \
1186                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1187                 goto EXIT_POWER;
1188         }
1189
1190         while (ret) {
1191                 ret = time_before(jiffies, time_loop);
1192                 regs = mci_readl(slot->host, STATUS);
1193                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1194                         break;
1195         };
1196
1197         if(false == ret)
1198         {
1199                 printk("slot->flags = %lu ", slot->flags);
1200                 dump_stack();
1201                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1202                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1203         }
1204 #endif
1205         switch (ios->bus_width) {
1206         case MMC_BUS_WIDTH_4:
1207                 slot->ctype = SDMMC_CTYPE_4BIT;
1208                 break;
1209         case MMC_BUS_WIDTH_8:
1210                 slot->ctype = SDMMC_CTYPE_8BIT;
1211                 break;
1212         default:
1213                 /* set default 1 bit mode */
1214                 slot->ctype = SDMMC_CTYPE_1BIT;
1215                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1216         }
1217
1218         regs = mci_readl(slot->host, UHS_REG);
1219
1220         /* DDR mode set */
1221         if (ios->timing == MMC_TIMING_UHS_DDR50)
1222                 regs |= ((0x1 << slot->id) << 16);
1223         else
1224                 regs &= ~((0x1 << slot->id) << 16);
1225
1226         mci_writel(slot->host, UHS_REG, regs);
1227         slot->host->timing = ios->timing;
1228
1229         /*
1230          * Use mirror of ios->clock to prevent race with mmc
1231          * core ios update when finding the minimum.
1232          */
1233         slot->clock = ios->clock;
1234
1235         if (drv_data && drv_data->set_ios)
1236                 drv_data->set_ios(slot->host, ios);
1237
1238         /* Slot specific timing and width adjustment */
1239         dw_mci_setup_bus(slot, false);
1240                 //return -EAGAIN;
1241
1242 EXIT_POWER:
1243         switch (ios->power_mode) {
1244         case MMC_POWER_UP:
1245                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1246                 /* Power up slot */
1247                 if (slot->host->pdata->setpower)
1248                         slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1249                 regs = mci_readl(slot->host, PWREN);
1250                 regs |= (1 << slot->id);
1251                 mci_writel(slot->host, PWREN, regs);
1252                 break;
1253         case MMC_POWER_OFF:
1254                 /* Power down slot */
1255                 if (slot->host->pdata->setpower)
1256                         slot->host->pdata->setpower(slot->id, 0);
1257                 regs = mci_readl(slot->host, PWREN);
1258                 regs &= ~(1 << slot->id);
1259                 mci_writel(slot->host, PWREN, regs);
1260                 break;
1261         default:
1262                 break;
1263         }
1264 }
1265
1266 static int dw_mci_get_ro(struct mmc_host *mmc)
1267 {
1268         int read_only;
1269         struct dw_mci_slot *slot = mmc_priv(mmc);
1270         struct dw_mci_board *brd = slot->host->pdata;
1271
1272         /* Use platform get_ro function, else try on board write protect */
1273         if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1274                 read_only = 0;
1275         else if (brd->get_ro)
1276                 read_only = brd->get_ro(slot->id);
1277         else if (gpio_is_valid(slot->wp_gpio))
1278                 read_only = gpio_get_value(slot->wp_gpio);
1279         else
1280                 read_only =
1281                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1282
1283         dev_dbg(&mmc->class_dev, "card is %s\n",
1284                 read_only ? "read-only" : "read-write");
1285
1286         return read_only;
1287 }
1288
1289 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1290 {
1291         struct dw_mci_slot *slot = mmc_priv(mmc);
1292         /*struct dw_mci_board *brd = slot->host->pdata;*/
1293         struct dw_mci *host = slot->host;
1294         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1295                 return 0;
1296
1297         spin_lock_bh(&host->lock);
1298         if(val){
1299                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1300                 if(__clk_is_enabled(host->hclk_mmc) == false)
1301                         clk_prepare_enable(host->hclk_mmc);
1302                 if(__clk_is_enabled(host->clk_mmc) == false)
1303                         clk_prepare_enable(host->clk_mmc);
1304         }else{
1305                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1306                 if(__clk_is_enabled(host->clk_mmc) == true)
1307                         clk_disable_unprepare(slot->host->clk_mmc);
1308                 if(__clk_is_enabled(host->hclk_mmc) == true)
1309                         clk_disable_unprepare(slot->host->hclk_mmc);
1310         }
1311         spin_unlock_bh(&host->lock);
1312         mmc_detect_change(slot->mmc, 20);
1313
1314         return 0;
1315 }
1316
1317
1318
1319 static int dw_mci_get_cd(struct mmc_host *mmc)
1320 {
1321         int present;
1322         struct dw_mci_slot *slot = mmc_priv(mmc);
1323         struct dw_mci_board *brd = slot->host->pdata;
1324         struct dw_mci *host = slot->host;
1325         int gpio_cd = mmc_gpio_get_cd(mmc);
1326
1327     if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1328         return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1329
1330         /* Use platform get_cd function, else try onboard card detect */
1331         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1332                 present = 1;
1333         else if (brd->get_cd)
1334                 present = !brd->get_cd(slot->id);
1335         else if (!IS_ERR_VALUE(gpio_cd))
1336                 present = gpio_cd;
1337         else
1338                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1339                         == 0 ? 1 : 0;
1340
1341         spin_lock_bh(&host->lock);
1342         if (present) {
1343                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1344                 dev_dbg(&mmc->class_dev, "card is present\n");
1345         } else {
1346                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1347                 dev_dbg(&mmc->class_dev, "card is not present\n");
1348         }
1349         spin_unlock_bh(&host->lock);
1350
1351         return present;
1352 }
1353
1354 static void dw_mci_hw_reset(struct mmc_host *mmc)
1355 {
1356         struct dw_mci_slot *slot = mmc_priv(mmc);
1357         struct dw_mci *host = slot->host;
1358         u32 cmd_flags, regs;
1359         unsigned long timeout;
1360         bool ret = true;
1361
1362         /* (1) CMD12 to end any transfer in process */
1363         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1364                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1365
1366         if(host->mmc->hold_reg_flag)
1367                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1368         mci_writel(host, CMDARG, 0);
1369         wmb();
1370         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1371         wmb();
1372         timeout = jiffies + msecs_to_jiffies(500);
1373         while(ret){
1374                 ret = time_before(jiffies, timeout);
1375                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1376                         break;
1377         }
1378
1379         if(false == ret)
1380                 MMC_DBG_ERR_FUNC(host->mmc,
1381                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1382                         __func__, mmc_hostname(host->mmc));
1383
1384         /* (2) wait DTO, even if no response is sent back by card */
1385         ret = true;
1386         timeout = jiffies + msecs_to_jiffies(5);
1387         while(ret){
1388                 ret = time_before(jiffies, timeout);
1389                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1390                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1391                         break;
1392                 }
1393         }
1394
1395         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1396
1397         /* Software reset - BMOD[0] for IDMA only */
1398         regs = mci_readl(host, BMOD);
1399         regs |= SDMMC_IDMAC_SWRESET;
1400         mci_writel(host, BMOD, regs);
1401         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1402         regs = mci_readl(host, BMOD);
1403         if(regs & SDMMC_IDMAC_SWRESET)
1404                 MMC_DBG_WARN_FUNC(host->mmc,
1405                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1406                         __func__, mmc_hostname(host->mmc));
1407
1408         /* DMA reset - CTRL[2] */
1409         regs = mci_readl(host, CTRL);
1410         regs |= SDMMC_CTRL_DMA_RESET;
1411         mci_writel(host, CTRL, regs);
1412         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1413         regs = mci_readl(host, CTRL);
1414         if(regs & SDMMC_CTRL_DMA_RESET)
1415                 MMC_DBG_WARN_FUNC(host->mmc,
1416                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1417                         __func__, mmc_hostname(host->mmc));
1418
1419         /* FIFO reset - CTRL[1] */
1420         regs = mci_readl(host, CTRL);
1421         regs |= SDMMC_CTRL_FIFO_RESET;
1422         mci_writel(host, CTRL, regs);
1423         mdelay(1); /* no timing limited, 1ms is random value */
1424         regs = mci_readl(host, CTRL);
1425         if(regs & SDMMC_CTRL_FIFO_RESET)
1426                 MMC_DBG_WARN_FUNC(host->mmc,
1427                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1428                         __func__, mmc_hostname(host->mmc));
1429
1430         /* (4) CARD_RESET
1431         According to eMMC spec
1432         tRstW >= 1us ;   RST_n pulse width
1433         tRSCA >= 200us ; RST_n to Command time
1434         tRSTH >= 1us ;   RST_n high period
1435         */
1436
1437         mci_writel(slot->host, RST_n, 0x1);
1438         dsb();
1439         udelay(10); /* 10us for bad quality eMMc. */
1440
1441         mci_writel(slot->host, RST_n, 0x0);
1442         dsb();
1443         usleep_range(500, 1000); /* at least 500(> 200us) */
1444 }
1445
1446 /*
1447  * Disable lower power mode.
1448  *
1449  * Low power mode will stop the card clock when idle.  According to the
1450  * description of the CLKENA register we should disable low power mode
1451  * for SDIO cards if we need SDIO interrupts to work.
1452  *
1453  * This function is fast if low power mode is already disabled.
1454  */
1455 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1456 {
1457         struct dw_mci *host = slot->host;
1458         u32 clk_en_a;
1459         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1460
1461         clk_en_a = mci_readl(host, CLKENA);
1462
1463         if (clk_en_a & clken_low_pwr) {
1464                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1465                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1466                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1467         }
1468 }
1469
1470 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1471 {
1472         struct dw_mci_slot *slot = mmc_priv(mmc);
1473         struct dw_mci *host = slot->host;
1474         u32 int_mask;
1475         u32 sdio_int;
1476
1477         /* Enable/disable Slot Specific SDIO interrupt */
1478         int_mask = mci_readl(host, INTMASK);
1479
1480     if (host->verid < DW_MMC_240A)
1481                 sdio_int = SDMMC_INT_SDIO(slot->id);
1482         else
1483                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1484
1485         if (enb) {
1486                 /*
1487                  * Turn off low power mode if it was enabled.  This is a bit of
1488                  * a heavy operation and we disable / enable IRQs a lot, so
1489                  * we'll leave low power mode disabled and it will get
1490                  * re-enabled again in dw_mci_setup_bus().
1491                  */
1492                 dw_mci_disable_low_power(slot);
1493
1494                 mci_writel(host, INTMASK,
1495                            (int_mask | sdio_int));
1496         } else {
1497                 mci_writel(host, INTMASK,
1498                            (int_mask & ~sdio_int));
1499         }
1500 }
1501
1502 #if 0
1503 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1504                                                 struct mmc_ios *ios)
1505 {
1506         int ret;
1507         unsigned int value,uhs_reg;
1508
1509         /*
1510          * Signal Voltage Switching is only applicable for Host Controllers
1511          * v3.00 and above.
1512          */
1513         if (host->verid < DW_MMC_240A)
1514                 return 0;
1515
1516         uhs_reg = mci_readl(host, UHS_REG);
1517     MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1518         __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1519
1520         switch (ios->signal_voltage) {
1521         case MMC_SIGNAL_VOLTAGE_330:
1522                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1523                 if (host->vmmc) {
1524                         ret = io_domain_regulator_set_voltage(host->vmmc, 3300000, 3300000);
1525                         //regulator_put(host->vmmc); //to be done in remove function.
1526
1527                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1528                             __func__, regulator_get_voltage(host->vmmc), ret);
1529                         if (ret) {
1530                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1531                                                 " failed\n", mmc_hostname(host->mmc));
1532                                 return -EIO;
1533                         }
1534                 }
1535             MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__, __FUNCTION__, mmc_hostname(host->mmc));
1536
1537                 //set High-power mode
1538                 value = mci_readl(host, CLKENA);
1539                 mci_writel(host,CLKENA , value& ~SDMMC_CLKEN_LOW_PWR);
1540                 //SDMMC_UHS_REG
1541                 mci_writel(host,UHS_REG , uhs_reg & ~SDMMC_UHS_VOLT_REG_18);
1542
1543                 /* Wait for 5ms */
1544                 usleep_range(5000, 5500);
1545
1546                 /* 3.3V regulator output should be stable within 5 ms */
1547                 uhs_reg = mci_readl(host, UHS_REG);
1548             if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1549                 return 0;
1550
1551                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1552                                 mmc_hostname(host->mmc));
1553
1554                 return -EAGAIN;
1555         case MMC_SIGNAL_VOLTAGE_180:
1556                 if (host->vmmc) {
1557                         ret = io_domain_regulator_set_voltage(host->vmmc,1800000, 1800000);
1558 //                      regulator_put(host->vmmc);//to be done in remove function.
1559
1560                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1561                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1562                         if (ret) {
1563                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1564                                                 " failed\n", mmc_hostname(host->mmc));
1565                                 return -EIO;
1566                         }
1567                 }
1568
1569                 /*
1570                  * Enable 1.8V Signal Enable in the Host Control2
1571                  * register
1572                  */
1573             mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1574
1575                 /* Wait for 5ms */
1576                 usleep_range(5000, 5500);
1577             MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__, __FUNCTION__,mmc_hostname(host->mmc));
1578
1579                 /* 1.8V regulator output should be stable within 5 ms */
1580                 uhs_reg = mci_readl(host, UHS_REG);
1581             if( uhs_reg & SDMMC_UHS_VOLT_REG_18){
1582
1583                 return 0;
1584             }
1585
1586                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1587                                 mmc_hostname(host->mmc));
1588
1589                 return -EAGAIN;
1590         case MMC_SIGNAL_VOLTAGE_120:
1591                 if (host->vmmc) {
1592                         ret = io_domain_regulator_set_voltage(host->vmmc, 1200000, 1200000);
1593                         if (ret) {
1594                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1595                                                 " failed\n", mmc_hostname(host->mmc));
1596                                 return -EIO;
1597                         }
1598                 }
1599                 return 0;
1600         default:
1601                 /* No signal voltage switch required */
1602                 return 0;
1603         }
1604 }
1605
1606
1607 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1608         struct mmc_ios *ios)
1609 {
1610         struct dw_mci_slot *slot = mmc_priv(mmc);
1611         struct dw_mci *host = slot->host;
1612         int err;
1613
1614         if (host->verid < DW_MMC_240A)
1615                 return 0;
1616         //sdhci_runtime_pm_get(host);
1617         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1618         //sdhci_runtime_pm_put(host);
1619         return err;
1620 }
1621 #endif
1622 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1623 {
1624         struct dw_mci_slot *slot = mmc_priv(mmc);
1625         struct dw_mci *host = slot->host;
1626         const struct dw_mci_drv_data *drv_data = host->drv_data;
1627         struct dw_mci_tuning_data tuning_data;
1628         int err = -ENOSYS;
1629
1630         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1631                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1632                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1633                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1634                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1635                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1636                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1637                 } else {
1638                         return -EINVAL;
1639                 }
1640         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1641                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1642                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1643         } else {
1644                 dev_err(host->dev,
1645                         "Undefined command(%d) for tuning\n", opcode);
1646                 return -EINVAL;
1647         }
1648
1649
1650         /* Recommend sample phase and delayline
1651            Fixme: Mix-use these three controllers will cause
1652            con_id mismatch.
1653          */
1654         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1655             tuning_data.con_id = 3;
1656         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1657             tuning_data.con_id = 1;
1658         else
1659             tuning_data.con_id = 0;
1660
1661         /* 0: driver, from host->devices
1662            1: sample, from devices->host
1663          */
1664         tuning_data.tuning_type = 1;
1665
1666         if (drv_data && drv_data->execute_tuning)
1667                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1668
1669         return err;
1670 }
1671
1672 static const struct mmc_host_ops dw_mci_ops = {
1673         .request                = dw_mci_request,
1674         .pre_req                = dw_mci_pre_req,
1675         .post_req               = dw_mci_post_req,
1676         .set_ios                = dw_mci_set_ios,
1677         .get_ro                 = dw_mci_get_ro,
1678         .get_cd                 = dw_mci_get_cd,
1679         .set_sdio_status    = dw_mci_set_sdio_status,
1680         .hw_reset       = dw_mci_hw_reset,
1681         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1682         .execute_tuning         = dw_mci_execute_tuning,
1683         //.start_signal_voltage_switch  = dw_mci_start_signal_voltage_switch,
1684         //.card_busy  = dw_mci_card_busy,
1685 };
1686 #if 0
1687 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
1688 {
1689         unsigned long flags;
1690
1691     if(!host)
1692         return;
1693
1694         local_irq_save(flags);
1695         if(host->irq_state != irqflag)
1696         {
1697             host->irq_state = irqflag;
1698             if(irqflag)
1699             {
1700                 enable_irq(host->irq);
1701             }
1702             else
1703             {
1704                 disable_irq(host->irq);
1705             }
1706         }
1707         local_irq_restore(flags);
1708 }
1709 #endif
1710 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
1711         __releases(&host->lock)
1712         __acquires(&host->lock)
1713 {
1714         if(DW_MCI_SEND_STATUS == host->dir_status){
1715             #if 0
1716             if( MMC_BUS_TEST_W != host->cmd->opcode){
1717                 if(host->data_status & SDMMC_INT_DCRC)
1718                     host->data->error = -EILSEQ;
1719                 else if(host->data_status & SDMMC_INT_EBE)
1720                     host->data->error = -ETIMEDOUT;
1721             } else {
1722                 dw_mci_wait_unbusy(host);
1723             }
1724             #else
1725             dw_mci_wait_unbusy(host);
1726             #endif
1727
1728         }
1729 }
1730
1731 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1732         __releases(&host->lock)
1733         __acquires(&host->lock)
1734 {
1735         struct dw_mci_slot *slot;
1736         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1737
1738         WARN_ON(host->cmd || host->data);
1739
1740     dw_mci_deal_data_end(host, mrq);
1741
1742         if(mrq->cmd)
1743        MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
1744             mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
1745         if(mrq->data)
1746        MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
1747             mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
1748
1749         host->cur_slot->mrq = NULL;
1750         host->mrq = NULL;
1751         if (!list_empty(&host->queue)) {
1752                 slot = list_entry(host->queue.next,
1753                                   struct dw_mci_slot, queue_node);
1754                 list_del(&slot->queue_node);
1755                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1756                          mmc_hostname(slot->mmc));
1757                 host->state = STATE_SENDING_CMD;
1758                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
1759                 dw_mci_start_request(host, slot);
1760         } else {
1761                 dev_vdbg(host->dev, "list empty\n");
1762                 host->state = STATE_IDLE;
1763         }
1764
1765         spin_unlock(&host->lock);
1766         mmc_request_done(prev_mmc, mrq);
1767         spin_lock(&host->lock);
1768 }
1769
1770 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1771 {
1772         u32 status = host->cmd_status;
1773
1774         host->cmd_status = 0;
1775
1776         /* Read the response from the card (up to 16 bytes) */
1777         if (cmd->flags & MMC_RSP_PRESENT) {
1778                 if (cmd->flags & MMC_RSP_136) {
1779                         cmd->resp[3] = mci_readl(host, RESP0);
1780                         cmd->resp[2] = mci_readl(host, RESP1);
1781                         cmd->resp[1] = mci_readl(host, RESP2);
1782                         cmd->resp[0] = mci_readl(host, RESP3);
1783
1784             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
1785                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
1786                 } else {
1787                         cmd->resp[0] = mci_readl(host, RESP0);
1788                         cmd->resp[1] = 0;
1789                         cmd->resp[2] = 0;
1790                         cmd->resp[3] = 0;
1791             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
1792                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
1793                 }
1794         }
1795
1796         if (status & SDMMC_INT_RTO)
1797         {
1798             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1799                 host->cmd_rto += 1;
1800
1801                 cmd->error = -ETIMEDOUT;
1802         }
1803         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1804                 cmd->error = -EILSEQ;
1805         else if (status & SDMMC_INT_RESP_ERR)
1806                 cmd->error = -EIO;
1807         else
1808                 cmd->error = 0;
1809     MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",cmd->opcode, cmd->error,mmc_hostname(host->mmc));
1810
1811         if (cmd->error) {
1812             if(MMC_SEND_STATUS != cmd->opcode)
1813                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
1814                 MMC_DBG_ERR_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
1815                     cmd->opcode, cmd->error,mmc_hostname(host->mmc));
1816                host->cmd_rto = 0;
1817          }
1818
1819                 /* newer ip versions need a delay between retries */
1820                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1821                         mdelay(20);
1822         }
1823
1824 }
1825
1826 static void dw_mci_tasklet_func(unsigned long priv)
1827 {
1828         struct dw_mci *host = (struct dw_mci *)priv;
1829     struct dw_mci_slot *slot = mmc_priv(host->mmc);
1830         struct mmc_data *data;
1831         struct mmc_command *cmd;
1832         enum dw_mci_state state;
1833         enum dw_mci_state prev_state;
1834         u32 status, cmd_flags;
1835         unsigned long timeout = 0;
1836         bool ret = true;
1837
1838         spin_lock(&host->lock);
1839
1840         state = host->state;
1841         data = host->data;
1842
1843         do {
1844                 prev_state = state;
1845
1846                 switch (state) {
1847                 case STATE_IDLE:
1848                         break;
1849
1850                 case STATE_SENDING_CMD:
1851                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1852                                                 &host->pending_events))
1853                                 break;
1854
1855                         cmd = host->cmd;
1856                         host->cmd = NULL;
1857                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1858                         dw_mci_command_complete(host, cmd);
1859                         if (cmd == host->mrq->sbc && !cmd->error) {
1860                                 prev_state = state = STATE_SENDING_CMD;
1861                                 __dw_mci_start_request(host, host->cur_slot,
1862                                                        host->mrq->cmd);
1863                                 goto unlock;
1864                         }
1865
1866             if (cmd->data && cmd->error) {
1867                                 dw_mci_stop_dma(host);
1868                                 #if 1
1869                 if (data->stop) {
1870                     send_stop_cmd(host, data);
1871                     state = STATE_SENDING_STOP;
1872                     break;
1873                 } else {
1874                     host->data = NULL;
1875                 }
1876                                 #else
1877                                 send_stop_abort(host, data);
1878                                 state = STATE_SENDING_STOP;
1879                                 break;
1880                                 #endif
1881                         }
1882
1883
1884                         if (!host->mrq->data || cmd->error) {
1885                                 dw_mci_request_end(host, host->mrq);
1886                                 goto unlock;
1887                         }
1888
1889                         prev_state = state = STATE_SENDING_DATA;
1890                         /* fall through */
1891
1892                 case STATE_SENDING_DATA:
1893                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
1894                                 dw_mci_stop_dma(host);
1895                                 #if 1
1896                                 if (data->stop){
1897                                         send_stop_cmd(host, data);
1898                                 }else{
1899                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
1900                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
1901                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
1902
1903                                                 mci_writel(host, CMDARG, 0);
1904                         wmb();
1905                         cmd_flags = SDMMC_CMD_STOP |SDMMC_CMD_RESP_CRC|SDMMC_CMD_RESP_EXP|MMC_STOP_TRANSMISSION;
1906
1907                                                 if(host->mmc->hold_reg_flag)
1908                            cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1909
1910                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1911                         wmb();
1912                         timeout = jiffies + msecs_to_jiffies(500);
1913
1914                                         while(ret){
1915                                                 ret = time_before(jiffies, timeout);
1916                             if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1917                                  break;
1918                         }
1919
1920                                         if(false == ret)
1921                                                 MMC_DBG_ERR_FUNC(host->mmc,
1922                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
1923                              __func__, mmc_hostname(host->mmc));
1924                 }
1925                                 #else
1926                                 send_stop_abort(host, data);
1927                                 #endif
1928                                 state = STATE_DATA_ERROR;
1929                                 break;
1930                         }
1931
1932                         MMC_DBG_CMD_FUNC(host->mmc,
1933                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
1934                         prev_state,state, mmc_hostname(host->mmc));
1935
1936                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1937                                                 &host->pending_events))
1938                                 break;
1939                         MMC_DBG_INFO_FUNC(host->mmc,
1940                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
1941                                           prev_state,state,mmc_hostname(host->mmc));
1942
1943                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1944                         prev_state = state = STATE_DATA_BUSY;
1945                         /* fall through */
1946
1947                 case STATE_DATA_BUSY:
1948                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1949                                                 &host->pending_events))
1950                                 break;
1951
1952                         dw_mci_deal_data_end(host, host->mrq);
1953                         MMC_DBG_INFO_FUNC(host->mmc,
1954                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
1955                                           prev_state,state,mmc_hostname(host->mmc));
1956
1957                         host->data = NULL;
1958                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1959                         status = host->data_status;
1960
1961                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1962                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
1963                                 MMC_DBG_ERR_FUNC(host->mmc,
1964                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
1965                             prev_state,state, status, mmc_hostname(host->mmc));
1966
1967                         if (status & SDMMC_INT_DRTO) {
1968                                         data->error = -ETIMEDOUT;
1969                                 } else if (status & SDMMC_INT_DCRC) {
1970                                         data->error = -EILSEQ;
1971                                 } else if (status & SDMMC_INT_EBE &&
1972                                 host->dir_status == DW_MCI_SEND_STATUS){
1973                                         /*
1974                                          * No data CRC status was returned.
1975                                          * The number of bytes transferred will
1976                                          * be exaggerated in PIO mode.
1977                                          */
1978                                         data->bytes_xfered = 0;
1979                                         data->error = -ETIMEDOUT;
1980                                 } else {
1981                                         dev_err(host->dev,
1982                                                 "data FIFO error "
1983                                                 "(status=%08x)\n",
1984                                                 status);
1985                                         data->error = -EIO;
1986                                 }
1987                                 /*
1988                                  * After an error, there may be data lingering
1989                                  * in the FIFO, so reset it - doing so
1990                                  * generates a block interrupt, hence setting
1991                                  * the scatter-gather pointer to NULL.
1992                                  */
1993                                 dw_mci_fifo_reset(host);
1994                         } else {
1995                                 data->bytes_xfered = data->blocks * data->blksz;
1996                                 data->error = 0;
1997                         }
1998
1999                         if (!data->stop) {
2000                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2001                                       prev_state,state,mmc_hostname(host->mmc));
2002                                 dw_mci_request_end(host, host->mrq);
2003                                 goto unlock;
2004                         }
2005                     MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2006                 prev_state,state,mmc_hostname(host->mmc));
2007
2008                         if (host->mrq->sbc && !data->error) {
2009                                 data->stop->error = 0;
2010
2011                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2012                     prev_state,state,mmc_hostname(host->mmc));
2013
2014                                 dw_mci_request_end(host, host->mrq);
2015                                 goto unlock;
2016                         }
2017
2018                         prev_state = state = STATE_SENDING_STOP;
2019                         if (!data->error)
2020                             send_stop_cmd(host, data);
2021                         #if 0
2022                         if (data->stop && !data->error) {
2023                                 /* stop command for open-ended transfer*/
2024
2025                                 send_stop_abort(host, data);
2026                         }
2027                         #endif
2028                         /* fall through */
2029             MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2030                 prev_state,state,mmc_hostname(host->mmc));
2031
2032                 case STATE_SENDING_STOP:
2033                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2034                                                 &host->pending_events))
2035                                 break;
2036             MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2037                 prev_state,state,mmc_hostname(host->mmc));
2038
2039              /* CMD error in data command */
2040                         if (host->mrq->cmd->error && host->mrq->data) {
2041                                 dw_mci_fifo_reset(host);
2042                         }
2043
2044                         host->cmd = NULL;
2045                         host->data = NULL;
2046             #if 1
2047             dw_mci_command_complete(host, host->mrq->stop);
2048             #else
2049                         if (host->mrq->stop)
2050                                 dw_mci_command_complete(host, host->mrq->stop);
2051                         else
2052                                 host->cmd_status = 0;
2053             #endif
2054
2055                         dw_mci_request_end(host, host->mrq);
2056                         goto unlock;
2057
2058                 case STATE_DATA_ERROR:
2059                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2060                                                 &host->pending_events))
2061                                 break;
2062
2063                         state = STATE_DATA_BUSY;
2064                         break;
2065                 }
2066         } while (state != prev_state);
2067
2068         host->state = state;
2069 unlock:
2070         spin_unlock(&host->lock);
2071
2072 }
2073
2074 /* push final bytes to part_buf, only use during push */
2075 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2076 {
2077         memcpy((void *)&host->part_buf, buf, cnt);
2078         host->part_buf_count = cnt;
2079 }
2080
2081 /* append bytes to part_buf, only use during push */
2082 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2083 {
2084         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2085         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2086         host->part_buf_count += cnt;
2087         return cnt;
2088 }
2089
2090 /* pull first bytes from part_buf, only use during pull */
2091 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2092 {
2093         cnt = min(cnt, (int)host->part_buf_count);
2094         if (cnt) {
2095                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2096                        cnt);
2097                 host->part_buf_count -= cnt;
2098                 host->part_buf_start += cnt;
2099         }
2100         return cnt;
2101 }
2102
2103 /* pull final bytes from the part_buf, assuming it's just been filled */
2104 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2105 {
2106         memcpy(buf, &host->part_buf, cnt);
2107         host->part_buf_start = cnt;
2108         host->part_buf_count = (1 << host->data_shift) - cnt;
2109 }
2110
2111 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2112 {
2113         struct mmc_data *data = host->data;
2114         int init_cnt = cnt;
2115
2116         /* try and push anything in the part_buf */
2117         if (unlikely(host->part_buf_count)) {
2118                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2119                 buf += len;
2120                 cnt -= len;
2121                 if (host->part_buf_count == 2) {
2122                         mci_writew(host, DATA(host->data_offset),
2123                                         host->part_buf16);
2124                         host->part_buf_count = 0;
2125                 }
2126         }
2127 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2128         if (unlikely((unsigned long)buf & 0x1)) {
2129                 while (cnt >= 2) {
2130                         u16 aligned_buf[64];
2131                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2132                         int items = len >> 1;
2133                         int i;
2134                         /* memcpy from input buffer into aligned buffer */
2135                         memcpy(aligned_buf, buf, len);
2136                         buf += len;
2137                         cnt -= len;
2138                         /* push data from aligned buffer into fifo */
2139                         for (i = 0; i < items; ++i)
2140                                 mci_writew(host, DATA(host->data_offset),
2141                                                 aligned_buf[i]);
2142                 }
2143         } else
2144 #endif
2145         {
2146                 u16 *pdata = buf;
2147                 for (; cnt >= 2; cnt -= 2)
2148                         mci_writew(host, DATA(host->data_offset), *pdata++);
2149                 buf = pdata;
2150         }
2151         /* put anything remaining in the part_buf */
2152         if (cnt) {
2153                 dw_mci_set_part_bytes(host, buf, cnt);
2154                  /* Push data if we have reached the expected data length */
2155                 if ((data->bytes_xfered + init_cnt) ==
2156                     (data->blksz * data->blocks))
2157                         mci_writew(host, DATA(host->data_offset),
2158                                    host->part_buf16);
2159         }
2160 }
2161
2162 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2163 {
2164 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2165         if (unlikely((unsigned long)buf & 0x1)) {
2166                 while (cnt >= 2) {
2167                         /* pull data from fifo into aligned buffer */
2168                         u16 aligned_buf[64];
2169                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2170                         int items = len >> 1;
2171                         int i;
2172                         for (i = 0; i < items; ++i)
2173                                 aligned_buf[i] = mci_readw(host,
2174                                                 DATA(host->data_offset));
2175                         /* memcpy from aligned buffer into output buffer */
2176                         memcpy(buf, aligned_buf, len);
2177                         buf += len;
2178                         cnt -= len;
2179                 }
2180         } else
2181 #endif
2182         {
2183                 u16 *pdata = buf;
2184                 for (; cnt >= 2; cnt -= 2)
2185                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2186                 buf = pdata;
2187         }
2188         if (cnt) {
2189                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2190                 dw_mci_pull_final_bytes(host, buf, cnt);
2191         }
2192 }
2193
2194 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2195 {
2196         struct mmc_data *data = host->data;
2197         int init_cnt = cnt;
2198
2199         /* try and push anything in the part_buf */
2200         if (unlikely(host->part_buf_count)) {
2201                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2202                 buf += len;
2203                 cnt -= len;
2204                 if (host->part_buf_count == 4) {
2205                         mci_writel(host, DATA(host->data_offset),
2206                                         host->part_buf32);
2207                         host->part_buf_count = 0;
2208                 }
2209         }
2210 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2211         if (unlikely((unsigned long)buf & 0x3)) {
2212                 while (cnt >= 4) {
2213                         u32 aligned_buf[32];
2214                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2215                         int items = len >> 2;
2216                         int i;
2217                         /* memcpy from input buffer into aligned buffer */
2218                         memcpy(aligned_buf, buf, len);
2219                         buf += len;
2220                         cnt -= len;
2221                         /* push data from aligned buffer into fifo */
2222                         for (i = 0; i < items; ++i)
2223                                 mci_writel(host, DATA(host->data_offset),
2224                                                 aligned_buf[i]);
2225                 }
2226         } else
2227 #endif
2228         {
2229                 u32 *pdata = buf;
2230                 for (; cnt >= 4; cnt -= 4)
2231                         mci_writel(host, DATA(host->data_offset), *pdata++);
2232                 buf = pdata;
2233         }
2234         /* put anything remaining in the part_buf */
2235         if (cnt) {
2236                 dw_mci_set_part_bytes(host, buf, cnt);
2237                  /* Push data if we have reached the expected data length */
2238                 if ((data->bytes_xfered + init_cnt) ==
2239                     (data->blksz * data->blocks))
2240                         mci_writel(host, DATA(host->data_offset),
2241                                    host->part_buf32);
2242         }
2243 }
2244
2245 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2246 {
2247 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2248         if (unlikely((unsigned long)buf & 0x3)) {
2249                 while (cnt >= 4) {
2250                         /* pull data from fifo into aligned buffer */
2251                         u32 aligned_buf[32];
2252                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2253                         int items = len >> 2;
2254                         int i;
2255                         for (i = 0; i < items; ++i)
2256                                 aligned_buf[i] = mci_readl(host,
2257                                                 DATA(host->data_offset));
2258                         /* memcpy from aligned buffer into output buffer */
2259                         memcpy(buf, aligned_buf, len);
2260                         buf += len;
2261                         cnt -= len;
2262                 }
2263         } else
2264 #endif
2265         {
2266                 u32 *pdata = buf;
2267                 for (; cnt >= 4; cnt -= 4)
2268                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2269                 buf = pdata;
2270         }
2271         if (cnt) {
2272                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2273                 dw_mci_pull_final_bytes(host, buf, cnt);
2274         }
2275 }
2276
2277 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2278 {
2279         struct mmc_data *data = host->data;
2280         int init_cnt = cnt;
2281
2282         /* try and push anything in the part_buf */
2283         if (unlikely(host->part_buf_count)) {
2284                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2285                 buf += len;
2286                 cnt -= len;
2287
2288                 if (host->part_buf_count == 8) {
2289                         mci_writeq(host, DATA(host->data_offset),
2290                                         host->part_buf);
2291                         host->part_buf_count = 0;
2292                 }
2293         }
2294 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2295         if (unlikely((unsigned long)buf & 0x7)) {
2296                 while (cnt >= 8) {
2297                         u64 aligned_buf[16];
2298                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2299                         int items = len >> 3;
2300                         int i;
2301                         /* memcpy from input buffer into aligned buffer */
2302                         memcpy(aligned_buf, buf, len);
2303                         buf += len;
2304                         cnt -= len;
2305                         /* push data from aligned buffer into fifo */
2306                         for (i = 0; i < items; ++i)
2307                                 mci_writeq(host, DATA(host->data_offset),
2308                                                 aligned_buf[i]);
2309                 }
2310         } else
2311 #endif
2312         {
2313                 u64 *pdata = buf;
2314                 for (; cnt >= 8; cnt -= 8)
2315                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2316                 buf = pdata;
2317         }
2318         /* put anything remaining in the part_buf */
2319         if (cnt) {
2320                 dw_mci_set_part_bytes(host, buf, cnt);
2321                 /* Push data if we have reached the expected data length */
2322                 if ((data->bytes_xfered + init_cnt) ==
2323                     (data->blksz * data->blocks))
2324                         mci_writeq(host, DATA(host->data_offset),
2325                                    host->part_buf);
2326         }
2327 }
2328
2329 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2330 {
2331 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2332         if (unlikely((unsigned long)buf & 0x7)) {
2333                 while (cnt >= 8) {
2334                         /* pull data from fifo into aligned buffer */
2335                         u64 aligned_buf[16];
2336                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2337                         int items = len >> 3;
2338                         int i;
2339                         for (i = 0; i < items; ++i)
2340                                 aligned_buf[i] = mci_readq(host,
2341                                                 DATA(host->data_offset));
2342                         /* memcpy from aligned buffer into output buffer */
2343                         memcpy(buf, aligned_buf, len);
2344                         buf += len;
2345                         cnt -= len;
2346                 }
2347         } else
2348 #endif
2349         {
2350                 u64 *pdata = buf;
2351                 for (; cnt >= 8; cnt -= 8)
2352                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2353                 buf = pdata;
2354         }
2355         if (cnt) {
2356                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2357                 dw_mci_pull_final_bytes(host, buf, cnt);
2358         }
2359 }
2360
2361 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2362 {
2363         int len;
2364
2365         /* get remaining partial bytes */
2366         len = dw_mci_pull_part_bytes(host, buf, cnt);
2367         if (unlikely(len == cnt))
2368                 return;
2369         buf += len;
2370         cnt -= len;
2371
2372         /* get the rest of the data */
2373         host->pull_data(host, buf, cnt);
2374 }
2375
2376 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2377 {
2378         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2379         void *buf;
2380         unsigned int offset;
2381         struct mmc_data *data = host->data;
2382         int shift = host->data_shift;
2383         u32 status;
2384         unsigned int len;
2385         unsigned int remain, fcnt;
2386
2387         if(!host->mmc->bus_refs){
2388                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2389                 goto host_put;
2390         }
2391         do {
2392                 if (!sg_miter_next(sg_miter))
2393                         goto done;
2394
2395                 host->sg = sg_miter->piter.sg;
2396                 buf = sg_miter->addr;
2397                 remain = sg_miter->length;
2398                 offset = 0;
2399
2400                 do {
2401                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2402                                         << shift) + host->part_buf_count;
2403                         len = min(remain, fcnt);
2404                         if (!len)
2405                                 break;
2406                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2407                         data->bytes_xfered += len;
2408                         offset += len;
2409                         remain -= len;
2410                 } while (remain);
2411
2412                 sg_miter->consumed = offset;
2413                 status = mci_readl(host, MINTSTS);
2414                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2415         /* if the RXDR is ready read again */
2416         } while ((status & SDMMC_INT_RXDR) ||
2417                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2418
2419         if (!remain) {
2420                 if (!sg_miter_next(sg_miter))
2421                         goto done;
2422                 sg_miter->consumed = 0;
2423         }
2424         sg_miter_stop(sg_miter);
2425         return;
2426
2427 done:
2428         sg_miter_stop(sg_miter);
2429 host_put:
2430         host->sg = NULL;
2431         smp_wmb();
2432         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2433 }
2434
2435 static void dw_mci_write_data_pio(struct dw_mci *host)
2436 {
2437         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2438         void *buf;
2439         unsigned int offset;
2440         struct mmc_data *data = host->data;
2441         int shift = host->data_shift;
2442         u32 status;
2443         unsigned int len;
2444         unsigned int fifo_depth = host->fifo_depth;
2445         unsigned int remain, fcnt;
2446
2447         if(!host->mmc->bus_refs){
2448                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2449                 goto host_put;
2450         }
2451
2452         do {
2453                 if (!sg_miter_next(sg_miter))
2454                         goto done;
2455
2456                 host->sg = sg_miter->piter.sg;
2457                 buf = sg_miter->addr;
2458                 remain = sg_miter->length;
2459                 offset = 0;
2460
2461                 do {
2462                         fcnt = ((fifo_depth -
2463                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2464                                         << shift) - host->part_buf_count;
2465                         len = min(remain, fcnt);
2466                         if (!len)
2467                                 break;
2468                         host->push_data(host, (void *)(buf + offset), len);
2469                         data->bytes_xfered += len;
2470                         offset += len;
2471                         remain -= len;
2472                 } while (remain);
2473
2474                 sg_miter->consumed = offset;
2475                 status = mci_readl(host, MINTSTS);
2476                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2477         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2478
2479         if (!remain) {
2480                 if (!sg_miter_next(sg_miter))
2481                         goto done;
2482                 sg_miter->consumed = 0;
2483         }
2484         sg_miter_stop(sg_miter);
2485         return;
2486
2487 done:
2488         sg_miter_stop(sg_miter);
2489 host_put:
2490         host->sg = NULL;
2491         smp_wmb();
2492         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2493 }
2494
2495 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2496 {
2497         if (!host->cmd_status)
2498             host->cmd_status = status;
2499
2500         smp_wmb();
2501
2502         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2503         tasklet_schedule(&host->tasklet);
2504 }
2505
2506 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2507 {
2508         struct dw_mci *host = dev_id;
2509         u32 pending, sdio_int;
2510         int i;
2511
2512         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2513         //if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
2514         //      printk("%s pending: 0x%08x\n",__func__,pending);
2515         /*
2516                  * DTO fix - version 2.10a and below, and only if internal DMA
2517                  * is configured.
2518                  */
2519                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2520                         if (!pending &&
2521                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2522                                 pending |= SDMMC_INT_DATA_OVER;
2523         }
2524
2525         if (pending) {
2526                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2527                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2528                         host->cmd_status = pending;
2529                         smp_wmb();
2530                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
2531                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
2532
2533                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2534                 }
2535
2536                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2537                         /* if there is an error report DATA_ERROR */
2538                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2539                         host->data_status = pending;
2540                         smp_wmb();
2541                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2542
2543                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
2544                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
2545                         tasklet_schedule(&host->tasklet);
2546                 }
2547
2548                 if (pending & SDMMC_INT_DATA_OVER) {
2549                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2550                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2551                         if (!host->data_status)
2552                                 host->data_status = pending;
2553                         smp_wmb();
2554                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2555                                 if (host->sg != NULL)
2556                                         dw_mci_read_data_pio(host, true);
2557                         }
2558                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2559                         tasklet_schedule(&host->tasklet);
2560                 }
2561
2562                 if (pending & SDMMC_INT_RXDR) {
2563                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2564                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2565                                 dw_mci_read_data_pio(host, false);
2566                 }
2567
2568                 if (pending & SDMMC_INT_TXDR) {
2569                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2570                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2571                                 dw_mci_write_data_pio(host);
2572                 }
2573
2574                 if (pending & SDMMC_INT_VSI) {
2575                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2576                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2577                         dw_mci_cmd_interrupt(host, pending);
2578                 }
2579
2580                 if (pending & SDMMC_INT_CMD_DONE) {
2581                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
2582                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2583                         dw_mci_cmd_interrupt(host, pending);
2584                 }
2585
2586                 if (pending & SDMMC_INT_CD) {
2587                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2588                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
2589                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2590                         queue_work(host->card_workqueue, &host->card_work);
2591                 }
2592
2593                 if (pending & SDMMC_INT_HLE) {
2594                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2595                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
2596
2597                 }
2598
2599                 /* Handle SDIO Interrupts */
2600                 for (i = 0; i < host->num_slots; i++) {
2601                         struct dw_mci_slot *slot = host->slot[i];
2602
2603                         if (host->verid < DW_MMC_240A)
2604                                 sdio_int = SDMMC_INT_SDIO(i);
2605                         else
2606                                 sdio_int = SDMMC_INT_SDIO(i + 8);
2607
2608                         if (pending & sdio_int) {
2609                                 mci_writel(host, RINTSTS, sdio_int);
2610                                 mmc_signal_sdio_irq(slot->mmc);
2611                         }
2612                 }
2613
2614         }
2615
2616 #ifdef CONFIG_MMC_DW_IDMAC
2617         /* Handle DMA interrupts */
2618         pending = mci_readl(host, IDSTS);
2619         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2620                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2621                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2622                 host->dma_ops->complete(host);
2623         }
2624 #endif
2625
2626         return IRQ_HANDLED;
2627 }
2628
2629 static void dw_mci_work_routine_card(struct work_struct *work)
2630 {
2631         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2632         int i;
2633
2634         for (i = 0; i < host->num_slots; i++) {
2635                 struct dw_mci_slot *slot = host->slot[i];
2636                 struct mmc_host *mmc = slot->mmc;
2637                 struct mmc_request *mrq;
2638                 int present;
2639
2640                 present = dw_mci_get_cd(mmc);
2641                 while (present != slot->last_detect_state) {
2642                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
2643                                 present ? "inserted" : "removed");
2644                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
2645                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
2646
2647                         rk_send_wakeup_key();//wake up system
2648                         spin_lock_bh(&host->lock);
2649
2650                         /* Card change detected */
2651                         slot->last_detect_state = present;
2652
2653                         /* Clean up queue if present */
2654                         mrq = slot->mrq;
2655                         if (mrq) {
2656                                 if (mrq == host->mrq) {
2657                                         host->data = NULL;
2658                                         host->cmd = NULL;
2659
2660                                         switch (host->state) {
2661                                         case STATE_IDLE:
2662                                                 break;
2663                                         case STATE_SENDING_CMD:
2664                                                 mrq->cmd->error = -ENOMEDIUM;
2665                                                 if (!mrq->data)
2666                                                         break;
2667                                                 /* fall through */
2668                                         case STATE_SENDING_DATA:
2669                                                 mrq->data->error = -ENOMEDIUM;
2670                                                 dw_mci_stop_dma(host);
2671                                                 break;
2672                                         case STATE_DATA_BUSY:
2673                                         case STATE_DATA_ERROR:
2674                                                 if (mrq->data->error == -EINPROGRESS)
2675                                                         mrq->data->error = -ENOMEDIUM;
2676                                                 if (!mrq->stop)
2677                                                         break;
2678                                                 /* fall through */
2679                                         case STATE_SENDING_STOP:
2680                                                 mrq->stop->error = -ENOMEDIUM;
2681                                                 break;
2682                                         }
2683
2684                                         dw_mci_request_end(host, mrq);
2685                                 } else {
2686                                         list_del(&slot->queue_node);
2687                                         mrq->cmd->error = -ENOMEDIUM;
2688                                         if (mrq->data)
2689                                                 mrq->data->error = -ENOMEDIUM;
2690                                         if (mrq->stop)
2691                                                 mrq->stop->error = -ENOMEDIUM;
2692
2693                     MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",mrq->cmd->opcode, mmc_hostname(mmc));
2694
2695                                         spin_unlock(&host->lock);
2696                                         mmc_request_done(slot->mmc, mrq);
2697                                         spin_lock(&host->lock);
2698                                 }
2699                         }
2700
2701                         /* Power down slot */
2702                         if (present == 0) {
2703                                 /* Clear down the FIFO */
2704                                 dw_mci_fifo_reset(host);
2705 #ifdef CONFIG_MMC_DW_IDMAC
2706                                 dw_mci_idmac_reset(host);
2707 #endif
2708
2709                         }
2710
2711                         spin_unlock_bh(&host->lock);
2712
2713                         present = dw_mci_get_cd(mmc);
2714                 }
2715
2716                 mmc_detect_change(slot->mmc,
2717                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2718         }
2719 }
2720
2721 #ifdef CONFIG_OF
2722 /* given a slot id, find out the device node representing that slot */
2723 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2724 {
2725         struct device_node *np;
2726         const __be32 *addr;
2727         int len;
2728
2729         if (!dev || !dev->of_node)
2730                 return NULL;
2731
2732         for_each_child_of_node(dev->of_node, np) {
2733                 addr = of_get_property(np, "reg", &len);
2734                 if (!addr || (len < sizeof(int)))
2735                         continue;
2736                 if (be32_to_cpup(addr) == slot)
2737                         return np;
2738         }
2739         return NULL;
2740 }
2741
2742 static struct dw_mci_of_slot_quirks {
2743         char *quirk;
2744         int id;
2745 } of_slot_quirks[] = {
2746         {
2747                 .quirk  = "disable-wp",
2748                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2749         },
2750 };
2751
2752 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2753 {
2754         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2755         int quirks = 0;
2756         int idx;
2757
2758         /* get quirks */
2759         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2760                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
2761                         quirks |= of_slot_quirks[idx].id;
2762
2763         return quirks;
2764 }
2765
2766 /* find out bus-width for a given slot */
2767 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
2768 {
2769         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
2770         u32 bus_wd = 1;
2771
2772         if (!np)
2773                 return 1;
2774
2775         if (of_property_read_u32(np, "bus-width", &bus_wd))
2776                 dev_err(dev, "bus-width property not found, assuming width"
2777                                " as 1\n");
2778         return bus_wd;
2779 }
2780
2781
2782 /* find the pwr-en gpio for a given slot; or -1 if none specified */
2783 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
2784 {
2785         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
2786         int gpio;
2787
2788         if (!np)
2789                 return -EINVAL;
2790
2791         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
2792
2793         /* Having a missing entry is valid; return silently */
2794         if (!gpio_is_valid(gpio))
2795                 return -EINVAL;
2796
2797         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
2798                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
2799                 return -EINVAL;
2800         }
2801
2802     gpio_direction_output(gpio, 0);//set 0 to pwr-en
2803
2804         return gpio;
2805 }
2806
2807
2808 /* find the write protect gpio for a given slot; or -1 if none specified */
2809 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
2810 {
2811         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2812         int gpio;
2813
2814         if (!np)
2815                 return -EINVAL;
2816
2817         gpio = of_get_named_gpio(np, "wp-gpios", 0);
2818
2819         /* Having a missing entry is valid; return silently */
2820         if (!gpio_is_valid(gpio))
2821                 return -EINVAL;
2822
2823         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
2824                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
2825                 return -EINVAL;
2826         }
2827
2828         return gpio;
2829 }
2830
2831 /* find the cd gpio for a given slot */
2832 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
2833                                         struct mmc_host *mmc)
2834 {
2835         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
2836         int gpio;
2837
2838         if (!np)
2839                 return;
2840
2841         gpio = of_get_named_gpio(np, "cd-gpios", 0);
2842
2843         /* Having a missing entry is valid; return silently */
2844         if (!gpio_is_valid(gpio))
2845                 return;
2846
2847         if (mmc_gpio_request_cd(mmc, gpio, 0))
2848                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
2849 }
2850 #else /* CONFIG_OF */
2851 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2852 {
2853         return 0;
2854 }
2855 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
2856 {
2857         return 1;
2858 }
2859 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2860 {
2861         return NULL;
2862 }
2863 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
2864 {
2865         return -EINVAL;
2866 }
2867 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
2868                                         struct mmc_host *mmc)
2869 {
2870         return;
2871 }
2872 #endif /* CONFIG_OF */
2873
2874 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2875 {
2876         struct mmc_host *mmc;
2877         struct dw_mci_slot *slot;
2878         const struct dw_mci_drv_data *drv_data = host->drv_data;
2879         int ctrl_id, ret;
2880         u32 freq[2];
2881         u8 bus_width;
2882
2883         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2884         if (!mmc)
2885                 return -ENOMEM;
2886
2887         slot = mmc_priv(mmc);
2888         slot->id = id;
2889         slot->mmc = mmc;
2890         slot->host = host;
2891         host->slot[id] = slot;
2892         host->mmc = mmc;
2893
2894         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2895
2896         mmc->ops = &dw_mci_ops;
2897
2898         if (of_property_read_u32_array(host->dev->of_node,
2899                                        "clock-freq-min-max", freq, 2)) {
2900                 mmc->f_min = DW_MCI_FREQ_MIN;
2901                 mmc->f_max = DW_MCI_FREQ_MAX;
2902
2903         printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__,__FUNCTION__,
2904                 mmc->f_min, mmc->f_max, mmc_hostname(mmc));
2905         } else {
2906                 mmc->f_min = freq[0];
2907                 mmc->f_max = freq[1];
2908
2909         printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__,__FUNCTION__,
2910                 mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
2911         }
2912
2913     if(strstr("mmc0",mmc_hostname(mmc)))
2914         printk("Line%d..%s: The rk_sdmmc %s",__LINE__, __FUNCTION__,RK_SDMMC_DRIVER_VERSION);
2915
2916         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
2917                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
2918         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
2919                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
2920         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
2921                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
2922
2923         if (host->pdata->get_ocr)
2924                 mmc->ocr_avail = host->pdata->get_ocr(id);
2925         else
2926         {
2927                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
2928                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
2929                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
2930                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
2931         }
2932
2933         /*
2934          * Start with slot power disabled, it will be enabled when a card
2935          * is detected.
2936          */
2937         if (host->pdata->setpower)
2938                 host->pdata->setpower(id, 0);
2939
2940         if (host->pdata->caps)
2941                 mmc->caps = host->pdata->caps;
2942
2943         if (host->pdata->pm_caps)
2944                 mmc->pm_caps = host->pdata->pm_caps;
2945
2946         if (host->dev->of_node) {
2947                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2948                 if (ctrl_id < 0)
2949                         ctrl_id = 0;
2950         } else {
2951                 ctrl_id = to_platform_device(host->dev)->id;
2952         }
2953         if (drv_data && drv_data->caps)
2954                 mmc->caps |= drv_data->caps[ctrl_id];
2955         if (drv_data && drv_data->hold_reg_flag)
2956                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
2957
2958         //set the compatibility of driver.
2959     mmc->caps |= MMC_CAP_UHS_SDR12|MMC_CAP_UHS_SDR25|MMC_CAP_UHS_SDR50|MMC_CAP_UHS_SDR104|MMC_CAP_ERASE ;
2960
2961         if (host->pdata->caps2)
2962                 mmc->caps2 = host->pdata->caps2;
2963
2964         if (host->pdata->get_bus_wd)
2965                 bus_width = host->pdata->get_bus_wd(slot->id);
2966         else if (host->dev->of_node)
2967                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
2968         else
2969                 bus_width = 1;
2970
2971         switch (bus_width) {
2972         case 8:
2973                 mmc->caps |= MMC_CAP_8_BIT_DATA;
2974         case 4:
2975                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2976         }
2977         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
2978                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
2979         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
2980                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2981         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
2982                 mmc->caps |= MMC_CAP_HW_RESET;
2983         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
2984                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
2985         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
2986                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
2987     if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
2988         mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
2989         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
2990                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2991
2992     /*Assign pm_caps pass to pm_flags*/
2993         mmc->pm_flags = mmc->pm_caps;
2994
2995         if (host->pdata->blk_settings) {
2996                 mmc->max_segs = host->pdata->blk_settings->max_segs;
2997                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2998                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2999                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3000                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3001         } else {
3002                 /* Useful defaults if platform data is unset. */
3003 #ifdef CONFIG_MMC_DW_IDMAC
3004                 mmc->max_segs = host->ring_size;
3005                 mmc->max_blk_size = 65536;
3006                 mmc->max_blk_count = host->ring_size;
3007                 mmc->max_seg_size = 0x1000;
3008                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3009 #else
3010                 mmc->max_segs = 64;
3011                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3012                 mmc->max_blk_count = 512;
3013                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3014                 mmc->max_seg_size = mmc->max_req_size;
3015 #endif /* CONFIG_MMC_DW_IDMAC */
3016         }
3017     //pwr_en
3018     slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3019
3020     if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))//(gpio_is_valid(slot->pwr_en_gpio))
3021     {
3022         host->vmmc = NULL;
3023     }else{
3024
3025         if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3026         {
3027             host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3028         }
3029         else
3030         {
3031             host->vmmc = NULL;
3032         }
3033
3034         if (IS_ERR(host->vmmc)) {
3035                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3036                 host->vmmc = NULL;
3037         } else {
3038                 ret = regulator_enable(host->vmmc);
3039                 if (ret) {
3040                         dev_err(host->dev,
3041                                 "failed to enable regulator: %d\n", ret);
3042                         goto err_setup_bus;
3043                 }
3044         }
3045     }
3046
3047         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3048
3049     if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3050         clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3051
3052         ret = mmc_add_host(mmc);
3053         if (ret)
3054                 goto err_setup_bus;
3055
3056     /* Pinctrl set default iomux state to fucntion port.
3057      * Fixme: DON'T TOUCH EMMC SETTING!
3058      */
3059      if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3060      {
3061         host->pinctrl = devm_pinctrl_get(host->dev);
3062         if(IS_ERR(host->pinctrl))
3063             printk("%s: Warning : No pinctrl used!\n",mmc_hostname(host->mmc));
3064         else
3065         {
3066             host->pins_idle= pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_IDLE);
3067             if(IS_ERR(host->pins_default))
3068                 printk("%s: Warning : No IDLE pinctrl matched!\n", mmc_hostname(host->mmc));
3069             else
3070             {
3071                 if(pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3072                     printk("%s: Warning :  Idle pinctrl setting failed!\n", mmc_hostname(host->mmc));
3073             }
3074
3075             host->pins_default = pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_DEFAULT);
3076             if(IS_ERR(host->pins_default))
3077                 printk("%s: Warning : No default pinctrl matched!\n", mmc_hostname(host->mmc));
3078             else
3079             {
3080                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3081                    printk("%s: Warning :  Default pinctrl setting failed!\n", mmc_hostname(host->mmc));
3082             }
3083          }
3084      }
3085
3086
3087 #if defined(CONFIG_DEBUG_FS)
3088         dw_mci_init_debugfs(slot);
3089 #endif
3090
3091         /* Card initially undetected */
3092         slot->last_detect_state = 1;
3093
3094         return 0;
3095
3096 err_setup_bus:
3097         mmc_free_host(mmc);
3098         return -EINVAL;
3099 }
3100
3101 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3102 {
3103         /* Shutdown detect IRQ */
3104         if (slot->host->pdata->exit)
3105                 slot->host->pdata->exit(id);
3106
3107         /* Debugfs stuff is cleaned up by mmc core */
3108         mmc_remove_host(slot->mmc);
3109         slot->host->slot[id] = NULL;
3110         mmc_free_host(slot->mmc);
3111 }
3112
3113 static void dw_mci_init_dma(struct dw_mci *host)
3114 {
3115         /* Alloc memory for sg translation */
3116         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3117                                           &host->sg_dma, GFP_KERNEL);
3118         if (!host->sg_cpu) {
3119                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3120                         __func__);
3121                 goto no_dma;
3122         }
3123
3124         /* Determine which DMA interface to use */
3125 #ifdef CONFIG_MMC_DW_IDMAC
3126         host->dma_ops = &dw_mci_idmac_ops;
3127         dev_info(host->dev, "Using internal DMA controller.\n");
3128 #endif
3129
3130         if (!host->dma_ops)
3131                 goto no_dma;
3132
3133         if (host->dma_ops->init && host->dma_ops->start &&
3134             host->dma_ops->stop && host->dma_ops->cleanup) {
3135                 if (host->dma_ops->init(host)) {
3136                         dev_err(host->dev, "%s: Unable to initialize "
3137                                 "DMA Controller.\n", __func__);
3138                         goto no_dma;
3139                 }
3140         } else {
3141                 dev_err(host->dev, "DMA initialization not found.\n");
3142                 goto no_dma;
3143         }
3144
3145         host->use_dma = 1;
3146         return;
3147
3148 no_dma:
3149         dev_info(host->dev, "Using PIO mode.\n");
3150         host->use_dma = 0;
3151         return;
3152 }
3153
3154 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3155 {
3156         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3157         u32 ctrl;
3158
3159         ctrl = mci_readl(host, CTRL);
3160         ctrl |= reset;
3161         mci_writel(host, CTRL, ctrl);
3162
3163         /* wait till resets clear */
3164         do {
3165                 ctrl = mci_readl(host, CTRL);
3166                 if (!(ctrl & reset))
3167                         return true;
3168         } while (time_before(jiffies, timeout));
3169
3170         dev_err(host->dev,
3171                 "Timeout resetting block (ctrl reset %#x)\n",
3172                 ctrl & reset);
3173
3174         return false;
3175 }
3176
3177 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3178 {
3179         /*
3180          * Reseting generates a block interrupt, hence setting
3181          * the scatter-gather pointer to NULL.
3182          */
3183         if (host->sg) {
3184                 sg_miter_stop(&host->sg_miter);
3185                 host->sg = NULL;
3186         }
3187
3188         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3189 }
3190
3191 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3192 {
3193         return dw_mci_ctrl_reset(host,
3194                                  SDMMC_CTRL_FIFO_RESET |
3195                                  SDMMC_CTRL_RESET |
3196                                  SDMMC_CTRL_DMA_RESET);
3197 }
3198
3199 #ifdef CONFIG_OF
3200 /*
3201 static struct dw_mci_of_quirks {
3202         char *quirk;
3203         int id;
3204 } of_quirks[] = {
3205         {
3206                 .quirk  = "broken-cd",
3207                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3208         },
3209 };
3210 */
3211 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3212 {
3213         struct dw_mci_board *pdata;
3214         struct device *dev = host->dev;
3215         struct device_node *np = dev->of_node;
3216         const struct dw_mci_drv_data *drv_data = host->drv_data;
3217         int  ret;
3218         u32 clock_frequency;
3219
3220         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3221         if (!pdata) {
3222                 dev_err(dev, "could not allocate memory for pdata\n");
3223                 return ERR_PTR(-ENOMEM);
3224         }
3225
3226         /* find out number of slots supported */
3227         if (of_property_read_u32(dev->of_node, "num-slots",
3228                                 &pdata->num_slots)) {
3229                 dev_info(dev, "num-slots property not found, "
3230                                 "assuming 1 slot is available\n");
3231                 pdata->num_slots = 1;
3232         }
3233 #if 0
3234         /* get quirks */
3235         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3236                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3237                         pdata->quirks |= of_quirks[idx].id;
3238 #endif
3239
3240         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3241                 dev_info(dev, "fifo-depth property not found, using "
3242                                 "value of FIFOTH register as default\n");
3243
3244         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3245
3246         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3247                 pdata->bus_hz = clock_frequency;
3248
3249         if (drv_data && drv_data->parse_dt) {
3250                 ret = drv_data->parse_dt(host);
3251                 if (ret)
3252                         return ERR_PTR(ret);
3253         }
3254
3255         if (of_find_property(np, "keep-power-in-suspend", NULL))
3256                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3257
3258         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3259                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3260
3261         if (of_find_property(np, "supports-highspeed", NULL))
3262                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3263
3264     if (of_find_property(np, "supports-UHS_SDR104", NULL))
3265                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3266
3267     if (of_find_property(np, "supports-DDR_MODE", NULL))
3268                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3269
3270     if (of_find_property(np, "caps2-mmc-hs200", NULL))
3271                 pdata->caps2 |= MMC_CAP2_HS200;
3272
3273         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3274                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3275
3276         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3277                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3278
3279         if (of_get_property(np, "cd-inverted", NULL))
3280                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3281         if (of_get_property(np, "bootpart-no-access", NULL))
3282                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3283
3284         return pdata;
3285 }
3286
3287 #else /* CONFIG_OF */
3288 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3289 {
3290         return ERR_PTR(-EINVAL);
3291 }
3292 #endif /* CONFIG_OF */
3293
3294 int dw_mci_probe(struct dw_mci *host)
3295 {
3296         const struct dw_mci_drv_data *drv_data = host->drv_data;
3297         int width, i, ret = 0;
3298         u32 fifo_size;
3299         int init_slots = 0;
3300         u32 regs;
3301
3302         if (!host->pdata) {
3303                 host->pdata = dw_mci_parse_dt(host);
3304                 if (IS_ERR(host->pdata)) {
3305                         dev_err(host->dev, "platform data not available\n");
3306                         return -EINVAL;
3307                 }
3308         }
3309
3310         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3311                 dev_err(host->dev,
3312                         "Platform data must supply select_slot function\n");
3313                 return -ENODEV;
3314         }
3315
3316         /*
3317          * In 2.40a spec, Data offset is changed.
3318          * Need to check the version-id and set data-offset for DATA register.
3319          */
3320         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3321         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3322
3323         if (host->verid < DW_MMC_240A)
3324                 host->data_offset = DATA_OFFSET;
3325         else
3326                 host->data_offset = DATA_240A_OFFSET;
3327
3328         //hclk enable
3329         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3330         if (IS_ERR(host->hclk_mmc)) {
3331                 dev_err(host->dev, "failed to get hclk_mmc\n");
3332                 ret = PTR_ERR(host->hclk_mmc);
3333                 goto err_hclk_mmc;
3334         }
3335
3336         clk_prepare_enable(host->hclk_mmc);
3337
3338         //mmc clk enable
3339         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3340         if (IS_ERR(host->clk_mmc)) {
3341                 dev_err(host->dev, "failed to get clk mmc_per\n");
3342                 ret = PTR_ERR(host->clk_mmc);
3343                 goto err_clk_mmc;
3344         }
3345
3346         host->bus_hz = host->pdata->bus_hz;
3347         if (!host->bus_hz) {
3348                 dev_err(host->dev,"Platform data must supply bus speed\n");
3349                 ret = -ENODEV;
3350                 goto err_clk_mmc;
3351         }
3352
3353         if (host->verid < DW_MMC_240A)
3354                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
3355         else
3356                 //rockchip: fix divider 2 in clksum before controlller
3357                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
3358
3359         if(ret < 0) {
3360             dev_err(host->dev, "failed to set clk mmc\n");
3361             goto err_clk_mmc;
3362         }
3363         clk_prepare_enable(host->clk_mmc);
3364
3365         if (drv_data && drv_data->setup_clock) {
3366         ret = drv_data->setup_clock(host);
3367         if (ret) {
3368             dev_err(host->dev,
3369                 "implementation specific clock setup failed\n");
3370             goto err_clk_mmc;
3371         }
3372     }
3373
3374         host->quirks = host->pdata->quirks;
3375         host->irq_state = true;
3376         host->set_speed = 0;
3377         host->set_div = 0;
3378
3379         spin_lock_init(&host->lock);
3380         INIT_LIST_HEAD(&host->queue);
3381
3382         /*
3383          * Get the host data width - this assumes that HCON has been set with
3384          * the correct values.
3385          */
3386         i = (mci_readl(host, HCON) >> 7) & 0x7;
3387         if (!i) {
3388                 host->push_data = dw_mci_push_data16;
3389                 host->pull_data = dw_mci_pull_data16;
3390                 width = 16;
3391                 host->data_shift = 1;
3392         } else if (i == 2) {
3393                 host->push_data = dw_mci_push_data64;
3394                 host->pull_data = dw_mci_pull_data64;
3395                 width = 64;
3396                 host->data_shift = 3;
3397         } else {
3398                 /* Check for a reserved value, and warn if it is */
3399                 WARN((i != 1),
3400                      "HCON reports a reserved host data width!\n"
3401                      "Defaulting to 32-bit access.\n");
3402                 host->push_data = dw_mci_push_data32;
3403                 host->pull_data = dw_mci_pull_data32;
3404                 width = 32;
3405                 host->data_shift = 2;
3406         }
3407
3408         /* Reset all blocks */
3409         if (!dw_mci_ctrl_all_reset(host))
3410                 return -ENODEV;
3411
3412         host->dma_ops = host->pdata->dma_ops;
3413         dw_mci_init_dma(host);
3414
3415         /* Clear the interrupts for the host controller */
3416         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3417         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3418
3419         /* Put in max timeout */
3420         mci_writel(host, TMOUT, 0xFFFFFFFF);
3421
3422         /*
3423          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3424          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3425          */
3426         if (!host->pdata->fifo_depth) {
3427                 /*
3428                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3429                  * have been overwritten by the bootloader, just like we're
3430                  * about to do, so if you know the value for your hardware, you
3431                  * should put it in the platform data.
3432                  */
3433                 fifo_size = mci_readl(host, FIFOTH);
3434                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3435         } else {
3436                 fifo_size = host->pdata->fifo_depth;
3437         }
3438         host->fifo_depth = fifo_size;
3439         host->fifoth_val =
3440                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3441         mci_writel(host, FIFOTH, host->fifoth_val);
3442
3443         /* disable clock to CIU */
3444         mci_writel(host, CLKENA, 0);
3445         mci_writel(host, CLKSRC, 0);
3446
3447         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3448         host->card_workqueue = alloc_workqueue("dw-mci-card",
3449                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
3450         if (!host->card_workqueue) {
3451                 ret = -ENOMEM;
3452                 goto err_dmaunmap;
3453         }
3454         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
3455         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3456                                host->irq_flags, "dw-mci", host);
3457         if (ret)
3458                 goto err_workqueue;
3459
3460         if (host->pdata->num_slots)
3461                 host->num_slots = host->pdata->num_slots;
3462         else
3463                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
3464
3465         /* We need at least one slot to succeed */
3466         for (i = 0; i < host->num_slots; i++) {
3467                 ret = dw_mci_init_slot(host, i);
3468                 if (ret)
3469                         dev_dbg(host->dev, "slot %d init failed\n", i);
3470                 else
3471                         init_slots++;
3472         }
3473
3474         /*
3475          * Enable interrupts for command done, data over, data empty, card det,
3476          * receive ready and error such as transmit, receive timeout, crc error
3477          */
3478         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3479         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
3480                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
3481         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3482             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3483             regs |= SDMMC_INT_CD;
3484
3485         mci_writel(host, INTMASK, regs);
3486
3487         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
3488
3489         dev_info(host->dev, "DW MMC controller at irq %d, "
3490                  "%d bit host data width, "
3491                  "%u deep fifo\n",
3492                  host->irq, width, fifo_size);
3493
3494         if (init_slots) {
3495                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3496         } else {
3497                 dev_dbg(host->dev, "attempted to initialize %d slots, "
3498                                         "but failed on all\n", host->num_slots);
3499                 goto err_workqueue;
3500         }
3501
3502
3503         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3504                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3505
3506         return 0;
3507
3508 err_workqueue:
3509         destroy_workqueue(host->card_workqueue);
3510
3511 err_dmaunmap:
3512         if (host->use_dma && host->dma_ops->exit)
3513                 host->dma_ops->exit(host);
3514
3515         if (host->vmmc){
3516                 regulator_disable(host->vmmc);
3517                 regulator_put(host->vmmc);
3518         }
3519
3520 err_clk_mmc:
3521     if (!IS_ERR(host->clk_mmc))
3522                 clk_disable_unprepare(host->clk_mmc);
3523 err_hclk_mmc:
3524     if (!IS_ERR(host->hclk_mmc))
3525                 clk_disable_unprepare(host->hclk_mmc);
3526
3527         return ret;
3528 }
3529 EXPORT_SYMBOL(dw_mci_probe);
3530
3531 void dw_mci_remove(struct dw_mci *host)
3532 {
3533         int i;
3534
3535         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3536         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3537
3538         for (i = 0; i < host->num_slots; i++) {
3539                 dev_dbg(host->dev, "remove slot %d\n", i);
3540                 if (host->slot[i])
3541                         dw_mci_cleanup_slot(host->slot[i], i);
3542         }
3543
3544         /* disable clock to CIU */
3545         mci_writel(host, CLKENA, 0);
3546         mci_writel(host, CLKSRC, 0);
3547
3548         destroy_workqueue(host->card_workqueue);
3549
3550         if (host->use_dma && host->dma_ops->exit)
3551                 host->dma_ops->exit(host);
3552
3553         if (host->vmmc){
3554                 regulator_disable(host->vmmc);
3555                 regulator_put(host->vmmc);
3556         }
3557
3558     if (!IS_ERR(host->clk_mmc))
3559                 clk_disable_unprepare(host->clk_mmc);
3560
3561     if (!IS_ERR(host->hclk_mmc))
3562                 clk_disable_unprepare(host->hclk_mmc);
3563 }
3564 EXPORT_SYMBOL(dw_mci_remove);
3565
3566
3567
3568 #ifdef CONFIG_PM_SLEEP
3569 /*
3570  * TODO: we should probably disable the clock to the card in the suspend path.
3571  */
3572 int dw_mci_suspend(struct dw_mci *host)
3573 {
3574
3575         if (host->vmmc)
3576                 regulator_disable(host->vmmc);
3577
3578         /*only for sdmmc controller*/
3579         if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3580                 host->mmc->rescan_disable = 1;
3581                 if (cancel_delayed_work_sync(&host->mmc->detect)){
3582                         wake_unlock(&host->mmc->detect_wake_lock);
3583                 }
3584                 disable_irq(host->irq);
3585                 if(pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3586                         printk("%s: Warning :  Idle pinctrl setting failed!\n", mmc_hostname(host->mmc));
3587                 dw_mci_of_get_cd_gpio(host->dev,0,host->mmc);
3588                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3589                 mci_writel(host, INTMASK, 0x00);
3590                 mci_writel(host, CTRL, 0x00);
3591                 enable_irq_wake(host->mmc->slot.cd_irq);
3592     }
3593         return 0;
3594 }
3595 EXPORT_SYMBOL(dw_mci_suspend);
3596
3597 int dw_mci_resume(struct dw_mci *host)
3598 {
3599         int i, ret, retry_cnt = 0;
3600         u32 regs;
3601         struct dw_mci_slot *slot;
3602
3603         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO){
3604                 slot = mmc_priv(host->mmc);
3605
3606                 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
3607                         return 0;
3608         }
3609         /*only for sdmmc controller*/
3610         if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3611                 disable_irq_wake(host->mmc->slot.cd_irq);
3612                 mmc_gpio_free_cd(host->mmc);
3613                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3614                         printk("%s: Warning :  Default pinctrl setting failed!\n", mmc_hostname(host->mmc));
3615                 host->mmc->rescan_disable = 0;
3616                 if(cpu_is_rk3288()) {
3617                         grf_writel(((1<<12)<<16)|(0<<12), RK3288_GRF_SOC_CON0);//disable jtag
3618                 }
3619         }
3620         if (host->vmmc) {
3621                 ret = regulator_enable(host->vmmc);
3622                 if (ret) {
3623                         dev_err(host->dev,
3624                                 "failed to enable regulator: %d\n", ret);
3625                         return ret;
3626                 }
3627         }
3628
3629         if (!dw_mci_ctrl_all_reset(host)) {
3630                 ret = -ENODEV;
3631                 return ret;
3632         }
3633
3634         if (host->use_dma && host->dma_ops->init)
3635                 host->dma_ops->init(host);
3636
3637         /*
3638          * Restore the initial value at FIFOTH register
3639          * And Invalidate the prev_blksz with zero
3640          */
3641         mci_writel(host, FIFOTH, host->fifoth_val);
3642         host->prev_blksz = 0;
3643         /* Put in max timeout */
3644         mci_writel(host, TMOUT, 0xFFFFFFFF);
3645
3646         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3647         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
3648                    DW_MCI_ERROR_FLAGS;
3649         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
3650             regs |= SDMMC_INT_CD;
3651         mci_writel(host, INTMASK, regs);
3652         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3653         /*only for sdmmc controller*/
3654         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)&& (!retry_cnt)) {
3655                 enable_irq(host->irq);
3656         }
3657
3658
3659         for (i = 0; i < host->num_slots; i++) {
3660                 struct dw_mci_slot *slot = host->slot[i];
3661                 if (!slot)
3662                         continue;
3663                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3664                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3665                         dw_mci_setup_bus(slot, true);
3666                 }
3667         }
3668
3669         return 0;
3670 }
3671 EXPORT_SYMBOL(dw_mci_resume);
3672 #endif /* CONFIG_PM_SLEEP */
3673
3674 static int __init dw_mci_init(void)
3675 {
3676         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3677         return 0;
3678 }
3679
3680 static void __exit dw_mci_exit(void)
3681 {
3682 }
3683
3684 module_init(dw_mci_init);
3685 module_exit(dw_mci_exit);
3686
3687 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3688
3689 MODULE_AUTHOR("NXP Semiconductor VietNam");
3690 MODULE_AUTHOR("Imagination Technologies Ltd");
3691 MODULE_AUTHOR("Rockchip Electronics£¬Bangwang Xie < xbw@rock-chips.com> ");
3692
3693 MODULE_LICENSE("GPL v2");