drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  * Copyright (C) 2014 - 2015 Fuzhou Rockchip Electronics Co.Ltd.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/blkdev.h>
  16 #include <linux/clk.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/module.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/suspend.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/card.h>
  37 #include <linux/mmc/sdio.h>
  38 #include <linux/mmc/rk_mmc.h>
  39 #include <linux/bitops.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/of.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/mmc/slot-gpio.h>
  45 #include <linux/clk-private.h>
  46 #include <linux/rockchip/cpu.h>
  47 #include <linux/rfkill-wlan.h>
  48 #include <linux/mfd/syscon.h>
  49 #include <linux/regmap.h>
  50 #include <linux/log2.h>
  51 #include <asm-generic/dma-mapping-common.h>
  52 #include "rk_sdmmc.h"
  53 #include "rk_sdmmc_dbg.h"
  54 #include <linux/regulator/rockchip_io_vol_domain.h>
  55 #include "../../clk/rockchip/clk-ops.h"
  56
  57 #define RK_SDMMC_DRIVER_VERSION "Ver 2.00 2015-06-10"
  58
  59 /* Common flag combinations */
  60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  61                                  SDMMC_INT_SBE  | \
  62                                  SDMMC_INT_EBE)
  63 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  64                                  SDMMC_INT_RESP_ERR)
  65 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  66                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  67 #define DW_MCI_SEND_STATUS      1
  68 #define DW_MCI_RECV_STATUS      2
  69 #define DW_MCI_DMA_THRESHOLD    16
  70 #define DW_MCI_FREQ_MAX         50000000        /* unit: HZ */
  71 #define DW_MCI_FREQ_MIN         300000          /* unit: HZ */
  72
  73 /* Max is 250ms showed in Spec */
  74 #define SDMMC_DATA_TIMEOUT_SD   500
  75 #define SDMMC_DATA_TIMEOUT_SDIO 250
  76 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  77 #define SDMMC_CMD_RTO_MAX_HOLD  200
  78 #define SDMMC_WAIT_FOR_UNBUSY   2500
  79
  80 #define DW_REGS_SIZE    (0x0098 + 4)
  81 #define DW_REGS_NUM     (0x0098 / 4)
  82
  83 #ifdef CONFIG_MMC_DW_IDMAC
  84 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  85                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  86                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  87                                  SDMMC_IDMAC_INT_TI)
  88
  89 struct idmac_desc {
  90         u32             des0;   /* Control Descriptor */
  91 #define IDMAC_DES0_DIC  BIT(1)
  92 #define IDMAC_DES0_LD   BIT(2)
  93 #define IDMAC_DES0_FD   BIT(3)
  94 #define IDMAC_DES0_CH   BIT(4)
  95 #define IDMAC_DES0_ER   BIT(5)
  96 #define IDMAC_DES0_CES  BIT(30)
  97 #define IDMAC_DES0_OWN  BIT(31)
  98
  99         u32             des1;   /* Buffer sizes */
 100 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 101         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 102
 103         u32             des2;   /* buffer 1 physical address */
 104
 105         u32             des3;   /* buffer 2 physical address */
 106 };
 107 #endif /* CONFIG_MMC_DW_IDMAC */
 108
 109
 110 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 111 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 112 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 113 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 114 extern void rk_send_wakeup_key(void);
 115
 116 #if defined(CONFIG_DEBUG_FS)
 117 static int dw_mci_req_show(struct seq_file *s, void *v)
 118 {
 119         struct dw_mci_slot *slot = s->private;
 120         struct mmc_request *mrq;
 121         struct mmc_command *cmd;
 122         struct mmc_command *stop;
 123         struct mmc_data *data;
 124
 125         /* Make sure we get a consistent snapshot */
 126         spin_lock_bh(&slot->host->lock);
 127         mrq = slot->mrq;
 128
 129         if (mrq) {
 130                 cmd = mrq->cmd;
 131                 data = mrq->data;
 132                 stop = mrq->stop;
 133
 134                 if (cmd)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    cmd->opcode, cmd->arg, cmd->flags,
 138                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 139                                    cmd->resp[2], cmd->error);
 140                 if (data)
 141                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 142                                    data->bytes_xfered, data->blocks,
 143                                    data->blksz, data->flags, data->error);
 144                 if (stop)
 145                         seq_printf(s,
 146                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 147                                    stop->opcode, stop->arg, stop->flags,
 148                                    stop->resp[0], stop->resp[1], stop->resp[2],
 149                                    stop->resp[2], stop->error);
 150         }
 151
 152         spin_unlock_bh(&slot->host->lock);
 153
 154         return 0;
 155 }
 156
 157 static int dw_mci_req_open(struct inode *inode, struct file *file)
 158 {
 159         return single_open(file, dw_mci_req_show, inode->i_private);
 160 }
 161
 162 static const struct file_operations dw_mci_req_fops = {
 163         .owner          = THIS_MODULE,
 164         .open           = dw_mci_req_open,
 165         .read           = seq_read,
 166         .llseek         = seq_lseek,
 167         .release        = single_release,
 168 };
 169
 170 static int dw_mci_regs_show(struct seq_file *s, void *v)
 171 {
 172         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 173         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 174         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 175         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 176         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 177         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 178
 179         return 0;
 180 }
 181
 182 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 183 {
 184         return single_open(file, dw_mci_regs_show, inode->i_private);
 185 }
 186
 187 static const struct file_operations dw_mci_regs_fops = {
 188         .owner          = THIS_MODULE,
 189         .open           = dw_mci_regs_open,
 190         .read           = seq_read,
 191         .llseek         = seq_lseek,
 192         .release        = single_release,
 193 };
 194
 195 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 196 {
 197         struct mmc_host *mmc = slot->mmc;
 198         struct dw_mci *host = slot->host;
 199         struct dentry *root;
 200         struct dentry *node;
 201
 202         root = mmc->debugfs_root;
 203         if (!root)
 204                 return;
 205
 206         node = debugfs_create_file("regs", S_IRUSR, root, host,
 207                                    &dw_mci_regs_fops);
 208         if (!node)
 209                 goto err;
 210
 211         node = debugfs_create_file("req", S_IRUSR, root, slot,
 212                                    &dw_mci_req_fops);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 217         if (!node)
 218                 goto err;
 219
 220         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 221                                   (u32 *)&host->pending_events);
 222         if (!node)
 223                 goto err;
 224
 225         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 226                                   (u32 *)&host->completed_events);
 227         if (!node)
 228                 goto err;
 229
 230         return;
 231
 232 err:
 233         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 234 }
 235 #endif /* defined(CONFIG_DEBUG_FS) */
 236
 237 static void dw_mci_set_timeout(struct dw_mci *host)
 238 {
 239         /* timeout (maximum) */
 240         mci_writel(host, TMOUT, 0xffffffff);
 241 }
 242
 243 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 244 {
 245         struct mmc_data *data;
 246         struct dw_mci_slot *slot = mmc_priv(mmc);
 247         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 248         u32 cmdr;
 249         cmd->error = -EINPROGRESS;
 250
 251         cmdr = cmd->opcode;
 252
 253         if (cmdr == MMC_STOP_TRANSMISSION)
 254                 cmdr |= SDMMC_CMD_STOP;
 255         else
 256                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 257
 258         if (cmd->flags & MMC_RSP_PRESENT) {
 259                 /* We expect a response, so set this bit */
 260                 cmdr |= SDMMC_CMD_RESP_EXP;
 261                 if (cmd->flags & MMC_RSP_136)
 262                         cmdr |= SDMMC_CMD_RESP_LONG;
 263         }
 264
 265         if (cmd->flags & MMC_RSP_CRC)
 266                 cmdr |= SDMMC_CMD_RESP_CRC;
 267
 268         data = cmd->data;
 269         if (data) {
 270                 cmdr |= SDMMC_CMD_DAT_EXP;
 271                 if (data->flags & MMC_DATA_STREAM)
 272                         cmdr |= SDMMC_CMD_STRM_MODE;
 273                 if (data->flags & MMC_DATA_WRITE)
 274                         cmdr |= SDMMC_CMD_DAT_WR;
 275         }
 276
 277         if (drv_data && drv_data->prepare_command)
 278                 drv_data->prepare_command(slot->host, &cmdr);
 279
 280         return cmdr;
 281 }
 282
 283 static void dw_mci_start_command(struct dw_mci *host,
 284                                  struct mmc_command *cmd, u32 cmd_flags)
 285 {
 286         struct dw_mci_slot *slot = host->slot[0];
 287
 288         host->pre_cmd = host->cmd;
 289         host->cmd = cmd;
 290         dev_vdbg(host->dev,
 291                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 292                 cmd->arg, cmd_flags);
 293
 294         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 295                 /*confirm non-low-power mode*/
 296                 mci_writel(host, CMDARG, 0);
 297                 dw_mci_disable_low_power(slot);
 298
 299                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 300                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 301
 302                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 303         }
 304
 305         mci_writel(host, CMDARG, cmd->arg);
 306         wmb();
 307
 308         /* Fix the value to 1 in current soc */
 309         if(host->mmc->hold_reg_flag)
 310                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 311
 312         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 313         wmb();
 314 }
 315
 316 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 317 {
 318         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 319 }
 320
 321 /* DMA interface functions */
 322 static void dw_mci_stop_dma(struct dw_mci *host)
 323 {
 324         if (host->using_dma) {
 325                 /* Fixme: No need to terminate edma, may cause flush op */
 326                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 327                         host->dma_ops->stop(host);
 328                 host->dma_ops->cleanup(host);
 329         }
 330
 331         /* Data transfer was stopped by the interrupt handler */
 332         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 333 }
 334
 335 static int dw_mci_get_dma_dir(struct mmc_data *data)
 336 {
 337         if (data->flags & MMC_DATA_WRITE)
 338                 return DMA_TO_DEVICE;
 339         else
 340                 return DMA_FROM_DEVICE;
 341 }
 342
 343 #ifdef CONFIG_MMC_DW_IDMAC
 344 static void dw_mci_dma_cleanup(struct dw_mci *host)
 345 {
 346         struct mmc_data *data = host->data;
 347
 348         if (data)
 349                 if (!data->host_cookie)
 350                         dma_unmap_sg(host->dev,
 351                                      data->sg,
 352                                      data->sg_len,
 353                                      dw_mci_get_dma_dir(data));
 354 }
 355
 356 static void dw_mci_idmac_reset(struct dw_mci *host)
 357 {
 358         u32 bmod = mci_readl(host, BMOD);
 359         /* Software reset of DMA */
 360         bmod |= SDMMC_IDMAC_SWRESET;
 361         mci_writel(host, BMOD, bmod);
 362 }
 363
 364 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 365 {
 366         u32 temp;
 367
 368         /* Disable and reset the IDMAC interface */
 369         temp = mci_readl(host, CTRL);
 370         temp &= ~SDMMC_CTRL_USE_IDMAC;
 371         temp |= SDMMC_CTRL_DMA_RESET;
 372         mci_writel(host, CTRL, temp);
 373
 374         /* Stop the IDMAC running */
 375         temp = mci_readl(host, BMOD);
 376         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 377         temp |= SDMMC_IDMAC_SWRESET;
 378         mci_writel(host, BMOD, temp);
 379 }
 380
 381 static void dw_mci_idmac_complete_dma(void *arg)
 382 {
 383         struct dw_mci *host = arg;
 384         struct mmc_data *data = host->data;
 385
 386         dev_vdbg(host->dev, "DMA complete\n");
 387
 388         host->dma_ops->cleanup(host);
 389
 390         /*
 391          * If the card was removed, data will be NULL. No point in trying to
 392          * send the stop command or waiting for NBUSY in this case.
 393          */
 394         if(data){
 395                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 396                 tasklet_schedule(&host->tasklet);
 397         }
 398 }
 399
 400 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 401                                     unsigned int sg_len)
 402 {
 403         int i;
 404         struct idmac_desc *desc = host->sg_cpu;
 405
 406         for (i = 0; i < sg_len; i++, desc++) {
 407                 unsigned int length = sg_dma_len(&data->sg[i]);
 408                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 409
 410                 /* Set the OWN bit and disable interrupts for this descriptor */
 411                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 412
 413                 /* Buffer length */
 414                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 415
 416                 /* Physical address to DMA to/from */
 417                 desc->des2 = mem_addr;
 418         }
 419
 420         /* Set first descriptor */
 421         desc = host->sg_cpu;
 422         desc->des0 |= IDMAC_DES0_FD;
 423
 424         /* Set last descriptor */
 425         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 426         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 427         desc->des0 |= IDMAC_DES0_LD;
 428
 429         wmb();
 430 }
 431
 432 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 433 {
 434         u32 temp;
 435
 436         dw_mci_translate_sglist(host, host->data, sg_len);
 437
 438         /* Select IDMAC interface */
 439         temp = mci_readl(host, CTRL);
 440         temp |= SDMMC_CTRL_USE_IDMAC;
 441         mci_writel(host, CTRL, temp);
 442
 443         wmb();
 444
 445         /* Enable the IDMAC */
 446         temp = mci_readl(host, BMOD);
 447         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 448         mci_writel(host, BMOD, temp);
 449
 450         /* Start it running */
 451         mci_writel(host, PLDMND, 1);
 452 }
 453
 454 static int dw_mci_idmac_init(struct dw_mci *host)
 455 {
 456         struct idmac_desc *p;
 457         int i;
 458
 459         /* Number of descriptors in the ring buffer */
 460         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 461
 462         /* Forward link the descriptor list */
 463         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) {
 464                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 465                 p->des1 = 0;
 466         }
 467         /* Set the last descriptor as the end-of-ring descriptor */
 468         p->des3 = host->sg_dma;
 469         p->des0 = IDMAC_DES0_ER;
 470
 471         dw_mci_idmac_reset(host);
 472
 473         /* Mask out interrupts - get Tx & Rx complete only */
 474         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 475         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 476                    SDMMC_IDMAC_INT_TI);
 477
 478         /* Set the descriptor base address */
 479         mci_writel(host, DBADDR, host->sg_dma);
 480         return 0;
 481 }
 482
 483 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 484         .init = dw_mci_idmac_init,
 485         .start = dw_mci_idmac_start_dma,
 486         .stop = dw_mci_idmac_stop_dma,
 487         .complete = dw_mci_idmac_complete_dma,
 488         .cleanup = dw_mci_dma_cleanup,
 489 };
 490
 491
 492 static void dw_mci_edma_cleanup(struct dw_mci *host)
 493 {
 494         struct mmc_data *data = host->data;
 495
 496         if (data)
 497                 if (!data->host_cookie)
 498                         dma_unmap_sg(host->dev,
 499                                         data->sg, data->sg_len,
 500                                         dw_mci_get_dma_dir(data));
 501 }
 502
 503 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 504 {
 505         dmaengine_terminate_all(host->dms->ch);
 506 }
 507
 508 static void dw_mci_edmac_complete_dma(void *arg)
 509 {
 510         struct dw_mci *host = arg;
 511         struct mmc_data *data = host->data;
 512
 513         dev_vdbg(host->dev, "DMA complete\n");
 514
 515         if(data)
 516                 if(data->flags & MMC_DATA_READ)
 517                         /* Invalidate cache after read */
 518                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 519                                 data->sg_len, DMA_FROM_DEVICE);
 520
 521         host->dma_ops->cleanup(host);
 522
 523         /*
 524          * If the card was removed, data will be NULL. No point in trying to
 525          * send the stop command or waiting for NBUSY in this case.
 526          */
 527         if (data) {
 528                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 529                 tasklet_schedule(&host->tasklet);
 530         }
 531 }
 532
 533 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 534 {
 535         struct dma_slave_config slave_config;
 536         struct dma_async_tx_descriptor *desc = NULL;
 537         struct scatterlist *sgl = host->data->sg;
 538         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 539         u32 sg_elems = host->data->sg_len;
 540         u32 fifoth_val, mburst;
 541         u32 burst_limit = 0;
 542         u32 idx, rx_wmark, tx_wmark;
 543         int ret = 0;
 544
 545         /* Set external dma config: burst size, burst width*/
 546         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 547         slave_config.src_addr = slave_config.dst_addr;
 548         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 549         slave_config.src_addr_width = slave_config.dst_addr_width;
 550
 551         /* Match FIFO dma burst MSIZE with external dma config*/
 552         fifoth_val = mci_readl(host, FIFOTH);
 553         mburst = mszs[(fifoth_val >> 28) & 0x7];
 554
 555         /* Edmac limit burst to 16, but work around for rk3036 to 8 */
 556         if (unlikely(cpu_is_rk3036()))
 557                 burst_limit = 8;
 558         else
 559                 burst_limit = 16;
 560
 561         if (mburst > burst_limit) {
 562                 mburst = burst_limit;
 563                 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
 564
 565                 rx_wmark = mszs[idx] - 1;
 566                 tx_wmark = (host->fifo_depth) / 2;
 567                 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
 568
 569                 mci_writel(host, FIFOTH, fifoth_val);
 570         }
 571
 572         slave_config.dst_maxburst = mburst;
 573         slave_config.src_maxburst = slave_config.dst_maxburst;
 574
 575         if(host->data->flags & MMC_DATA_WRITE){
 576                 slave_config.direction = DMA_MEM_TO_DEV;
 577                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 578                 if(ret){
 579                         dev_err(host->dev,
 580                                 "Error in dw_mci edmac write configuration.\n");
 581                         return;
 582                 }
 583
 584                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 585                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 586                 if (!desc) {
 587                         dev_err(host->dev,
 588                                 "Cannot prepare slave write sg the dw_mci edmac!\n");
 589                         return;
 590                 }
 591
 592                 /* Set dw_mci_edmac_complete_dma as callback */
 593                 desc->callback = dw_mci_edmac_complete_dma;
 594                 desc->callback_param = (void *)host;
 595                 dmaengine_submit(desc);
 596
 597                 /* Flush cache before write */
 598                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 599                                 sg_elems, DMA_TO_DEVICE);
 600                 dma_async_issue_pending(host->dms->ch);
 601         } else {
 602                 /* MMC_DATA_READ*/
 603                 slave_config.direction = DMA_DEV_TO_MEM;
 604                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 605                 if (ret) {
 606                         dev_err(host->dev,
 607                                 "Error in dw_mci edmac read configuration.\n");
 608                         return;
 609                 }
 610                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 611                                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 612                 if (!desc) {
 613                         dev_err(host->dev,
 614                                 "Cannot prepare slave read sg for the dw_mci edmac!\n");
 615                         return;
 616                 }
 617                 /* set dw_mci_edmac_complete_dma as callback */
 618                 desc->callback = dw_mci_edmac_complete_dma;
 619                 desc->callback_param = (void *)host;
 620                 dmaengine_submit(desc);
 621                 dma_async_issue_pending(host->dms->ch);
 622         }
 623 }
 624
 625 static int dw_mci_edmac_init(struct dw_mci *host)
 626 {
 627         int ret = 0;
 628
 629         /* Request external dma channel, SHOULD decide chn in dts */
 630         host->dms = NULL;
 631         host->dms = (struct dw_mci_dma_slave *)kzalloc
 632                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 633         if (NULL == host->dms) {
 634                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 635                 return -ENOMEM;
 636         }
 637
 638         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 639         if (!host->dms->ch) {
 640                 dev_err(host->dev,
 641                         "Failed to get external DMA channel %d\n",
 642                         host->dms->ch->chan_id);
 643                 kfree(host->dms);
 644                 host->dms = NULL;
 645                 return -ENXIO;
 646         }
 647
 648         return ret;
 649 }
 650
 651 static void dw_mci_edmac_exit(struct dw_mci *host)
 652 {
 653         if (NULL != host->dms) {
 654                 if (NULL != host->dms->ch) {
 655                         dma_release_channel(host->dms->ch);
 656                         host->dms->ch = NULL;
 657                 }
 658                 kfree(host->dms);
 659                 host->dms = NULL;
 660         }
 661 }
 662
 663 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 664         .init = dw_mci_edmac_init,
 665         .exit = dw_mci_edmac_exit,
 666         .start = dw_mci_edmac_start_dma,
 667         .stop = dw_mci_edmac_stop_dma,
 668         .complete = dw_mci_edmac_complete_dma,
 669         .cleanup = dw_mci_edma_cleanup,
 670 };
 671 #endif /* CONFIG_MMC_DW_IDMAC */
 672
 673 static struct dma_attrs dw_mci_direct_attrs;
 674
 675 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 676                                    struct mmc_data *data,
 677                                    bool next)
 678 {
 679         struct scatterlist *sg;
 680         unsigned int i, sg_len;
 681 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
 682         struct dma_attrs *attrs;
 683 #endif
 684
 685         if (!next && data->host_cookie)
 686                 return data->host_cookie;
 687
 688         /*
 689          * We don't do DMA on "complex" transfers, i.e. with
 690          * non-word-aligned buffers or lengths. Also, we don't bother
 691          * with all the DMA setup overhead for short transfers.
 692          */
 693         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 694                 return -EINVAL;
 695
 696         if (data->blksz & 3)
 697                 return -EINVAL;
 698
 699         for_each_sg(data->sg, sg, data->sg_len, i) {
 700                 if (sg->offset & 3 || sg->length & 3)
 701                         return -EINVAL;
 702         }
 703 #ifdef CONFIG_MMC_DW_SKIP_CACHE_OP
 704         attrs = (data->flags & MMC_DATA_DIRECT) ? &dw_mci_direct_attrs : NULL;
 705         sg_len = dma_map_sg_attrs(host->dev,
 706                                  data->sg,
 707                                  data->sg_len,
 708                                  dw_mci_get_dma_dir(data), attrs);
 709 #else
 710
 711         sg_len = dma_map_sg(host->dev,
 712                             data->sg,
 713                             data->sg_len,
 714                             dw_mci_get_dma_dir(data));
 715 #endif
 716         if (sg_len == 0)
 717                 return -EINVAL;
 718
 719         if (next)
 720                 data->host_cookie = sg_len;
 721
 722         return sg_len;
 723 }
 724
 725 static void dw_mci_pre_req(struct mmc_host *mmc,
 726                            struct mmc_request *mrq,
 727                            bool is_first_req)
 728 {
 729         struct dw_mci_slot *slot = mmc_priv(mmc);
 730         struct mmc_data *data = mrq->data;
 731
 732         if (!slot->host->use_dma || !data)
 733                 return;
 734
 735         if (data->host_cookie) {
 736                 data->host_cookie = 0;
 737                 return;
 738         }
 739
 740         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 741                 data->host_cookie = 0;
 742 }
 743
 744 static void dw_mci_post_req(struct mmc_host *mmc,
 745                             struct mmc_request *mrq,
 746                             int err)
 747 {
 748         struct dw_mci_slot *slot = mmc_priv(mmc);
 749         struct mmc_data *data = mrq->data;
 750
 751         if (!slot->host->use_dma || !data)
 752                 return;
 753
 754         if (data->host_cookie)
 755                 dma_unmap_sg(slot->host->dev,
 756                              data->sg,
 757                              data->sg_len,
 758                              dw_mci_get_dma_dir(data));
 759         data->host_cookie = 0;
 760 }
 761
 762 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 763 {
 764 #ifdef CONFIG_MMC_DW_IDMAC
 765         unsigned int blksz = data->blksz;
 766         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 767         u32 fifo_width = 1 << host->data_shift;
 768         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 769         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 770         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 771
 772         tx_wmark = (host->fifo_depth) / 2;
 773         tx_wmark_invers = host->fifo_depth - tx_wmark;
 774
 775         /*
 776          * MSIZE is '1',
 777          * if blksz is not a multiple of the FIFO width
 778          */
 779         if (blksz % fifo_width) {
 780                 msize = 0;
 781                 rx_wmark = 1;
 782                 goto done;
 783         }
 784
 785         do {
 786                 if (!((blksz_depth % mszs[idx]) ||
 787                      (tx_wmark_invers % mszs[idx]))) {
 788                         msize = idx;
 789                         rx_wmark = mszs[idx] - 1;
 790                         break;
 791                 }
 792         } while (--idx > 0);
 793         /*
 794          * If idx is '0', it won't be tried
 795          * Thus, initial values are uesed
 796          */
 797 done:
 798         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 799         mci_writel(host, FIFOTH, fifoth_val);
 800
 801 #endif
 802 }
 803
 804 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 805 {
 806         unsigned int blksz = data->blksz;
 807         u32 blksz_depth, fifo_depth;
 808         u16 thld_size;
 809
 810         WARN_ON(!(data->flags & MMC_DATA_READ));
 811
 812         if (host->timing != MMC_TIMING_MMC_HS200 &&
 813             host->timing != MMC_TIMING_UHS_SDR104)
 814                 goto disable;
 815
 816         blksz_depth = blksz / (1 << host->data_shift);
 817         fifo_depth = host->fifo_depth;
 818
 819         if (blksz_depth > fifo_depth)
 820                 goto disable;
 821
 822         /*
 823          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 824          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 825          * Currently just choose blksz.
 826          */
 827         thld_size = blksz;
 828         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 829         return;
 830
 831 disable:
 832         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 833 }
 834
 835 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 836 {
 837         int sg_len;
 838         unsigned long flags;
 839         u32 temp;
 840
 841         host->using_dma = 0;
 842
 843         /* If we don't have a channel, we can't do DMA */
 844         if (!host->use_dma)
 845                 return -ENODEV;
 846
 847         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 848         if (sg_len < 0) {
 849                 /* Fixme: No need terminate edma, may cause flush op */
 850                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 851                         host->dma_ops->stop(host);
 852                 return sg_len;
 853         }
 854
 855         host->using_dma = 1;
 856
 857         dev_vdbg(host->dev,
 858                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 859                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 860                  sg_len);
 861
 862         /*
 863          * Decide the MSIZE and RX/TX Watermark.
 864          * If current block size is same with previous size,
 865          * no need to update fifoth.
 866          */
 867         if (host->prev_blksz != data->blksz)
 868                 dw_mci_adjust_fifoth(host, data);
 869
 870         /* Reset DMA FIFO*/
 871         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 872
 873         /* Enable the DMA interface */
 874         temp = mci_readl(host, CTRL);
 875         temp |= SDMMC_CTRL_DMA_ENABLE;
 876         mci_writel(host, CTRL, temp);
 877
 878         /* Disable RX/TX IRQs, let DMA handle it */
 879         spin_lock_irqsave(&host->slock, flags);
 880         temp = mci_readl(host, INTMASK);
 881         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 882         mci_writel(host, INTMASK, temp);
 883         spin_unlock_irqrestore(&host->slock, flags);
 884
 885         host->dma_ops->start(host, sg_len);
 886
 887         return 0;
 888 }
 889
 890 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 891 {
 892         u32 temp;
 893         unsigned long flag;
 894
 895         data->error = -EINPROGRESS;
 896
 897         //WARN_ON(host->data);
 898         host->sg = NULL;
 899         host->data = data;
 900
 901         /* Reset FIFO*/
 902         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 903
 904         if (data->flags & MMC_DATA_READ) {
 905                 host->dir_status = DW_MCI_RECV_STATUS;
 906                 dw_mci_ctrl_rd_thld(host, data);
 907         } else {
 908                 host->dir_status = DW_MCI_SEND_STATUS;
 909         }
 910
 911         MMC_DBG_INFO_FUNC(host->mmc,
 912                         "Dw_mci_submit_data, blocks = %d, blksz = %d [%s]",
 913                         data->blocks, data->blksz, mmc_hostname(host->mmc));
 914
 915         if (dw_mci_submit_data_dma(host, data)) {
 916                 int flags = SG_MITER_ATOMIC;
 917                 if (host->data->flags & MMC_DATA_READ)
 918                         flags |= SG_MITER_TO_SG;
 919                 else
 920                         flags |= SG_MITER_FROM_SG;
 921
 922                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 923                 host->sg = data->sg;
 924                 host->part_buf_start = 0;
 925                 host->part_buf_count = 0;
 926
 927                 spin_lock_irqsave(&host->slock, flag);
 928                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 929                 temp = mci_readl(host, INTMASK);
 930                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 931                 mci_writel(host, INTMASK, temp);
 932                 spin_unlock_irqrestore(&host->slock, flag);
 933
 934                 temp = mci_readl(host, CTRL);
 935                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 936                 mci_writel(host, CTRL, temp);
 937
 938                 /*
 939                  * Use the initial fifoth_val for PIO mode.
 940                  * If next issued data may be transfered by DMA mode,
 941                  * prev_blksz should be invalidated.
 942                  */
 943                 mci_writel(host, FIFOTH, host->fifoth_val);
 944                 host->prev_blksz = 0;
 945         } else {
 946                 /*
 947                  * Keep the current block size.
 948                  * It will be used to decide whether to update
 949                  * fifoth register next time.
 950                  */
 951                 host->prev_blksz = data->blksz;
 952         }
 953 }
 954
 955 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 956 {
 957         struct dw_mci *host = slot->host;
 958         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 959         unsigned int cmd_status = 0;
 960
 961 #ifdef SDMMC_WAIT_FOR_UNBUSY
 962         bool ret = true;
 963         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
 964
 965         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 966                 while (ret) {
 967                         ret =  time_before(jiffies, timeout);
 968                         cmd_status = mci_readl(host, STATUS);
 969                         if (!(cmd_status &
 970                                 (SDMMC_STAUTS_DATA_BUSY |
 971                                 SDMMC_STAUTS_MC_BUSY)))
 972                                 break;
 973                 };
 974
 975                 if(false == ret)
 976                         MMC_DBG_ERR_FUNC(host->mmc,
 977                                 "mci_send_cmd: wait for unbusy timeout! [%s]",
 978                                 mmc_hostname(host->mmc));
 979         }
 980 #endif
 981
 982         mci_writel(host, CMDARG, arg);
 983         wmb();
 984         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 985         if(cmd & SDMMC_CMD_UPD_CLK)
 986                 timeout = jiffies + msecs_to_jiffies(50);
 987         else
 988                 timeout = jiffies + msecs_to_jiffies(500);
 989
 990         while (time_before(jiffies, timeout)) {
 991                 cmd_status = mci_readl(host, CMD);
 992                 if (!(cmd_status & SDMMC_CMD_START))
 993                         return;
 994         }
 995
 996         dev_err(&slot->mmc->class_dev,
 997                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 998                 cmd, arg, cmd_status);
 999 }
1000
1001 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1002 {
1003         struct dw_mci *host = slot->host;
1004         unsigned int tempck,clock = slot->clock;
1005         u32 div;
1006         u32 clk_en_a;
1007         u32 sdio_int;
1008
1009         MMC_DBG_INFO_FUNC(host->mmc,
1010                         "%s: clock=%d, current_speed=%d, bus_hz=%d, forc=%d[%s]\n",
1011                         __FUNCTION__, clock, host->current_speed, host->bus_hz,
1012                         force_clkinit, mmc_hostname(host->mmc));
1013
1014         if (!clock) {
1015                 mci_writel(host, CLKENA, 0);
1016                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1017                 if(host->svi_flags == 0)
1018                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1019                 #else
1020                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1021                 #endif
1022         } else if (clock != host->current_speed || force_clkinit) {
1023                 div = host->bus_hz / clock;
1024                 if (host->bus_hz % clock && host->bus_hz > clock)
1025                         /*
1026                          * move the + 1 after the divide to prevent
1027                          * over-clocking the card.
1028                          */
1029                         div += 1;
1030
1031                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1032
1033                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1034                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1035                         dev_info(&slot->mmc->class_dev,
1036                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1037                                  slot->id, host->bus_hz, clock,
1038                                  tempck, div);
1039
1040                         host->set_speed = tempck;
1041                         host->set_div = div;
1042                 }
1043
1044                 /* disable clock */
1045                 mci_writel(host, CLKENA, 0);
1046                 mci_writel(host, CLKSRC, 0);
1047
1048                 /* inform CIU */
1049                 mci_send_cmd(slot,
1050                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1051
1052                 if(clock <= 400*1000){
1053                         MMC_DBG_BOOT_FUNC(host->mmc,
1054                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1055                                 clock * 2, mmc_hostname(host->mmc));
1056                         /* clk_mmc will change parents to 24MHz xtal*/
1057                         clk_set_rate(host->clk_mmc, clock * 2);
1058
1059                         div = 0;
1060                         host->set_div = div;
1061                 }
1062                 else
1063                 {
1064                         MMC_DBG_BOOT_FUNC(host->mmc,
1065                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1066                                 mmc_hostname(host->mmc));
1067                         if(div > 1)
1068                         {
1069                                 MMC_DBG_ERR_FUNC(host->mmc,
1070                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1071                                         mmc_hostname(host->mmc));
1072                                  div = 1;
1073                                  host->set_div = div;
1074                                  host->bus_hz = host->set_speed * 2;
1075                                  MMC_DBG_BOOT_FUNC(host->mmc,
1076                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1077                                         div, host->bus_hz, mmc_hostname(host->mmc));
1078                         }
1079                         /* BUG may be here, come on,  Linux BSP engineer looks!
1080                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1081                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1082                            some oops happened like that:
1083                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1084                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1085                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1086                            mmc0: new high speed DDR MMC card at address 0001
1087                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1088                            ....
1089                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1090                            mmcblk0: retrying using single block read
1091                            mmcblk0: error -110 sending status command, retrying
1092
1093                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1094                          */
1095                         if ((div == 0) &&
1096                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1097                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1098                                 /*  Fixup DDR MMC */
1099                                 div = 1;
1100                                 host->set_div = div;
1101                                 host->bus_hz = host->set_speed * 2;
1102                                 MMC_DBG_BOOT_FUNC(host->mmc,
1103                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1104                                         div, host->bus_hz, mmc_hostname(host->mmc));
1105                         }
1106
1107                         if (host->verid < DW_MMC_240A)
1108                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1109                         else
1110                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1111
1112
1113
1114                 }
1115
1116                 /* set clock to desired speed */
1117                 mci_writel(host, CLKDIV, div);
1118
1119                 /* inform CIU */
1120                 mci_send_cmd(slot,
1121                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1122
1123                 /* enable clock; only low power if no SDIO */
1124                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1125
1126                 if (host->verid < DW_MMC_240A)
1127                     sdio_int = SDMMC_INT_SDIO(slot->id);
1128                 else
1129                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1130
1131                 if (!(mci_readl(host, INTMASK) & sdio_int))
1132                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1133                 mci_writel(host, CLKENA, clk_en_a);
1134
1135                 /* inform CIU */
1136                 mci_send_cmd(slot,
1137                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1138                 /* keep the clock with reflecting clock dividor */
1139                 slot->__clk_old = clock << div;
1140         }
1141
1142         host->current_speed = clock;
1143
1144         if(slot->ctype != slot->pre_ctype)
1145                 MMC_DBG_BOOT_FUNC(host->mmc,
1146                                 "Bus speed=%dHz,Bus width=%s.[%s]",
1147                                 host->set_speed,
1148                                 (slot->ctype == SDMMC_CTYPE_4BIT) ? "4bits" : "8bits",
1149                                 mmc_hostname(host->mmc));
1150
1151         slot->pre_ctype = slot->ctype;
1152
1153         /* Set the current slot bus width */
1154         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1155 }
1156
1157 extern struct mmc_card *this_card;
1158 static void dw_mci_wait_unbusy(struct dw_mci *host)
1159 {
1160         unsigned int timeout = SDMMC_DATA_TIMEOUT_SDIO;
1161         unsigned long time_loop;
1162         unsigned int status;
1163         unsigned int tmo = 300000;
1164         /* Secure erase flag */
1165         u32 se_flag = 0;
1166
1167         MMC_DBG_INFO_FUNC(host->mmc,
1168                 "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1169
1170         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1171                 if (host->cmd && (host->cmd->opcode == MMC_ERASE) && this_card) {
1172                 /* Special care for (secure)erase timeout calculation */
1173                         if ((host->cmd->arg & (0x1 << 31)) == 1)
1174                                 se_flag = 0x1;
1175
1176                         if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1177                                 se_flag ?
1178                                 (timeout = (this_card->ext_csd.hc_erase_timeout) *
1179                                 tmo * (this_card->ext_csd.sec_erase_mult)) :
1180                                 (timeout = (this_card->ext_csd.hc_erase_timeout) * tmo);
1181                 }
1182
1183                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1184                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1185         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1186                 timeout = SDMMC_DATA_TIMEOUT_SD;
1187         }
1188
1189         time_loop = jiffies + msecs_to_jiffies(timeout);
1190         do {
1191                 status = mci_readl(host, STATUS);
1192                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1193                         break;
1194         } while (time_before(jiffies, time_loop));
1195 }
1196
1197 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1198 /*
1199 *   result:
1200 *   0--status is busy.
1201 *   1--status is unbusy.
1202 */
1203 int dw_mci_card_busy(struct mmc_host *mmc)
1204 {
1205         struct dw_mci_slot *slot = mmc_priv(mmc);
1206         struct dw_mci *host = slot->host;
1207
1208         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1209                                 host->svi_flags, mmc_hostname(host->mmc));
1210
1211         /* svi toggle*/
1212         if(host->svi_flags == 0){
1213                 /*first svi*/
1214                 host->svi_flags = 1;
1215                 return host->svi_flags;
1216
1217         }else{
1218                 host->svi_flags = 0;
1219                 return host->svi_flags;
1220         }
1221
1222
1223 }
1224 #endif
1225 static void __dw_mci_start_request(struct dw_mci *host,
1226                                    struct dw_mci_slot *slot,
1227                                    struct mmc_command *cmd)
1228 {
1229         struct mmc_request *mrq;
1230         struct mmc_data *data;
1231         u32 cmdflags;
1232
1233         mrq = slot->mrq;
1234         if (host->pdata->select_slot)
1235                 host->pdata->select_slot(slot->id);
1236
1237         host->cur_slot = slot;
1238         host->mrq = mrq;
1239
1240         dw_mci_wait_unbusy(host);
1241
1242         host->pending_events = 0;
1243         host->completed_events = 0;
1244         host->data_status = 0;
1245
1246         data = cmd->data;
1247         if (data) {
1248                 dw_mci_set_timeout(host);
1249                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1250                 mci_writel(host, BLKSIZ, data->blksz);
1251         }
1252
1253         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1254
1255         /* this is the first command, send the initialization clock */
1256         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1257                 cmdflags |= SDMMC_CMD_INIT;
1258
1259         if (data) {
1260                 dw_mci_submit_data(host, data);
1261                 wmb();
1262         }
1263
1264         dw_mci_start_command(host, cmd, cmdflags);
1265
1266         if (mrq->stop)
1267                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1268 }
1269
1270 static void dw_mci_start_request(struct dw_mci *host,
1271                                  struct dw_mci_slot *slot)
1272 {
1273         struct mmc_request *mrq = slot->mrq;
1274         struct mmc_command *cmd;
1275
1276         MMC_DBG_INFO_FUNC(host->mmc,
1277                 " Begin to start the new request. cmd=%d(arg=0x%x)[%s]",
1278                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1279
1280         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1281         __dw_mci_start_request(host, slot, cmd);
1282 }
1283
1284 /* must be called with host->lock held */
1285 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1286                                  struct mmc_request *mrq)
1287 {
1288         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1289                  host->state);
1290
1291         slot->mrq = mrq;
1292
1293         if (host->state == STATE_IDLE) {
1294                 host->state = STATE_SENDING_CMD;
1295                 dw_mci_start_request(host, slot);
1296         } else {
1297                 list_add_tail(&slot->queue_node, &host->queue);
1298         }
1299 }
1300
1301 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1302 {
1303         struct dw_mci_slot *slot = mmc_priv(mmc);
1304         struct dw_mci *host = slot->host;
1305
1306         WARN_ON(slot->mrq);
1307
1308         /*
1309          * The check for card presence and queueing of the request must be
1310          * atomic, otherwise the card could be removed in between and the
1311          * request wouldn't fail until another card was inserted.
1312          */
1313         spin_lock_bh(&host->lock);
1314
1315         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1316                 spin_unlock_bh(&host->lock);
1317                 mrq->cmd->error = -ENOMEDIUM;
1318                 MMC_DBG_CMD_FUNC(host->mmc, "%s: no card,so reqeuest done, cmd=%d [%s]",
1319                                 __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1320
1321                 mmc_request_done(mmc, mrq);
1322                 return;
1323         }
1324
1325         MMC_DBG_CMD_FUNC(host->mmc,
1326                 "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]",
1327                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1328
1329         dw_mci_queue_request(host, slot, mrq);
1330
1331         spin_unlock_bh(&host->lock);
1332 }
1333
1334 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1335 {
1336         struct dw_mci_slot *slot = mmc_priv(mmc);
1337         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1338         struct dw_mci *host = slot->host;
1339         #endif
1340         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1341         u32 regs;
1342
1343         #ifdef SDMMC_WAIT_FOR_UNBUSY
1344         unsigned long   time_loop;
1345         bool ret = true;
1346
1347         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1348         if(host->svi_flags == 1)
1349                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1350         else
1351                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1352         #else
1353                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1354         #endif
1355
1356         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1357                 printk("%d..%s:  no card. [%s]\n", \
1358                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1359                 goto EXIT_POWER;
1360         }
1361
1362         while (ret) {
1363                 ret = time_before(jiffies, time_loop);
1364                 regs = mci_readl(slot->host, STATUS);
1365                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY |
1366                         SDMMC_STAUTS_MC_BUSY)))
1367                         break;
1368         };
1369
1370         if(false == ret)
1371         {
1372                 printk("slot->flags = %lu ", slot->flags);
1373                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1374                 if(host->svi_flags != 1)
1375                 #endif
1376                         dump_stack();
1377                 printk("%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n",
1378                          __FUNCTION__, regs, mmc_hostname(mmc));
1379         }
1380         #endif
1381
1382         switch (ios->bus_width) {
1383         case MMC_BUS_WIDTH_4:
1384                 slot->ctype = SDMMC_CTYPE_4BIT;
1385                 break;
1386         case MMC_BUS_WIDTH_8:
1387                 slot->ctype = SDMMC_CTYPE_8BIT;
1388                 break;
1389         default:
1390                 /* set default 1 bit mode */
1391                 slot->ctype = SDMMC_CTYPE_1BIT;
1392                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1393         }
1394
1395         regs = mci_readl(slot->host, UHS_REG);
1396
1397         /* DDR mode set */
1398         if (ios->timing == MMC_TIMING_UHS_DDR50)
1399                 regs |= ((0x1 << slot->id) << 16);
1400         else
1401                 regs &= ~((0x1 << slot->id) << 16);
1402
1403         mci_writel(slot->host, UHS_REG, regs);
1404         slot->host->timing = ios->timing;
1405
1406         /*
1407          * Use mirror of ios->clock to prevent race with mmc
1408          * core ios update when finding the minimum.
1409          */
1410         slot->clock = ios->clock;
1411
1412         if (drv_data && drv_data->set_ios)
1413                 drv_data->set_ios(slot->host, ios);
1414
1415         /* Slot specific timing and width adjustment */
1416         dw_mci_setup_bus(slot, false);
1417                 //return -EAGAIN;
1418
1419 EXIT_POWER:
1420         switch (ios->power_mode) {
1421         case MMC_POWER_UP:
1422         /* Power up slot */
1423                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1424                 if (slot->host->pdata->setpower)
1425                         slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1426                 regs = mci_readl(slot->host, PWREN);
1427                 regs |= (1 << slot->id);
1428                 mci_writel(slot->host, PWREN, regs);
1429                 break;
1430         case MMC_POWER_OFF:
1431         /* Power down slot */
1432                 if(slot->host->pdata->setpower)
1433                         slot->host->pdata->setpower(slot->id, 0);
1434                 regs = mci_readl(slot->host, PWREN);
1435                 regs &= ~(1 << slot->id);
1436                 mci_writel(slot->host, PWREN, regs);
1437                 break;
1438         default:
1439                 break;
1440         }
1441 }
1442
1443 static int dw_mci_get_ro(struct mmc_host *mmc)
1444 {
1445         int read_only;
1446         struct dw_mci_slot *slot = mmc_priv(mmc);
1447         struct dw_mci_board *brd = slot->host->pdata;
1448
1449         /* Use platform get_ro function, else try on board write protect */
1450         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1451                 read_only = 0;
1452         else if(brd->get_ro)
1453                 read_only = brd->get_ro(slot->id);
1454         else if(gpio_is_valid(slot->wp_gpio))
1455                 read_only = gpio_get_value(slot->wp_gpio);
1456         else
1457                 read_only =
1458                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1459
1460         dev_dbg(&mmc->class_dev, "card is %s\n",
1461                 read_only ? "read-only" : "read-write");
1462
1463         return read_only;
1464 }
1465
1466 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1467 {
1468         struct dw_mci_slot *slot = mmc_priv(mmc);
1469         struct dw_mci *host = slot->host;
1470
1471         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1472                 return 0;
1473
1474         spin_lock_bh(&host->lock);
1475
1476         if(val)
1477                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1478         else
1479                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1480
1481         spin_unlock_bh(&host->lock);
1482
1483         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1484                 if (__clk_is_enabled(host->hclk_mmc) == false)
1485                         clk_prepare_enable(host->hclk_mmc);
1486                 if (__clk_is_enabled(host->clk_mmc) == false)
1487                         clk_prepare_enable(host->clk_mmc);
1488         } else {
1489                 if (__clk_is_enabled(host->clk_mmc) == true)
1490                         clk_disable_unprepare(slot->host->clk_mmc);
1491                 if (__clk_is_enabled(host->hclk_mmc) == true)
1492                         clk_disable_unprepare(slot->host->hclk_mmc);
1493         }
1494
1495         mmc_detect_change(slot->mmc, 20);
1496         return 0;
1497 }
1498
1499
1500
1501 static int dw_mci_get_cd(struct mmc_host *mmc)
1502 {
1503         int present;
1504         struct dw_mci_slot *slot = mmc_priv(mmc);
1505         struct dw_mci_board *brd = slot->host->pdata;
1506         struct dw_mci *host = slot->host;
1507         int gpio_cd = mmc_gpio_get_cd(mmc);
1508         int force_jtag_bit, force_jtag_reg;
1509         int gpio_val;
1510         int irq;
1511
1512         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1513                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1514                 gpio_cd = slot->cd_gpio;
1515                 irq = gpio_to_irq(gpio_cd);
1516                 if (gpio_is_valid(gpio_cd)) {
1517                         gpio_val = gpio_get_value(gpio_cd);
1518                         if (soc_is_rk3036()) {
1519                                 force_jtag_bit = 11;
1520                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1521                         } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1522                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1523                                 force_jtag_bit = 8;
1524                         }
1525                         msleep(10);
1526                         if (gpio_val == gpio_get_value(gpio_cd)) {
1527                                 gpio_cd = (gpio_val == 0 ? 1 : 0);
1528                                 if (gpio_cd == 0) {
1529                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1530                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1531                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1532                                                         force_jtag_reg);
1533                                         dw_mci_ctrl_all_reset(host);
1534                                 } else {
1535                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1536                                         /* Really card detected: SHOULD disable force_jtag */
1537                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1538                                                         force_jtag_reg);
1539                                 }
1540                         } else {
1541                                 /* Jitter */
1542                                 gpio_val = gpio_get_value(gpio_cd);
1543                                 (gpio_val == 0) ?
1544                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
1545                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW  | IRQF_ONESHOT);
1546                                 return slot->last_detect_state;
1547                         }
1548                 } else {
1549                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1550                 }
1551         }
1552
1553         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1554                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1555
1556         /* Use platform get_cd function, else try onboard card detect */
1557         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1558                 present = 1;
1559         else if (brd->get_cd)
1560                 present = !brd->get_cd(slot->id);
1561         else if (!IS_ERR_VALUE(gpio_cd))
1562                 present = gpio_cd;
1563         else
1564                 present = ((mci_readl(slot->host, CDETECT) & (1 << slot->id))
1565                         == 0) ? 1 : 0;
1566
1567         spin_lock_bh(&host->lock);
1568         if (present) {
1569                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1570                 dev_dbg(&mmc->class_dev, "card is present\n");
1571         } else {
1572                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1573                 dev_dbg(&mmc->class_dev, "card is not present\n");
1574         }
1575         spin_unlock_bh(&host->lock);
1576
1577         return present;
1578 }
1579
1580
1581 /*
1582  * Dts Should caps emmc controller with poll-hw-reset
1583  */
1584 static void dw_mci_hw_reset(struct mmc_host *mmc)
1585 {
1586         struct dw_mci_slot *slot = mmc_priv(mmc);
1587         struct dw_mci *host = slot->host;
1588         u32 regs;
1589
1590         #if 0
1591         u32 cmd_flags;
1592         unsigned long timeout;
1593         bool ret = true;
1594
1595         /* (1) CMD12 to end any transfer in process */
1596         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1597                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1598
1599         if(host->mmc->hold_reg_flag)
1600                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1601         mci_writel(host, CMDARG, 0);
1602         wmb();
1603         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1604         wmb();
1605         timeout = jiffies + msecs_to_jiffies(500);
1606         while(ret){
1607                 ret = time_before(jiffies, timeout);
1608                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1609                         break;
1610         }
1611
1612         if(false == ret)
1613                 MMC_DBG_ERR_FUNC(host->mmc,
1614                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1615                         __func__, mmc_hostname(host->mmc));
1616
1617         /* (2) wait DTO, even if no response is sent back by card */
1618         ret = true;
1619         timeout = jiffies + msecs_to_jiffies(5);
1620         while(ret){
1621                 ret = time_before(jiffies, timeout);
1622                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1623                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1624                         break;
1625                 }
1626         }
1627         #endif
1628
1629         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1630
1631         /* Software reset - BMOD[0] for IDMA only */
1632         regs = mci_readl(host, BMOD);
1633         regs |= SDMMC_IDMAC_SWRESET;
1634         mci_writel(host, BMOD, regs);
1635         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1636         regs = mci_readl(host, BMOD);
1637         if(regs & SDMMC_IDMAC_SWRESET)
1638                 MMC_DBG_WARN_FUNC(host->mmc,
1639                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1640                         __func__, mmc_hostname(host->mmc));
1641
1642         /* DMA reset - CTRL[2] */
1643         regs = mci_readl(host, CTRL);
1644         regs |= SDMMC_CTRL_DMA_RESET;
1645         mci_writel(host, CTRL, regs);
1646         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1647         regs = mci_readl(host, CTRL);
1648         if(regs & SDMMC_CTRL_DMA_RESET)
1649                 MMC_DBG_WARN_FUNC(host->mmc,
1650                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1651                         __func__, mmc_hostname(host->mmc));
1652
1653         /* FIFO reset - CTRL[1] */
1654         regs = mci_readl(host, CTRL);
1655         regs |= SDMMC_CTRL_FIFO_RESET;
1656         mci_writel(host, CTRL, regs);
1657         mdelay(1); /* no timing limited, 1ms is random value */
1658         regs = mci_readl(host, CTRL);
1659         if(regs & SDMMC_CTRL_FIFO_RESET)
1660                 MMC_DBG_WARN_FUNC(host->mmc,
1661                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1662                         __func__, mmc_hostname(host->mmc));
1663
1664         /* (4) CARD_RESET
1665         According to eMMC spec
1666         tRstW >= 1us ;   RST_n pulse width
1667         tRSCA >= 200us ; RST_n to Command time
1668         tRSTH >= 1us ;   RST_n high period
1669         */
1670         mci_writel(slot->host, PWREN, 0x0);
1671         mci_writel(slot->host, RST_N, 0x0);
1672         dsb(sy);
1673         udelay(10); /* 10us for bad quality eMMc. */
1674
1675         mci_writel(slot->host, PWREN, 0x1);
1676         mci_writel(slot->host, RST_N, 0x1);
1677         dsb(sy);
1678         usleep_range(500, 1000); /* at least 500(> 200us) */
1679 }
1680
1681 /*
1682  * Disable lower power mode.
1683  *
1684  * Low power mode will stop the card clock when idle.  According to the
1685  * description of the CLKENA register we should disable low power mode
1686  * for SDIO cards if we need SDIO interrupts to work.
1687  *
1688  * This function is fast if low power mode is already disabled.
1689  */
1690 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1691 {
1692         struct dw_mci *host = slot->host;
1693         u32 clk_en_a;
1694         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1695
1696         clk_en_a = mci_readl(host, CLKENA);
1697
1698         if (clk_en_a & clken_low_pwr) {
1699                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1700                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1701                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1702         }
1703 }
1704
1705 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1706 {
1707         struct dw_mci_slot *slot = mmc_priv(mmc);
1708         struct dw_mci *host = slot->host;
1709         unsigned long flags;
1710         u32 int_mask;
1711         u32 sdio_int;
1712
1713         spin_lock_irqsave(&host->slock, flags);
1714
1715         /* Enable/disable Slot Specific SDIO interrupt */
1716         int_mask = mci_readl(host, INTMASK);
1717
1718         if (host->verid < DW_MMC_240A)
1719                 sdio_int = SDMMC_INT_SDIO(slot->id);
1720         else
1721                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1722
1723         if (enb) {
1724                 /*
1725                  * Turn off low power mode if it was enabled.  This is a bit of
1726                  * a heavy operation and we disable / enable IRQs a lot, so
1727                  * we'll leave low power mode disabled and it will get
1728                  * re-enabled again in dw_mci_setup_bus().
1729                  */
1730                 dw_mci_disable_low_power(slot);
1731
1732                 mci_writel(host, INTMASK,
1733                            (int_mask | sdio_int));
1734         } else {
1735                 mci_writel(host, INTMASK,
1736                            (int_mask & ~sdio_int));
1737         }
1738
1739         spin_unlock_irqrestore(&host->slock, flags);
1740 }
1741
1742 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1743 enum{
1744         IO_DOMAIN_12 = 1200,
1745         IO_DOMAIN_18 = 1800,
1746         IO_DOMAIN_33 = 3300,
1747 };
1748 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1749 {
1750         switch(voltage){
1751         case IO_DOMAIN_33:
1752                 voltage = 0;
1753                 break;
1754         case IO_DOMAIN_18:
1755                 voltage = 1;
1756                 break;
1757         case IO_DOMAIN_12:
1758                 MMC_DBG_ERR_FUNC(host->mmc,
1759                         "%s : Not support io domain voltage [%s]\n",
1760                         __FUNCTION__, mmc_hostname(host->mmc));
1761                 break;
1762         default:
1763                 MMC_DBG_ERR_FUNC(host->mmc,
1764                         "%s : Err io domain voltage [%s]\n",
1765                         __FUNCTION__, mmc_hostname(host->mmc));
1766                 break;
1767         }
1768
1769         if (cpu_is_rk3288()) {
1770                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1771                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1772                 else
1773                         return ;
1774         } else if (host->cid == DW_MCI_TYPE_RK3368) {
1775                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1776                          regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1777                 else
1778                         return;
1779         } else {
1780                 MMC_DBG_ERR_FUNC(host->mmc,
1781                         "%s : unknown chip [%s]\n",
1782                         __FUNCTION__, mmc_hostname(host->mmc));
1783         }
1784 }
1785
1786 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1787                                                 struct mmc_ios *ios)
1788 {
1789         int ret;
1790         unsigned int value,uhs_reg;
1791
1792         /*
1793          * Signal Voltage Switching is only applicable for Host Controllers
1794          * v3.00 and above.
1795          */
1796         if (host->verid < DW_MMC_240A)
1797                 return 0;
1798
1799         uhs_reg = mci_readl(host, UHS_REG);
1800         MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: vol=%d.[%s]\n",
1801                  __FUNCTION__, ios->signal_voltage, mmc_hostname(host->mmc));
1802
1803         switch (ios->signal_voltage) {
1804         case MMC_SIGNAL_VOLTAGE_330:
1805         /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1806                 if (host->vmmc) {
1807                         if (cpu_is_rk3288())
1808                                 ret = io_domain_regulator_set_voltage(
1809                                                 host->vmmc, 3300000, 3300000);
1810                         else
1811                                 ret = regulator_set_voltage(host->vmmc,
1812                                                         3300000, 3300000);
1813
1814                         /* regulator_put(host->vmmc); */
1815                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s =%dmV set 3.3 end, ret = %d\n",
1816                                 __func__, regulator_get_voltage(host->vmmc), ret);
1817                         if (ret) {
1818                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1819                                         "%s: Switching to 3.3V signalling voltage "
1820                                         " failed\n", mmc_hostname(host->mmc));
1821                                 return -EIO;
1822                         }
1823                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1824                 }
1825
1826                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: [%s]\n",
1827                                 __FUNCTION__, mmc_hostname(host->mmc));
1828
1829                 /* set High-power mode */
1830                 value = mci_readl(host, CLKENA);
1831                 value &= ~SDMMC_CLKEN_LOW_PWR;
1832                 mci_writel(host,CLKENA , value);
1833                 /* SDMMC_UHS_REG */
1834                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1835                 mci_writel(host,UHS_REG , uhs_reg);
1836
1837                 /* Wait for 5ms */
1838                 usleep_range(5000, 5500);
1839
1840                 /* 3.3V regulator output should be stable within 5 ms */
1841                 uhs_reg = mci_readl(host, UHS_REG);
1842                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1843                         return 0;
1844
1845                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1846                         "%s: 3.3V regulator output did not became stable\n",
1847                         mmc_hostname(host->mmc));
1848
1849                 return -EAGAIN;
1850         case MMC_SIGNAL_VOLTAGE_180:
1851                 if (host->vmmc) {
1852                         if (cpu_is_rk3288())
1853                                 ret = io_domain_regulator_set_voltage(
1854                                         host->vmmc, 1800000, 1800000);
1855                         else
1856                                 ret = regulator_set_voltage(
1857                                                 host->vmmc, 1800000, 1800000);
1858                         /* regulator_put(host->vmmc); */
1859                         MMC_DBG_SW_VOL_FUNC(host->mmc,
1860                                         "%s   =%dmV  set 1.8end, ret=%d . \n",
1861                                         __func__, regulator_get_voltage(host->vmmc), ret);
1862                         if (ret) {
1863                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1864                                         "%s: Switching to 1.8V signalling voltage "
1865                                         " failed\n", mmc_hostname(host->mmc));
1866                                 return -EIO;
1867                         }
1868                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1869                 }
1870
1871                 /*
1872                 * Enable 1.8V Signal Enable in the Host Control2
1873                 * register
1874                 */
1875                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1876
1877                 /* Wait for 5ms */
1878                 usleep_range(5000, 5500);
1879                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%d..%s: .[%s]\n",__LINE__,
1880                                 __FUNCTION__, mmc_hostname(host->mmc));
1881
1882                 /* 1.8V regulator output should be stable within 5 ms */
1883                 uhs_reg = mci_readl(host, UHS_REG);
1884                 if (uhs_reg & SDMMC_UHS_VOLT_REG_18)
1885                         return 0;
1886
1887                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1888                         "%s: 1.8V regulator output did not became stable\n",
1889                         mmc_hostname(host->mmc));
1890
1891                 return -EAGAIN;
1892         case MMC_SIGNAL_VOLTAGE_120:
1893                 if (host->vmmc) {
1894                         if (cpu_is_rk3288())
1895                                 ret = io_domain_regulator_set_voltage(
1896                                         host->vmmc, 1200000, 1200000);
1897                         else
1898                                 ret = regulator_set_voltage(host->vmmc,
1899                                         1200000, 1200000);
1900                         if (ret) {
1901                                 MMC_DBG_SW_VOL_FUNC(host->mmc,
1902                                         "%s: Switching to 1.2V signalling voltage "
1903                                         " failed\n", mmc_hostname(host->mmc));
1904                                 return -EIO;
1905                         }
1906                 }
1907                 return 0;
1908         default:
1909                 /* No signal voltage switch required */
1910                 return 0;
1911         }
1912 }
1913
1914
1915 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1916         struct mmc_ios *ios)
1917 {
1918         struct dw_mci_slot *slot = mmc_priv(mmc);
1919         struct dw_mci *host = slot->host;
1920         int err;
1921
1922         if (host->verid < DW_MMC_240A)
1923                 return 0;
1924
1925         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1926         return err;
1927 }
1928
1929 #endif
1930
1931 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1932 {
1933         struct dw_mci_slot *slot = mmc_priv(mmc);
1934         struct dw_mci *host = slot->host;
1935         const struct dw_mci_drv_data *drv_data = host->drv_data;
1936         struct dw_mci_tuning_data tuning_data;
1937         int err = -ENOSYS;
1938
1939         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1940         if(cpu_is_rk3036() || cpu_is_rk312x())
1941                 return err;
1942
1943         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1944                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1945                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1946                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1947                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1948                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1949                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1950                 } else {
1951                         return -EINVAL;
1952                 }
1953         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1954                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1955                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1956         } else {
1957                 dev_err(host->dev,
1958                         "Undefined command(%d) for tuning\n", opcode);
1959                 return -EINVAL;
1960         }
1961
1962         if (drv_data && drv_data->execute_tuning)
1963                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1964
1965         return err;
1966 }
1967
1968 static void dw_mci_post_tmo(struct mmc_host *mmc)
1969 {
1970         struct dw_mci_slot *slot = mmc_priv(mmc);
1971         struct dw_mci *host = slot->host;
1972         struct mmc_data *data;
1973         u32 ret, i, regs, cmd_flags;
1974         u32 sdio_int;
1975         unsigned long timeout = 0;
1976         bool ret_timeout = true;
1977         u32 opcode;
1978
1979         opcode = host->mrq->cmd->opcode;
1980         host->cur_slot->mrq = NULL;
1981         host->mrq = NULL;
1982         host->state = STATE_IDLE;
1983
1984         data = host->data;
1985
1986         if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) ||
1987             (opcode == MMC_SEND_TUNING_BLOCK))
1988             return;
1989
1990         printk("[%s] -- Timeout recovery procedure start --\n",
1991                 mmc_hostname(host->mmc));
1992
1993         mci_writel(host, CMDARG, 0);
1994         wmb();
1995         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
1996                         SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1997
1998         if (host->mmc->hold_reg_flag)
1999                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2000
2001         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2002         wmb();
2003         timeout = jiffies + msecs_to_jiffies(500);
2004
2005         while(ret_timeout) {
2006                 ret_timeout = time_before(jiffies, timeout);
2007                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2008                         break;
2009         }
2010
2011         if (false == ret_timeout)
2012                 MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
2013                                  mmc_hostname(host->mmc));
2014
2015         if (!dw_mci_ctrl_all_reset(host)) {
2016                 ret = -ENODEV;
2017                 return ;
2018         }
2019
2020 #ifdef CONFIG_MMC_DW_IDMAC
2021         if (!(cpu_is_rk3036() || cpu_is_rk312x()))
2022                 if (host->use_dma && host->dma_ops->init)
2023                         host->dma_ops->init(host);
2024 #endif
2025
2026         /*
2027         * Restore the initial value at FIFOTH register
2028         * And Invalidate the prev_blksz with zero
2029         */
2030         mci_writel(host, FIFOTH, host->fifoth_val);
2031         host->prev_blksz = 0;
2032         mci_writel(host, TMOUT, 0xFFFFFFFF);
2033         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2034         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
2035                         | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
2036         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2037                 regs |= SDMMC_INT_CD;
2038
2039         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2040                 if (host->verid < DW_MMC_240A)
2041                         sdio_int = SDMMC_INT_SDIO(0);
2042                 else
2043                         sdio_int = SDMMC_INT_SDIO(8);
2044
2045                 if (mci_readl(host, INTMASK) & sdio_int)
2046                         regs |= sdio_int;
2047         }
2048
2049         mci_writel(host, INTMASK, regs);
2050         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2051         for (i = 0; i < host->num_slots; i++) {
2052                 struct dw_mci_slot *slot = host->slot[i];
2053                 if (!slot)
2054                         continue;
2055                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2056                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2057                         dw_mci_setup_bus(slot, true);
2058                 }
2059         }
2060         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2061
2062         printk("[%s] -- Timeout recovery procedure finished --\n",
2063                 mmc_hostname(host->mmc));
2064 }
2065
2066 static const struct mmc_host_ops dw_mci_ops = {
2067         .request                = dw_mci_request,
2068         .pre_req                = dw_mci_pre_req,
2069         .post_req               = dw_mci_post_req,
2070         .set_ios                = dw_mci_set_ios,
2071         .get_ro                 = dw_mci_get_ro,
2072         .get_cd                 = dw_mci_get_cd,
2073         .set_sdio_status        = dw_mci_set_sdio_status,
2074         .hw_reset               = dw_mci_hw_reset,
2075         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
2076         .execute_tuning         = dw_mci_execute_tuning,
2077         .post_tmo               = dw_mci_post_tmo,
2078         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2079         .start_signal_voltage_switch
2080                                 = dw_mci_start_signal_voltage_switch,
2081         .card_busy              = dw_mci_card_busy,
2082         #endif
2083 };
2084
2085 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2086         __releases(&host->lock)
2087         __acquires(&host->lock)
2088 {
2089         if (DW_MCI_SEND_STATUS == host->dir_status){
2090                 dw_mci_wait_unbusy(host);
2091         }
2092 }
2093
2094 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2095         __releases(&host->lock)
2096         __acquires(&host->lock)
2097 {
2098         struct dw_mci_slot *slot;
2099         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2100
2101         //WARN_ON(host->cmd || host->data);
2102
2103         dw_mci_deal_data_end(host, mrq);
2104
2105         if(mrq->cmd)
2106                 MMC_DBG_CMD_FUNC(host->mmc,
2107                         " reqeust end--reqeuest done, cmd=%d, "
2108                         "cmderr=%d, host->state=%d [%s]",
2109                         mrq->cmd->opcode, mrq->cmd->error,
2110                         host->state,mmc_hostname(host->mmc));
2111         if(mrq->data)
2112                 MMC_DBG_CMD_FUNC(host->mmc,
2113                         " reqeust end--reqeuest done, cmd=%d, "
2114                         "dataerr=%d, host->state=%d [%s]",
2115                         mrq->cmd->opcode,mrq->data->error,
2116                         host->state, mmc_hostname(host->mmc));
2117
2118         host->cur_slot->mrq = NULL;
2119         host->mrq = NULL;
2120         if (!list_empty(&host->queue)) {
2121                 slot = list_entry(host->queue.next,
2122                                   struct dw_mci_slot, queue_node);
2123                 list_del(&slot->queue_node);
2124                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2125                          mmc_hostname(slot->mmc));
2126                 host->state = STATE_SENDING_CMD;
2127                 MMC_DBG_CMD_FUNC(host->mmc,
2128                         " list is not empty. run the request in list. [%s]",
2129                         mmc_hostname(host->mmc));
2130                 dw_mci_start_request(host, slot);
2131         } else {
2132                 dev_vdbg(host->dev, "list empty\n");
2133                 host->state = STATE_IDLE;
2134         }
2135
2136         spin_unlock(&host->lock);
2137         mmc_request_done(prev_mmc, mrq);
2138         spin_lock(&host->lock);
2139 }
2140
2141 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2142 {
2143         u32 status = host->cmd_status;
2144
2145         host->cmd_status = 0;
2146
2147         /* Read the response from the card (up to 16 bytes) */
2148         if (cmd->flags & MMC_RSP_PRESENT) {
2149                 if (cmd->flags & MMC_RSP_136) {
2150                         cmd->resp[3] = mci_readl(host, RESP0);
2151                         cmd->resp[2] = mci_readl(host, RESP1);
2152                         cmd->resp[1] = mci_readl(host, RESP2);
2153                         cmd->resp[0] = mci_readl(host, RESP3);
2154
2155             MMC_DBG_INFO_FUNC(host->mmc,
2156                 "Command complete cmd=%d, "
2157                 "resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]",
2158                 cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0],
2159                 mmc_hostname(host->mmc));
2160         } else {
2161                 cmd->resp[0] = mci_readl(host, RESP0);
2162                 cmd->resp[1] = 0;
2163                 cmd->resp[2] = 0;
2164                 cmd->resp[3] = 0;
2165                 MMC_DBG_INFO_FUNC(host->mmc,
2166                         "Command complete cmd=%d,resp[0]=0x%x. [%s]",
2167                         cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2168                 }
2169         }
2170
2171         if (status & SDMMC_INT_RTO)
2172         {
2173                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2174                         host->cmd_rto += 1;
2175
2176                 cmd->error = -ETIMEDOUT;
2177         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2178                 cmd->error = -EILSEQ;
2179         }else if (status & SDMMC_INT_RESP_ERR){
2180                 cmd->error = -EIO;
2181         }else{
2182                 cmd->error = 0;
2183         }
2184
2185         MMC_DBG_CMD_FUNC(host->mmc,
2186                         "Command complete, cmd=%d,cmdError=%d [%s]",
2187                         cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2188
2189         if (cmd->error) {
2190                 if(MMC_SEND_STATUS != cmd->opcode)
2191                         if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2192                                 MMC_DBG_CMD_FUNC(host->mmc,
2193                                         "Command complete, cmd=%d,cmdError=%d [%s]",
2194                                         cmd->opcode, cmd->error, mmc_hostname(host->mmc));
2195                                 host->cmd_rto = 0;
2196                         }
2197
2198                 /* newer ip versions need a delay between retries */
2199                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2200                         mdelay(20);
2201         }
2202 }
2203
2204 static void dw_mci_tasklet_func(unsigned long priv)
2205 {
2206         struct dw_mci *host = (struct dw_mci *)priv;
2207         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2208         struct mmc_data *data;
2209         struct mmc_command *cmd;
2210         enum dw_mci_state state;
2211         enum dw_mci_state prev_state;
2212         u32 status, cmd_flags;
2213         unsigned long timeout = 0;
2214         bool ret = true;
2215
2216         spin_lock(&host->lock);
2217
2218         state = host->state;
2219         data = host->data;
2220
2221         do {
2222                 prev_state = state;
2223
2224                 switch (state) {
2225                 case STATE_IDLE:
2226                         break;
2227
2228                 case STATE_SENDING_CMD:
2229                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2230                                                 &host->pending_events))
2231                                 break;
2232
2233                         cmd = host->cmd;
2234                         host->cmd = NULL;
2235                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2236                         dw_mci_command_complete(host, cmd);
2237                         if (cmd == host->mrq->sbc && !cmd->error) {
2238                                 prev_state = state = STATE_SENDING_CMD;
2239                                 __dw_mci_start_request(host, host->cur_slot,
2240                                                        host->mrq->cmd);
2241                                 goto unlock;
2242                         }
2243
2244                         if (cmd->data && cmd->error) {
2245                                 dw_mci_stop_dma(host);
2246                                 #if 1
2247                                 if (data->stop) {
2248                                         send_stop_cmd(host, data);
2249                                         state = STATE_SENDING_STOP;
2250                                         break;
2251                                 }else{
2252                                        /*  host->data = NULL; */
2253                                 }
2254                                 #else
2255                                 send_stop_abort(host, data);
2256                                 state = STATE_SENDING_STOP;
2257                                 break;
2258                                 #endif
2259                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2260                         }
2261
2262                         if (!host->mrq->data || cmd->error) {
2263                                 dw_mci_request_end(host, host->mrq);
2264                                 goto unlock;
2265                         }
2266
2267                         prev_state = state = STATE_SENDING_DATA;
2268                         /* fall through */
2269
2270                 case STATE_SENDING_DATA:
2271                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2272                                 &host->pending_events)) {
2273                                 dw_mci_stop_dma(host);
2274                                 #if 1
2275                                 if (data->stop){
2276                                         send_stop_cmd(host, data);
2277                                 }else{
2278                                         /*single block read/write, send stop cmd
2279                                         manually to prevent host controller halt*/
2280                                         MMC_DBG_INFO_FUNC(host->mmc,
2281                                                 "%s status 1 0x%08x [%s]\n",
2282                                                 __func__, mci_readl(host, STATUS),
2283                                                 mmc_hostname(host->mmc));
2284
2285                                         mci_writel(host, CMDARG, 0);
2286                                         wmb();
2287                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2288                                                 SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2289
2290                                         if(host->mmc->hold_reg_flag)
2291                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2292
2293                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2294                                         wmb();
2295                                         timeout = jiffies + msecs_to_jiffies(500);
2296
2297                                         while(ret) {
2298                                                 ret = time_before(jiffies, timeout);
2299                                                 if (!(mci_readl(host, CMD) & SDMMC_CMD_START))
2300                                                         break;
2301                                         }
2302                                         if(false == ret)
2303                                                 MMC_DBG_ERR_FUNC(host->mmc,
2304                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2305                                                         __func__, mmc_hostname(host->mmc));
2306                                 }
2307                                 #else
2308                                 send_stop_abort(host, data);
2309                                 #endif
2310                                 state = STATE_DATA_ERROR;
2311                                 break;
2312                         }
2313
2314                         MMC_DBG_CMD_FUNC(host->mmc,
2315                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2316                                 "wait for EVENT_XFER_COMPLETE.[%s]",
2317                                 prev_state, state, mmc_hostname(host->mmc));
2318
2319                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2320                                 &host->pending_events))
2321                                 break;
2322                         MMC_DBG_INFO_FUNC(host->mmc,
2323                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, "
2324                                 "wait for EVENT_DATA_COMPLETE. [%s]",
2325                                 prev_state, state, mmc_hostname(host->mmc));
2326
2327                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2328                         prev_state = state = STATE_DATA_BUSY;
2329                         /* fall through */
2330
2331                 case STATE_DATA_BUSY:
2332                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2333                                                 &host->pending_events))
2334                                 break;
2335
2336                         dw_mci_deal_data_end(host, host->mrq);
2337                         MMC_DBG_INFO_FUNC(host->mmc,
2338                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, "
2339                                 "after EVENT_DATA_COMPLETE. [%s]",
2340                                 prev_state, state, mmc_hostname(host->mmc));
2341
2342                         /* host->data = NULL; */
2343                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2344                         status = host->data_status;
2345
2346                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2347                                 if((SDMMC_CTYPE_1BIT != slot->ctype) &&
2348                                         (MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2349                                         MMC_DBG_ERR_FUNC(host->mmc,
2350                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,"
2351                                         "datastatus=0x%x [%s]",
2352                                         prev_state, state, status, mmc_hostname(host->mmc));
2353
2354                         if (status & SDMMC_INT_DRTO) {
2355                                         data->error = -ETIMEDOUT;
2356                                 } else if (status & SDMMC_INT_DCRC) {
2357                                         data->error = -EILSEQ;
2358                                 } else if (status & SDMMC_INT_EBE &&
2359                                 host->dir_status == DW_MCI_SEND_STATUS){
2360                                         /*
2361                                          * No data CRC status was returned.
2362                                          * The number of bytes transferred will
2363                                          * be exaggerated in PIO mode.
2364                                          */
2365                                         data->bytes_xfered = 0;
2366                                         data->error = -ETIMEDOUT;
2367                                 } else {
2368                                         dev_err(host->dev,
2369                                                 "data FIFO error "
2370                                                 "(status=%08x)\n",
2371                                                 status);
2372                                         data->error = -EIO;
2373                                 }
2374                                 /*
2375                                  * After an error, there may be data lingering
2376                                  * in the FIFO, so reset it - doing so
2377                                  * generates a block interrupt, hence setting
2378                                  * the scatter-gather pointer to NULL.
2379                                  */
2380                                 dw_mci_fifo_reset(host);
2381                         } else {
2382                                 data->bytes_xfered = data->blocks * data->blksz;
2383                                 data->error = 0;
2384                         }
2385
2386                         if (!data->stop) {
2387                                 MMC_DBG_CMD_FUNC(host->mmc,
2388                                         "Pre-state[%d]-->NowState[%d]: "
2389                                         "no stop and no dataerr, exit [%s]",
2390                                         prev_state, state, mmc_hostname(host->mmc));
2391                                 dw_mci_request_end(host, host->mrq);
2392                                 goto unlock;
2393                         }
2394                         MMC_DBG_CMD_FUNC(host->mmc,
2395                                 "Pre-state[%d]-->NowState[%d]: begin to stop [%s]",
2396                                 prev_state, state, mmc_hostname(host->mmc));
2397
2398                         if (host->mrq->sbc && !data->error) {
2399                                 data->stop->error = 0;
2400
2401                                 MMC_DBG_CMD_FUNC(host->mmc,
2402                                         "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit [%s]",
2403                                         prev_state,state,mmc_hostname(host->mmc));
2404
2405                                 dw_mci_request_end(host, host->mrq);
2406                                 goto unlock;
2407                         }
2408
2409                         prev_state = state = STATE_SENDING_STOP;
2410                         if (!data->error)
2411                                 send_stop_cmd(host, data);
2412                         /* fall through */
2413                         MMC_DBG_CMD_FUNC(host->mmc,
2414                                 "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP [%s]",
2415                                 prev_state, state, mmc_hostname(host->mmc));
2416
2417                 case STATE_SENDING_STOP:
2418                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2419                                 &host->pending_events))
2420                                 break;
2421
2422                         MMC_DBG_CMD_FUNC(host->mmc,
2423                                 "Pre-state[%d]-->NowState[%d]: begin to send cmd12 [%s]",
2424                                 prev_state, state, mmc_hostname(host->mmc));
2425
2426                         /* CMD error in data command */
2427                         if (host->mrq->cmd->error && host->mrq->data) {
2428                                 dw_mci_fifo_reset(host);
2429                         }
2430
2431                         /*
2432                         host->cmd = NULL;
2433                         host->data = NULL;
2434                         */
2435                         #if 1
2436                         dw_mci_command_complete(host, host->mrq->stop);
2437                         #else
2438                         if (host->mrq->stop)
2439                                 dw_mci_command_complete(host, host->mrq->stop);
2440                         else
2441                                 host->cmd_status = 0;
2442                         #endif
2443
2444                         dw_mci_request_end(host, host->mrq);
2445                         goto unlock;
2446
2447                 case STATE_DATA_ERROR:
2448                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2449                                                 &host->pending_events))
2450                                 break;
2451
2452                         state = STATE_DATA_BUSY;
2453                         break;
2454                 }
2455         } while (state != prev_state);
2456
2457         host->state = state;
2458 unlock:
2459         spin_unlock(&host->lock);
2460 }
2461
2462 /* push final bytes to part_buf, only use during push */
2463 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2464 {
2465         memcpy((void *)&host->part_buf, buf, cnt);
2466         host->part_buf_count = cnt;
2467 }
2468
2469 /* append bytes to part_buf, only use during push */
2470 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2471 {
2472         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2473         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2474         host->part_buf_count += cnt;
2475         return cnt;
2476 }
2477
2478 /* pull first bytes from part_buf, only use during pull */
2479 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2480 {
2481         cnt = min(cnt, (int)host->part_buf_count);
2482         if (cnt) {
2483                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2484                        cnt);
2485                 host->part_buf_count -= cnt;
2486                 host->part_buf_start += cnt;
2487         }
2488         return cnt;
2489 }
2490
2491 /* pull final bytes from the part_buf, assuming it's just been filled */
2492 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2493 {
2494         memcpy(buf, &host->part_buf, cnt);
2495         host->part_buf_start = cnt;
2496         host->part_buf_count = (1 << host->data_shift) - cnt;
2497 }
2498
2499 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2500 {
2501         struct mmc_data *data = host->data;
2502         int init_cnt = cnt;
2503
2504         /* try and push anything in the part_buf */
2505         if (unlikely(host->part_buf_count)) {
2506                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2507                 buf += len;
2508                 cnt -= len;
2509                 if (host->part_buf_count == 2) {
2510                         mci_writew(host, DATA(host->data_offset),
2511                                         host->part_buf16);
2512                         host->part_buf_count = 0;
2513                 }
2514         }
2515 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2516         if (unlikely((unsigned long)buf & 0x1)) {
2517                 while (cnt >= 2) {
2518                         u16 aligned_buf[64];
2519                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2520                         int items = len >> 1;
2521                         int i;
2522                         /* memcpy from input buffer into aligned buffer */
2523                         memcpy(aligned_buf, buf, len);
2524                         buf += len;
2525                         cnt -= len;
2526                         /* push data from aligned buffer into fifo */
2527                         for (i = 0; i < items; ++i)
2528                                 mci_writew(host, DATA(host->data_offset),
2529                                                 aligned_buf[i]);
2530                 }
2531         } else
2532 #endif
2533         {
2534                 u16 *pdata = buf;
2535                 for (; cnt >= 2; cnt -= 2)
2536                         mci_writew(host, DATA(host->data_offset), *pdata++);
2537                 buf = pdata;
2538         }
2539         /* put anything remaining in the part_buf */
2540         if (cnt) {
2541                 dw_mci_set_part_bytes(host, buf, cnt);
2542                  /* Push data if we have reached the expected data length */
2543                 if ((data->bytes_xfered + init_cnt) ==
2544                     (data->blksz * data->blocks))
2545                         mci_writew(host, DATA(host->data_offset),
2546                                    host->part_buf16);
2547         }
2548 }
2549
2550 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2551 {
2552 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2553         if (unlikely((unsigned long)buf & 0x1)) {
2554                 while (cnt >= 2) {
2555                         /* pull data from fifo into aligned buffer */
2556                         u16 aligned_buf[64];
2557                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2558                         int items = len >> 1;
2559                         int i;
2560                         for (i = 0; i < items; ++i)
2561                                 aligned_buf[i] = mci_readw(host,
2562                                                 DATA(host->data_offset));
2563                         /* memcpy from aligned buffer into output buffer */
2564                         memcpy(buf, aligned_buf, len);
2565                         buf += len;
2566                         cnt -= len;
2567                 }
2568         } else
2569 #endif
2570         {
2571                 u16 *pdata = buf;
2572                 for (; cnt >= 2; cnt -= 2)
2573                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2574                 buf = pdata;
2575         }
2576         if (cnt) {
2577                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2578                 dw_mci_pull_final_bytes(host, buf, cnt);
2579         }
2580 }
2581
2582 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2583 {
2584         struct mmc_data *data = host->data;
2585         int init_cnt = cnt;
2586
2587         /* try and push anything in the part_buf */
2588         if (unlikely(host->part_buf_count)) {
2589                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2590                 buf += len;
2591                 cnt -= len;
2592                 if (host->part_buf_count == 4) {
2593                         mci_writel(host, DATA(host->data_offset),
2594                                         host->part_buf32);
2595                         host->part_buf_count = 0;
2596                 }
2597         }
2598 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2599         if (unlikely((unsigned long)buf & 0x3)) {
2600                 while (cnt >= 4) {
2601                         u32 aligned_buf[32];
2602                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2603                         int items = len >> 2;
2604                         int i;
2605                         /* memcpy from input buffer into aligned buffer */
2606                         memcpy(aligned_buf, buf, len);
2607                         buf += len;
2608                         cnt -= len;
2609                         /* push data from aligned buffer into fifo */
2610                         for (i = 0; i < items; ++i)
2611                                 mci_writel(host, DATA(host->data_offset),
2612                                                 aligned_buf[i]);
2613                 }
2614         } else
2615 #endif
2616         {
2617                 u32 *pdata = buf;
2618                 for (; cnt >= 4; cnt -= 4)
2619                         mci_writel(host, DATA(host->data_offset), *pdata++);
2620                 buf = pdata;
2621         }
2622         /* put anything remaining in the part_buf */
2623         if (cnt) {
2624                 dw_mci_set_part_bytes(host, buf, cnt);
2625                  /* Push data if we have reached the expected data length */
2626                 if ((data->bytes_xfered + init_cnt) ==
2627                     (data->blksz * data->blocks))
2628                         mci_writel(host, DATA(host->data_offset),
2629                                    host->part_buf32);
2630         }
2631 }
2632
2633 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2634 {
2635 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2636         if (unlikely((unsigned long)buf & 0x3)) {
2637                 while (cnt >= 4) {
2638                         /* pull data from fifo into aligned buffer */
2639                         u32 aligned_buf[32];
2640                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2641                         int items = len >> 2;
2642                         int i;
2643                         for (i = 0; i < items; ++i)
2644                                 aligned_buf[i] = mci_readl(host,
2645                                                 DATA(host->data_offset));
2646                         /* memcpy from aligned buffer into output buffer */
2647                         memcpy(buf, aligned_buf, len);
2648                         buf += len;
2649                         cnt -= len;
2650                 }
2651         } else
2652 #endif
2653         {
2654                 u32 *pdata = buf;
2655                 for (; cnt >= 4; cnt -= 4)
2656                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2657                 buf = pdata;
2658         }
2659         if (cnt) {
2660                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2661                 dw_mci_pull_final_bytes(host, buf, cnt);
2662         }
2663 }
2664
2665 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2666 {
2667         struct mmc_data *data = host->data;
2668         int init_cnt = cnt;
2669
2670         /* try and push anything in the part_buf */
2671         if (unlikely(host->part_buf_count)) {
2672                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2673                 buf += len;
2674                 cnt -= len;
2675
2676                 if (host->part_buf_count == 8) {
2677                         mci_writeq(host, DATA(host->data_offset),
2678                                         host->part_buf);
2679                         host->part_buf_count = 0;
2680                 }
2681         }
2682 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2683         if (unlikely((unsigned long)buf & 0x7)) {
2684                 while (cnt >= 8) {
2685                         u64 aligned_buf[16];
2686                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2687                         int items = len >> 3;
2688                         int i;
2689                         /* memcpy from input buffer into aligned buffer */
2690                         memcpy(aligned_buf, buf, len);
2691                         buf += len;
2692                         cnt -= len;
2693                         /* push data from aligned buffer into fifo */
2694                         for (i = 0; i < items; ++i)
2695                                 mci_writeq(host, DATA(host->data_offset),
2696                                                 aligned_buf[i]);
2697                 }
2698         } else
2699 #endif
2700         {
2701                 u64 *pdata = buf;
2702                 for (; cnt >= 8; cnt -= 8)
2703                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2704                 buf = pdata;
2705         }
2706         /* put anything remaining in the part_buf */
2707         if (cnt) {
2708                 dw_mci_set_part_bytes(host, buf, cnt);
2709                 /* Push data if we have reached the expected data length */
2710                 if ((data->bytes_xfered + init_cnt) ==
2711                     (data->blksz * data->blocks))
2712                         mci_writeq(host, DATA(host->data_offset),
2713                                    host->part_buf);
2714         }
2715 }
2716
2717 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2718 {
2719 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2720         if (unlikely((unsigned long)buf & 0x7)) {
2721                 while (cnt >= 8) {
2722                         /* pull data from fifo into aligned buffer */
2723                         u64 aligned_buf[16];
2724                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2725                         int items = len >> 3;
2726                         int i;
2727                         for (i = 0; i < items; ++i)
2728                                 aligned_buf[i] = mci_readq(host,
2729                                                 DATA(host->data_offset));
2730                         /* memcpy from aligned buffer into output buffer */
2731                         memcpy(buf, aligned_buf, len);
2732                         buf += len;
2733                         cnt -= len;
2734                 }
2735         } else
2736 #endif
2737         {
2738                 u64 *pdata = buf;
2739                 for (; cnt >= 8; cnt -= 8)
2740                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2741                 buf = pdata;
2742         }
2743         if (cnt) {
2744                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2745                 dw_mci_pull_final_bytes(host, buf, cnt);
2746         }
2747 }
2748
2749 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2750 {
2751         int len;
2752
2753         /* get remaining partial bytes */
2754         len = dw_mci_pull_part_bytes(host, buf, cnt);
2755         if (unlikely(len == cnt))
2756                 return;
2757         buf += len;
2758         cnt -= len;
2759
2760         /* get the rest of the data */
2761         host->pull_data(host, buf, cnt);
2762 }
2763
2764 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2765 {
2766         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2767         void *buf;
2768         unsigned int offset;
2769         struct mmc_data *data = host->data;
2770         int shift = host->data_shift;
2771         u32 status;
2772         unsigned int len;
2773         unsigned int remain, fcnt;
2774
2775         if(!host->mmc->bus_refs){
2776                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2777                 goto host_put;
2778         }
2779         do {
2780                 if (!sg_miter_next(sg_miter))
2781                         goto done;
2782
2783                 host->sg = sg_miter->piter.sg;
2784                 buf = sg_miter->addr;
2785                 remain = sg_miter->length;
2786                 offset = 0;
2787
2788                 do {
2789                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2790                                         << shift) + host->part_buf_count;
2791                         len = min(remain, fcnt);
2792                         if (!len)
2793                                 break;
2794                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2795                         data->bytes_xfered += len;
2796                         offset += len;
2797                         remain -= len;
2798                 } while (remain);
2799
2800                 sg_miter->consumed = offset;
2801                 status = mci_readl(host, MINTSTS);
2802                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2803         /* if the RXDR is ready read again */
2804         } while ((status & SDMMC_INT_RXDR) ||
2805                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2806
2807         if (!remain) {
2808                 if (!sg_miter_next(sg_miter))
2809                         goto done;
2810                 sg_miter->consumed = 0;
2811         }
2812         sg_miter_stop(sg_miter);
2813         return;
2814
2815 done:
2816         sg_miter_stop(sg_miter);
2817 host_put:
2818         host->sg = NULL;
2819         smp_wmb();
2820         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2821 }
2822
2823 static void dw_mci_write_data_pio(struct dw_mci *host)
2824 {
2825         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2826         void *buf;
2827         unsigned int offset;
2828         struct mmc_data *data = host->data;
2829         int shift = host->data_shift;
2830         u32 status;
2831         unsigned int len;
2832         unsigned int fifo_depth = host->fifo_depth;
2833         unsigned int remain, fcnt;
2834
2835         if (!host->mmc->bus_refs){
2836                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2837                 goto host_put;
2838         }
2839
2840         do {
2841                 if (!sg_miter_next(sg_miter))
2842                         goto done;
2843
2844                 host->sg = sg_miter->piter.sg;
2845                 buf = sg_miter->addr;
2846                 remain = sg_miter->length;
2847                 offset = 0;
2848
2849                 do {
2850                         fcnt = ((fifo_depth -
2851                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2852                                         << shift) - host->part_buf_count;
2853                         len = min(remain, fcnt);
2854                         if (!len)
2855                                 break;
2856                         host->push_data(host, (void *)(buf + offset), len);
2857                         data->bytes_xfered += len;
2858                         offset += len;
2859                         remain -= len;
2860                 } while (remain);
2861
2862                 sg_miter->consumed = offset;
2863                 status = mci_readl(host, MINTSTS);
2864                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2865         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2866
2867         if (!remain) {
2868                 if (!sg_miter_next(sg_miter))
2869                         goto done;
2870                 sg_miter->consumed = 0;
2871         }
2872         sg_miter_stop(sg_miter);
2873         return;
2874
2875 done:
2876         sg_miter_stop(sg_miter);
2877 host_put:
2878         host->sg = NULL;
2879         smp_wmb();
2880         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2881 }
2882
2883 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2884 {
2885         if (!host->cmd_status)
2886             host->cmd_status = status;
2887
2888         if (!host->cmd)
2889                 goto cmd_exit;
2890
2891 cmd_exit:
2892         smp_wmb();
2893         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2894         tasklet_schedule(&host->tasklet);
2895 }
2896
2897 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2898 {
2899         struct dw_mci *host = dev_id;
2900         u32 pending, sdio_int;
2901         int i;
2902
2903         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2904
2905         /*
2906         * DTO fix - version 2.10a and below, and only if internal DMA
2907         * is configured.
2908         */
2909         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2910                         if (!pending &&
2911                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2912                                 pending |= SDMMC_INT_DATA_OVER;
2913         }
2914
2915         if (pending) {
2916                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2917                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2918                         host->cmd_status = pending;
2919                         smp_wmb();
2920                         MMC_DBG_INFO_FUNC(host->mmc,
2921                                 "%s cmd_status INT=0x%x,[%s]",
2922                                 __FUNCTION__, host->cmd_status,
2923                                 mmc_hostname(host->mmc));
2924
2925                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2926                 }
2927
2928                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2929                         /* if there is an error report DATA_ERROR */
2930                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2931                         host->data_status = pending;
2932                         smp_wmb();
2933                         printk(KERN_ERR "[%s] Data transmission error !!!!  MINTSTS: [0x%08x]\n",
2934                                mmc_hostname(host->mmc), pending);
2935                         mmc_retune_needed(host->mmc);
2936                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2937
2938                         MMC_DBG_INFO_FUNC(host->mmc,
2939                                 "%s data_status INT=0x%x,[%s]",
2940                                  __FUNCTION__, host->data_status,
2941                                  mmc_hostname(host->mmc));
2942                         tasklet_schedule(&host->tasklet);
2943                 }
2944
2945                 if (pending & SDMMC_INT_DATA_OVER) {
2946                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2947                         MMC_DBG_CMD_FUNC(host->mmc,
2948                                 "SDMMC_INT_DATA_OVER, INT-pending=0x%x [%s]",
2949                                 pending, mmc_hostname(host->mmc));
2950                         if (!host->data_status)
2951                                 host->data_status = pending;
2952                         smp_wmb();
2953                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2954                                 if (host->sg != NULL)
2955                                         dw_mci_read_data_pio(host, true);
2956                         }
2957                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2958                         tasklet_schedule(&host->tasklet);
2959                 }
2960
2961                 if (pending & SDMMC_INT_RXDR) {
2962                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2963                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2964                                 dw_mci_read_data_pio(host, false);
2965                 }
2966
2967                 if (pending & SDMMC_INT_TXDR) {
2968                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2969                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2970                                 dw_mci_write_data_pio(host);
2971                 }
2972
2973                 if (pending & SDMMC_INT_VSI) {
2974                         MMC_DBG_SW_VOL_FUNC(host->mmc,
2975                                 "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",
2976                                 pending, mmc_hostname(host->mmc));
2977                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2978                         dw_mci_cmd_interrupt(host, pending);
2979                 }
2980
2981                 if (pending & SDMMC_INT_CMD_DONE) {
2982                         MMC_DBG_CMD_FUNC(host->mmc,
2983                                 "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",
2984                                 mci_readl(host, CMD), pending, mmc_hostname(host->mmc));
2985                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2986                         dw_mci_cmd_interrupt(host, pending);
2987                 }
2988
2989                 if (pending & SDMMC_INT_CD) {
2990                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2991                         MMC_DBG_INFO_FUNC(host->mmc,
2992                                 "SDMMC_INT_CD, INT-pending=0x%x. [%s]",
2993                                 pending, mmc_hostname(host->mmc));
2994                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2995                         queue_work(host->card_workqueue, &host->card_work);
2996                 }
2997
2998                 if (pending & SDMMC_INT_HLE) {
2999                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
3000                         MMC_DBG_CMD_FUNC(host->mmc,
3001                                 "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",
3002                                 pending, mmc_hostname(host->mmc));
3003
3004                 }
3005
3006                 /* Handle SDIO Interrupts */
3007                 for (i = 0; i < host->num_slots; i++) {
3008                         struct dw_mci_slot *slot = host->slot[i];
3009
3010                         if (host->verid < DW_MMC_240A)
3011                                 sdio_int = SDMMC_INT_SDIO(i);
3012                         else
3013                                 sdio_int = SDMMC_INT_SDIO(i + 8);
3014
3015                         if (pending & sdio_int) {
3016                                 mci_writel(host, RINTSTS, sdio_int);
3017                                 mmc_signal_sdio_irq(slot->mmc);
3018                         }
3019                 }
3020
3021         }
3022
3023 #ifdef CONFIG_MMC_DW_IDMAC
3024         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3025         if (!(cpu_is_rk3036() || cpu_is_rk312x())){
3026                 /* Handle DMA interrupts */
3027                 pending = mci_readl(host, IDSTS);
3028                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3029                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3030                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3031                         host->dma_ops->complete((void *)host);
3032                 }
3033         }
3034 #endif
3035
3036         return IRQ_HANDLED;
3037 }
3038
3039 static void dw_mci_work_routine_card(struct work_struct *work)
3040 {
3041         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3042         int i;
3043
3044         for (i = 0; i < host->num_slots; i++) {
3045                 struct dw_mci_slot *slot = host->slot[i];
3046                 struct mmc_host *mmc = slot->mmc;
3047                 struct mmc_request *mrq;
3048                 int present;
3049
3050                 present = dw_mci_get_cd(mmc);
3051
3052                 /* Card insert, switch data line to uart function, and vice verse.
3053                 ONLY audi chip need switched by software, using udbg tag in dts!
3054                 */
3055                 if (!(IS_ERR(host->pins_udbg)) &&
3056                         !(IS_ERR(host->pins_default))) {
3057                         if (present) {
3058                                 if (pinctrl_select_state(host->pinctrl,
3059                                         host->pins_default) < 0)
3060                                         dev_err(host->dev,
3061                                                 "%s: Default pinctrl setting failed!\n",
3062                                                 mmc_hostname(host->mmc));
3063                         } else {
3064                                 if (pinctrl_select_state(host->pinctrl,
3065                                         host->pins_udbg) < 0)
3066                                         dev_err(host->dev,
3067                                                 "%s: Udbg pinctrl setting failed!\n",
3068                                                 mmc_hostname(host->mmc));
3069                         }
3070                 }
3071
3072                 while (present != slot->last_detect_state) {
3073                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
3074                                 present ? "inserted" : "removed");
3075                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
3076                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
3077
3078                         dw_mci_ctrl_all_reset(host);
3079                         /* Stop edma when rountine card triggered */
3080                         if(cpu_is_rk3036() || cpu_is_rk312x())
3081                                 if(host->dma_ops && host->dma_ops->stop)
3082                                         host->dma_ops->stop(host);
3083                         rk_send_wakeup_key();//wake up system
3084                         spin_lock_bh(&host->lock);
3085
3086                         /* Card change detected */
3087                         slot->last_detect_state = present;
3088
3089                         /* Clean up queue if present */
3090                         mrq = slot->mrq;
3091                         if (mrq) {
3092                                 if (mrq == host->mrq) {
3093                                         host->data = NULL;
3094                                         host->cmd = NULL;
3095
3096                                         switch (host->state) {
3097                                         case STATE_IDLE:
3098                                                 break;
3099                                         case STATE_SENDING_CMD:
3100                                                 mrq->cmd->error = -ENOMEDIUM;
3101                                                 if (!mrq->data)
3102                                                         break;
3103                                                 /* fall through */
3104                                         case STATE_SENDING_DATA:
3105                                                 mrq->data->error = -ENOMEDIUM;
3106                                                 dw_mci_stop_dma(host);
3107                                                 break;
3108                                         case STATE_DATA_BUSY:
3109                                         case STATE_DATA_ERROR:
3110                                                 if (mrq->data->error == -EINPROGRESS)
3111                                                         mrq->data->error = -ENOMEDIUM;
3112                                                 if (!mrq->stop)
3113                                                         break;
3114                                                 /* fall through */
3115                                         case STATE_SENDING_STOP:
3116                                                 mrq->stop->error = -ENOMEDIUM;
3117                                                 break;
3118                                         }
3119
3120                                         dw_mci_request_end(host, mrq);
3121                                 } else {
3122                                         list_del(&slot->queue_node);
3123                                         mrq->cmd->error = -ENOMEDIUM;
3124                                         if (mrq->data)
3125                                                 mrq->data->error = -ENOMEDIUM;
3126                                         if (mrq->stop)
3127                                                 mrq->stop->error = -ENOMEDIUM;
3128
3129                                         MMC_DBG_CMD_FUNC(host->mmc,
3130                                                 "dw_mci_work--reqeuest done, cmd=%d [%s]",
3131                                                 mrq->cmd->opcode, mmc_hostname(mmc));
3132
3133                                         spin_unlock(&host->lock);
3134                                         mmc_request_done(slot->mmc, mrq);
3135                                         spin_lock(&host->lock);
3136                                 }
3137                         }
3138
3139                         /* Power down slot */
3140                         if (present == 0) {
3141                                 /* Clear down the FIFO */
3142                                 dw_mci_fifo_reset(host);
3143 #ifdef CONFIG_MMC_DW_IDMAC
3144                                 if (!(cpu_is_rk3036() || cpu_is_rk312x()))
3145                                         dw_mci_idmac_reset(host);
3146 #endif
3147                         }
3148
3149                         spin_unlock_bh(&host->lock);
3150
3151                         present = dw_mci_get_cd(mmc);
3152                 }
3153
3154                 mmc_detect_change(slot->mmc,
3155                         msecs_to_jiffies(host->pdata->detect_delay_ms));
3156         }
3157 }
3158
3159 #ifdef CONFIG_OF
3160 /* given a slot id, find out the device node representing that slot */
3161 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3162 {
3163         struct device_node *np;
3164         const __be32 *addr;
3165         int len;
3166
3167         if (!dev || !dev->of_node)
3168                 return NULL;
3169
3170         for_each_child_of_node(dev->of_node, np) {
3171                 addr = of_get_property(np, "reg", &len);
3172                 if (!addr || (len < sizeof(int)))
3173                         continue;
3174                 if (be32_to_cpup(addr) == slot)
3175                         return np;
3176         }
3177         return NULL;
3178 }
3179
3180 static struct dw_mci_of_slot_quirks {
3181         char *quirk;
3182         int id;
3183 } of_slot_quirks[] = {
3184         {
3185                 .quirk  = "disable-wp",
3186                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3187         },
3188 };
3189
3190 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3191 {
3192         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3193         int quirks = 0;
3194         int idx;
3195
3196         /* get quirks */
3197         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3198                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3199                         quirks |= of_slot_quirks[idx].id;
3200
3201         return quirks;
3202 }
3203
3204 /* find out bus-width for a given slot */
3205 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3206 {
3207         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3208         u32 bus_wd = 1;
3209
3210         if (!np)
3211                 return 1;
3212
3213         if (of_property_read_u32(np, "bus-width", &bus_wd))
3214                 dev_err(dev, "bus-width property not found, assuming width"
3215                                " as 1\n");
3216         return bus_wd;
3217 }
3218
3219
3220 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3221 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3222 {
3223         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3224         int gpio;
3225
3226         if (!np)
3227                 return -EINVAL;
3228
3229         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3230
3231         /* Having a missing entry is valid; return silently */
3232         if (!gpio_is_valid(gpio))
3233                 return -EINVAL;
3234
3235         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3236                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3237                 return -EINVAL;
3238         }
3239
3240     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3241
3242         return gpio;
3243 }
3244
3245
3246 /* find the write protect gpio for a given slot; or -1 if none specified */
3247 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3248 {
3249         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3250         int gpio;
3251
3252         if (!np)
3253                 return -EINVAL;
3254
3255         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3256
3257         /* Having a missing entry is valid; return silently */
3258         if (!gpio_is_valid(gpio))
3259                 return -EINVAL;
3260
3261         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3262                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3263                 return -EINVAL;
3264         }
3265
3266         return gpio;
3267 }
3268
3269 /* find the cd gpio for a given slot */
3270 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3271                                         struct mmc_host *mmc)
3272 {
3273         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3274         int gpio;
3275
3276         if (!np)
3277                 return;
3278
3279         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3280
3281         /* Having a missing entry is valid; return silently */
3282         if (!gpio_is_valid(gpio))
3283                 return;
3284
3285         if (mmc_gpio_request_cd(mmc, gpio, 0))
3286                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3287 }
3288
3289 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3290 {
3291         struct mmc_host *mmc = dev_id;
3292         struct dw_mci_slot *slot = mmc_priv(mmc);
3293         struct dw_mci *host = slot->host;
3294         int gpio_cd = slot->cd_gpio;
3295
3296         (gpio_get_value(gpio_cd)  == 0) ?
3297                 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
3298                 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3299
3300         /* wakeup system whether gpio debounce or not */
3301         rk_send_wakeup_key();
3302
3303         /* no need to trigger detect flow when rescan is disabled.
3304            This case happended in dpm, that we just wakeup system and
3305            let suspend_post notify callback handle it.
3306          */
3307         if(mmc->rescan_disable == 0)
3308                 queue_work(host->card_workqueue, &host->card_work);
3309         else
3310                 printk("%s: rescan been disabled!\n", __FUNCTION__);
3311
3312         return IRQ_HANDLED;
3313 }
3314
3315 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3316                                         struct mmc_host *mmc)
3317 {
3318         struct dw_mci_slot *slot = mmc_priv(mmc);
3319         struct dw_mci *host = slot->host;
3320         int irq;
3321         int ret;
3322
3323         /* Having a missing entry is valid; return silently */
3324         if (!gpio_is_valid(gpio))
3325                 return;
3326
3327         irq = gpio_to_irq(gpio);
3328         if (irq >= 0) {
3329                 ret = devm_request_threaded_irq(
3330                                         &mmc->class_dev, irq,
3331                                         NULL, dw_mci_gpio_cd_irqt,
3332                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3333                                         "dw_mci_cd", mmc);
3334                 if (ret < 0) {
3335                         irq = ret;
3336                         dev_err(host->dev,
3337                                 "Request cd-gpio %d interrupt error!\n", gpio);
3338                 } else{
3339                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3340                         enable_irq_wake(irq);
3341                 }
3342         } else {
3343                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3344         }
3345 }
3346
3347 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3348                                         struct mmc_host *mmc)
3349 {
3350         if (!gpio_is_valid(gpio))
3351                 return;
3352
3353         if (gpio_to_irq(gpio) >= 0) {
3354                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3355                 devm_gpio_free(&mmc->class_dev, gpio);
3356         }
3357 }
3358 #else /* CONFIG_OF */
3359 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3360 {
3361         return 0;
3362 }
3363 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3364 {
3365         return 1;
3366 }
3367 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3368 {
3369         return NULL;
3370 }
3371 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3372 {
3373         return -EINVAL;
3374 }
3375 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3376                                         struct mmc_host *mmc)
3377 {
3378         return;
3379 }
3380 #endif /* CONFIG_OF */
3381
3382 /* @host: dw_mci host prvdata
3383  * Init pinctrl for each platform. Usually we assign
3384  * "defalut" tag for functional usage, "idle" tag for gpio
3385  * state and "udbg" tag for uart_dbg if any.
3386  */
3387 static void dw_mci_init_pinctrl(struct dw_mci *host)
3388 {
3389         /* Fixme: DON'T TOUCH EMMC SETTING! */
3390         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3391                 return;
3392
3393         /* Get pinctrl for DTS */
3394         host->pinctrl = devm_pinctrl_get(host->dev);
3395         if (IS_ERR(host->pinctrl)) {
3396                 dev_err(host->dev, "%s: No pinctrl used!\n",
3397                                 mmc_hostname(host->mmc));
3398                 return;
3399         }
3400
3401         /* Lookup idle state */
3402         host->pins_idle =
3403                 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_IDLE);
3404         if (IS_ERR(host->pins_idle)) {
3405                 dev_err(host->dev, "%s: No idle tag found!\n",
3406                                 mmc_hostname(host->mmc));
3407         } else {
3408                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3409                         dev_err(host->dev,
3410                                 "%s: Idle pinctrl setting failed!\n",
3411                                 mmc_hostname(host->mmc));
3412         }
3413
3414         /* Lookup default state */
3415         host->pins_default =
3416                 pinctrl_lookup_state(host->pinctrl, PINCTRL_STATE_DEFAULT);
3417         if (IS_ERR(host->pins_default)) {
3418                 dev_err(host->dev, "%s: No default pinctrl found!\n",
3419                 mmc_hostname(host->mmc));
3420         } else {
3421                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3422                         dev_err(host->dev,
3423                                 "%s:  Default pinctrl setting failed!\n",
3424                                 mmc_hostname(host->mmc));
3425         }
3426
3427         /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3428         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3429                 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3430                 if (IS_ERR(host->pins_udbg)) {
3431                         dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3432                                 mmc_hostname(host->mmc));
3433                 } else {
3434                         if (!dw_mci_get_cd(host->mmc))
3435                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3436                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3437                                                 mmc_hostname(host->mmc));
3438                 }
3439         }
3440 }
3441
3442 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3443                                         unsigned long mode, void *unused)
3444 {
3445         struct mmc_host *host = container_of(
3446                 notify_block, struct mmc_host, pm_notify);
3447         unsigned long flags;
3448
3449         switch (mode) {
3450         case PM_HIBERNATION_PREPARE:
3451         case PM_SUSPEND_PREPARE:
3452                 dev_err(host->parent,
3453                         "dw_mci_pm_notify:  suspend prepare\n");
3454                 spin_lock_irqsave(&host->lock, flags);
3455                 host->rescan_disable = 1;
3456                 spin_unlock_irqrestore(&host->lock, flags);
3457                 if (cancel_delayed_work(&host->detect))
3458                         wake_unlock(&host->detect_wake_lock);
3459                 break;
3460
3461         case PM_POST_SUSPEND:
3462         case PM_POST_HIBERNATION:
3463         case PM_POST_RESTORE:
3464                 dev_err(host->parent,
3465                         "dw_mci_pm_notify:  post suspend\n");
3466                 spin_lock_irqsave(&host->lock, flags);
3467                 host->rescan_disable = 0;
3468                 spin_unlock_irqrestore(&host->lock, flags);
3469                 mmc_detect_change(host, 10);
3470         }
3471
3472         return 0;
3473 }
3474
3475 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3476 {
3477         struct mmc_host *mmc;
3478         struct dw_mci_slot *slot;
3479         const struct dw_mci_drv_data *drv_data = host->drv_data;
3480         int ctrl_id, ret;
3481         u32 freq[2];
3482         u8 bus_width;
3483
3484         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3485         if (!mmc)
3486                 return -ENOMEM;
3487
3488         slot = mmc_priv(mmc);
3489         slot->id = id;
3490         slot->mmc = mmc;
3491         slot->host = host;
3492         host->slot[id] = slot;
3493         host->mmc = mmc;
3494
3495         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3496
3497         mmc->ops = &dw_mci_ops;
3498
3499         if (of_property_read_u32_array(host->dev->of_node,
3500                                        "clock-freq-min-max", freq, 2)) {
3501                 mmc->f_min = DW_MCI_FREQ_MIN;
3502                 mmc->f_max = DW_MCI_FREQ_MAX;
3503
3504                 printk("%s: fmin=%d, fmax=%d [%s]\n",
3505                          __FUNCTION__, mmc->f_min,
3506                          mmc->f_max, mmc_hostname(mmc));
3507         } else {
3508                 mmc->f_min = freq[0];
3509                 mmc->f_max = freq[1];
3510
3511                 printk("%s: fmin=%d, fmax=%d [%s]\n",
3512                          __FUNCTION__, mmc->f_min,
3513                          mmc->f_max, mmc_hostname(mmc));
3514         }
3515
3516         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3517                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3518         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3519                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3520         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3521                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3522
3523         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3524                 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3525                 if (register_pm_notifier(&mmc->pm_notify)) {
3526                         pr_err("dw_mci: register_pm_notifier failed\n");
3527                         goto err_pm_notifier;
3528                 }
3529         }
3530
3531         if (host->cid == DW_MCI_TYPE_RK3368) {
3532                 if (IS_ERR(host->grf))
3533                         pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3534                 else
3535                         /* Disable force_jtag */
3536                         regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3537         } else if (cpu_is_rk3288()) {
3538                 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3539         }
3540
3541         /* We assume only low-level chip use gpio_cd */
3542         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3543                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3544                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3545                 if (gpio_is_valid(slot->cd_gpio)) {
3546                         /* Request gpio int for card detection */
3547                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3548                 } else {
3549                         slot->cd_gpio = -ENODEV;
3550                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3551                 }
3552         }
3553
3554         if (host->pdata->get_ocr)
3555                 mmc->ocr_avail = host->pdata->get_ocr(id);
3556         else
3557         {
3558                 mmc->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
3559                                 MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33|
3560                                 MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36 |
3561                                 MMC_VDD_26_27 | MMC_VDD_25_26 | MMC_VDD_24_25 |
3562                                 MMC_VDD_23_24 | MMC_VDD_22_23 | MMC_VDD_21_22 |
3563                                 MMC_VDD_20_21 | MMC_VDD_165_195;
3564         }
3565
3566         /*
3567          * Start with slot power disabled, it will be enabled when a card
3568          * is detected.
3569          */
3570         if (host->pdata->setpower)
3571                 host->pdata->setpower(id, 0);
3572
3573         if (host->pdata->caps)
3574                 mmc->caps = host->pdata->caps;
3575
3576         if (host->pdata->pm_caps)
3577                 mmc->pm_caps = host->pdata->pm_caps;
3578
3579         if (host->dev->of_node) {
3580                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3581                 if (ctrl_id < 0)
3582                         ctrl_id = 0;
3583         } else {
3584                 ctrl_id = to_platform_device(host->dev)->id;
3585         }
3586         if (drv_data && drv_data->caps)
3587                 mmc->caps |= drv_data->caps[ctrl_id];
3588         if (drv_data && drv_data->hold_reg_flag)
3589                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3590
3591         /* set the compatibility of driver. */
3592         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3593                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3594
3595         if (host->pdata->caps2)
3596                 mmc->caps2 = host->pdata->caps2;
3597
3598         if (host->pdata->get_bus_wd)
3599                 bus_width = host->pdata->get_bus_wd(slot->id);
3600         else if (host->dev->of_node)
3601                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3602         else
3603                 bus_width = 1;
3604
3605         switch (bus_width) {
3606                 case 8:
3607                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3608                 case 4:
3609                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3610         }
3611
3612         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3613                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3614         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3615                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3616         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3617                 mmc->caps |= MMC_CAP_HW_RESET;
3618         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3619                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3620         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3621                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3622         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3623                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3624         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3625                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3626
3627         /*Assign pm_caps pass to pm_flags*/
3628         mmc->pm_flags = mmc->pm_caps;
3629
3630         if (host->pdata->blk_settings) {
3631                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3632                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3633                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3634                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3635                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3636         } else {
3637                 /* Useful defaults if platform data is unset. */
3638 #ifdef CONFIG_MMC_DW_IDMAC
3639                 mmc->max_segs = host->ring_size;
3640                 mmc->max_blk_size = 65536;
3641                 mmc->max_blk_count = host->ring_size;
3642                 mmc->max_seg_size = 0x1000;
3643                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3644                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3645                         /* fixup for external dmac setting */
3646                         mmc->max_segs = 64;
3647                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3648                         mmc->max_blk_count = 65535;
3649                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3650                         mmc->max_seg_size = mmc->max_req_size;
3651                 }
3652 #else
3653                 mmc->max_segs = 64;
3654                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3655                 mmc->max_blk_count = 512;
3656                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3657                 mmc->max_seg_size = mmc->max_req_size;
3658 #endif /* CONFIG_MMC_DW_IDMAC */
3659
3660         }
3661         /* pwr_en */
3662         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3663
3664         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3665         {
3666                 host->vmmc = NULL;
3667         }else{
3668
3669                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3670                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3671                 else
3672                         host->vmmc = NULL;
3673
3674                 if (IS_ERR(host->vmmc)) {
3675                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3676                         host->vmmc = NULL;
3677                 }else{
3678                         ret = regulator_enable(host->vmmc);
3679                         if (ret) {
3680                                 dev_err(host->dev,
3681                                         "failed to enable regulator: %d\n", ret);
3682                                 host->vmmc = NULL;
3683                                 goto err_setup_bus;
3684                         }
3685                 }
3686         }
3687
3688         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3689
3690         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3691                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3692
3693         dw_mci_init_pinctrl(host);
3694         ret = mmc_add_host(mmc);
3695         if (ret)
3696                 goto err_setup_bus;
3697
3698 #if defined(CONFIG_DEBUG_FS)
3699         dw_mci_init_debugfs(slot);
3700 #endif
3701
3702         /* Card initially undetected */
3703         slot->last_detect_state = 1;
3704
3705         return 0;
3706 err_pm_notifier:
3707         unregister_pm_notifier(&mmc->pm_notify);
3708
3709 err_setup_bus:
3710         if (gpio_is_valid(slot->cd_gpio))
3711                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3712         mmc_free_host(mmc);
3713         return -EINVAL;
3714 }
3715
3716 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3717 {
3718         /* Shutdown detect IRQ */
3719         if (slot->host->pdata->exit)
3720                 slot->host->pdata->exit(id);
3721
3722         /* Debugfs stuff is cleaned up by mmc core */
3723         mmc_remove_host(slot->mmc);
3724         slot->host->slot[id] = NULL;
3725         mmc_free_host(slot->mmc);
3726 }
3727
3728 static void dw_mci_init_dma(struct dw_mci *host)
3729 {
3730         /* Alloc memory for sg translation */
3731         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3732                                           &host->sg_dma, GFP_KERNEL);
3733         if (!host->sg_cpu) {
3734                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3735                         __func__);
3736                 goto no_dma;
3737         }
3738
3739         /* Determine which DMA interface to use */
3740 #if defined(CONFIG_MMC_DW_IDMAC)
3741         if(cpu_is_rk3036() || cpu_is_rk312x()){
3742                 host->dma_ops = &dw_mci_edmac_ops;
3743                 dev_info(host->dev, "Using external DMA controller.\n");
3744         }else{
3745                 host->dma_ops = &dw_mci_idmac_ops;
3746                 dev_info(host->dev, "Using internal DMA controller.\n");
3747         }
3748 #endif
3749
3750         if (!host->dma_ops)
3751                 goto no_dma;
3752
3753         if (host->dma_ops->init && host->dma_ops->start &&
3754             host->dma_ops->stop && host->dma_ops->cleanup) {
3755                 if (host->dma_ops->init(host)) {
3756                         dev_err(host->dev, "%s: Unable to initialize "
3757                                 "DMA Controller.\n", __func__);
3758                         goto no_dma;
3759                 }
3760         } else {
3761                 dev_err(host->dev, "DMA initialization not found.\n");
3762                 goto no_dma;
3763         }
3764
3765         host->use_dma = 1;
3766         return;
3767
3768 no_dma:
3769         dev_info(host->dev, "Using PIO mode.\n");
3770         host->use_dma = 0;
3771         return;
3772 }
3773
3774 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3775 {
3776         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3777         u32 ctrl;
3778
3779         ctrl = mci_readl(host, CTRL);
3780         ctrl |= reset;
3781         mci_writel(host, CTRL, ctrl);
3782
3783         /* wait till resets clear */
3784         do {
3785                 ctrl = mci_readl(host, CTRL);
3786                 if (!(ctrl & reset))
3787                         return true;
3788         } while (time_before(jiffies, timeout));
3789
3790         dev_err(host->dev,
3791                 "Timeout resetting block (ctrl reset %#x)\n",
3792                 ctrl & reset);
3793
3794         return false;
3795 }
3796
3797 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3798 {
3799         /*
3800          * Reseting generates a block interrupt, hence setting
3801          * the scatter-gather pointer to NULL.
3802          */
3803         if (host->sg) {
3804                 sg_miter_stop(&host->sg_miter);
3805                 host->sg = NULL;
3806         }
3807
3808         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3809 }
3810
3811 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3812 {
3813         return dw_mci_ctrl_reset(host,
3814                                  SDMMC_CTRL_FIFO_RESET |
3815                                  SDMMC_CTRL_RESET |
3816                                  SDMMC_CTRL_DMA_RESET);
3817 }
3818
3819 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3820 {
3821         u32 index;
3822         u32 *buffer;
3823
3824         buffer = host->regs_buffer;
3825
3826         for (index = 0; index < DW_REGS_NUM ; index++){
3827                 *buffer = mci_readreg(host, index*4);
3828                 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3829                         dw_mci_regs[index].name, *buffer);
3830                 buffer++;
3831         }
3832
3833         *buffer = mci_readl(host,CDTHRCTL);
3834         MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3835 }
3836
3837 static void dw_mci_rst_post_resume(struct dw_mci *host)
3838 {
3839         u32 index;
3840         u32 *buffer;
3841
3842         buffer = host->regs_buffer;
3843
3844         for (index = 0; index < DW_REGS_NUM; index++){
3845                 mci_writereg(host, index*4, *buffer);
3846                 buffer++;
3847         }
3848         mci_writel(host, CDTHRCTL, *buffer);
3849 }
3850
3851 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3852         .pre_suspend = dw_mci_rst_pre_suspend,
3853         .post_resume = dw_mci_rst_post_resume,
3854 };
3855
3856 #ifdef CONFIG_OF
3857 /*
3858 static struct dw_mci_of_quirks {
3859         char *quirk;
3860         int id;
3861 } of_quirks[] = {
3862         {
3863                 .quirk  = "broken-cd",
3864                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3865         },
3866 };
3867 */
3868 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3869 {
3870         struct dw_mci_board *pdata;
3871         struct device *dev = host->dev;
3872         struct device_node *np = dev->of_node;
3873         const struct dw_mci_drv_data *drv_data = host->drv_data;
3874         int  ret;
3875         u32 clock_frequency;
3876
3877         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3878         if (!pdata) {
3879                 dev_err(dev, "could not allocate memory for pdata\n");
3880                 return ERR_PTR(-ENOMEM);
3881         }
3882
3883         /* find out number of slots supported */
3884         if (of_property_read_u32(dev->of_node, "num-slots",
3885                                 &pdata->num_slots)) {
3886                 dev_info(dev, "num-slots property not found, "
3887                                 "assuming 1 slot is available\n");
3888                 pdata->num_slots = 1;
3889         }
3890
3891         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3892                 dev_info(dev, "fifo-depth property not found, using "
3893                                 "value of FIFOTH register as default\n");
3894
3895         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3896
3897         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3898                 pdata->bus_hz = clock_frequency;
3899
3900         if (drv_data && drv_data->parse_dt) {
3901                 ret = drv_data->parse_dt(host);
3902                 if (ret)
3903                         return ERR_PTR(ret);
3904         }
3905
3906         if (of_find_property(np, "keep-power-in-suspend", NULL))
3907                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3908
3909         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3910                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3911
3912         if (of_find_property(np, "supports-highspeed", NULL))
3913                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3914
3915         if (of_find_property(np, "supports-UHS_SDR104", NULL))
3916                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3917
3918         if (of_find_property(np, "supports-DDR_MODE", NULL))
3919                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3920
3921         if (of_find_property(np, "caps2-mmc-hs200", NULL))
3922                 pdata->caps2 |= MMC_CAP2_HS200;
3923
3924         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3925                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3926
3927         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3928                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3929
3930         if (of_get_property(np, "cd-inverted", NULL))
3931                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3932
3933         if (of_get_property(np, "bootpart-no-access", NULL))
3934                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3935
3936         if (of_get_property(np, "controller-power-down", NULL)) {
3937                 host->regs_buffer =
3938                         (u32 *)devm_kzalloc(host->dev,
3939                                             DW_REGS_SIZE, GFP_KERNEL);
3940                 if (!host->regs_buffer) {
3941                         dev_err(host->dev,
3942                                 "could not allocate memory for regs_buffer\n");
3943                         return ERR_PTR(-ENOMEM);
3944                 }
3945
3946                 host->rst_ops = &dw_mci_pdrst_ops;
3947         }
3948
3949         if (of_get_property(np, "assume_removable", NULL))
3950                 mmc_assume_removable = 0;
3951
3952         return pdata;
3953 }
3954
3955 #else /* CONFIG_OF */
3956 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3957 {
3958         return ERR_PTR(-EINVAL);
3959 }
3960 #endif /* CONFIG_OF */
3961
3962 int dw_mci_probe(struct dw_mci *host)
3963 {
3964         const struct dw_mci_drv_data *drv_data = host->drv_data;
3965         int width, i, ret = 0;
3966         u32 fifo_size;
3967         int init_slots = 0;
3968         u32 regs;
3969
3970         if (!host->pdata) {
3971                 host->pdata = dw_mci_parse_dt(host);
3972                 if (IS_ERR(host->pdata)) {
3973                         dev_err(host->dev, "platform data not available\n");
3974                         return -EINVAL;
3975                 }
3976         }
3977
3978         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3979                 dev_err(host->dev,
3980                         "Platform data must supply select_slot function\n");
3981                 return -ENODEV;
3982         }
3983
3984         /*
3985          * In 2.40a spec, Data offset is changed.
3986          * Need to check the version-id and set data-offset for DATA register.
3987          */
3988         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3989         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3990
3991         if (host->verid < DW_MMC_240A)
3992                 host->data_offset = DATA_OFFSET;
3993         else
3994                 host->data_offset = DATA_240A_OFFSET;
3995
3996         //hpclk enable
3997         host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
3998         if (IS_ERR(host->hpclk_mmc)) {
3999                 dev_err(host->dev, "failed to get hpclk_mmc\n");
4000         } else {
4001                 clk_prepare_enable(host->hpclk_mmc);
4002         }
4003
4004         //hclk enable
4005         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
4006         if (IS_ERR(host->hclk_mmc)) {
4007                 dev_err(host->dev, "failed to get hclk_mmc\n");
4008                 ret = PTR_ERR(host->hclk_mmc);
4009                 goto err_hclk_mmc;
4010         }
4011
4012         clk_prepare_enable(host->hclk_mmc);
4013
4014         //mmc clk enable
4015         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
4016         if (IS_ERR(host->clk_mmc)) {
4017                 dev_err(host->dev, "failed to get clk mmc_per\n");
4018                 ret = PTR_ERR(host->clk_mmc);
4019                 goto err_clk_mmc;
4020         }
4021
4022         host->bus_hz = host->pdata->bus_hz;
4023         if (!host->bus_hz) {
4024                 dev_err(host->dev, "Platform data must supply bus speed\n");
4025                 ret = -ENODEV;
4026                 goto err_clk_mmc;
4027         }
4028
4029         if (host->verid < DW_MMC_240A)
4030                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4031         else
4032                 //rockchip: fix divider 2 in clksum before controlller
4033                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4034
4035         if(ret < 0) {
4036                 dev_err(host->dev, "failed to set clk mmc\n");
4037                 goto err_clk_mmc;
4038         }
4039         clk_prepare_enable(host->clk_mmc);
4040
4041         if (drv_data && drv_data->setup_clock) {
4042                 ret = drv_data->setup_clock(host);
4043                 if (ret) {
4044                         dev_err(host->dev,
4045                         "implementation specific clock setup failed\n");
4046                         goto err_clk_mmc;
4047                 }
4048         }
4049
4050         host->quirks = host->pdata->quirks;
4051         host->irq_state = true;
4052         host->set_speed = 0;
4053         host->set_div = 0;
4054         host->svi_flags = 0;
4055
4056         spin_lock_init(&host->lock);
4057         spin_lock_init(&host->slock);
4058
4059         INIT_LIST_HEAD(&host->queue);
4060         /*
4061          * Get the host data width - this assumes that HCON has been set with
4062          * the correct values.
4063          */
4064         i = (mci_readl(host, HCON) >> 7) & 0x7;
4065         if (!i) {
4066                 host->push_data = dw_mci_push_data16;
4067                 host->pull_data = dw_mci_pull_data16;
4068                 width = 16;
4069                 host->data_shift = 1;
4070         } else if (i == 2) {
4071                 host->push_data = dw_mci_push_data64;
4072                 host->pull_data = dw_mci_pull_data64;
4073                 width = 64;
4074                 host->data_shift = 3;
4075         } else {
4076                 /* Check for a reserved value, and warn if it is */
4077                 WARN((i != 1),
4078                      "HCON reports a reserved host data width!\n"
4079                      "Defaulting to 32-bit access.\n");
4080                 host->push_data = dw_mci_push_data32;
4081                 host->pull_data = dw_mci_pull_data32;
4082                 width = 32;
4083                 host->data_shift = 2;
4084         }
4085
4086         /* Reset all blocks */
4087         if (!dw_mci_ctrl_all_reset(host))
4088                 return -ENODEV;
4089
4090         init_dma_attrs(&dw_mci_direct_attrs);
4091         dma_set_attr(DMA_ATTR_SKIP_CPU_SYNC, &dw_mci_direct_attrs);
4092
4093         host->dma_ops = host->pdata->dma_ops;
4094         dw_mci_init_dma(host);
4095
4096         /* Clear the interrupts for the host controller */
4097         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4098         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4099
4100         /* Put in max timeout */
4101         mci_writel(host, TMOUT, 0xFFFFFFFF);
4102
4103         /*
4104          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
4105          *                          Tx Mark = fifo_size / 2 DMA Size = 8
4106          */
4107         if (!host->pdata->fifo_depth) {
4108                 /*
4109                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4110                  * have been overwritten by the bootloader, just like we're
4111                  * about to do, so if you know the value for your hardware, you
4112                  * should put it in the platform data.
4113                  */
4114                 fifo_size = mci_readl(host, FIFOTH);
4115                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4116         } else {
4117                 fifo_size = host->pdata->fifo_depth;
4118         }
4119         host->fifo_depth = fifo_size;
4120         host->fifoth_val =
4121                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4122         mci_writel(host, FIFOTH, host->fifoth_val);
4123
4124         /* disable clock to CIU */
4125         mci_writel(host, CLKENA, 0);
4126         mci_writel(host, CLKSRC, 0);
4127
4128         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4129         host->card_workqueue = alloc_workqueue("dw-mci-card",
4130                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4131         if (!host->card_workqueue) {
4132                 ret = -ENOMEM;
4133                 goto err_dmaunmap;
4134         }
4135         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4136         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4137                                host->irq_flags, "dw-mci", host);
4138         if (ret)
4139                 goto err_workqueue;
4140
4141         if (host->pdata->num_slots)
4142                 host->num_slots = host->pdata->num_slots;
4143         else
4144                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4145
4146         /* We need at least one slot to succeed */
4147         for (i = 0; i < host->num_slots; i++) {
4148                 ret = dw_mci_init_slot(host, i);
4149                 if (ret)
4150                         dev_dbg(host->dev, "slot %d init failed\n", i);
4151                 else
4152                         init_slots++;
4153         }
4154
4155         /*
4156          * Enable interrupts for command done, data over, data empty, card det,
4157          * receive ready and error such as transmit, receive timeout, crc error
4158          */
4159         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4160         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4161                 SDMMC_INT_VSI | SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4162         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4163                 !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4164                 regs |= SDMMC_INT_CD;
4165
4166         mci_writel(host, INTMASK, regs);
4167
4168         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4169
4170         dev_info(host->dev, "DW MMC controller at irq %d, "
4171                  "%d bit host data width, "
4172                  "%u deep fifo\n",
4173                  host->irq, width, fifo_size);
4174
4175         if (init_slots) {
4176                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4177         } else {
4178                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4179                                         "but failed on all\n", host->num_slots);
4180                 goto err_workqueue;
4181         }
4182
4183
4184         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4185                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4186
4187         return 0;
4188
4189 err_workqueue:
4190         destroy_workqueue(host->card_workqueue);
4191
4192 err_dmaunmap:
4193         if (host->use_dma && host->dma_ops->exit)
4194                 host->dma_ops->exit(host);
4195
4196         if (host->vmmc){
4197                 regulator_disable(host->vmmc);
4198                 regulator_put(host->vmmc);
4199         }
4200
4201 err_clk_mmc:
4202         if (!IS_ERR(host->clk_mmc))
4203                 clk_disable_unprepare(host->clk_mmc);
4204 err_hclk_mmc:
4205         if (!IS_ERR(host->hclk_mmc))
4206                 clk_disable_unprepare(host->hclk_mmc);
4207         return ret;
4208 }
4209 EXPORT_SYMBOL(dw_mci_probe);
4210
4211 void dw_mci_remove(struct dw_mci *host)
4212 {
4213         struct mmc_host *mmc = host->mmc;
4214         struct dw_mci_slot *slot = mmc_priv(mmc);
4215         int i;
4216
4217         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4218         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4219
4220         for(i = 0; i < host->num_slots; i++){
4221                 dev_dbg(host->dev, "remove slot %d\n", i);
4222                 if(host->slot[i])
4223                         dw_mci_cleanup_slot(host->slot[i], i);
4224         }
4225
4226         /* disable clock to CIU */
4227         mci_writel(host, CLKENA, 0);
4228         mci_writel(host, CLKSRC, 0);
4229
4230         destroy_workqueue(host->card_workqueue);
4231         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4232                 unregister_pm_notifier(&host->mmc->pm_notify);
4233
4234         if (host->use_dma && host->dma_ops->exit)
4235                 host->dma_ops->exit(host);
4236
4237         if (gpio_is_valid(slot->cd_gpio))
4238                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4239
4240         if (host->vmmc){
4241                 regulator_disable(host->vmmc);
4242                 regulator_put(host->vmmc);
4243         }
4244         if (!IS_ERR(host->clk_mmc))
4245                 clk_disable_unprepare(host->clk_mmc);
4246
4247         if (!IS_ERR(host->hclk_mmc))
4248                 clk_disable_unprepare(host->hclk_mmc);
4249         if (!IS_ERR(host->hpclk_mmc))
4250                 clk_disable_unprepare(host->hpclk_mmc);
4251 }
4252 EXPORT_SYMBOL(dw_mci_remove);
4253
4254
4255
4256 #ifdef CONFIG_PM_SLEEP
4257 /*
4258  * TODO: we should probably disable the clock to the card in the suspend path.
4259  */
4260 extern int get_wifi_chip_type(void);
4261 int dw_mci_suspend(struct dw_mci *host)
4262 {
4263         int present = dw_mci_get_cd(host->mmc);
4264
4265         if((host->mmc->restrict_caps &
4266                 RESTRICT_CARD_TYPE_SDIO) &&
4267                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4268                 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4269                 return 0;
4270
4271         if(host->vmmc)
4272                 regulator_disable(host->vmmc);
4273
4274         /* Only for sdmmc controller */
4275         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4276                 disable_irq(host->irq);
4277                 if (present) {
4278                         if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4279                                 MMC_DBG_ERR_FUNC(host->mmc,
4280                                         "Idle pinctrl setting failed! [%s]",
4281                                         mmc_hostname(host->mmc));
4282                 }
4283
4284                 /* Soc rk3126/3036 already in gpio_cd mode */
4285                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4286                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4287                         enable_irq_wake(host->mmc->slot.cd_irq);
4288                 }
4289         }
4290
4291         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4292         mci_writel(host, INTMASK, 0x00);
4293         mci_writel(host, CTRL, 0x00);
4294
4295         if (host->rst_ops &&
4296                 host->rst_ops->pre_suspend)
4297                 host->rst_ops->pre_suspend(host);
4298
4299         return 0;
4300 }
4301 EXPORT_SYMBOL(dw_mci_suspend);
4302
4303 int dw_mci_resume(struct dw_mci *host)
4304 {
4305         int i, ret;
4306         u32 regs;
4307         struct dw_mci_slot *slot;
4308         int present = dw_mci_get_cd(host->mmc);
4309
4310         if (host->rst_ops &&
4311                 host->rst_ops->post_resume)
4312                 host->rst_ops->post_resume(host);
4313
4314
4315         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4316                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4317                         get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4318                 return 0;
4319
4320         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4321                 slot = mmc_priv(host->mmc);
4322                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4323                         return 0;
4324         }
4325
4326         /*only for sdmmc controller*/
4327         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4328                 /* Soc rk3126/3036 already in gpio_cd mode */
4329                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4330                         disable_irq_wake(host->mmc->slot.cd_irq);
4331                         mmc_gpio_free_cd(host->mmc);
4332                 }
4333
4334                 if (!present) {
4335                         if (!IS_ERR(host->pins_udbg)) {
4336                                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4337                                         MMC_DBG_ERR_FUNC(host->mmc,
4338                                                 "Idle pinctrl setting failed! [%s]",
4339                                                 mmc_hostname(host->mmc));
4340                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4341                                         MMC_DBG_ERR_FUNC(host->mmc,
4342                                                 "Udbg pinctrl setting failed! [%s]",
4343                                                 mmc_hostname(host->mmc));
4344                         } else {
4345                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4346                                         MMC_DBG_ERR_FUNC(host->mmc,
4347                                                 "Default pinctrl setting failed! [%s]",
4348                                                 mmc_hostname(host->mmc));
4349                         }
4350                 } else {
4351                         if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4352                                 MMC_DBG_ERR_FUNC(host->mmc,
4353                                         "Default pinctrl setting failed! [%s]",
4354                                         mmc_hostname(host->mmc));
4355                 }
4356
4357                 /* Disable jtag*/
4358                 if (cpu_is_rk3288())
4359                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4360                 else if (cpu_is_rk3036())
4361                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4362                 else if (cpu_is_rk312x())
4363                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4364                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4365         }
4366         if (host->vmmc){
4367                 ret = regulator_enable(host->vmmc);
4368                 if (ret){
4369                         dev_err(host->dev,
4370                                 "failed to enable regulator: %d\n", ret);
4371                         return ret;
4372                 }
4373         }
4374
4375         if (!dw_mci_ctrl_all_reset(host)){
4376                 ret = -ENODEV;
4377                 return ret;
4378         }
4379
4380         if (!(cpu_is_rk3036() || cpu_is_rk312x()))
4381                 if(host->use_dma && host->dma_ops->init)
4382                         host->dma_ops->init(host);
4383
4384         /*
4385          * Restore the initial value at FIFOTH register
4386          * And Invalidate the prev_blksz with zero
4387          */
4388         mci_writel(host, FIFOTH, host->fifoth_val);
4389         host->prev_blksz = 0;
4390         /* Put in max timeout */
4391         mci_writel(host, TMOUT, 0xFFFFFFFF);
4392
4393         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4394         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4395                 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4396
4397         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4398             regs |= SDMMC_INT_CD;
4399
4400         mci_writel(host, INTMASK, regs);
4401         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4402
4403         /* Only for sdmmc controller */
4404         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
4405                 enable_irq(host->irq);
4406
4407         for (i = 0; i < host->num_slots; i++){
4408                 struct dw_mci_slot *slot = host->slot[i];
4409                 if (!slot)
4410                         continue;
4411                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4412                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4413                         dw_mci_setup_bus(slot, true);
4414                 }
4415         }
4416
4417         return 0;
4418 }
4419 EXPORT_SYMBOL(dw_mci_resume);
4420 #endif /* CONFIG_PM_SLEEP */
4421
4422 static int __init dw_mci_init(void)
4423 {
4424         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4425         pr_info("MHSC version = %s\n", RK_SDMMC_DRIVER_VERSION);
4426         return 0;
4427 }
4428
4429 static void __exit dw_mci_exit(void)
4430 {
4431 }
4432
4433 module_init(dw_mci_init);
4434 module_exit(dw_mci_exit);
4435
4436 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4437 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4438 MODULE_LICENSE("GPL v2");