drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/card.h>
  37 #include <linux/mmc/sdio.h>
  38 #include <linux/mmc/rk_mmc.h>
  39 #include <linux/bitops.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/of.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/mmc/slot-gpio.h>
  45 #include <linux/clk-private.h>
  46 #include <linux/rockchip/cpu.h>
  47
  48 #include "rk_sdmmc.h"
  49 #include "rk_sdmmc_dbg.h"
  50 #include <linux/regulator/rockchip_io_vol_domain.h>
  51 #include "../../clk/rockchip/clk-ops.h"
  52
  53 #define RK_SDMMC_DRIVER_VERSION "Ver 1.12 2014-07-08"
  54
  55 /* Common flag combinations */
  56 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  57                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  58                                  SDMMC_INT_EBE)
  59 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  60                                  SDMMC_INT_RESP_ERR)
  61 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  62                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  63 #define DW_MCI_SEND_STATUS      1
  64 #define DW_MCI_RECV_STATUS      2
  65 #define DW_MCI_DMA_THRESHOLD    16
  66
  67 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  68 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  69
  70 /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  71 #define SDMMC_DATA_TIMEOUT_SD   500
  72 #define SDMMC_DATA_TIMEOUT_SDIO 250
  73 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  74
  75 #define SDMMC_CMD_RTO_MAX_HOLD  200
  76 #define SDMMC_WAIT_FOR_UNBUSY   2500
  77
  78 #ifdef CONFIG_MMC_DW_IDMAC
  79 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  80                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  81                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  82                                  SDMMC_IDMAC_INT_TI)
  83
  84 struct idmac_desc {
  85         u32             des0;   /* Control Descriptor */
  86 #define IDMAC_DES0_DIC  BIT(1)
  87 #define IDMAC_DES0_LD   BIT(2)
  88 #define IDMAC_DES0_FD   BIT(3)
  89 #define IDMAC_DES0_CH   BIT(4)
  90 #define IDMAC_DES0_ER   BIT(5)
  91 #define IDMAC_DES0_CES  BIT(30)
  92 #define IDMAC_DES0_OWN  BIT(31)
  93
  94         u32             des1;   /* Buffer sizes */
  95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  96         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  97
  98         u32             des2;   /* buffer 1 physical address */
  99
 100         u32             des3;   /* buffer 2 physical address */
 101 };
 102 #endif /* CONFIG_MMC_DW_IDMAC */
 103
 104 static const u8 tuning_blk_pattern_4bit[] = {
 105         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 106         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 107         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 108         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 109         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 110         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 111         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 112         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 113 };
 114
 115 static const u8 tuning_blk_pattern_8bit[] = {
 116         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 117         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 118         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 119         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 120         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 121         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 122         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 123         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 124         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 125         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 126         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 127         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 128         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 129         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 130         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 131         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 132 };
 133
 134 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 135 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 136 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 137 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 138
 139 /*printk the all register of current host*/
 140 #if 0
 141 static int dw_mci_regs_printk(struct dw_mci *host)
 142 {
 143     struct sdmmc_reg *regs = dw_mci_regs;
 144
 145     while( regs->name != 0 ){
 146         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 147         regs++;
 148     }
 149     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 150     return 0;
 151 }
 152 #endif
 153
 154 #if defined(CONFIG_DEBUG_FS)
 155 static int dw_mci_req_show(struct seq_file *s, void *v)
 156 {
 157         struct dw_mci_slot *slot = s->private;
 158         struct mmc_request *mrq;
 159         struct mmc_command *cmd;
 160         struct mmc_command *stop;
 161         struct mmc_data *data;
 162
 163         /* Make sure we get a consistent snapshot */
 164         spin_lock_bh(&slot->host->lock);
 165         mrq = slot->mrq;
 166
 167         if (mrq) {
 168                 cmd = mrq->cmd;
 169                 data = mrq->data;
 170                 stop = mrq->stop;
 171
 172                 if (cmd)
 173                         seq_printf(s,
 174                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 175                                    cmd->opcode, cmd->arg, cmd->flags,
 176                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 177                                    cmd->resp[2], cmd->error);
 178                 if (data)
 179                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 180                                    data->bytes_xfered, data->blocks,
 181                                    data->blksz, data->flags, data->error);
 182                 if (stop)
 183                         seq_printf(s,
 184                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 185                                    stop->opcode, stop->arg, stop->flags,
 186                                    stop->resp[0], stop->resp[1], stop->resp[2],
 187                                    stop->resp[2], stop->error);
 188         }
 189
 190         spin_unlock_bh(&slot->host->lock);
 191
 192         return 0;
 193 }
 194
 195 static int dw_mci_req_open(struct inode *inode, struct file *file)
 196 {
 197         return single_open(file, dw_mci_req_show, inode->i_private);
 198 }
 199
 200 static const struct file_operations dw_mci_req_fops = {
 201         .owner          = THIS_MODULE,
 202         .open           = dw_mci_req_open,
 203         .read           = seq_read,
 204         .llseek         = seq_lseek,
 205         .release        = single_release,
 206 };
 207
 208 static int dw_mci_regs_show(struct seq_file *s, void *v)
 209 {
 210         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 211         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 212         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 213         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 214         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 215         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 216
 217         return 0;
 218 }
 219
 220 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 221 {
 222         return single_open(file, dw_mci_regs_show, inode->i_private);
 223 }
 224
 225 static const struct file_operations dw_mci_regs_fops = {
 226         .owner          = THIS_MODULE,
 227         .open           = dw_mci_regs_open,
 228         .read           = seq_read,
 229         .llseek         = seq_lseek,
 230         .release        = single_release,
 231 };
 232
 233 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 234 {
 235         struct mmc_host *mmc = slot->mmc;
 236         struct dw_mci *host = slot->host;
 237         struct dentry *root;
 238         struct dentry *node;
 239
 240         root = mmc->debugfs_root;
 241         if (!root)
 242                 return;
 243
 244         node = debugfs_create_file("regs", S_IRUSR, root, host,
 245                                    &dw_mci_regs_fops);
 246         if (!node)
 247                 goto err;
 248
 249         node = debugfs_create_file("req", S_IRUSR, root, slot,
 250                                    &dw_mci_req_fops);
 251         if (!node)
 252                 goto err;
 253
 254         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 255         if (!node)
 256                 goto err;
 257
 258         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 259                                   (u32 *)&host->pending_events);
 260         if (!node)
 261                 goto err;
 262
 263         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 264                                   (u32 *)&host->completed_events);
 265         if (!node)
 266                 goto err;
 267
 268         return;
 269
 270 err:
 271         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 272 }
 273 #endif /* defined(CONFIG_DEBUG_FS) */
 274
 275 static void dw_mci_set_timeout(struct dw_mci *host)
 276 {
 277         /* timeout (maximum) */
 278         mci_writel(host, TMOUT, 0xffffffff);
 279 }
 280
 281 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 282 {
 283         struct mmc_data *data;
 284         struct dw_mci_slot *slot = mmc_priv(mmc);
 285         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 286         u32 cmdr;
 287         cmd->error = -EINPROGRESS;
 288
 289         cmdr = cmd->opcode;
 290
 291         if (cmdr == MMC_STOP_TRANSMISSION)
 292                 cmdr |= SDMMC_CMD_STOP;
 293         else
 294                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 295
 296         if (cmd->flags & MMC_RSP_PRESENT) {
 297                 /* We expect a response, so set this bit */
 298                 cmdr |= SDMMC_CMD_RESP_EXP;
 299                 if (cmd->flags & MMC_RSP_136)
 300                         cmdr |= SDMMC_CMD_RESP_LONG;
 301         }
 302
 303         if (cmd->flags & MMC_RSP_CRC)
 304                 cmdr |= SDMMC_CMD_RESP_CRC;
 305
 306         data = cmd->data;
 307         if (data) {
 308                 cmdr |= SDMMC_CMD_DAT_EXP;
 309                 if (data->flags & MMC_DATA_STREAM)
 310                         cmdr |= SDMMC_CMD_STRM_MODE;
 311                 if (data->flags & MMC_DATA_WRITE)
 312                         cmdr |= SDMMC_CMD_DAT_WR;
 313         }
 314
 315         if (drv_data && drv_data->prepare_command)
 316                 drv_data->prepare_command(slot->host, &cmdr);
 317
 318         return cmdr;
 319 }
 320
 321 #if 0
 322 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 323 {
 324         struct mmc_command *stop;
 325         u32 cmdr;
 326
 327         if (!cmd->data)
 328                 return 0;
 329
 330         stop = &host->stop_abort;
 331         cmdr = cmd->opcode;
 332         memset(stop, 0, sizeof(struct mmc_command));
 333
 334         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 335             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 336             cmdr == MMC_WRITE_BLOCK ||
 337             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 338                 stop->opcode = MMC_STOP_TRANSMISSION;
 339                 stop->arg = 0;
 340                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 341         } else if (cmdr == SD_IO_RW_EXTENDED) {
 342                 stop->opcode = SD_IO_RW_DIRECT;
 343                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 344                              ((cmd->arg >> 28) & 0x7);
 345                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 346         } else {
 347                 return 0;
 348         }
 349
 350         cmdr = stop->opcode | SDMMC_CMD_STOP |
 351                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 352
 353         return cmdr;
 354 }
 355 #endif
 356 static void dw_mci_start_command(struct dw_mci *host,
 357                                  struct mmc_command *cmd, u32 cmd_flags)
 358 {
 359         struct dw_mci_slot *slot = host->slot[0];
 360         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 361
 362         host->pre_cmd = host->cmd;
 363         host->cmd = cmd;
 364         dev_vdbg(host->dev,
 365                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 366                 cmd->arg, cmd_flags);
 367
 368         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 369                 /*confirm non-low-power mode*/
 370                 mci_writel(host, CMDARG, 0);
 371                 dw_mci_disable_low_power(slot);
 372
 373                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 374                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 375
 376                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 377         }
 378
 379         mci_writel(host, CMDARG, cmd->arg);
 380         wmb();
 381
 382         /* fix the value to 1 in some Soc,for example RK3188. */
 383         if(host->mmc->hold_reg_flag)
 384                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 385
 386         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 387         wmb();
 388 }
 389
 390 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 391 {
 392         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 393 }
 394
 395 /* DMA interface functions */
 396 static void dw_mci_stop_dma(struct dw_mci *host)
 397 {
 398         if (host->using_dma) {
 399                 host->dma_ops->stop(host);
 400                 host->dma_ops->cleanup(host);
 401         }
 402
 403         /* Data transfer was stopped by the interrupt handler */
 404         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 405 }
 406
 407 static int dw_mci_get_dma_dir(struct mmc_data *data)
 408 {
 409         if (data->flags & MMC_DATA_WRITE)
 410                 return DMA_TO_DEVICE;
 411         else
 412                 return DMA_FROM_DEVICE;
 413 }
 414
 415 #ifdef CONFIG_MMC_DW_IDMAC
 416 static void dw_mci_dma_cleanup(struct dw_mci *host)
 417 {
 418         struct mmc_data *data = host->data;
 419
 420         if (data)
 421                 if (!data->host_cookie)
 422                         dma_unmap_sg(host->dev,
 423                                      data->sg,
 424                                      data->sg_len,
 425                                      dw_mci_get_dma_dir(data));
 426 }
 427
 428 static void dw_mci_idmac_reset(struct dw_mci *host)
 429 {
 430         u32 bmod = mci_readl(host, BMOD);
 431         /* Software reset of DMA */
 432         bmod |= SDMMC_IDMAC_SWRESET;
 433         mci_writel(host, BMOD, bmod);
 434 }
 435
 436 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 437 {
 438         u32 temp;
 439
 440         /* Disable and reset the IDMAC interface */
 441         temp = mci_readl(host, CTRL);
 442         temp &= ~SDMMC_CTRL_USE_IDMAC;
 443         temp |= SDMMC_CTRL_DMA_RESET;
 444         mci_writel(host, CTRL, temp);
 445
 446         /* Stop the IDMAC running */
 447         temp = mci_readl(host, BMOD);
 448         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 449         temp |= SDMMC_IDMAC_SWRESET;
 450         mci_writel(host, BMOD, temp);
 451 }
 452
 453 static void dw_mci_idmac_complete_dma(void *arg)
 454 {
 455         struct dw_mci *host = arg;
 456         struct mmc_data *data = host->data;
 457
 458         dev_vdbg(host->dev, "DMA complete\n");
 459
 460         /*
 461         MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 462                 host->mrq->cmd->opcode,host->mrq->cmd->arg,
 463                 data->blocks,data->blksz,mmc_hostname(host->mmc));
 464         */
 465
 466         host->dma_ops->cleanup(host);
 467
 468         /*
 469          * If the card was removed, data will be NULL. No point in trying to
 470          * send the stop command or waiting for NBUSY in this case.
 471          */
 472         if(data){
 473                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 474                 tasklet_schedule(&host->tasklet);
 475         }
 476 }
 477
 478 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 479                                     unsigned int sg_len)
 480 {
 481         int i;
 482         struct idmac_desc *desc = host->sg_cpu;
 483
 484         for (i = 0; i < sg_len; i++, desc++) {
 485                 unsigned int length = sg_dma_len(&data->sg[i]);
 486                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 487
 488                 /* Set the OWN bit and disable interrupts for this descriptor */
 489                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 490
 491                 /* Buffer length */
 492                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 493
 494                 /* Physical address to DMA to/from */
 495                 desc->des2 = mem_addr;
 496         }
 497
 498         /* Set first descriptor */
 499         desc = host->sg_cpu;
 500         desc->des0 |= IDMAC_DES0_FD;
 501
 502         /* Set last descriptor */
 503         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 504         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 505         desc->des0 |= IDMAC_DES0_LD;
 506
 507         wmb();
 508 }
 509
 510 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 511 {
 512         u32 temp;
 513
 514         dw_mci_translate_sglist(host, host->data, sg_len);
 515
 516         /* Select IDMAC interface */
 517         temp = mci_readl(host, CTRL);
 518         temp |= SDMMC_CTRL_USE_IDMAC;
 519         mci_writel(host, CTRL, temp);
 520
 521         wmb();
 522
 523         /* Enable the IDMAC */
 524         temp = mci_readl(host, BMOD);
 525         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 526         mci_writel(host, BMOD, temp);
 527
 528         /* Start it running */
 529         mci_writel(host, PLDMND, 1);
 530 }
 531
 532 static int dw_mci_idmac_init(struct dw_mci *host)
 533 {
 534         struct idmac_desc *p;
 535         int i;
 536
 537         /* Number of descriptors in the ring buffer */
 538         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 539
 540         /* Forward link the descriptor list */
 541         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 542                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 543
 544         /* Set the last descriptor as the end-of-ring descriptor */
 545         p->des3 = host->sg_dma;
 546         p->des0 = IDMAC_DES0_ER;
 547
 548         dw_mci_idmac_reset(host);
 549
 550         /* Mask out interrupts - get Tx & Rx complete only */
 551         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 552         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 553                    SDMMC_IDMAC_INT_TI);
 554
 555         /* Set the descriptor base address */
 556         mci_writel(host, DBADDR, host->sg_dma);
 557         return 0;
 558 }
 559
 560 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 561         .init = dw_mci_idmac_init,
 562         .start = dw_mci_idmac_start_dma,
 563         .stop = dw_mci_idmac_stop_dma,
 564         .complete = dw_mci_idmac_complete_dma,
 565         .cleanup = dw_mci_dma_cleanup,
 566 };
 567
 568
 569 static void dw_mci_edma_cleanup(struct dw_mci *host)
 570 {
 571         struct mmc_data *data = host->data;
 572
 573         if (data)
 574                 if (!data->host_cookie)
 575                         dma_unmap_sg(host->dev,
 576                                         data->sg, data->sg_len,
 577                                         dw_mci_get_dma_dir(data));
 578 }
 579
 580 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 581 {
 582         dmaengine_terminate_all(host->dms->ch);
 583 }
 584
 585 static void dw_mci_edmac_complete_dma(void *arg)
 586 {
 587         struct dw_mci *host = arg;
 588         struct mmc_data *data = host->data;
 589
 590         dev_vdbg(host->dev, "DMA complete\n");
 591
 592         if(data)
 593                 if(data->flags & MMC_DATA_READ)
 594                         /* Invalidate cache after read */
 595                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 596                                 data->sg_len, DMA_FROM_DEVICE);
 597
 598         host->dma_ops->cleanup(host);
 599
 600         /*
 601          * If the card was removed, data will be NULL. No point in trying to
 602          * send the stop command or waiting for NBUSY in this case.
 603          */
 604         if (data) {
 605                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 606                 tasklet_schedule(&host->tasklet);
 607         }
 608 }
 609
 610 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 611 {
 612         struct dma_slave_config slave_config;
 613         struct dma_async_tx_descriptor *desc = NULL;
 614         struct scatterlist *sgl = host->data->sg;
 615         u32 sg_elems = host->data->sg_len;
 616         int ret = 0;
 617
 618         /* Set external dma config: burst size, burst width*/
 619         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 620         slave_config.src_addr = slave_config.dst_addr;
 621         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 622         slave_config.src_addr_width = slave_config.dst_addr_width;
 623
 624         /* Match FIFO dma burst MSIZE with external dma config*/
 625         slave_config.dst_maxburst = ((host->fifoth_val) >> 28) && 0x7;
 626         slave_config.src_maxburst = slave_config.dst_maxburst;
 627
 628         if(host->data->flags & MMC_DATA_WRITE){
 629                 slave_config.direction = DMA_MEM_TO_DEV;
 630                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 631                 if(ret){
 632                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 633                         return;
 634                 }
 635
 636                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 637                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 638                 if(!desc){
 639                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 640                         return;
 641                 }
 642                 /* Set dw_mci_edmac_complete_dma as callback */
 643                 desc->callback = dw_mci_edmac_complete_dma;
 644                 desc->callback_param = (void *)host;
 645                 dmaengine_submit(desc);
 646
 647                 /* Flush cache before write */
 648                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 649                                         sg_elems, DMA_TO_DEVICE);
 650                 dma_async_issue_pending(host->dms->ch);
 651         }else{
 652                 /* MMC_DATA_READ*/
 653                 slave_config.direction = DMA_DEV_TO_MEM;
 654                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 655                 if(ret){
 656                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 657                         return;
 658                 }
 659                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 660                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 661                 if(!desc){
 662                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 663                         return;
 664                 }
 665                 /* set dw_mci_edmac_complete_dma as callback */
 666                 desc->callback = dw_mci_edmac_complete_dma;
 667                 desc->callback_param = (void *)host;
 668                 dmaengine_submit(desc);
 669                 dma_async_issue_pending(host->dms->ch);
 670         }
 671 }
 672
 673 static int dw_mci_edmac_init(struct dw_mci *host)
 674 {
 675         /* 1) request external dma channel, SHOULD decide chn in dts */
 676         host->dms = (struct dw_mci_dma_slave *)kmalloc(sizeof(struct dw_mci_dma_slave),GFP_KERNEL);
 677         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 678         if (!host->dms->ch){
 679                 dev_err(host->dev, "Failed to get external DMA channel: channel id = %d\n",
 680                                 host->dms->ch->chan_id);
 681                 goto err_exit;
 682         }
 683
 684         /* anything? */
 685
 686         return 0;
 687
 688 err_exit:
 689         return -ENODEV;
 690
 691 }
 692
 693 static void dw_mci_edmac_exit(struct dw_mci *host)
 694 {
 695         dma_release_channel(host->dms->ch);
 696 }
 697
 698 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 699         .init = dw_mci_edmac_init,
 700         .exit = dw_mci_edmac_exit,
 701         .start = dw_mci_edmac_start_dma,
 702         .stop = dw_mci_edmac_stop_dma,
 703         .complete = dw_mci_edmac_complete_dma,
 704         .cleanup = dw_mci_edma_cleanup,
 705 };
 706 #endif /* CONFIG_MMC_DW_IDMAC */
 707
 708 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 709                                    struct mmc_data *data,
 710                                    bool next)
 711 {
 712         struct scatterlist *sg;
 713         unsigned int i, sg_len;
 714
 715         if (!next && data->host_cookie)
 716                 return data->host_cookie;
 717
 718         /*
 719          * We don't do DMA on "complex" transfers, i.e. with
 720          * non-word-aligned buffers or lengths. Also, we don't bother
 721          * with all the DMA setup overhead for short transfers.
 722          */
 723         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 724                 return -EINVAL;
 725
 726         if (data->blksz & 3)
 727                 return -EINVAL;
 728
 729         for_each_sg(data->sg, sg, data->sg_len, i) {
 730                 if (sg->offset & 3 || sg->length & 3)
 731                         return -EINVAL;
 732         }
 733
 734         sg_len = dma_map_sg(host->dev,
 735                             data->sg,
 736                             data->sg_len,
 737                             dw_mci_get_dma_dir(data));
 738         if (sg_len == 0)
 739                 return -EINVAL;
 740
 741         if (next)
 742                 data->host_cookie = sg_len;
 743
 744         return sg_len;
 745 }
 746
 747 static void dw_mci_pre_req(struct mmc_host *mmc,
 748                            struct mmc_request *mrq,
 749                            bool is_first_req)
 750 {
 751         struct dw_mci_slot *slot = mmc_priv(mmc);
 752         struct mmc_data *data = mrq->data;
 753
 754         if (!slot->host->use_dma || !data)
 755                 return;
 756
 757         if (data->host_cookie) {
 758                 data->host_cookie = 0;
 759                 return;
 760         }
 761
 762         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 763                 data->host_cookie = 0;
 764 }
 765
 766 static void dw_mci_post_req(struct mmc_host *mmc,
 767                             struct mmc_request *mrq,
 768                             int err)
 769 {
 770         struct dw_mci_slot *slot = mmc_priv(mmc);
 771         struct mmc_data *data = mrq->data;
 772
 773         if (!slot->host->use_dma || !data)
 774                 return;
 775
 776         if (data->host_cookie)
 777                 dma_unmap_sg(slot->host->dev,
 778                              data->sg,
 779                              data->sg_len,
 780                              dw_mci_get_dma_dir(data));
 781         data->host_cookie = 0;
 782 }
 783
 784 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 785 {
 786 #ifdef CONFIG_MMC_DW_IDMAC
 787         unsigned int blksz = data->blksz;
 788         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 789         u32 fifo_width = 1 << host->data_shift;
 790         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 791         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 792         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 793
 794         tx_wmark = (host->fifo_depth) / 2;
 795         tx_wmark_invers = host->fifo_depth - tx_wmark;
 796
 797         /*
 798          * MSIZE is '1',
 799          * if blksz is not a multiple of the FIFO width
 800          */
 801         if (blksz % fifo_width) {
 802                 msize = 0;
 803                 rx_wmark = 1;
 804                 goto done;
 805         }
 806
 807         do {
 808                 if (!((blksz_depth % mszs[idx]) ||
 809                      (tx_wmark_invers % mszs[idx]))) {
 810                         msize = idx;
 811                         rx_wmark = mszs[idx] - 1;
 812                         break;
 813                 }
 814         } while (--idx > 0);
 815         /*
 816          * If idx is '0', it won't be tried
 817          * Thus, initial values are uesed
 818          */
 819 done:
 820         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 821         mci_writel(host, FIFOTH, fifoth_val);
 822 #endif
 823 }
 824
 825 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 826 {
 827         unsigned int blksz = data->blksz;
 828         u32 blksz_depth, fifo_depth;
 829         u16 thld_size;
 830
 831         WARN_ON(!(data->flags & MMC_DATA_READ));
 832
 833         if (host->timing != MMC_TIMING_MMC_HS200 &&
 834             host->timing != MMC_TIMING_UHS_SDR104)
 835                 goto disable;
 836
 837         blksz_depth = blksz / (1 << host->data_shift);
 838         fifo_depth = host->fifo_depth;
 839
 840         if (blksz_depth > fifo_depth)
 841                 goto disable;
 842
 843         /*
 844          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 845          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 846          * Currently just choose blksz.
 847          */
 848         thld_size = blksz;
 849         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 850         return;
 851
 852 disable:
 853         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 854 }
 855
 856 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 857 {
 858         int sg_len;
 859         u32 temp;
 860
 861         host->using_dma = 0;
 862
 863         /* If we don't have a channel, we can't do DMA */
 864         if (!host->use_dma)
 865                 return -ENODEV;
 866
 867         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 868         if (sg_len < 0) {
 869                 host->dma_ops->stop(host);
 870                 return sg_len;
 871         }
 872
 873         host->using_dma = 1;
 874
 875         dev_vdbg(host->dev,
 876                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 877                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 878                  sg_len);
 879
 880         /*
 881          * Decide the MSIZE and RX/TX Watermark.
 882          * If current block size is same with previous size,
 883          * no need to update fifoth.
 884          */
 885         if (host->prev_blksz != data->blksz)
 886                 dw_mci_adjust_fifoth(host, data);
 887
 888         /* Reset DMA FIFO*/
 889         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 890
 891         /* Enable the DMA interface */
 892         temp = mci_readl(host, CTRL);
 893         temp |= SDMMC_CTRL_DMA_ENABLE;
 894         mci_writel(host, CTRL, temp);
 895
 896         /* Disable RX/TX IRQs, let DMA handle it */
 897         temp = mci_readl(host, INTMASK);
 898         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 899         mci_writel(host, INTMASK, temp);
 900
 901         host->dma_ops->start(host, sg_len);
 902
 903         return 0;
 904 }
 905
 906 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 907 {
 908         u32 temp;
 909
 910         data->error = -EINPROGRESS;
 911
 912         WARN_ON(host->data);
 913         host->sg = NULL;
 914         host->data = data;
 915
 916         /* Reset FIFO*/
 917         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
 918
 919         if (data->flags & MMC_DATA_READ) {
 920                 host->dir_status = DW_MCI_RECV_STATUS;
 921                 dw_mci_ctrl_rd_thld(host, data);
 922         } else {
 923                 host->dir_status = DW_MCI_SEND_STATUS;
 924         }
 925
 926     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
 927          data->blocks, data->blksz, mmc_hostname(host->mmc));
 928
 929         if (dw_mci_submit_data_dma(host, data)) {
 930                 int flags = SG_MITER_ATOMIC;
 931                 if (host->data->flags & MMC_DATA_READ)
 932                         flags |= SG_MITER_TO_SG;
 933                 else
 934                         flags |= SG_MITER_FROM_SG;
 935
 936                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 937                 host->sg = data->sg;
 938                 host->part_buf_start = 0;
 939                 host->part_buf_count = 0;
 940
 941                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 942                 temp = mci_readl(host, INTMASK);
 943                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 944                 mci_writel(host, INTMASK, temp);
 945
 946                 temp = mci_readl(host, CTRL);
 947                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 948                 mci_writel(host, CTRL, temp);
 949
 950                 /*
 951                  * Use the initial fifoth_val for PIO mode.
 952                  * If next issued data may be transfered by DMA mode,
 953                  * prev_blksz should be invalidated.
 954                  */
 955                 mci_writel(host, FIFOTH, host->fifoth_val);
 956                 host->prev_blksz = 0;
 957         } else {
 958                 /*
 959                  * Keep the current block size.
 960                  * It will be used to decide whether to update
 961                  * fifoth register next time.
 962                  */
 963                 host->prev_blksz = data->blksz;
 964         }
 965 }
 966
 967 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 968 {
 969         struct dw_mci *host = slot->host;
 970         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
 971         unsigned int cmd_status = 0;
 972 #ifdef SDMMC_WAIT_FOR_UNBUSY
 973         bool ret = true;
 974         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
 975
 976     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 977         while (ret) {
 978                 ret =  time_before(jiffies, timeout);
 979                 cmd_status = mci_readl(host, STATUS);
 980                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
 981                         break;
 982         } ;
 983         if(false == ret)
 984             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
 985                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
 986     }
 987 #endif
 988         mci_writel(host, CMDARG, arg);
 989         wmb();
 990         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 991         if(cmd & SDMMC_CMD_UPD_CLK)
 992                 timeout = jiffies + msecs_to_jiffies(50);
 993         else
 994                 timeout = jiffies + msecs_to_jiffies(500);
 995         while (time_before(jiffies, timeout)) {
 996                 cmd_status = mci_readl(host, CMD);
 997                 if (!(cmd_status & SDMMC_CMD_START))
 998                         return ;
 999         }
1000         dev_err(&slot->mmc->class_dev,
1001                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1002                 cmd, arg, cmd_status);
1003 }
1004
1005 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1006 {
1007         struct dw_mci *host = slot->host;
1008         unsigned int tempck,clock = slot->clock;
1009         u32 div;
1010         u32 clk_en_a;
1011         u32 sdio_int;
1012
1013         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
1014                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
1015
1016         if (!clock) {
1017                 mci_writel(host, CLKENA, 0);
1018                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1019                 if(host->svi_flags == 0)
1020                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1021                 #else
1022                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1023                 #endif
1024         } else if (clock != host->current_speed || force_clkinit) {
1025                 div = host->bus_hz / clock;
1026                 if (host->bus_hz % clock && host->bus_hz > clock)
1027                         /*
1028                          * move the + 1 after the divide to prevent
1029                          * over-clocking the card.
1030                          */
1031                         div += 1;
1032
1033                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1034
1035                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1036                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1037                         dev_info(&slot->mmc->class_dev,
1038                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1039                                  slot->id, host->bus_hz, clock,
1040                                  tempck, div);
1041
1042                         host->set_speed = tempck;
1043                         host->set_div = div;
1044                 }
1045
1046                 /* disable clock */
1047                 mci_writel(host, CLKENA, 0);
1048                 mci_writel(host, CLKSRC, 0);
1049
1050                 /* inform CIU */
1051                 mci_send_cmd(slot,
1052                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1053
1054                 if(clock <= 400*1000){
1055                         MMC_DBG_BOOT_FUNC(host->mmc,
1056                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1057                                 clock * 2, mmc_hostname(host->mmc));
1058                         /* clk_mmc will change parents to 24MHz xtal*/
1059                         clk_set_rate(host->clk_mmc, clock * 2);
1060
1061                         div = 0;
1062                         host->set_div = div;
1063                 }
1064                 else
1065                 {
1066                         MMC_DBG_BOOT_FUNC(host->mmc,
1067                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1068                                 mmc_hostname(host->mmc));
1069                         if(div > 1)
1070                         {
1071                                 MMC_DBG_ERR_FUNC(host->mmc,
1072                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1073                                         mmc_hostname(host->mmc));
1074                                  div = 1;
1075                                  host->set_div = div;
1076                                  host->bus_hz = host->set_speed * 2;
1077                                  MMC_DBG_BOOT_FUNC(host->mmc,
1078                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1079                                         div, host->bus_hz, mmc_hostname(host->mmc));
1080                         }
1081                         /* BUG may be here, come on,  Linux BSP engineer looks!
1082                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1083                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1084                            some oops happened like that:
1085                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1086                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1087                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1088                            mmc0: new high speed DDR MMC card at address 0001
1089                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1090                            ....
1091                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1092                            mmcblk0: retrying using single block read
1093                            mmcblk0: error -110 sending status command, retrying
1094
1095                            How to: If eMMC HW version < 4.51, or > 4.51 but no caps2-mmc-hs200 support in dts
1096                                    Please set dts emmc clk to 100M or 150M, I will workaround it!
1097                          */
1098
1099                         if (host->verid < DW_MMC_240A)
1100                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1101                         else
1102                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1103
1104
1105
1106                 }
1107
1108                 /* set clock to desired speed */
1109                 mci_writel(host, CLKDIV, div);
1110
1111                 /* inform CIU */
1112                 mci_send_cmd(slot,
1113                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1114
1115                 /* enable clock; only low power if no SDIO */
1116                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1117
1118                 if (host->verid < DW_MMC_240A)
1119                     sdio_int = SDMMC_INT_SDIO(slot->id);
1120                 else
1121                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1122
1123                 if (!(mci_readl(host, INTMASK) & sdio_int))
1124                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1125                 mci_writel(host, CLKENA, clk_en_a);
1126
1127                 /* inform CIU */
1128                 mci_send_cmd(slot,
1129                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1130                 /* keep the clock with reflecting clock dividor */
1131                 slot->__clk_old = clock << div;
1132         }
1133
1134         host->current_speed = clock;
1135
1136     if(slot->ctype != slot->pre_ctype)
1137         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
1138             host->set_speed,
1139             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
1140             mmc_hostname(host->mmc));
1141     slot->pre_ctype = slot->ctype;
1142
1143         /* Set the current slot bus width */
1144         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1145 }
1146
1147 extern struct mmc_card *this_card;
1148 static void dw_mci_wait_unbusy(struct dw_mci *host)
1149 {
1150
1151         unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1152         unsigned long   time_loop;
1153         unsigned int    status;
1154         u32 se_flag = 0;
1155
1156         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1157
1158         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1159                 if (host->cmd && (host->cmd->opcode == MMC_ERASE)) {
1160                 /* Special care for (secure)erase timeout calculation */
1161                         if(this_card){
1162                                 if((host->cmd->arg & (0x1 << 31)) == 1) /* secure erase */
1163                                         se_flag = 0x1;
1164
1165                                 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1) ;
1166                                         se_flag ? (timeout = (this_card->ext_csd.hc_erase_timeout) *
1167                                                         300000 * (this_card->ext_csd.sec_erase_mult)) :
1168                                                         (timeout = (this_card->ext_csd.hc_erase_timeout) * 300000);
1169                         }
1170                 }
1171
1172                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1173                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1174         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1175                 timeout = SDMMC_DATA_TIMEOUT_SD;
1176         }
1177
1178         time_loop = jiffies + msecs_to_jiffies(timeout);
1179         do {
1180                 status = mci_readl(host, STATUS);
1181                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1182                         break;
1183         } while (time_before(jiffies, time_loop));
1184 }
1185
1186
1187
1188 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1189 /*
1190 *   result:
1191 *   0--status is busy.
1192 *   1--status is unbusy.
1193 */
1194 int dw_mci_card_busy(struct mmc_host *mmc)
1195 {
1196         struct dw_mci_slot *slot = mmc_priv(mmc);
1197         struct dw_mci *host = slot->host;
1198
1199         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1200                                 host->svi_flags, mmc_hostname(host->mmc));
1201
1202         /* svi toggle*/
1203         if(host->svi_flags == 0){
1204                 /*first svi*/
1205                 host->svi_flags = 1;
1206                 return host->svi_flags;
1207
1208         }else{
1209                 host->svi_flags = 0;
1210                 return host->svi_flags;
1211         }
1212
1213
1214 }
1215 #endif
1216 static void __dw_mci_start_request(struct dw_mci *host,
1217                                    struct dw_mci_slot *slot,
1218                                    struct mmc_command *cmd)
1219 {
1220         struct mmc_request *mrq;
1221         struct mmc_data *data;
1222         u32 cmdflags;
1223
1224         mrq = slot->mrq;
1225         if (host->pdata->select_slot)
1226                 host->pdata->select_slot(slot->id);
1227
1228         host->cur_slot = slot;
1229         host->mrq = mrq;
1230
1231         dw_mci_wait_unbusy(host);
1232
1233         host->pending_events = 0;
1234         host->completed_events = 0;
1235         host->data_status = 0;
1236
1237         data = cmd->data;
1238         if (data) {
1239                 dw_mci_set_timeout(host);
1240                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1241                 mci_writel(host, BLKSIZ, data->blksz);
1242         }
1243
1244         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1245
1246         /* this is the first command, send the initialization clock */
1247         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1248                 cmdflags |= SDMMC_CMD_INIT;
1249
1250         if (data) {
1251                 dw_mci_submit_data(host, data);
1252                 wmb();
1253         }
1254
1255         dw_mci_start_command(host, cmd, cmdflags);
1256
1257         if (mrq->stop)
1258                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1259 }
1260
1261 static void dw_mci_start_request(struct dw_mci *host,
1262                                  struct dw_mci_slot *slot)
1263 {
1264         struct mmc_request *mrq = slot->mrq;
1265         struct mmc_command *cmd;
1266
1267         MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1268                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1269
1270         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1271         __dw_mci_start_request(host, slot, cmd);
1272 }
1273
1274 /* must be called with host->lock held */
1275 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1276                                  struct mmc_request *mrq)
1277 {
1278         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1279                  host->state);
1280
1281         slot->mrq = mrq;
1282
1283         if (host->state == STATE_IDLE) {
1284                 host->state = STATE_SENDING_CMD;
1285                 dw_mci_start_request(host, slot);
1286         } else {
1287                 list_add_tail(&slot->queue_node, &host->queue);
1288         }
1289 }
1290
1291 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1292 {
1293         struct dw_mci_slot *slot = mmc_priv(mmc);
1294         struct dw_mci *host = slot->host;
1295
1296         WARN_ON(slot->mrq);
1297
1298         /*
1299          * The check for card presence and queueing of the request must be
1300          * atomic, otherwise the card could be removed in between and the
1301          * request wouldn't fail until another card was inserted.
1302          */
1303         spin_lock_bh(&host->lock);
1304
1305         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1306                 spin_unlock_bh(&host->lock);
1307                 mrq->cmd->error = -ENOMEDIUM;
1308                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1309                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1310
1311                 mmc_request_done(mmc, mrq);
1312                 return;
1313         }
1314
1315         MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1316                                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1317
1318         dw_mci_queue_request(host, slot, mrq);
1319
1320         spin_unlock_bh(&host->lock);
1321 }
1322
1323 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1324 {
1325         struct dw_mci_slot *slot = mmc_priv(mmc);
1326         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1327         struct dw_mci *host = slot->host;
1328         #endif
1329         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1330         u32 regs;
1331
1332         #ifdef SDMMC_WAIT_FOR_UNBUSY
1333         unsigned long   time_loop;
1334         bool ret = true;
1335
1336         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1337         if(host->svi_flags == 1)
1338                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1339         else
1340                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1341         #else
1342                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1343         #endif
1344
1345         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1346                 printk("%d..%s:  no card. [%s]\n", \
1347                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1348                 goto EXIT_POWER;
1349         }
1350
1351         while (ret) {
1352                 ret = time_before(jiffies, time_loop);
1353                 regs = mci_readl(slot->host, STATUS);
1354                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1355                         break;
1356         };
1357
1358         if(false == ret)
1359         {
1360                 printk("slot->flags = %lu ", slot->flags);
1361                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1362                 if(host->svi_flags != 1)
1363                 #endif
1364                         dump_stack();
1365                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1366                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1367         }
1368         #endif
1369
1370         switch (ios->bus_width) {
1371         case MMC_BUS_WIDTH_4:
1372                 slot->ctype = SDMMC_CTYPE_4BIT;
1373                 break;
1374         case MMC_BUS_WIDTH_8:
1375                 slot->ctype = SDMMC_CTYPE_8BIT;
1376                 break;
1377         default:
1378                 /* set default 1 bit mode */
1379                 slot->ctype = SDMMC_CTYPE_1BIT;
1380                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1381         }
1382
1383         regs = mci_readl(slot->host, UHS_REG);
1384
1385         /* DDR mode set */
1386         if (ios->timing == MMC_TIMING_UHS_DDR50)
1387                 regs |= ((0x1 << slot->id) << 16);
1388         else
1389                 regs &= ~((0x1 << slot->id) << 16);
1390
1391         mci_writel(slot->host, UHS_REG, regs);
1392         slot->host->timing = ios->timing;
1393
1394         /*
1395          * Use mirror of ios->clock to prevent race with mmc
1396          * core ios update when finding the minimum.
1397          */
1398         slot->clock = ios->clock;
1399
1400         if (drv_data && drv_data->set_ios)
1401                 drv_data->set_ios(slot->host, ios);
1402
1403         /* Slot specific timing and width adjustment */
1404         dw_mci_setup_bus(slot, false);
1405                 //return -EAGAIN;
1406
1407 EXIT_POWER:
1408         switch (ios->power_mode) {
1409                 case MMC_POWER_UP:
1410                         set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1411                         /* Power up slot */
1412                         if (slot->host->pdata->setpower)
1413                                 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1414                         regs = mci_readl(slot->host, PWREN);
1415                         regs |= (1 << slot->id);
1416                         mci_writel(slot->host, PWREN, regs);
1417                         break;
1418                 case MMC_POWER_OFF:
1419                         /* Power down slot */
1420                         if(slot->host->pdata->setpower)
1421                                 slot->host->pdata->setpower(slot->id, 0);
1422                         regs = mci_readl(slot->host, PWREN);
1423                         regs &= ~(1 << slot->id);
1424                         mci_writel(slot->host, PWREN, regs);
1425                         break;
1426                 default:
1427                         break;
1428         }
1429 }
1430
1431 static int dw_mci_get_ro(struct mmc_host *mmc)
1432 {
1433         int read_only;
1434         struct dw_mci_slot *slot = mmc_priv(mmc);
1435         struct dw_mci_board *brd = slot->host->pdata;
1436
1437         /* Use platform get_ro function, else try on board write protect */
1438         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1439                 read_only = 0;
1440         else if(brd->get_ro)
1441                 read_only = brd->get_ro(slot->id);
1442         else if(gpio_is_valid(slot->wp_gpio))
1443                 read_only = gpio_get_value(slot->wp_gpio);
1444         else
1445                 read_only =
1446                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1447
1448         dev_dbg(&mmc->class_dev, "card is %s\n",
1449                 read_only ? "read-only" : "read-write");
1450
1451         return read_only;
1452 }
1453
1454 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1455 {
1456         struct dw_mci_slot *slot = mmc_priv(mmc);
1457         struct dw_mci *host = slot->host;
1458         /*struct dw_mci_board *brd = slot->host->pdata;*/
1459
1460         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1461                 return 0;
1462
1463         spin_lock_bh(&host->lock);
1464
1465         if(val)
1466                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1467         else
1468                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1469
1470         spin_unlock_bh(&host->lock);
1471
1472         if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1473                 if(__clk_is_enabled(host->hclk_mmc) == false)
1474                         clk_prepare_enable(host->hclk_mmc);
1475                 if(__clk_is_enabled(host->clk_mmc) == false)
1476                         clk_prepare_enable(host->clk_mmc);
1477         }else{
1478                 if(__clk_is_enabled(host->clk_mmc) == true)
1479                         clk_disable_unprepare(slot->host->clk_mmc);
1480                 if(__clk_is_enabled(host->hclk_mmc) == true)
1481                         clk_disable_unprepare(slot->host->hclk_mmc);
1482         }
1483
1484         mmc_detect_change(slot->mmc, 20);
1485         return 0;
1486 }
1487
1488
1489
1490 static int dw_mci_get_cd(struct mmc_host *mmc)
1491 {
1492         int present;
1493         struct dw_mci_slot *slot = mmc_priv(mmc);
1494         struct dw_mci_board *brd = slot->host->pdata;
1495         struct dw_mci *host = slot->host;
1496         int gpio_cd = mmc_gpio_get_cd(mmc);
1497         int gpio_val;
1498
1499         if (cpu_is_rk312x() &&
1500                 soc_is_rk3126() &&
1501                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1502                 gpio_cd = slot->cd_gpio;
1503                 if (gpio_is_valid(gpio_cd)) {
1504                         gpio_val = gpio_get_value_cansleep(gpio_cd);
1505                         msleep(10);
1506                         if (gpio_val == gpio_get_value_cansleep(gpio_cd)) {
1507                                 gpio_cd = gpio_get_value_cansleep(gpio_cd) == 0 ? 1 : 0;
1508                                 if (gpio_cd == 0)
1509                                         dw_mci_ctrl_all_reset(host);
1510                         } else {
1511                                 /* Jitter */
1512                                 return slot->last_detect_state;
1513                         }
1514                 } else {
1515                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1516                 }
1517         }
1518
1519         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1520                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1521
1522         /* Use platform get_cd function, else try onboard card detect */
1523         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1524                 present = 1;
1525         else if (brd->get_cd)
1526                 present = !brd->get_cd(slot->id);
1527         else if (!IS_ERR_VALUE(gpio_cd))
1528                 present = gpio_cd;
1529         else
1530                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1531                         == 0 ? 1 : 0;
1532
1533         spin_lock_bh(&host->lock);
1534         if (present) {
1535                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1536                 dev_dbg(&mmc->class_dev, "card is present\n");
1537         } else {
1538                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1539                 dev_dbg(&mmc->class_dev, "card is not present\n");
1540         }
1541         spin_unlock_bh(&host->lock);
1542
1543         return present;
1544 }
1545
1546
1547 /*
1548  * Dts Should caps emmc controller with poll-hw-reset
1549  */
1550 static void dw_mci_hw_reset(struct mmc_host *mmc)
1551 {
1552         struct dw_mci_slot *slot = mmc_priv(mmc);
1553         struct dw_mci *host = slot->host;
1554         u32 regs;
1555
1556         #if 0
1557         u32 cmd_flags;
1558         unsigned long timeout;
1559         bool ret = true;
1560
1561         /* (1) CMD12 to end any transfer in process */
1562         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1563                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1564
1565         if(host->mmc->hold_reg_flag)
1566                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1567         mci_writel(host, CMDARG, 0);
1568         wmb();
1569         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1570         wmb();
1571         timeout = jiffies + msecs_to_jiffies(500);
1572         while(ret){
1573                 ret = time_before(jiffies, timeout);
1574                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1575                         break;
1576         }
1577
1578         if(false == ret)
1579                 MMC_DBG_ERR_FUNC(host->mmc,
1580                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1581                         __func__, mmc_hostname(host->mmc));
1582
1583         /* (2) wait DTO, even if no response is sent back by card */
1584         ret = true;
1585         timeout = jiffies + msecs_to_jiffies(5);
1586         while(ret){
1587                 ret = time_before(jiffies, timeout);
1588                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1589                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1590                         break;
1591                 }
1592         }
1593         #endif
1594
1595         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1596
1597         /* Software reset - BMOD[0] for IDMA only */
1598         regs = mci_readl(host, BMOD);
1599         regs |= SDMMC_IDMAC_SWRESET;
1600         mci_writel(host, BMOD, regs);
1601         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1602         regs = mci_readl(host, BMOD);
1603         if(regs & SDMMC_IDMAC_SWRESET)
1604                 MMC_DBG_WARN_FUNC(host->mmc,
1605                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1606                         __func__, mmc_hostname(host->mmc));
1607
1608         /* DMA reset - CTRL[2] */
1609         regs = mci_readl(host, CTRL);
1610         regs |= SDMMC_CTRL_DMA_RESET;
1611         mci_writel(host, CTRL, regs);
1612         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1613         regs = mci_readl(host, CTRL);
1614         if(regs & SDMMC_CTRL_DMA_RESET)
1615                 MMC_DBG_WARN_FUNC(host->mmc,
1616                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1617                         __func__, mmc_hostname(host->mmc));
1618
1619         /* FIFO reset - CTRL[1] */
1620         regs = mci_readl(host, CTRL);
1621         regs |= SDMMC_CTRL_FIFO_RESET;
1622         mci_writel(host, CTRL, regs);
1623         mdelay(1); /* no timing limited, 1ms is random value */
1624         regs = mci_readl(host, CTRL);
1625         if(regs & SDMMC_CTRL_FIFO_RESET)
1626                 MMC_DBG_WARN_FUNC(host->mmc,
1627                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1628                         __func__, mmc_hostname(host->mmc));
1629
1630         /* (4) CARD_RESET
1631         According to eMMC spec
1632         tRstW >= 1us ;   RST_n pulse width
1633         tRSCA >= 200us ; RST_n to Command time
1634         tRSTH >= 1us ;   RST_n high period
1635         */
1636         mci_writel(slot->host, PWREN, 0x0);
1637         mci_writel(slot->host, RST_N, 0x0);
1638         dsb();
1639         udelay(10); /* 10us for bad quality eMMc. */
1640
1641         mci_writel(slot->host, PWREN, 0x1);
1642         mci_writel(slot->host, RST_N, 0x1);
1643         dsb();
1644         usleep_range(500, 1000); /* at least 500(> 200us) */
1645 }
1646
1647 /*
1648  * Disable lower power mode.
1649  *
1650  * Low power mode will stop the card clock when idle.  According to the
1651  * description of the CLKENA register we should disable low power mode
1652  * for SDIO cards if we need SDIO interrupts to work.
1653  *
1654  * This function is fast if low power mode is already disabled.
1655  */
1656 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1657 {
1658         struct dw_mci *host = slot->host;
1659         u32 clk_en_a;
1660         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1661
1662         clk_en_a = mci_readl(host, CLKENA);
1663
1664         if (clk_en_a & clken_low_pwr) {
1665                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1666                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1667                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1668         }
1669 }
1670
1671 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1672 {
1673         struct dw_mci_slot *slot = mmc_priv(mmc);
1674         struct dw_mci *host = slot->host;
1675         u32 int_mask;
1676         u32 sdio_int;
1677
1678         /* Enable/disable Slot Specific SDIO interrupt */
1679         int_mask = mci_readl(host, INTMASK);
1680
1681         if (host->verid < DW_MMC_240A)
1682                 sdio_int = SDMMC_INT_SDIO(slot->id);
1683         else
1684                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1685
1686         if (enb) {
1687                 /*
1688                  * Turn off low power mode if it was enabled.  This is a bit of
1689                  * a heavy operation and we disable / enable IRQs a lot, so
1690                  * we'll leave low power mode disabled and it will get
1691                  * re-enabled again in dw_mci_setup_bus().
1692                  */
1693                 dw_mci_disable_low_power(slot);
1694
1695                 mci_writel(host, INTMASK,
1696                            (int_mask | sdio_int));
1697         } else {
1698                 mci_writel(host, INTMASK,
1699                            (int_mask & ~sdio_int));
1700         }
1701 }
1702
1703 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1704 enum{
1705         IO_DOMAIN_12 = 1200,
1706         IO_DOMAIN_18 = 1800,
1707         IO_DOMAIN_33 = 3300,
1708 };
1709 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1710 {
1711         switch(voltage){
1712                 case IO_DOMAIN_33:
1713                         voltage = 0;
1714                         break;
1715                 case IO_DOMAIN_18:
1716                         voltage = 1;
1717                         break;
1718                 case IO_DOMAIN_12:
1719                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Not support io domain voltage [%s]\n",
1720                                                         __FUNCTION__, mmc_hostname(host->mmc));
1721                         break;
1722                 default:
1723                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Err io domain voltage [%s]\n",
1724                                                         __FUNCTION__, mmc_hostname(host->mmc));
1725                         break;
1726         }
1727
1728         if(cpu_is_rk3288()){
1729                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1730                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1731                 else
1732                         return ;
1733         }else{
1734                 MMC_DBG_ERR_FUNC(host->mmc,"%s : unknown chip [%s]\n",
1735                                         __FUNCTION__, mmc_hostname(host->mmc));
1736         }
1737 }
1738
1739 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1740                                                 struct mmc_ios *ios)
1741 {
1742         int ret;
1743         unsigned int value,uhs_reg;
1744
1745         /*
1746          * Signal Voltage Switching is only applicable for Host Controllers
1747          * v3.00 and above.
1748          */
1749         if (host->verid < DW_MMC_240A)
1750                 return 0;
1751
1752         uhs_reg = mci_readl(host, UHS_REG);
1753         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1754                 __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1755
1756         switch (ios->signal_voltage) {
1757         case MMC_SIGNAL_VOLTAGE_330:
1758                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1759                 if (host->vmmc) {
1760                         ret = io_domain_regulator_set_voltage(host->vmmc, 3300000, 3300000);
1761                         /* regulator_put(host->vmmc); //to be done in remove function. */
1762
1763                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1764                             __func__, regulator_get_voltage(host->vmmc), ret);
1765                         if (ret) {
1766                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 3.3V signalling voltage "
1767                                                 " failed\n", mmc_hostname(host->mmc));
1768                                 return -EIO;
1769                         }
1770                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1771                 }
1772                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__,
1773                                         __FUNCTION__, mmc_hostname(host->mmc));
1774
1775                 /* set High-power mode */
1776                 value = mci_readl(host, CLKENA);
1777                 value &= ~SDMMC_CLKEN_LOW_PWR;
1778                 mci_writel(host,CLKENA , value);
1779                 /* SDMMC_UHS_REG */
1780                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1781                 mci_writel(host,UHS_REG , uhs_reg);
1782
1783                 /* Wait for 5ms */
1784                 usleep_range(5000, 5500);
1785
1786                 /* 3.3V regulator output should be stable within 5 ms */
1787                 uhs_reg = mci_readl(host, UHS_REG);
1788                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1789                         return 0;
1790
1791                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 3.3V regulator output did not became stable\n",
1792                                 mmc_hostname(host->mmc));
1793
1794                 return -EAGAIN;
1795         case MMC_SIGNAL_VOLTAGE_180:
1796                 if (host->vmmc) {
1797                         ret = io_domain_regulator_set_voltage(host->vmmc,1800000, 1800000);
1798                         /* regulator_put(host->vmmc);//to be done in remove function. */
1799
1800                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1801                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1802                         if (ret) {
1803                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.8V signalling voltage "
1804                                                 " failed\n", mmc_hostname(host->mmc));
1805                                 return -EIO;
1806                         }
1807                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1808                 }
1809
1810                 /*
1811                  * Enable 1.8V Signal Enable in the Host Control2
1812                  * register
1813                  */
1814                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1815
1816                 /* Wait for 5ms */
1817                 usleep_range(5000, 5500);
1818                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__,
1819                                         __FUNCTION__,mmc_hostname(host->mmc));
1820
1821                 /* 1.8V regulator output should be stable within 5 ms */
1822                 uhs_reg = mci_readl(host, UHS_REG);
1823                 if(uhs_reg & SDMMC_UHS_VOLT_REG_18)
1824                         return 0;
1825
1826                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 1.8V regulator output did not became stable\n",
1827                                 mmc_hostname(host->mmc));
1828
1829                 return -EAGAIN;
1830         case MMC_SIGNAL_VOLTAGE_120:
1831                 if (host->vmmc) {
1832                         ret = io_domain_regulator_set_voltage(host->vmmc, 1200000, 1200000);
1833                         if (ret) {
1834                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.2V signalling voltage "
1835                                                 " failed\n", mmc_hostname(host->mmc));
1836                                 return -EIO;
1837                         }
1838                 }
1839                 return 0;
1840         default:
1841                 /* No signal voltage switch required */
1842                 return 0;
1843         }
1844 }
1845
1846
1847 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1848         struct mmc_ios *ios)
1849 {
1850         struct dw_mci_slot *slot = mmc_priv(mmc);
1851         struct dw_mci *host = slot->host;
1852         int err;
1853
1854         if (host->verid < DW_MMC_240A)
1855                 return 0;
1856
1857         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1858         return err;
1859 }
1860
1861 #endif
1862
1863 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1864 {
1865         struct dw_mci_slot *slot = mmc_priv(mmc);
1866         struct dw_mci *host = slot->host;
1867         const struct dw_mci_drv_data *drv_data = host->drv_data;
1868         struct dw_mci_tuning_data tuning_data;
1869         int err = -ENOSYS;
1870
1871         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1872         if(cpu_is_rk3036() || cpu_is_rk312x())
1873                 return err;
1874
1875         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1876                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1877                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1878                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1879                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1880                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1881                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1882                 } else {
1883                         return -EINVAL;
1884                 }
1885         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1886                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1887                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1888         } else {
1889                 dev_err(host->dev,
1890                         "Undefined command(%d) for tuning\n", opcode);
1891                 return -EINVAL;
1892         }
1893
1894
1895         /* Recommend sample phase and delayline
1896            Fixme: Mix-use these three controllers will cause
1897            con_id mismatch.
1898          */
1899         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1900             tuning_data.con_id = 3;
1901         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1902             tuning_data.con_id = 1;
1903         else
1904             tuning_data.con_id = 0;
1905
1906         /* 0: driver, from host->devices
1907            1: sample, from devices->host
1908          */
1909         tuning_data.tuning_type = 1;
1910
1911         if (drv_data && drv_data->execute_tuning)
1912                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1913
1914         return err;
1915 }
1916
1917 static const struct mmc_host_ops dw_mci_ops = {
1918         .request                = dw_mci_request,
1919         .pre_req                = dw_mci_pre_req,
1920         .post_req               = dw_mci_post_req,
1921         .set_ios                = dw_mci_set_ios,
1922         .get_ro                 = dw_mci_get_ro,
1923         .get_cd                 = dw_mci_get_cd,
1924         .set_sdio_status    = dw_mci_set_sdio_status,
1925         .hw_reset       = dw_mci_hw_reset,
1926         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1927         .execute_tuning         = dw_mci_execute_tuning,
1928         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1929         .start_signal_voltage_switch    = dw_mci_start_signal_voltage_switch,
1930         .card_busy  = dw_mci_card_busy,
1931         #endif
1932 };
1933
1934 #if 0
1935 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
1936 {
1937         unsigned long flags;
1938
1939     if(!host)
1940         return;
1941
1942         local_irq_save(flags);
1943         if(host->irq_state != irqflag)
1944         {
1945             host->irq_state = irqflag;
1946             if(irqflag)
1947             {
1948                 enable_irq(host->irq);
1949             }
1950             else
1951             {
1952                 disable_irq(host->irq);
1953             }
1954         }
1955         local_irq_restore(flags);
1956 }
1957 #endif
1958
1959 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
1960         __releases(&host->lock)
1961         __acquires(&host->lock)
1962 {
1963         if(DW_MCI_SEND_STATUS == host->dir_status){
1964             #if 0
1965             if( MMC_BUS_TEST_W != host->cmd->opcode){
1966                 if(host->data_status & SDMMC_INT_DCRC)
1967                     host->data->error = -EILSEQ;
1968                 else if(host->data_status & SDMMC_INT_EBE)
1969                     host->data->error = -ETIMEDOUT;
1970             } else {
1971                 dw_mci_wait_unbusy(host);
1972             }
1973             #else
1974             dw_mci_wait_unbusy(host);
1975             #endif
1976         }
1977 }
1978
1979 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1980         __releases(&host->lock)
1981         __acquires(&host->lock)
1982 {
1983         struct dw_mci_slot *slot;
1984         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1985
1986         WARN_ON(host->cmd || host->data);
1987
1988         del_timer_sync(&host->dto_timer);
1989         dw_mci_deal_data_end(host, mrq);
1990
1991         if(mrq->cmd)
1992                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
1993                         mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
1994         if(mrq->data)
1995                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
1996                         mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
1997
1998         host->cur_slot->mrq = NULL;
1999         host->mrq = NULL;
2000         if (!list_empty(&host->queue)) {
2001                 slot = list_entry(host->queue.next,
2002                                   struct dw_mci_slot, queue_node);
2003                 list_del(&slot->queue_node);
2004                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2005                          mmc_hostname(slot->mmc));
2006                 host->state = STATE_SENDING_CMD;
2007                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
2008                 dw_mci_start_request(host, slot);
2009         } else {
2010                 dev_vdbg(host->dev, "list empty\n");
2011                 host->state = STATE_IDLE;
2012         }
2013
2014         spin_unlock(&host->lock);
2015         mmc_request_done(prev_mmc, mrq);
2016         spin_lock(&host->lock);
2017 }
2018
2019 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2020 {
2021         u32 status = host->cmd_status;
2022
2023         host->cmd_status = 0;
2024
2025         /* Read the response from the card (up to 16 bytes) */
2026         if (cmd->flags & MMC_RSP_PRESENT) {
2027                 if (cmd->flags & MMC_RSP_136) {
2028                         cmd->resp[3] = mci_readl(host, RESP0);
2029                         cmd->resp[2] = mci_readl(host, RESP1);
2030                         cmd->resp[1] = mci_readl(host, RESP2);
2031                         cmd->resp[0] = mci_readl(host, RESP3);
2032
2033             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
2034                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
2035                 } else {
2036                         cmd->resp[0] = mci_readl(host, RESP0);
2037                         cmd->resp[1] = 0;
2038                         cmd->resp[2] = 0;
2039                         cmd->resp[3] = 0;
2040             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
2041                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2042                 }
2043         }
2044
2045         if (status & SDMMC_INT_RTO)
2046         {
2047             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2048                 host->cmd_rto += 1;
2049
2050                 cmd->error = -ETIMEDOUT;
2051                 del_timer_sync(&host->dto_timer);
2052         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2053                 del_timer_sync(&host->dto_timer);
2054                 cmd->error = -EILSEQ;
2055         }else if (status & SDMMC_INT_RESP_ERR){
2056                 del_timer_sync(&host->dto_timer);
2057                 cmd->error = -EIO;
2058         }else{
2059                 cmd->error = 0;
2060         }
2061         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",
2062                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2063
2064         if (cmd->error) {
2065                 del_timer_sync(&host->dto_timer);
2066             if(MMC_SEND_STATUS != cmd->opcode)
2067                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2068                         MMC_DBG_ERR_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
2069                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2070                         host->cmd_rto = 0;
2071                 }
2072
2073                 /* newer ip versions need a delay between retries */
2074                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2075                         mdelay(20);
2076         }
2077
2078 }
2079
2080 static void dw_mci_tasklet_func(unsigned long priv)
2081 {
2082         struct dw_mci *host = (struct dw_mci *)priv;
2083         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2084         struct mmc_data *data;
2085         struct mmc_command *cmd;
2086         enum dw_mci_state state;
2087         enum dw_mci_state prev_state;
2088         u32 status, cmd_flags;
2089         unsigned long timeout = 0;
2090         bool ret = true;
2091
2092         spin_lock(&host->lock);
2093
2094         state = host->state;
2095         data = host->data;
2096
2097         do {
2098                 prev_state = state;
2099
2100                 switch (state) {
2101                 case STATE_IDLE:
2102                         break;
2103
2104                 case STATE_SENDING_CMD:
2105                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2106                                                 &host->pending_events))
2107                                 break;
2108
2109                         cmd = host->cmd;
2110                         host->cmd = NULL;
2111                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2112                         dw_mci_command_complete(host, cmd);
2113                         if (cmd == host->mrq->sbc && !cmd->error) {
2114                                 prev_state = state = STATE_SENDING_CMD;
2115                                 __dw_mci_start_request(host, host->cur_slot,
2116                                                        host->mrq->cmd);
2117                                 goto unlock;
2118                         }
2119
2120                         if (cmd->data && cmd->error) {
2121                                 del_timer_sync(&host->dto_timer); /* delete the timer for INT_DTO */
2122                                 dw_mci_stop_dma(host);
2123                                 #if 1
2124                                 if (data->stop) {
2125                                         send_stop_cmd(host, data);
2126                                         state = STATE_SENDING_STOP;
2127                                         break;
2128                                 }else{
2129                                         host->data = NULL;
2130                                 }
2131                                 #else
2132                                 send_stop_abort(host, data);
2133                                 state = STATE_SENDING_STOP;
2134                                 break;
2135                                 #endif
2136                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2137                         }
2138
2139                         if (!host->mrq->data || cmd->error) {
2140                                 dw_mci_request_end(host, host->mrq);
2141                                 goto unlock;
2142                         }
2143
2144                         prev_state = state = STATE_SENDING_DATA;
2145                         /* fall through */
2146
2147                 case STATE_SENDING_DATA:
2148                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
2149                                 dw_mci_stop_dma(host);
2150                                 #if 1
2151                                 if (data->stop){
2152                                         send_stop_cmd(host, data);
2153                                 }else{
2154                                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
2155                                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
2156                                                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
2157
2158                                         mci_writel(host, CMDARG, 0);
2159                                         wmb();
2160                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
2161                                                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2162
2163                                         if(host->mmc->hold_reg_flag)
2164                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2165
2166                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2167                                         wmb();
2168                                         timeout = jiffies + msecs_to_jiffies(500);
2169
2170                                         while(ret){
2171                                                 ret = time_before(jiffies, timeout);
2172                                                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2173                                                         break;
2174                                         }
2175                                         if(false == ret)
2176                                                 MMC_DBG_ERR_FUNC(host->mmc,
2177                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2178                                                         __func__, mmc_hostname(host->mmc));
2179                                 }
2180                                 #else
2181                                 send_stop_abort(host, data);
2182                                 #endif
2183                                 state = STATE_DATA_ERROR;
2184                                 break;
2185                         }
2186
2187                         MMC_DBG_CMD_FUNC(host->mmc,
2188                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
2189                         prev_state,state, mmc_hostname(host->mmc));
2190
2191                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2192                                                 &host->pending_events))
2193                                 break;
2194                         MMC_DBG_INFO_FUNC(host->mmc,
2195                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
2196                                           prev_state,state,mmc_hostname(host->mmc));
2197
2198                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2199                         prev_state = state = STATE_DATA_BUSY;
2200                         /* fall through */
2201
2202                 case STATE_DATA_BUSY:
2203                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2204                                                 &host->pending_events))
2205                                 break;
2206
2207                         dw_mci_deal_data_end(host, host->mrq);
2208                         del_timer_sync(&host->dto_timer); //delete the timer for INT_DTO
2209                         MMC_DBG_INFO_FUNC(host->mmc,
2210                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
2211                                           prev_state,state,mmc_hostname(host->mmc));
2212
2213                         host->data = NULL;
2214                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2215                         status = host->data_status;
2216
2217                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2218                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2219                                 MMC_DBG_ERR_FUNC(host->mmc,
2220                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
2221                             prev_state,state, status, mmc_hostname(host->mmc));
2222
2223                         if (status & SDMMC_INT_DRTO) {
2224                                         data->error = -ETIMEDOUT;
2225                                 } else if (status & SDMMC_INT_DCRC) {
2226                                         data->error = -EILSEQ;
2227                                 } else if (status & SDMMC_INT_EBE &&
2228                                 host->dir_status == DW_MCI_SEND_STATUS){
2229                                         /*
2230                                          * No data CRC status was returned.
2231                                          * The number of bytes transferred will
2232                                          * be exaggerated in PIO mode.
2233                                          */
2234                                         data->bytes_xfered = 0;
2235                                         data->error = -ETIMEDOUT;
2236                                 } else {
2237                                         dev_err(host->dev,
2238                                                 "data FIFO error "
2239                                                 "(status=%08x)\n",
2240                                                 status);
2241                                         data->error = -EIO;
2242                                 }
2243                                 /*
2244                                  * After an error, there may be data lingering
2245                                  * in the FIFO, so reset it - doing so
2246                                  * generates a block interrupt, hence setting
2247                                  * the scatter-gather pointer to NULL.
2248                                  */
2249                                 dw_mci_fifo_reset(host);
2250                         } else {
2251                                 data->bytes_xfered = data->blocks * data->blksz;
2252                                 data->error = 0;
2253                         }
2254
2255                         if (!data->stop) {
2256                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2257                                       prev_state,state,mmc_hostname(host->mmc));
2258                                 dw_mci_request_end(host, host->mrq);
2259                                 goto unlock;
2260                         }
2261                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2262                                                 prev_state,state,mmc_hostname(host->mmc));
2263
2264                         if (host->mrq->sbc && !data->error) {
2265                                 data->stop->error = 0;
2266
2267                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2268                                                 prev_state,state,mmc_hostname(host->mmc));
2269
2270                                 dw_mci_request_end(host, host->mrq);
2271                                 goto unlock;
2272                         }
2273
2274                         prev_state = state = STATE_SENDING_STOP;
2275                         if (!data->error)
2276                             send_stop_cmd(host, data);
2277                         #if 0
2278                         if (data->stop && !data->error) {
2279                                 /* stop command for open-ended transfer*/
2280
2281                                 send_stop_abort(host, data);
2282                         }
2283                         #endif
2284                         /* fall through */
2285                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2286                                                 prev_state,state,mmc_hostname(host->mmc));
2287
2288                 case STATE_SENDING_STOP:
2289                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2290                                 break;
2291
2292                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2293                                                 prev_state, state, mmc_hostname(host->mmc));
2294
2295                         /* CMD error in data command */
2296                         if (host->mrq->cmd->error && host->mrq->data) {
2297                                 dw_mci_fifo_reset(host);
2298                         }
2299
2300                         host->cmd = NULL;
2301                         host->data = NULL;
2302                         #if 1
2303                         dw_mci_command_complete(host, host->mrq->stop);
2304                         #else
2305                         if (host->mrq->stop)
2306                                 dw_mci_command_complete(host, host->mrq->stop);
2307                         else
2308                                 host->cmd_status = 0;
2309                         #endif
2310
2311                         dw_mci_request_end(host, host->mrq);
2312                         goto unlock;
2313
2314                 case STATE_DATA_ERROR:
2315                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2316                                                 &host->pending_events))
2317                                 break;
2318
2319                         state = STATE_DATA_BUSY;
2320                         break;
2321                 }
2322         } while (state != prev_state);
2323
2324         host->state = state;
2325 unlock:
2326         spin_unlock(&host->lock);
2327
2328 }
2329
2330 /* push final bytes to part_buf, only use during push */
2331 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2332 {
2333         memcpy((void *)&host->part_buf, buf, cnt);
2334         host->part_buf_count = cnt;
2335 }
2336
2337 /* append bytes to part_buf, only use during push */
2338 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2339 {
2340         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2341         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2342         host->part_buf_count += cnt;
2343         return cnt;
2344 }
2345
2346 /* pull first bytes from part_buf, only use during pull */
2347 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2348 {
2349         cnt = min(cnt, (int)host->part_buf_count);
2350         if (cnt) {
2351                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2352                        cnt);
2353                 host->part_buf_count -= cnt;
2354                 host->part_buf_start += cnt;
2355         }
2356         return cnt;
2357 }
2358
2359 /* pull final bytes from the part_buf, assuming it's just been filled */
2360 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2361 {
2362         memcpy(buf, &host->part_buf, cnt);
2363         host->part_buf_start = cnt;
2364         host->part_buf_count = (1 << host->data_shift) - cnt;
2365 }
2366
2367 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2368 {
2369         struct mmc_data *data = host->data;
2370         int init_cnt = cnt;
2371
2372         /* try and push anything in the part_buf */
2373         if (unlikely(host->part_buf_count)) {
2374                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2375                 buf += len;
2376                 cnt -= len;
2377                 if (host->part_buf_count == 2) {
2378                         mci_writew(host, DATA(host->data_offset),
2379                                         host->part_buf16);
2380                         host->part_buf_count = 0;
2381                 }
2382         }
2383 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2384         if (unlikely((unsigned long)buf & 0x1)) {
2385                 while (cnt >= 2) {
2386                         u16 aligned_buf[64];
2387                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2388                         int items = len >> 1;
2389                         int i;
2390                         /* memcpy from input buffer into aligned buffer */
2391                         memcpy(aligned_buf, buf, len);
2392                         buf += len;
2393                         cnt -= len;
2394                         /* push data from aligned buffer into fifo */
2395                         for (i = 0; i < items; ++i)
2396                                 mci_writew(host, DATA(host->data_offset),
2397                                                 aligned_buf[i]);
2398                 }
2399         } else
2400 #endif
2401         {
2402                 u16 *pdata = buf;
2403                 for (; cnt >= 2; cnt -= 2)
2404                         mci_writew(host, DATA(host->data_offset), *pdata++);
2405                 buf = pdata;
2406         }
2407         /* put anything remaining in the part_buf */
2408         if (cnt) {
2409                 dw_mci_set_part_bytes(host, buf, cnt);
2410                  /* Push data if we have reached the expected data length */
2411                 if ((data->bytes_xfered + init_cnt) ==
2412                     (data->blksz * data->blocks))
2413                         mci_writew(host, DATA(host->data_offset),
2414                                    host->part_buf16);
2415         }
2416 }
2417
2418 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2419 {
2420 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2421         if (unlikely((unsigned long)buf & 0x1)) {
2422                 while (cnt >= 2) {
2423                         /* pull data from fifo into aligned buffer */
2424                         u16 aligned_buf[64];
2425                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2426                         int items = len >> 1;
2427                         int i;
2428                         for (i = 0; i < items; ++i)
2429                                 aligned_buf[i] = mci_readw(host,
2430                                                 DATA(host->data_offset));
2431                         /* memcpy from aligned buffer into output buffer */
2432                         memcpy(buf, aligned_buf, len);
2433                         buf += len;
2434                         cnt -= len;
2435                 }
2436         } else
2437 #endif
2438         {
2439                 u16 *pdata = buf;
2440                 for (; cnt >= 2; cnt -= 2)
2441                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2442                 buf = pdata;
2443         }
2444         if (cnt) {
2445                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2446                 dw_mci_pull_final_bytes(host, buf, cnt);
2447         }
2448 }
2449
2450 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2451 {
2452         struct mmc_data *data = host->data;
2453         int init_cnt = cnt;
2454
2455         /* try and push anything in the part_buf */
2456         if (unlikely(host->part_buf_count)) {
2457                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2458                 buf += len;
2459                 cnt -= len;
2460                 if (host->part_buf_count == 4) {
2461                         mci_writel(host, DATA(host->data_offset),
2462                                         host->part_buf32);
2463                         host->part_buf_count = 0;
2464                 }
2465         }
2466 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2467         if (unlikely((unsigned long)buf & 0x3)) {
2468                 while (cnt >= 4) {
2469                         u32 aligned_buf[32];
2470                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2471                         int items = len >> 2;
2472                         int i;
2473                         /* memcpy from input buffer into aligned buffer */
2474                         memcpy(aligned_buf, buf, len);
2475                         buf += len;
2476                         cnt -= len;
2477                         /* push data from aligned buffer into fifo */
2478                         for (i = 0; i < items; ++i)
2479                                 mci_writel(host, DATA(host->data_offset),
2480                                                 aligned_buf[i]);
2481                 }
2482         } else
2483 #endif
2484         {
2485                 u32 *pdata = buf;
2486                 for (; cnt >= 4; cnt -= 4)
2487                         mci_writel(host, DATA(host->data_offset), *pdata++);
2488                 buf = pdata;
2489         }
2490         /* put anything remaining in the part_buf */
2491         if (cnt) {
2492                 dw_mci_set_part_bytes(host, buf, cnt);
2493                  /* Push data if we have reached the expected data length */
2494                 if ((data->bytes_xfered + init_cnt) ==
2495                     (data->blksz * data->blocks))
2496                         mci_writel(host, DATA(host->data_offset),
2497                                    host->part_buf32);
2498         }
2499 }
2500
2501 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2502 {
2503 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2504         if (unlikely((unsigned long)buf & 0x3)) {
2505                 while (cnt >= 4) {
2506                         /* pull data from fifo into aligned buffer */
2507                         u32 aligned_buf[32];
2508                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2509                         int items = len >> 2;
2510                         int i;
2511                         for (i = 0; i < items; ++i)
2512                                 aligned_buf[i] = mci_readl(host,
2513                                                 DATA(host->data_offset));
2514                         /* memcpy from aligned buffer into output buffer */
2515                         memcpy(buf, aligned_buf, len);
2516                         buf += len;
2517                         cnt -= len;
2518                 }
2519         } else
2520 #endif
2521         {
2522                 u32 *pdata = buf;
2523                 for (; cnt >= 4; cnt -= 4)
2524                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2525                 buf = pdata;
2526         }
2527         if (cnt) {
2528                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2529                 dw_mci_pull_final_bytes(host, buf, cnt);
2530         }
2531 }
2532
2533 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2534 {
2535         struct mmc_data *data = host->data;
2536         int init_cnt = cnt;
2537
2538         /* try and push anything in the part_buf */
2539         if (unlikely(host->part_buf_count)) {
2540                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2541                 buf += len;
2542                 cnt -= len;
2543
2544                 if (host->part_buf_count == 8) {
2545                         mci_writeq(host, DATA(host->data_offset),
2546                                         host->part_buf);
2547                         host->part_buf_count = 0;
2548                 }
2549         }
2550 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2551         if (unlikely((unsigned long)buf & 0x7)) {
2552                 while (cnt >= 8) {
2553                         u64 aligned_buf[16];
2554                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2555                         int items = len >> 3;
2556                         int i;
2557                         /* memcpy from input buffer into aligned buffer */
2558                         memcpy(aligned_buf, buf, len);
2559                         buf += len;
2560                         cnt -= len;
2561                         /* push data from aligned buffer into fifo */
2562                         for (i = 0; i < items; ++i)
2563                                 mci_writeq(host, DATA(host->data_offset),
2564                                                 aligned_buf[i]);
2565                 }
2566         } else
2567 #endif
2568         {
2569                 u64 *pdata = buf;
2570                 for (; cnt >= 8; cnt -= 8)
2571                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2572                 buf = pdata;
2573         }
2574         /* put anything remaining in the part_buf */
2575         if (cnt) {
2576                 dw_mci_set_part_bytes(host, buf, cnt);
2577                 /* Push data if we have reached the expected data length */
2578                 if ((data->bytes_xfered + init_cnt) ==
2579                     (data->blksz * data->blocks))
2580                         mci_writeq(host, DATA(host->data_offset),
2581                                    host->part_buf);
2582         }
2583 }
2584
2585 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2586 {
2587 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2588         if (unlikely((unsigned long)buf & 0x7)) {
2589                 while (cnt >= 8) {
2590                         /* pull data from fifo into aligned buffer */
2591                         u64 aligned_buf[16];
2592                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2593                         int items = len >> 3;
2594                         int i;
2595                         for (i = 0; i < items; ++i)
2596                                 aligned_buf[i] = mci_readq(host,
2597                                                 DATA(host->data_offset));
2598                         /* memcpy from aligned buffer into output buffer */
2599                         memcpy(buf, aligned_buf, len);
2600                         buf += len;
2601                         cnt -= len;
2602                 }
2603         } else
2604 #endif
2605         {
2606                 u64 *pdata = buf;
2607                 for (; cnt >= 8; cnt -= 8)
2608                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2609                 buf = pdata;
2610         }
2611         if (cnt) {
2612                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2613                 dw_mci_pull_final_bytes(host, buf, cnt);
2614         }
2615 }
2616
2617 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2618 {
2619         int len;
2620
2621         /* get remaining partial bytes */
2622         len = dw_mci_pull_part_bytes(host, buf, cnt);
2623         if (unlikely(len == cnt))
2624                 return;
2625         buf += len;
2626         cnt -= len;
2627
2628         /* get the rest of the data */
2629         host->pull_data(host, buf, cnt);
2630 }
2631
2632 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2633 {
2634         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2635         void *buf;
2636         unsigned int offset;
2637         struct mmc_data *data = host->data;
2638         int shift = host->data_shift;
2639         u32 status;
2640         unsigned int len;
2641         unsigned int remain, fcnt;
2642
2643         if(!host->mmc->bus_refs){
2644                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2645                 goto host_put;
2646         }
2647         do {
2648                 if (!sg_miter_next(sg_miter))
2649                         goto done;
2650
2651                 host->sg = sg_miter->piter.sg;
2652                 buf = sg_miter->addr;
2653                 remain = sg_miter->length;
2654                 offset = 0;
2655
2656                 do {
2657                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2658                                         << shift) + host->part_buf_count;
2659                         len = min(remain, fcnt);
2660                         if (!len)
2661                                 break;
2662                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2663                         data->bytes_xfered += len;
2664                         offset += len;
2665                         remain -= len;
2666                 } while (remain);
2667
2668                 sg_miter->consumed = offset;
2669                 status = mci_readl(host, MINTSTS);
2670                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2671         /* if the RXDR is ready read again */
2672         } while ((status & SDMMC_INT_RXDR) ||
2673                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2674
2675         if (!remain) {
2676                 if (!sg_miter_next(sg_miter))
2677                         goto done;
2678                 sg_miter->consumed = 0;
2679         }
2680         sg_miter_stop(sg_miter);
2681         return;
2682
2683 done:
2684         sg_miter_stop(sg_miter);
2685 host_put:
2686         host->sg = NULL;
2687         smp_wmb();
2688         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2689 }
2690
2691 static void dw_mci_write_data_pio(struct dw_mci *host)
2692 {
2693         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2694         void *buf;
2695         unsigned int offset;
2696         struct mmc_data *data = host->data;
2697         int shift = host->data_shift;
2698         u32 status;
2699         unsigned int len;
2700         unsigned int fifo_depth = host->fifo_depth;
2701         unsigned int remain, fcnt;
2702
2703         if(!host->mmc->bus_refs){
2704                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2705                 goto host_put;
2706         }
2707
2708         do {
2709                 if (!sg_miter_next(sg_miter))
2710                         goto done;
2711
2712                 host->sg = sg_miter->piter.sg;
2713                 buf = sg_miter->addr;
2714                 remain = sg_miter->length;
2715                 offset = 0;
2716
2717                 do {
2718                         fcnt = ((fifo_depth -
2719                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2720                                         << shift) - host->part_buf_count;
2721                         len = min(remain, fcnt);
2722                         if (!len)
2723                                 break;
2724                         host->push_data(host, (void *)(buf + offset), len);
2725                         data->bytes_xfered += len;
2726                         offset += len;
2727                         remain -= len;
2728                 } while (remain);
2729
2730                 sg_miter->consumed = offset;
2731                 status = mci_readl(host, MINTSTS);
2732                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2733         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2734
2735         if (!remain) {
2736                 if (!sg_miter_next(sg_miter))
2737                         goto done;
2738                 sg_miter->consumed = 0;
2739         }
2740         sg_miter_stop(sg_miter);
2741         return;
2742
2743 done:
2744         sg_miter_stop(sg_miter);
2745 host_put:
2746         host->sg = NULL;
2747         smp_wmb();
2748         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2749 }
2750
2751 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2752 {
2753         u32 multi, unit;
2754
2755         if (!host->cmd_status)
2756             host->cmd_status = status;
2757
2758         if(!host->cmd)
2759                 goto cmd_exit;
2760
2761         if((MMC_STOP_TRANSMISSION != host->cmd->opcode))
2762         {
2763                 unit = 2*1024*1024;
2764                 multi = mci_readl(host, BYTCNT)/unit;
2765                 multi += ((mci_readl(host, BYTCNT) % unit) ? 1 :0 );
2766                 multi = (multi > 0) ? multi : 1;
2767                 multi += (host->cmd->retries > 2)? 2 : host->cmd->retries;
2768                 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(4500 * multi));//max wait 8s larger
2769         }
2770
2771 cmd_exit:
2772         smp_wmb();
2773         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2774         tasklet_schedule(&host->tasklet);
2775 }
2776
2777 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2778 {
2779         struct dw_mci *host = dev_id;
2780         u32 pending, sdio_int;
2781         int i;
2782
2783         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2784
2785         /*
2786         * DTO fix - version 2.10a and below, and only if internal DMA
2787         * is configured.
2788         */
2789         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2790                         if (!pending &&
2791                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2792                                 pending |= SDMMC_INT_DATA_OVER;
2793         }
2794
2795         if (pending) {
2796                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2797                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2798                         host->cmd_status = pending;
2799                         smp_wmb();
2800                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
2801                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
2802
2803                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2804                 }
2805
2806                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2807                         /* if there is an error report DATA_ERROR */
2808                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2809                         host->data_status = pending;
2810                         smp_wmb();
2811                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2812
2813                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
2814                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
2815                         tasklet_schedule(&host->tasklet);
2816                 }
2817
2818                 if (pending & SDMMC_INT_DATA_OVER) {
2819                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2820                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2821                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2822                         if (!host->data_status)
2823                                 host->data_status = pending;
2824                         smp_wmb();
2825                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2826                                 if (host->sg != NULL)
2827                                         dw_mci_read_data_pio(host, true);
2828                         }
2829                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2830                         tasklet_schedule(&host->tasklet);
2831                 }
2832
2833                 if (pending & SDMMC_INT_RXDR) {
2834                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2835                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2836                                 dw_mci_read_data_pio(host, false);
2837                 }
2838
2839                 if (pending & SDMMC_INT_TXDR) {
2840                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2841                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2842                                 dw_mci_write_data_pio(host);
2843                 }
2844
2845                 if (pending & SDMMC_INT_VSI) {
2846                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2847                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2848                         dw_mci_cmd_interrupt(host, pending);
2849                 }
2850
2851                 if (pending & SDMMC_INT_CMD_DONE) {
2852                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
2853                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2854                         dw_mci_cmd_interrupt(host, pending);
2855                 }
2856
2857                 if (pending & SDMMC_INT_CD) {
2858                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2859                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
2860                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2861                         queue_work(host->card_workqueue, &host->card_work);
2862                 }
2863
2864                 if (pending & SDMMC_INT_HLE) {
2865                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2866                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
2867
2868                 }
2869
2870                 /* Handle SDIO Interrupts */
2871                 for (i = 0; i < host->num_slots; i++) {
2872                         struct dw_mci_slot *slot = host->slot[i];
2873
2874                         if (host->verid < DW_MMC_240A)
2875                                 sdio_int = SDMMC_INT_SDIO(i);
2876                         else
2877                                 sdio_int = SDMMC_INT_SDIO(i + 8);
2878
2879                         if (pending & sdio_int) {
2880                                 mci_writel(host, RINTSTS, sdio_int);
2881                                 mmc_signal_sdio_irq(slot->mmc);
2882                         }
2883                 }
2884
2885         }
2886
2887 #ifdef CONFIG_MMC_DW_IDMAC
2888         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
2889         if(!(cpu_is_rk3036() || cpu_is_rk312x())){
2890                 /* Handle DMA interrupts */
2891                 pending = mci_readl(host, IDSTS);
2892                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2893                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2894                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2895                         host->dma_ops->complete((void *)host);
2896                 }
2897         }
2898 #endif
2899
2900         return IRQ_HANDLED;
2901 }
2902
2903 static void dw_mci_work_routine_card(struct work_struct *work)
2904 {
2905         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2906         int i;
2907
2908         for (i = 0; i < host->num_slots; i++) {
2909                 struct dw_mci_slot *slot = host->slot[i];
2910                 struct mmc_host *mmc = slot->mmc;
2911                 struct mmc_request *mrq;
2912                 int present;
2913
2914                 present = dw_mci_get_cd(mmc);
2915                 while (present != slot->last_detect_state) {
2916                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
2917                                 present ? "inserted" : "removed");
2918                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
2919                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
2920
2921                         rk_send_wakeup_key();//wake up system
2922                         spin_lock_bh(&host->lock);
2923
2924                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2925                         /* Card change detected */
2926                         slot->last_detect_state = present;
2927
2928                         /* Clean up queue if present */
2929                         mrq = slot->mrq;
2930                         if (mrq) {
2931                                 if (mrq == host->mrq) {
2932                                         host->data = NULL;
2933                                         host->cmd = NULL;
2934
2935                                         switch (host->state) {
2936                                         case STATE_IDLE:
2937                                                 break;
2938                                         case STATE_SENDING_CMD:
2939                                                 mrq->cmd->error = -ENOMEDIUM;
2940                                                 if (!mrq->data)
2941                                                         break;
2942                                                 /* fall through */
2943                                         case STATE_SENDING_DATA:
2944                                                 mrq->data->error = -ENOMEDIUM;
2945                                                 dw_mci_stop_dma(host);
2946                                                 break;
2947                                         case STATE_DATA_BUSY:
2948                                         case STATE_DATA_ERROR:
2949                                                 if (mrq->data->error == -EINPROGRESS)
2950                                                         mrq->data->error = -ENOMEDIUM;
2951                                                 if (!mrq->stop)
2952                                                         break;
2953                                                 /* fall through */
2954                                         case STATE_SENDING_STOP:
2955                                                 mrq->stop->error = -ENOMEDIUM;
2956                                                 break;
2957                                         }
2958
2959                                         dw_mci_request_end(host, mrq);
2960                                 } else {
2961                                         list_del(&slot->queue_node);
2962                                         mrq->cmd->error = -ENOMEDIUM;
2963                                         if (mrq->data)
2964                                                 mrq->data->error = -ENOMEDIUM;
2965                                         if (mrq->stop)
2966                                                 mrq->stop->error = -ENOMEDIUM;
2967
2968                                         MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",
2969                                                         mrq->cmd->opcode, mmc_hostname(mmc));
2970
2971                                         spin_unlock(&host->lock);
2972                                         mmc_request_done(slot->mmc, mrq);
2973                                         spin_lock(&host->lock);
2974                                 }
2975                         }
2976
2977                         /* Power down slot */
2978                         if (present == 0) {
2979                                 /* Clear down the FIFO */
2980                                 dw_mci_fifo_reset(host);
2981 #ifdef CONFIG_MMC_DW_IDMAC
2982                                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
2983                                         dw_mci_idmac_reset(host);
2984 #endif
2985
2986                         }
2987
2988                         spin_unlock_bh(&host->lock);
2989
2990                         present = dw_mci_get_cd(mmc);
2991                 }
2992
2993                 mmc_detect_change(slot->mmc,
2994                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2995         }
2996 }
2997
2998 #ifdef CONFIG_OF
2999 /* given a slot id, find out the device node representing that slot */
3000 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3001 {
3002         struct device_node *np;
3003         const __be32 *addr;
3004         int len;
3005
3006         if (!dev || !dev->of_node)
3007                 return NULL;
3008
3009         for_each_child_of_node(dev->of_node, np) {
3010                 addr = of_get_property(np, "reg", &len);
3011                 if (!addr || (len < sizeof(int)))
3012                         continue;
3013                 if (be32_to_cpup(addr) == slot)
3014                         return np;
3015         }
3016         return NULL;
3017 }
3018
3019 static struct dw_mci_of_slot_quirks {
3020         char *quirk;
3021         int id;
3022 } of_slot_quirks[] = {
3023         {
3024                 .quirk  = "disable-wp",
3025                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3026         },
3027 };
3028
3029 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3030 {
3031         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3032         int quirks = 0;
3033         int idx;
3034
3035         /* get quirks */
3036         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3037                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3038                         quirks |= of_slot_quirks[idx].id;
3039
3040         return quirks;
3041 }
3042
3043 /* find out bus-width for a given slot */
3044 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3045 {
3046         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3047         u32 bus_wd = 1;
3048
3049         if (!np)
3050                 return 1;
3051
3052         if (of_property_read_u32(np, "bus-width", &bus_wd))
3053                 dev_err(dev, "bus-width property not found, assuming width"
3054                                " as 1\n");
3055         return bus_wd;
3056 }
3057
3058
3059 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3060 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3061 {
3062         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3063         int gpio;
3064
3065         if (!np)
3066                 return -EINVAL;
3067
3068         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3069
3070         /* Having a missing entry is valid; return silently */
3071         if (!gpio_is_valid(gpio))
3072                 return -EINVAL;
3073
3074         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3075                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3076                 return -EINVAL;
3077         }
3078
3079     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3080
3081         return gpio;
3082 }
3083
3084
3085 /* find the write protect gpio for a given slot; or -1 if none specified */
3086 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3087 {
3088         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3089         int gpio;
3090
3091         if (!np)
3092                 return -EINVAL;
3093
3094         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3095
3096         /* Having a missing entry is valid; return silently */
3097         if (!gpio_is_valid(gpio))
3098                 return -EINVAL;
3099
3100         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3101                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3102                 return -EINVAL;
3103         }
3104
3105         return gpio;
3106 }
3107
3108 /* find the cd gpio for a given slot */
3109 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3110                                         struct mmc_host *mmc)
3111 {
3112         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3113         int gpio;
3114
3115         if (!np)
3116                 return;
3117
3118         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3119
3120         /* Having a missing entry is valid; return silently */
3121         if (!gpio_is_valid(gpio))
3122                 return;
3123
3124         if (mmc_gpio_request_cd(mmc, gpio, 0))
3125                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3126 }
3127
3128 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3129 {
3130         struct mmc_host *mmc = dev_id;
3131         struct dw_mci_slot *slot = mmc_priv(mmc);
3132         struct dw_mci *host = slot->host;
3133
3134         queue_work(host->card_workqueue, &host->card_work);
3135
3136         return IRQ_HANDLED;
3137 }
3138
3139 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3140                                         struct mmc_host *mmc)
3141 {
3142         struct dw_mci_slot *slot = mmc_priv(mmc);
3143         struct dw_mci *host = slot->host;
3144         int irq;
3145         int ret;
3146
3147         /* Having a missing entry is valid; return silently */
3148         if (!gpio_is_valid(gpio))
3149                 return;
3150
3151         irq = gpio_to_irq(gpio);
3152         if (irq >= 0) {
3153                 ret = devm_request_threaded_irq(&mmc->class_dev, irq,
3154                         NULL, dw_mci_gpio_cd_irqt,
3155                         IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3156                         "dw_mci_cd", mmc);
3157                 if (ret < 0)
3158                         irq = ret;
3159         } else {
3160                 dev_err(host->dev, "Request cd-gpio interrupt error!\n");
3161         }
3162 }
3163 #else /* CONFIG_OF */
3164 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3165 {
3166         return 0;
3167 }
3168 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3169 {
3170         return 1;
3171 }
3172 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3173 {
3174         return NULL;
3175 }
3176 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3177 {
3178         return -EINVAL;
3179 }
3180 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3181                                         struct mmc_host *mmc)
3182 {
3183         return;
3184 }
3185 #endif /* CONFIG_OF */
3186
3187 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3188 {
3189         struct mmc_host *mmc;
3190         struct dw_mci_slot *slot;
3191         const struct dw_mci_drv_data *drv_data = host->drv_data;
3192         int ctrl_id, ret;
3193         u32 freq[2];
3194         u8 bus_width;
3195
3196         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3197         if (!mmc)
3198                 return -ENOMEM;
3199
3200         slot = mmc_priv(mmc);
3201         slot->id = id;
3202         slot->mmc = mmc;
3203         slot->host = host;
3204         host->slot[id] = slot;
3205         host->mmc = mmc;
3206
3207         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3208
3209         mmc->ops = &dw_mci_ops;
3210
3211         if (of_property_read_u32_array(host->dev->of_node,
3212                                        "clock-freq-min-max", freq, 2)) {
3213                 mmc->f_min = DW_MCI_FREQ_MIN;
3214                 mmc->f_max = DW_MCI_FREQ_MAX;
3215
3216         printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__,__FUNCTION__,
3217                 mmc->f_min, mmc->f_max, mmc_hostname(mmc));
3218         } else {
3219                 mmc->f_min = freq[0];
3220                 mmc->f_max = freq[1];
3221
3222         printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__,__FUNCTION__,
3223                 mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
3224         }
3225
3226     if(strstr("mmc0",mmc_hostname(mmc)))
3227         printk("Line%d..%s: The rk_sdmmc %s",__LINE__, __FUNCTION__,RK_SDMMC_DRIVER_VERSION);
3228
3229         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3230                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3231         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3232                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3233         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3234                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3235
3236         /* We assume only low-level chip use gpio_cd */
3237         if (cpu_is_rk312x() &&
3238                 soc_is_rk3126() &&
3239                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3240                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3241                 if (gpio_is_valid(slot->cd_gpio)) {
3242                         /* Request gpio int for card detection */
3243                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3244                 } else {
3245                         slot->cd_gpio = -ENODEV;
3246                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3247                 }
3248         }
3249
3250         if (host->pdata->get_ocr)
3251                 mmc->ocr_avail = host->pdata->get_ocr(id);
3252         else
3253         {
3254                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
3255                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
3256                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
3257                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
3258         }
3259
3260         /*
3261          * Start with slot power disabled, it will be enabled when a card
3262          * is detected.
3263          */
3264         if (host->pdata->setpower)
3265                 host->pdata->setpower(id, 0);
3266
3267         if (host->pdata->caps)
3268                 mmc->caps = host->pdata->caps;
3269
3270         if (host->pdata->pm_caps)
3271                 mmc->pm_caps = host->pdata->pm_caps;
3272
3273         if (host->dev->of_node) {
3274                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3275                 if (ctrl_id < 0)
3276                         ctrl_id = 0;
3277         } else {
3278                 ctrl_id = to_platform_device(host->dev)->id;
3279         }
3280         if (drv_data && drv_data->caps)
3281                 mmc->caps |= drv_data->caps[ctrl_id];
3282         if (drv_data && drv_data->hold_reg_flag)
3283                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3284
3285         /* set the compatibility of driver. */
3286         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3287                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3288
3289         if (host->pdata->caps2)
3290                 mmc->caps2 = host->pdata->caps2;
3291
3292         if (host->pdata->get_bus_wd)
3293                 bus_width = host->pdata->get_bus_wd(slot->id);
3294         else if (host->dev->of_node)
3295                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3296         else
3297                 bus_width = 1;
3298
3299         switch (bus_width) {
3300                 case 8:
3301                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3302                 case 4:
3303                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3304         }
3305
3306         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3307                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3308         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3309                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3310         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3311                 mmc->caps |= MMC_CAP_HW_RESET;
3312         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3313                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3314         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3315                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3316         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3317                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3318         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3319                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3320
3321         /*Assign pm_caps pass to pm_flags*/
3322         mmc->pm_flags = mmc->pm_caps;
3323
3324         if (host->pdata->blk_settings) {
3325                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3326                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3327                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3328                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3329                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3330         } else {
3331                 /* Useful defaults if platform data is unset. */
3332 #ifdef CONFIG_MMC_DW_IDMAC
3333                 mmc->max_segs = host->ring_size;
3334                 mmc->max_blk_size = 65536;
3335                 mmc->max_blk_count = host->ring_size;
3336                 mmc->max_seg_size = 0x1000;
3337                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3338                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3339                         /* fixup for external dmac setting */
3340                         mmc->max_segs = 64;
3341                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3342                         mmc->max_blk_count = 65535;
3343                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3344                         mmc->max_seg_size = mmc->max_req_size;
3345                 }
3346 #else
3347                 mmc->max_segs = 64;
3348                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3349                 mmc->max_blk_count = 512;
3350                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3351                 mmc->max_seg_size = mmc->max_req_size;
3352 #endif /* CONFIG_MMC_DW_IDMAC */
3353
3354         }
3355         /* pwr_en */
3356         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3357
3358         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3359         {
3360                 host->vmmc = NULL;
3361         }else{
3362
3363                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3364                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3365                 else
3366                         host->vmmc = NULL;
3367
3368                 if (IS_ERR(host->vmmc)) {
3369                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3370                         host->vmmc = NULL;
3371                 }else{
3372                         ret = regulator_enable(host->vmmc);
3373                         if (ret) {
3374                                 dev_err(host->dev,
3375                                         "failed to enable regulator: %d\n", ret);
3376                                 host->vmmc = NULL;
3377                                 goto err_setup_bus;
3378                         }
3379                 }
3380         }
3381
3382         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3383
3384         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3385                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3386
3387         ret = mmc_add_host(mmc);
3388         if (ret)
3389                 goto err_setup_bus;
3390
3391         /* Pinctrl set default iomux state to fucntion port.
3392          * Fixme: DON'T TOUCH EMMC SETTING!
3393          */
3394         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3395         {
3396                 host->pinctrl = devm_pinctrl_get(host->dev);
3397                 if(IS_ERR(host->pinctrl)){
3398                         printk("%s: Warning : No pinctrl used!\n",mmc_hostname(host->mmc));
3399                 }else{
3400                         host->pins_idle= pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_IDLE);
3401                         if(IS_ERR(host->pins_default)){
3402                                 printk("%s: Warning : No IDLE pinctrl matched!\n", mmc_hostname(host->mmc));
3403                         }
3404                         else
3405                         {
3406                                 if(pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3407                                         printk("%s: Warning :  Idle pinctrl setting failed!\n", mmc_hostname(host->mmc));
3408                         }
3409
3410                         host->pins_default = pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_DEFAULT);
3411                         if(IS_ERR(host->pins_default)){
3412                                 printk("%s: Warning : No default pinctrl matched!\n", mmc_hostname(host->mmc));
3413                         }
3414                         else
3415                         {
3416                                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3417                                         printk("%s: Warning :  Default pinctrl setting failed!\n", mmc_hostname(host->mmc));
3418                         }
3419                 }
3420         }
3421
3422
3423 #if defined(CONFIG_DEBUG_FS)
3424         dw_mci_init_debugfs(slot);
3425 #endif
3426
3427         /* Card initially undetected */
3428         slot->last_detect_state = 1;
3429
3430         return 0;
3431
3432 err_setup_bus:
3433         mmc_free_host(mmc);
3434         return -EINVAL;
3435 }
3436
3437 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3438 {
3439         /* Shutdown detect IRQ */
3440         if (slot->host->pdata->exit)
3441                 slot->host->pdata->exit(id);
3442
3443         /* Debugfs stuff is cleaned up by mmc core */
3444         mmc_remove_host(slot->mmc);
3445         slot->host->slot[id] = NULL;
3446         mmc_free_host(slot->mmc);
3447 }
3448
3449 static void dw_mci_init_dma(struct dw_mci *host)
3450 {
3451         /* Alloc memory for sg translation */
3452         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3453                                           &host->sg_dma, GFP_KERNEL);
3454         if (!host->sg_cpu) {
3455                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3456                         __func__);
3457                 goto no_dma;
3458         }
3459
3460         /* Determine which DMA interface to use */
3461 #if defined(CONFIG_MMC_DW_IDMAC)
3462         if(cpu_is_rk3036() || cpu_is_rk312x()){
3463                 host->dma_ops = &dw_mci_edmac_ops;
3464                 dev_info(host->dev, "Using external DMA controller.\n");
3465         }else{
3466                 host->dma_ops = &dw_mci_idmac_ops;
3467                 dev_info(host->dev, "Using internal DMA controller.\n");
3468         }
3469 #endif
3470
3471         if (!host->dma_ops)
3472                 goto no_dma;
3473
3474         if (host->dma_ops->init && host->dma_ops->start &&
3475             host->dma_ops->stop && host->dma_ops->cleanup) {
3476                 if (host->dma_ops->init(host)) {
3477                         dev_err(host->dev, "%s: Unable to initialize "
3478                                 "DMA Controller.\n", __func__);
3479                         goto no_dma;
3480                 }
3481         } else {
3482                 dev_err(host->dev, "DMA initialization not found.\n");
3483                 goto no_dma;
3484         }
3485
3486         host->use_dma = 1;
3487         return;
3488
3489 no_dma:
3490         dev_info(host->dev, "Using PIO mode.\n");
3491         host->use_dma = 0;
3492         return;
3493 }
3494
3495 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3496 {
3497         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3498         u32 ctrl;
3499
3500         ctrl = mci_readl(host, CTRL);
3501         ctrl |= reset;
3502         mci_writel(host, CTRL, ctrl);
3503
3504         /* wait till resets clear */
3505         do {
3506                 ctrl = mci_readl(host, CTRL);
3507                 if (!(ctrl & reset))
3508                         return true;
3509         } while (time_before(jiffies, timeout));
3510
3511         dev_err(host->dev,
3512                 "Timeout resetting block (ctrl reset %#x)\n",
3513                 ctrl & reset);
3514
3515         return false;
3516 }
3517
3518 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3519 {
3520         /*
3521          * Reseting generates a block interrupt, hence setting
3522          * the scatter-gather pointer to NULL.
3523          */
3524         if (host->sg) {
3525                 sg_miter_stop(&host->sg_miter);
3526                 host->sg = NULL;
3527         }
3528
3529         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3530 }
3531
3532 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3533 {
3534         return dw_mci_ctrl_reset(host,
3535                                  SDMMC_CTRL_FIFO_RESET |
3536                                  SDMMC_CTRL_RESET |
3537                                  SDMMC_CTRL_DMA_RESET);
3538 }
3539
3540 #ifdef CONFIG_OF
3541 /*
3542 static struct dw_mci_of_quirks {
3543         char *quirk;
3544         int id;
3545 } of_quirks[] = {
3546         {
3547                 .quirk  = "broken-cd",
3548                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3549         },
3550 };
3551 */
3552 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3553 {
3554         struct dw_mci_board *pdata;
3555         struct device *dev = host->dev;
3556         struct device_node *np = dev->of_node;
3557         const struct dw_mci_drv_data *drv_data = host->drv_data;
3558         int  ret;
3559         u32 clock_frequency;
3560
3561         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3562         if (!pdata) {
3563                 dev_err(dev, "could not allocate memory for pdata\n");
3564                 return ERR_PTR(-ENOMEM);
3565         }
3566
3567         /* find out number of slots supported */
3568         if (of_property_read_u32(dev->of_node, "num-slots",
3569                                 &pdata->num_slots)) {
3570                 dev_info(dev, "num-slots property not found, "
3571                                 "assuming 1 slot is available\n");
3572                 pdata->num_slots = 1;
3573         }
3574 #if 0
3575         /* get quirks */
3576         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3577                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3578                         pdata->quirks |= of_quirks[idx].id;
3579 #endif
3580
3581         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3582                 dev_info(dev, "fifo-depth property not found, using "
3583                                 "value of FIFOTH register as default\n");
3584
3585         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3586
3587         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3588                 pdata->bus_hz = clock_frequency;
3589
3590         if (drv_data && drv_data->parse_dt) {
3591                 ret = drv_data->parse_dt(host);
3592                 if (ret)
3593                         return ERR_PTR(ret);
3594         }
3595
3596         if (of_find_property(np, "keep-power-in-suspend", NULL))
3597                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3598
3599         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3600                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3601
3602         if (of_find_property(np, "supports-highspeed", NULL))
3603                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3604
3605     if (of_find_property(np, "supports-UHS_SDR104", NULL))
3606                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3607
3608     if (of_find_property(np, "supports-DDR_MODE", NULL))
3609                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3610
3611     if (of_find_property(np, "caps2-mmc-hs200", NULL))
3612                 pdata->caps2 |= MMC_CAP2_HS200;
3613
3614         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3615                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3616
3617         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3618                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3619
3620         if (of_get_property(np, "cd-inverted", NULL))
3621                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3622         if (of_get_property(np, "bootpart-no-access", NULL))
3623                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3624
3625         return pdata;
3626 }
3627
3628 #else /* CONFIG_OF */
3629 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3630 {
3631         return ERR_PTR(-EINVAL);
3632 }
3633 #endif /* CONFIG_OF */
3634
3635 static void dw_mci_dealwith_timeout(struct dw_mci *host)
3636 {
3637         u32 ret, i, regs;
3638
3639         switch(host->state){
3640                 case STATE_IDLE:
3641                         break;
3642                 case STATE_SENDING_DATA:
3643                 case STATE_DATA_BUSY:
3644                         host->data_status |= (SDMMC_INT_DCRC|SDMMC_INT_EBE);
3645                         mci_writel(host, RINTSTS, SDMMC_INT_DRTO);  // clear interrupt
3646                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3647                         host->state = STATE_DATA_BUSY;
3648                         if (!dw_mci_ctrl_all_reset(host)) {
3649                                 ret = -ENODEV;
3650                                 return ;
3651                         }
3652
3653                         /* NO requirement to reclaim slave chn using external dmac */
3654                         #ifdef CONFIG_MMC_DW_IDMAC
3655                         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3656                                 if (host->use_dma && host->dma_ops->init)
3657                                         host->dma_ops->init(host);
3658                         #endif
3659
3660                         /*
3661                          * Restore the initial value at FIFOTH register
3662                          * And Invalidate the prev_blksz with zero
3663                          */
3664                         mci_writel(host, FIFOTH, host->fifoth_val);
3665                         host->prev_blksz = 0;
3666                         mci_writel(host, TMOUT, 0xFFFFFFFF);
3667                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3668                         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
3669                                         | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
3670                         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
3671                                 regs |= SDMMC_INT_CD;
3672                                 mci_writel(host, INTMASK, regs);
3673                         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3674                         for (i = 0; i < host->num_slots; i++) {
3675                                 struct dw_mci_slot *slot = host->slot[i];
3676                                 if (!slot)
3677                                         continue;
3678                                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3679                                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3680                                         dw_mci_setup_bus(slot, true);
3681                                 }
3682                         }
3683                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3684                         tasklet_schedule(&host->tasklet);
3685                         break;
3686                 default:
3687                         break;
3688     }
3689 }
3690 static void dw_mci_dto_timeout(unsigned long host_data)
3691 {
3692         struct dw_mci *host = (struct dw_mci *) host_data;
3693
3694         disable_irq(host->irq);
3695
3696         host->data_status = SDMMC_INT_EBE;
3697         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3698         dw_mci_dealwith_timeout(host);
3699
3700         enable_irq(host->irq);
3701 }
3702 int dw_mci_probe(struct dw_mci *host)
3703 {
3704         const struct dw_mci_drv_data *drv_data = host->drv_data;
3705         int width, i, ret = 0;
3706         u32 fifo_size;
3707         int init_slots = 0;
3708         u32 regs;
3709
3710         if (!host->pdata) {
3711                 host->pdata = dw_mci_parse_dt(host);
3712                 if (IS_ERR(host->pdata)) {
3713                         dev_err(host->dev, "platform data not available\n");
3714                         return -EINVAL;
3715                 }
3716         }
3717
3718         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3719                 dev_err(host->dev,
3720                         "Platform data must supply select_slot function\n");
3721                 return -ENODEV;
3722         }
3723
3724         /*
3725          * In 2.40a spec, Data offset is changed.
3726          * Need to check the version-id and set data-offset for DATA register.
3727          */
3728         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3729         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3730
3731         if (host->verid < DW_MMC_240A)
3732                 host->data_offset = DATA_OFFSET;
3733         else
3734                 host->data_offset = DATA_240A_OFFSET;
3735
3736         //hclk enable
3737         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3738         if (IS_ERR(host->hclk_mmc)) {
3739                 dev_err(host->dev, "failed to get hclk_mmc\n");
3740                 ret = PTR_ERR(host->hclk_mmc);
3741                 goto err_hclk_mmc;
3742         }
3743
3744         clk_prepare_enable(host->hclk_mmc);
3745
3746         //mmc clk enable
3747         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3748         if (IS_ERR(host->clk_mmc)) {
3749                 dev_err(host->dev, "failed to get clk mmc_per\n");
3750                 ret = PTR_ERR(host->clk_mmc);
3751                 goto err_clk_mmc;
3752         }
3753
3754         host->bus_hz = host->pdata->bus_hz;
3755         if (!host->bus_hz) {
3756                 dev_err(host->dev,"Platform data must supply bus speed\n");
3757                 ret = -ENODEV;
3758                 goto err_clk_mmc;
3759         }
3760
3761         if (host->verid < DW_MMC_240A)
3762                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
3763         else
3764                 //rockchip: fix divider 2 in clksum before controlller
3765                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
3766
3767         if(ret < 0) {
3768             dev_err(host->dev, "failed to set clk mmc\n");
3769             goto err_clk_mmc;
3770         }
3771         clk_prepare_enable(host->clk_mmc);
3772
3773         if (drv_data && drv_data->setup_clock) {
3774         ret = drv_data->setup_clock(host);
3775         if (ret) {
3776             dev_err(host->dev,
3777                 "implementation specific clock setup failed\n");
3778             goto err_clk_mmc;
3779         }
3780     }
3781
3782         host->quirks = host->pdata->quirks;
3783         host->irq_state = true;
3784         host->set_speed = 0;
3785         host->set_div = 0;
3786         host->svi_flags = 0;
3787
3788         spin_lock_init(&host->lock);
3789         INIT_LIST_HEAD(&host->queue);
3790
3791         /*
3792          * Get the host data width - this assumes that HCON has been set with
3793          * the correct values.
3794          */
3795         i = (mci_readl(host, HCON) >> 7) & 0x7;
3796         if (!i) {
3797                 host->push_data = dw_mci_push_data16;
3798                 host->pull_data = dw_mci_pull_data16;
3799                 width = 16;
3800                 host->data_shift = 1;
3801         } else if (i == 2) {
3802                 host->push_data = dw_mci_push_data64;
3803                 host->pull_data = dw_mci_pull_data64;
3804                 width = 64;
3805                 host->data_shift = 3;
3806         } else {
3807                 /* Check for a reserved value, and warn if it is */
3808                 WARN((i != 1),
3809                      "HCON reports a reserved host data width!\n"
3810                      "Defaulting to 32-bit access.\n");
3811                 host->push_data = dw_mci_push_data32;
3812                 host->pull_data = dw_mci_pull_data32;
3813                 width = 32;
3814                 host->data_shift = 2;
3815         }
3816
3817         /* Reset all blocks */
3818         if (!dw_mci_ctrl_all_reset(host))
3819                 return -ENODEV;
3820
3821         host->dma_ops = host->pdata->dma_ops;
3822         dw_mci_init_dma(host);
3823
3824         /* Clear the interrupts for the host controller */
3825         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3826         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3827
3828         /* Put in max timeout */
3829         mci_writel(host, TMOUT, 0xFFFFFFFF);
3830
3831         /*
3832          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3833          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3834          */
3835         if (!host->pdata->fifo_depth) {
3836                 /*
3837                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3838                  * have been overwritten by the bootloader, just like we're
3839                  * about to do, so if you know the value for your hardware, you
3840                  * should put it in the platform data.
3841                  */
3842                 fifo_size = mci_readl(host, FIFOTH);
3843                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3844         } else {
3845                 fifo_size = host->pdata->fifo_depth;
3846         }
3847         host->fifo_depth = fifo_size;
3848         host->fifoth_val =
3849                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3850         mci_writel(host, FIFOTH, host->fifoth_val);
3851
3852         /* disable clock to CIU */
3853         mci_writel(host, CLKENA, 0);
3854         mci_writel(host, CLKSRC, 0);
3855
3856         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3857         host->card_workqueue = alloc_workqueue("dw-mci-card",
3858                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
3859         if (!host->card_workqueue) {
3860                 ret = -ENOMEM;
3861                 goto err_dmaunmap;
3862         }
3863         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
3864         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3865                                host->irq_flags, "dw-mci", host);
3866         if (ret)
3867                 goto err_workqueue;
3868
3869         if (host->pdata->num_slots)
3870                 host->num_slots = host->pdata->num_slots;
3871         else
3872                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
3873
3874         setup_timer(&host->dto_timer, dw_mci_dto_timeout, (unsigned long)host);
3875         /* We need at least one slot to succeed */
3876         for (i = 0; i < host->num_slots; i++) {
3877                 ret = dw_mci_init_slot(host, i);
3878                 if (ret)
3879                         dev_dbg(host->dev, "slot %d init failed\n", i);
3880                 else
3881                         init_slots++;
3882         }
3883
3884         /*
3885          * Enable interrupts for command done, data over, data empty, card det,
3886          * receive ready and error such as transmit, receive timeout, crc error
3887          */
3888         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3889         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
3890                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
3891         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3892             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3893             regs |= SDMMC_INT_CD;
3894
3895         mci_writel(host, INTMASK, regs);
3896
3897         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
3898
3899         dev_info(host->dev, "DW MMC controller at irq %d, "
3900                  "%d bit host data width, "
3901                  "%u deep fifo\n",
3902                  host->irq, width, fifo_size);
3903
3904         if (init_slots) {
3905                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3906         } else {
3907                 dev_dbg(host->dev, "attempted to initialize %d slots, "
3908                                         "but failed on all\n", host->num_slots);
3909                 goto err_workqueue;
3910         }
3911
3912
3913         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
3914                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
3915
3916         return 0;
3917
3918 err_workqueue:
3919         destroy_workqueue(host->card_workqueue);
3920
3921 err_dmaunmap:
3922         if (host->use_dma && host->dma_ops->exit)
3923                 host->dma_ops->exit(host);
3924
3925         if (host->vmmc){
3926                 regulator_disable(host->vmmc);
3927                 regulator_put(host->vmmc);
3928         }
3929
3930 err_clk_mmc:
3931     if (!IS_ERR(host->clk_mmc))
3932                 clk_disable_unprepare(host->clk_mmc);
3933 err_hclk_mmc:
3934     if (!IS_ERR(host->hclk_mmc))
3935                 clk_disable_unprepare(host->hclk_mmc);
3936
3937         return ret;
3938 }
3939 EXPORT_SYMBOL(dw_mci_probe);
3940
3941 void dw_mci_remove(struct dw_mci *host)
3942 {
3943         int i;
3944         del_timer_sync(&host->dto_timer);
3945
3946         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3947         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3948
3949         for(i = 0; i < host->num_slots; i++){
3950                 dev_dbg(host->dev, "remove slot %d\n", i);
3951                 if(host->slot[i])
3952                         dw_mci_cleanup_slot(host->slot[i], i);
3953         }
3954
3955         /* disable clock to CIU */
3956         mci_writel(host, CLKENA, 0);
3957         mci_writel(host, CLKSRC, 0);
3958
3959         destroy_workqueue(host->card_workqueue);
3960
3961         if(host->use_dma && host->dma_ops->exit)
3962                 host->dma_ops->exit(host);
3963
3964         if(host->vmmc){
3965                 regulator_disable(host->vmmc);
3966                 regulator_put(host->vmmc);
3967         }
3968         if(!IS_ERR(host->clk_mmc))
3969                 clk_disable_unprepare(host->clk_mmc);
3970
3971         if(!IS_ERR(host->hclk_mmc))
3972                 clk_disable_unprepare(host->hclk_mmc);
3973 }
3974 EXPORT_SYMBOL(dw_mci_remove);
3975
3976
3977
3978 #ifdef CONFIG_PM_SLEEP
3979 /*
3980  * TODO: we should probably disable the clock to the card in the suspend path.
3981  */
3982 int dw_mci_suspend(struct dw_mci *host)
3983 {
3984         if(host->vmmc)
3985                 regulator_disable(host->vmmc);
3986
3987         if(host->use_dma && host->dma_ops->exit)
3988                 host->dma_ops->exit(host);
3989
3990         /*only for sdmmc controller*/
3991         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3992                 host->mmc->rescan_disable = 1;
3993                 if (cancel_delayed_work_sync(&host->mmc->detect))
3994                         wake_unlock(&host->mmc->detect_wake_lock);
3995
3996                 disable_irq(host->irq);
3997                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3998                         MMC_DBG_ERR_FUNC(host->mmc, "Idle pinctrl setting failed! [%s]",
3999                                                 mmc_hostname(host->mmc));
4000
4001                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4002                 mci_writel(host, INTMASK, 0x00);
4003                 mci_writel(host, CTRL, 0x00);
4004
4005                 /* Soc rk3126 already in gpio_cd mode */
4006                 if (!(cpu_is_rk312x() && soc_is_rk3126())) {
4007                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4008                         enable_irq_wake(host->mmc->slot.cd_irq);
4009                 }
4010         }
4011         return 0;
4012 }
4013 EXPORT_SYMBOL(dw_mci_suspend);
4014
4015 int dw_mci_resume(struct dw_mci *host)
4016 {
4017         int i, ret, retry_cnt = 0;
4018         u32 regs;
4019         struct dw_mci_slot *slot;
4020
4021         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO){
4022                 slot = mmc_priv(host->mmc);
4023
4024                 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4025                         return 0;
4026         }
4027         /*only for sdmmc controller*/
4028         if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4029                 /* Soc rk3126 already in gpio_cd mode */
4030                 if (!(cpu_is_rk312x() && soc_is_rk3126())) {
4031                         disable_irq_wake(host->mmc->slot.cd_irq);
4032                         mmc_gpio_free_cd(host->mmc);
4033                 }
4034                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4035                         MMC_DBG_ERR_FUNC(host->mmc, "Default pinctrl setting failed! [%s]",
4036                                                 mmc_hostname(host->mmc));
4037                 host->mmc->rescan_disable = 0;
4038                 /* Disable jtag*/
4039                 if(cpu_is_rk3288())
4040                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4041                 else if(cpu_is_rk3036())
4042                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4043                 else if(cpu_is_rk312x())
4044                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4045                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4046         }
4047         if(host->vmmc){
4048                 ret = regulator_enable(host->vmmc);
4049                 if (ret){
4050                         dev_err(host->dev,
4051                                 "failed to enable regulator: %d\n", ret);
4052                         return ret;
4053                 }
4054         }
4055
4056         if(!dw_mci_ctrl_all_reset(host)){
4057                 ret = -ENODEV;
4058                 return ret;
4059         }
4060
4061         if(host->use_dma && host->dma_ops->init)
4062                 host->dma_ops->init(host);
4063
4064         /*
4065          * Restore the initial value at FIFOTH register
4066          * And Invalidate the prev_blksz with zero
4067          */
4068         mci_writel(host, FIFOTH, host->fifoth_val);
4069         host->prev_blksz = 0;
4070         /* Put in max timeout */
4071         mci_writel(host, TMOUT, 0xFFFFFFFF);
4072
4073         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4074         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
4075                    DW_MCI_ERROR_FLAGS;
4076         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4077             regs |= SDMMC_INT_CD;
4078         mci_writel(host, INTMASK, regs);
4079         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4080         /*only for sdmmc controller*/
4081         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)&& (!retry_cnt)){
4082                 enable_irq(host->irq);
4083         }
4084
4085         for(i = 0; i < host->num_slots; i++){
4086                 struct dw_mci_slot *slot = host->slot[i];
4087                 if(!slot)
4088                         continue;
4089                 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4090                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4091                         dw_mci_setup_bus(slot, true);
4092                 }
4093         }
4094
4095         return 0;
4096 }
4097 EXPORT_SYMBOL(dw_mci_resume);
4098 #endif /* CONFIG_PM_SLEEP */
4099
4100 static int __init dw_mci_init(void)
4101 {
4102         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4103         return 0;
4104 }
4105
4106 static void __exit dw_mci_exit(void)
4107 {
4108 }
4109
4110 module_init(dw_mci_init);
4111 module_exit(dw_mci_exit);
4112
4113 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4114 MODULE_AUTHOR("NXP Semiconductor VietNam");
4115 MODULE_AUTHOR("Imagination Technologies Ltd");
4116 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4117 MODULE_AUTHOR("Rockchip Electronics£¬Bangwang Xie < xbw@rock-chips.com> ");
4118 MODULE_LICENSE("GPL v2");