drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/card.h>
  37 #include <linux/mmc/sdio.h>
  38 #include <linux/mmc/rk_mmc.h>
  39 #include <linux/bitops.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/of.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/mmc/slot-gpio.h>
  45 #include <linux/clk-private.h>
  46 #include <linux/rockchip/cpu.h>
  47
  48 #include "rk_sdmmc.h"
  49 #include "rk_sdmmc_dbg.h"
  50 #include <linux/regulator/rockchip_io_vol_domain.h>
  51 #include "../../clk/rockchip/clk-ops.h"
  52
  53 #define RK_SDMMC_DRIVER_VERSION "Ver 1.13 2014-09-05"
  54
  55 /* Common flag combinations */
  56 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  57                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  58                                  SDMMC_INT_EBE)
  59 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  60                                  SDMMC_INT_RESP_ERR)
  61 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  62                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  63 #define DW_MCI_SEND_STATUS      1
  64 #define DW_MCI_RECV_STATUS      2
  65 #define DW_MCI_DMA_THRESHOLD    16
  66
  67 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  68 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  69
  70 /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  71 #define SDMMC_DATA_TIMEOUT_SD   500
  72 #define SDMMC_DATA_TIMEOUT_SDIO 250
  73 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  74
  75 #define SDMMC_CMD_RTO_MAX_HOLD  200
  76 #define SDMMC_WAIT_FOR_UNBUSY   2500
  77
  78 #ifdef CONFIG_MMC_DW_IDMAC
  79 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  80                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  81                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  82                                  SDMMC_IDMAC_INT_TI)
  83
  84 struct idmac_desc {
  85         u32             des0;   /* Control Descriptor */
  86 #define IDMAC_DES0_DIC  BIT(1)
  87 #define IDMAC_DES0_LD   BIT(2)
  88 #define IDMAC_DES0_FD   BIT(3)
  89 #define IDMAC_DES0_CH   BIT(4)
  90 #define IDMAC_DES0_ER   BIT(5)
  91 #define IDMAC_DES0_CES  BIT(30)
  92 #define IDMAC_DES0_OWN  BIT(31)
  93
  94         u32             des1;   /* Buffer sizes */
  95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  96         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  97
  98         u32             des2;   /* buffer 1 physical address */
  99
 100         u32             des3;   /* buffer 2 physical address */
 101 };
 102 #endif /* CONFIG_MMC_DW_IDMAC */
 103
 104 static const u8 tuning_blk_pattern_4bit[] = {
 105         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 106         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 107         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 108         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 109         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 110         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 111         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 112         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 113 };
 114
 115 static const u8 tuning_blk_pattern_8bit[] = {
 116         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 117         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 118         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 119         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 120         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 121         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 122         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 123         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 124         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 125         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 126         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 127         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 128         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 129         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 130         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 131         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 132 };
 133
 134 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 135 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 136 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 137 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 138
 139 /*printk the all register of current host*/
 140 #if 0
 141 static int dw_mci_regs_printk(struct dw_mci *host)
 142 {
 143     struct sdmmc_reg *regs = dw_mci_regs;
 144
 145     while( regs->name != 0 ){
 146         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 147         regs++;
 148     }
 149     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 150     return 0;
 151 }
 152 #endif
 153
 154 #if defined(CONFIG_DEBUG_FS)
 155 static int dw_mci_req_show(struct seq_file *s, void *v)
 156 {
 157         struct dw_mci_slot *slot = s->private;
 158         struct mmc_request *mrq;
 159         struct mmc_command *cmd;
 160         struct mmc_command *stop;
 161         struct mmc_data *data;
 162
 163         /* Make sure we get a consistent snapshot */
 164         spin_lock_bh(&slot->host->lock);
 165         mrq = slot->mrq;
 166
 167         if (mrq) {
 168                 cmd = mrq->cmd;
 169                 data = mrq->data;
 170                 stop = mrq->stop;
 171
 172                 if (cmd)
 173                         seq_printf(s,
 174                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 175                                    cmd->opcode, cmd->arg, cmd->flags,
 176                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 177                                    cmd->resp[2], cmd->error);
 178                 if (data)
 179                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 180                                    data->bytes_xfered, data->blocks,
 181                                    data->blksz, data->flags, data->error);
 182                 if (stop)
 183                         seq_printf(s,
 184                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 185                                    stop->opcode, stop->arg, stop->flags,
 186                                    stop->resp[0], stop->resp[1], stop->resp[2],
 187                                    stop->resp[2], stop->error);
 188         }
 189
 190         spin_unlock_bh(&slot->host->lock);
 191
 192         return 0;
 193 }
 194
 195 static int dw_mci_req_open(struct inode *inode, struct file *file)
 196 {
 197         return single_open(file, dw_mci_req_show, inode->i_private);
 198 }
 199
 200 static const struct file_operations dw_mci_req_fops = {
 201         .owner          = THIS_MODULE,
 202         .open           = dw_mci_req_open,
 203         .read           = seq_read,
 204         .llseek         = seq_lseek,
 205         .release        = single_release,
 206 };
 207
 208 static int dw_mci_regs_show(struct seq_file *s, void *v)
 209 {
 210         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 211         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 212         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 213         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 214         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 215         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 216
 217         return 0;
 218 }
 219
 220 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 221 {
 222         return single_open(file, dw_mci_regs_show, inode->i_private);
 223 }
 224
 225 static const struct file_operations dw_mci_regs_fops = {
 226         .owner          = THIS_MODULE,
 227         .open           = dw_mci_regs_open,
 228         .read           = seq_read,
 229         .llseek         = seq_lseek,
 230         .release        = single_release,
 231 };
 232
 233 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 234 {
 235         struct mmc_host *mmc = slot->mmc;
 236         struct dw_mci *host = slot->host;
 237         struct dentry *root;
 238         struct dentry *node;
 239
 240         root = mmc->debugfs_root;
 241         if (!root)
 242                 return;
 243
 244         node = debugfs_create_file("regs", S_IRUSR, root, host,
 245                                    &dw_mci_regs_fops);
 246         if (!node)
 247                 goto err;
 248
 249         node = debugfs_create_file("req", S_IRUSR, root, slot,
 250                                    &dw_mci_req_fops);
 251         if (!node)
 252                 goto err;
 253
 254         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 255         if (!node)
 256                 goto err;
 257
 258         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 259                                   (u32 *)&host->pending_events);
 260         if (!node)
 261                 goto err;
 262
 263         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 264                                   (u32 *)&host->completed_events);
 265         if (!node)
 266                 goto err;
 267
 268         return;
 269
 270 err:
 271         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 272 }
 273 #endif /* defined(CONFIG_DEBUG_FS) */
 274
 275 static void dw_mci_set_timeout(struct dw_mci *host)
 276 {
 277         /* timeout (maximum) */
 278         mci_writel(host, TMOUT, 0xffffffff);
 279 }
 280
 281 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 282 {
 283         struct mmc_data *data;
 284         struct dw_mci_slot *slot = mmc_priv(mmc);
 285         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 286         u32 cmdr;
 287         cmd->error = -EINPROGRESS;
 288
 289         cmdr = cmd->opcode;
 290
 291         if (cmdr == MMC_STOP_TRANSMISSION)
 292                 cmdr |= SDMMC_CMD_STOP;
 293         else
 294                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 295
 296         if (cmd->flags & MMC_RSP_PRESENT) {
 297                 /* We expect a response, so set this bit */
 298                 cmdr |= SDMMC_CMD_RESP_EXP;
 299                 if (cmd->flags & MMC_RSP_136)
 300                         cmdr |= SDMMC_CMD_RESP_LONG;
 301         }
 302
 303         if (cmd->flags & MMC_RSP_CRC)
 304                 cmdr |= SDMMC_CMD_RESP_CRC;
 305
 306         data = cmd->data;
 307         if (data) {
 308                 cmdr |= SDMMC_CMD_DAT_EXP;
 309                 if (data->flags & MMC_DATA_STREAM)
 310                         cmdr |= SDMMC_CMD_STRM_MODE;
 311                 if (data->flags & MMC_DATA_WRITE)
 312                         cmdr |= SDMMC_CMD_DAT_WR;
 313         }
 314
 315         if (drv_data && drv_data->prepare_command)
 316                 drv_data->prepare_command(slot->host, &cmdr);
 317
 318         return cmdr;
 319 }
 320
 321 #if 0
 322 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 323 {
 324         struct mmc_command *stop;
 325         u32 cmdr;
 326
 327         if (!cmd->data)
 328                 return 0;
 329
 330         stop = &host->stop_abort;
 331         cmdr = cmd->opcode;
 332         memset(stop, 0, sizeof(struct mmc_command));
 333
 334         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 335             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 336             cmdr == MMC_WRITE_BLOCK ||
 337             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 338                 stop->opcode = MMC_STOP_TRANSMISSION;
 339                 stop->arg = 0;
 340                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 341         } else if (cmdr == SD_IO_RW_EXTENDED) {
 342                 stop->opcode = SD_IO_RW_DIRECT;
 343                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 344                              ((cmd->arg >> 28) & 0x7);
 345                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 346         } else {
 347                 return 0;
 348         }
 349
 350         cmdr = stop->opcode | SDMMC_CMD_STOP |
 351                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 352
 353         return cmdr;
 354 }
 355 #endif
 356 static void dw_mci_start_command(struct dw_mci *host,
 357                                  struct mmc_command *cmd, u32 cmd_flags)
 358 {
 359         struct dw_mci_slot *slot = host->slot[0];
 360         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 361
 362         host->pre_cmd = host->cmd;
 363         host->cmd = cmd;
 364         dev_vdbg(host->dev,
 365                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 366                 cmd->arg, cmd_flags);
 367
 368         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 369                 /*confirm non-low-power mode*/
 370                 mci_writel(host, CMDARG, 0);
 371                 dw_mci_disable_low_power(slot);
 372
 373                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 374                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 375
 376                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 377         }
 378
 379         mci_writel(host, CMDARG, cmd->arg);
 380         wmb();
 381
 382         /* fix the value to 1 in some Soc,for example RK3188. */
 383         if(host->mmc->hold_reg_flag)
 384                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 385
 386         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 387         wmb();
 388 }
 389
 390 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 391 {
 392         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 393 }
 394
 395 /* DMA interface functions */
 396 static void dw_mci_stop_dma(struct dw_mci *host)
 397 {
 398         if (host->using_dma) {
 399                 host->dma_ops->stop(host);
 400                 host->dma_ops->cleanup(host);
 401         }
 402
 403         /* Data transfer was stopped by the interrupt handler */
 404         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 405 }
 406
 407 static int dw_mci_get_dma_dir(struct mmc_data *data)
 408 {
 409         if (data->flags & MMC_DATA_WRITE)
 410                 return DMA_TO_DEVICE;
 411         else
 412                 return DMA_FROM_DEVICE;
 413 }
 414
 415 #ifdef CONFIG_MMC_DW_IDMAC
 416 static void dw_mci_dma_cleanup(struct dw_mci *host)
 417 {
 418         struct mmc_data *data = host->data;
 419
 420         if (data)
 421                 if (!data->host_cookie)
 422                         dma_unmap_sg(host->dev,
 423                                      data->sg,
 424                                      data->sg_len,
 425                                      dw_mci_get_dma_dir(data));
 426 }
 427
 428 static void dw_mci_idmac_reset(struct dw_mci *host)
 429 {
 430         u32 bmod = mci_readl(host, BMOD);
 431         /* Software reset of DMA */
 432         bmod |= SDMMC_IDMAC_SWRESET;
 433         mci_writel(host, BMOD, bmod);
 434 }
 435
 436 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 437 {
 438         u32 temp;
 439
 440         /* Disable and reset the IDMAC interface */
 441         temp = mci_readl(host, CTRL);
 442         temp &= ~SDMMC_CTRL_USE_IDMAC;
 443         temp |= SDMMC_CTRL_DMA_RESET;
 444         mci_writel(host, CTRL, temp);
 445
 446         /* Stop the IDMAC running */
 447         temp = mci_readl(host, BMOD);
 448         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 449         temp |= SDMMC_IDMAC_SWRESET;
 450         mci_writel(host, BMOD, temp);
 451 }
 452
 453 static void dw_mci_idmac_complete_dma(void *arg)
 454 {
 455         struct dw_mci *host = arg;
 456         struct mmc_data *data = host->data;
 457
 458         dev_vdbg(host->dev, "DMA complete\n");
 459
 460         /*
 461         MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 462                 host->mrq->cmd->opcode,host->mrq->cmd->arg,
 463                 data->blocks,data->blksz,mmc_hostname(host->mmc));
 464         */
 465
 466         host->dma_ops->cleanup(host);
 467
 468         /*
 469          * If the card was removed, data will be NULL. No point in trying to
 470          * send the stop command or waiting for NBUSY in this case.
 471          */
 472         if(data){
 473                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 474                 tasklet_schedule(&host->tasklet);
 475         }
 476 }
 477
 478 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 479                                     unsigned int sg_len)
 480 {
 481         int i;
 482         struct idmac_desc *desc = host->sg_cpu;
 483
 484         for (i = 0; i < sg_len; i++, desc++) {
 485                 unsigned int length = sg_dma_len(&data->sg[i]);
 486                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 487
 488                 /* Set the OWN bit and disable interrupts for this descriptor */
 489                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 490
 491                 /* Buffer length */
 492                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 493
 494                 /* Physical address to DMA to/from */
 495                 desc->des2 = mem_addr;
 496         }
 497
 498         /* Set first descriptor */
 499         desc = host->sg_cpu;
 500         desc->des0 |= IDMAC_DES0_FD;
 501
 502         /* Set last descriptor */
 503         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 504         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 505         desc->des0 |= IDMAC_DES0_LD;
 506
 507         wmb();
 508 }
 509
 510 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 511 {
 512         u32 temp;
 513
 514         dw_mci_translate_sglist(host, host->data, sg_len);
 515
 516         /* Select IDMAC interface */
 517         temp = mci_readl(host, CTRL);
 518         temp |= SDMMC_CTRL_USE_IDMAC;
 519         mci_writel(host, CTRL, temp);
 520
 521         wmb();
 522
 523         /* Enable the IDMAC */
 524         temp = mci_readl(host, BMOD);
 525         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 526         mci_writel(host, BMOD, temp);
 527
 528         /* Start it running */
 529         mci_writel(host, PLDMND, 1);
 530 }
 531
 532 static int dw_mci_idmac_init(struct dw_mci *host)
 533 {
 534         struct idmac_desc *p;
 535         int i;
 536
 537         /* Number of descriptors in the ring buffer */
 538         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 539
 540         /* Forward link the descriptor list */
 541         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 542                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 543
 544         /* Set the last descriptor as the end-of-ring descriptor */
 545         p->des3 = host->sg_dma;
 546         p->des0 = IDMAC_DES0_ER;
 547
 548         dw_mci_idmac_reset(host);
 549
 550         /* Mask out interrupts - get Tx & Rx complete only */
 551         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 552         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 553                    SDMMC_IDMAC_INT_TI);
 554
 555         /* Set the descriptor base address */
 556         mci_writel(host, DBADDR, host->sg_dma);
 557         return 0;
 558 }
 559
 560 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 561         .init = dw_mci_idmac_init,
 562         .start = dw_mci_idmac_start_dma,
 563         .stop = dw_mci_idmac_stop_dma,
 564         .complete = dw_mci_idmac_complete_dma,
 565         .cleanup = dw_mci_dma_cleanup,
 566 };
 567
 568
 569 static void dw_mci_edma_cleanup(struct dw_mci *host)
 570 {
 571         struct mmc_data *data = host->data;
 572
 573         if (data)
 574                 if (!data->host_cookie)
 575                         dma_unmap_sg(host->dev,
 576                                         data->sg, data->sg_len,
 577                                         dw_mci_get_dma_dir(data));
 578 }
 579
 580 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 581 {
 582         dmaengine_terminate_all(host->dms->ch);
 583 }
 584
 585 static void dw_mci_edmac_complete_dma(void *arg)
 586 {
 587         struct dw_mci *host = arg;
 588         struct mmc_data *data = host->data;
 589
 590         dev_vdbg(host->dev, "DMA complete\n");
 591
 592         if(data)
 593                 if(data->flags & MMC_DATA_READ)
 594                         /* Invalidate cache after read */
 595                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 596                                 data->sg_len, DMA_FROM_DEVICE);
 597
 598         host->dma_ops->cleanup(host);
 599
 600         /*
 601          * If the card was removed, data will be NULL. No point in trying to
 602          * send the stop command or waiting for NBUSY in this case.
 603          */
 604         if (data) {
 605                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 606                 tasklet_schedule(&host->tasklet);
 607         }
 608 }
 609
 610 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 611 {
 612         struct dma_slave_config slave_config;
 613         struct dma_async_tx_descriptor *desc = NULL;
 614         struct scatterlist *sgl = host->data->sg;
 615         u32 sg_elems = host->data->sg_len;
 616         int ret = 0;
 617
 618         /* Set external dma config: burst size, burst width*/
 619         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 620         slave_config.src_addr = slave_config.dst_addr;
 621         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 622         slave_config.src_addr_width = slave_config.dst_addr_width;
 623
 624         /* Match FIFO dma burst MSIZE with external dma config*/
 625         slave_config.dst_maxburst = ((host->fifoth_val) >> 28) && 0x7;
 626         slave_config.src_maxburst = slave_config.dst_maxburst;
 627
 628         if(host->data->flags & MMC_DATA_WRITE){
 629                 slave_config.direction = DMA_MEM_TO_DEV;
 630                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 631                 if(ret){
 632                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 633                         return;
 634                 }
 635
 636                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 637                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 638                 if(!desc){
 639                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 640                         return;
 641                 }
 642                 /* Set dw_mci_edmac_complete_dma as callback */
 643                 desc->callback = dw_mci_edmac_complete_dma;
 644                 desc->callback_param = (void *)host;
 645                 dmaengine_submit(desc);
 646
 647                 /* Flush cache before write */
 648                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 649                                         sg_elems, DMA_TO_DEVICE);
 650                 dma_async_issue_pending(host->dms->ch);
 651         }else{
 652                 /* MMC_DATA_READ*/
 653                 slave_config.direction = DMA_DEV_TO_MEM;
 654                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 655                 if(ret){
 656                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 657                         return;
 658                 }
 659                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 660                                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 661                 if(!desc){
 662                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 663                         return;
 664                 }
 665                 /* set dw_mci_edmac_complete_dma as callback */
 666                 desc->callback = dw_mci_edmac_complete_dma;
 667                 desc->callback_param = (void *)host;
 668                 dmaengine_submit(desc);
 669                 dma_async_issue_pending(host->dms->ch);
 670         }
 671 }
 672
 673 static int dw_mci_edmac_init(struct dw_mci *host)
 674 {
 675         /* Request external dma channel, SHOULD decide chn in dts */
 676         host->dms = NULL;
 677         host->dms = (struct dw_mci_dma_slave *)kmalloc
 678                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 679         if (NULL == host->dms) {
 680                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 681                 goto err_exit;
 682         }
 683
 684         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 685         if (!host->dms->ch) {
 686                 dev_err(host->dev, "Failed to get external DMA channel: channel id = %d\n",
 687                                 host->dms->ch->chan_id);
 688                 goto err_exit;
 689         }
 690
 691         return 0;
 692
 693 err_exit:
 694         if (NULL != host->dms) {
 695                 kfree(host->dms);
 696                 host->dms = NULL;
 697         }
 698         return -ENXIO;
 699
 700 }
 701
 702 static void dw_mci_edmac_exit(struct dw_mci *host)
 703 {
 704         if (NULL != host->dms) {
 705                 if (NULL != host->dms->ch) {
 706                         dma_release_channel(host->dms->ch);
 707                         host->dms->ch = NULL;
 708                 }
 709                 kfree(host->dms);
 710                 host->dms = NULL;
 711         }
 712 }
 713
 714 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 715         .init = dw_mci_edmac_init,
 716         .exit = dw_mci_edmac_exit,
 717         .start = dw_mci_edmac_start_dma,
 718         .stop = dw_mci_edmac_stop_dma,
 719         .complete = dw_mci_edmac_complete_dma,
 720         .cleanup = dw_mci_edma_cleanup,
 721 };
 722 #endif /* CONFIG_MMC_DW_IDMAC */
 723
 724 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 725                                    struct mmc_data *data,
 726                                    bool next)
 727 {
 728         struct scatterlist *sg;
 729         unsigned int i, sg_len;
 730
 731         if (!next && data->host_cookie)
 732                 return data->host_cookie;
 733
 734         /*
 735          * We don't do DMA on "complex" transfers, i.e. with
 736          * non-word-aligned buffers or lengths. Also, we don't bother
 737          * with all the DMA setup overhead for short transfers.
 738          */
 739         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 740                 return -EINVAL;
 741
 742         if (data->blksz & 3)
 743                 return -EINVAL;
 744
 745         for_each_sg(data->sg, sg, data->sg_len, i) {
 746                 if (sg->offset & 3 || sg->length & 3)
 747                         return -EINVAL;
 748         }
 749
 750         sg_len = dma_map_sg(host->dev,
 751                             data->sg,
 752                             data->sg_len,
 753                             dw_mci_get_dma_dir(data));
 754         if (sg_len == 0)
 755                 return -EINVAL;
 756
 757         if (next)
 758                 data->host_cookie = sg_len;
 759
 760         return sg_len;
 761 }
 762
 763 static void dw_mci_pre_req(struct mmc_host *mmc,
 764                            struct mmc_request *mrq,
 765                            bool is_first_req)
 766 {
 767         struct dw_mci_slot *slot = mmc_priv(mmc);
 768         struct mmc_data *data = mrq->data;
 769
 770         if (!slot->host->use_dma || !data)
 771                 return;
 772
 773         if (data->host_cookie) {
 774                 data->host_cookie = 0;
 775                 return;
 776         }
 777
 778         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 779                 data->host_cookie = 0;
 780 }
 781
 782 static void dw_mci_post_req(struct mmc_host *mmc,
 783                             struct mmc_request *mrq,
 784                             int err)
 785 {
 786         struct dw_mci_slot *slot = mmc_priv(mmc);
 787         struct mmc_data *data = mrq->data;
 788
 789         if (!slot->host->use_dma || !data)
 790                 return;
 791
 792         if (data->host_cookie)
 793                 dma_unmap_sg(slot->host->dev,
 794                              data->sg,
 795                              data->sg_len,
 796                              dw_mci_get_dma_dir(data));
 797         data->host_cookie = 0;
 798 }
 799
 800 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 801 {
 802 #ifdef CONFIG_MMC_DW_IDMAC
 803         unsigned int blksz = data->blksz;
 804         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 805         u32 fifo_width = 1 << host->data_shift;
 806         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 807         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 808         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 809
 810         tx_wmark = (host->fifo_depth) / 2;
 811         tx_wmark_invers = host->fifo_depth - tx_wmark;
 812
 813         /*
 814          * MSIZE is '1',
 815          * if blksz is not a multiple of the FIFO width
 816          */
 817         if (blksz % fifo_width) {
 818                 msize = 0;
 819                 rx_wmark = 1;
 820                 goto done;
 821         }
 822
 823         do {
 824                 if (!((blksz_depth % mszs[idx]) ||
 825                      (tx_wmark_invers % mszs[idx]))) {
 826                         msize = idx;
 827                         rx_wmark = mszs[idx] - 1;
 828                         break;
 829                 }
 830         } while (--idx > 0);
 831         /*
 832          * If idx is '0', it won't be tried
 833          * Thus, initial values are uesed
 834          */
 835 done:
 836         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 837         mci_writel(host, FIFOTH, fifoth_val);
 838 #endif
 839 }
 840
 841 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 842 {
 843         unsigned int blksz = data->blksz;
 844         u32 blksz_depth, fifo_depth;
 845         u16 thld_size;
 846
 847         WARN_ON(!(data->flags & MMC_DATA_READ));
 848
 849         if (host->timing != MMC_TIMING_MMC_HS200 &&
 850             host->timing != MMC_TIMING_UHS_SDR104)
 851                 goto disable;
 852
 853         blksz_depth = blksz / (1 << host->data_shift);
 854         fifo_depth = host->fifo_depth;
 855
 856         if (blksz_depth > fifo_depth)
 857                 goto disable;
 858
 859         /*
 860          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 861          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 862          * Currently just choose blksz.
 863          */
 864         thld_size = blksz;
 865         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 866         return;
 867
 868 disable:
 869         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 870 }
 871
 872 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 873 {
 874         int sg_len;
 875         unsigned long flags;
 876         u32 temp;
 877
 878         host->using_dma = 0;
 879
 880         /* If we don't have a channel, we can't do DMA */
 881         if (!host->use_dma)
 882                 return -ENODEV;
 883
 884         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 885         if (sg_len < 0) {
 886                 host->dma_ops->stop(host);
 887                 return sg_len;
 888         }
 889
 890         host->using_dma = 1;
 891
 892         dev_vdbg(host->dev,
 893                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 894                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 895                  sg_len);
 896
 897         /*
 898          * Decide the MSIZE and RX/TX Watermark.
 899          * If current block size is same with previous size,
 900          * no need to update fifoth.
 901          */
 902         if (host->prev_blksz != data->blksz)
 903                 dw_mci_adjust_fifoth(host, data);
 904
 905         /* Reset DMA FIFO*/
 906         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 907
 908         /* Enable the DMA interface */
 909         temp = mci_readl(host, CTRL);
 910         temp |= SDMMC_CTRL_DMA_ENABLE;
 911         mci_writel(host, CTRL, temp);
 912
 913         /* Disable RX/TX IRQs, let DMA handle it */
 914         spin_lock_irqsave(&host->slock, flags);
 915         temp = mci_readl(host, INTMASK);
 916         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 917         mci_writel(host, INTMASK, temp);
 918         spin_unlock_irqrestore(&host->slock, flags);
 919
 920         host->dma_ops->start(host, sg_len);
 921
 922         return 0;
 923 }
 924
 925 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 926 {
 927         u32 temp;
 928         unsigned long flag;
 929
 930         data->error = -EINPROGRESS;
 931
 932         WARN_ON(host->data);
 933         host->sg = NULL;
 934         host->data = data;
 935
 936         /* Reset FIFO*/
 937         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
 938
 939         if (data->flags & MMC_DATA_READ) {
 940                 host->dir_status = DW_MCI_RECV_STATUS;
 941                 dw_mci_ctrl_rd_thld(host, data);
 942         } else {
 943                 host->dir_status = DW_MCI_SEND_STATUS;
 944         }
 945
 946     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
 947          data->blocks, data->blksz, mmc_hostname(host->mmc));
 948
 949         if (dw_mci_submit_data_dma(host, data)) {
 950                 int flags = SG_MITER_ATOMIC;
 951                 if (host->data->flags & MMC_DATA_READ)
 952                         flags |= SG_MITER_TO_SG;
 953                 else
 954                         flags |= SG_MITER_FROM_SG;
 955
 956                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 957                 host->sg = data->sg;
 958                 host->part_buf_start = 0;
 959                 host->part_buf_count = 0;
 960
 961                 spin_lock_irqsave(&host->slock, flag);
 962                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 963                 temp = mci_readl(host, INTMASK);
 964                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 965                 mci_writel(host, INTMASK, temp);
 966                 spin_unlock_irqrestore(&host->slock, flag);
 967
 968                 temp = mci_readl(host, CTRL);
 969                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 970                 mci_writel(host, CTRL, temp);
 971
 972                 /*
 973                  * Use the initial fifoth_val for PIO mode.
 974                  * If next issued data may be transfered by DMA mode,
 975                  * prev_blksz should be invalidated.
 976                  */
 977                 mci_writel(host, FIFOTH, host->fifoth_val);
 978                 host->prev_blksz = 0;
 979         } else {
 980                 /*
 981                  * Keep the current block size.
 982                  * It will be used to decide whether to update
 983                  * fifoth register next time.
 984                  */
 985                 host->prev_blksz = data->blksz;
 986         }
 987 }
 988
 989 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 990 {
 991         struct dw_mci *host = slot->host;
 992         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
 993         unsigned int cmd_status = 0;
 994 #ifdef SDMMC_WAIT_FOR_UNBUSY
 995         bool ret = true;
 996         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
 997
 998     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 999         while (ret) {
1000                 ret =  time_before(jiffies, timeout);
1001                 cmd_status = mci_readl(host, STATUS);
1002                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1003                         break;
1004         } ;
1005         if(false == ret)
1006             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
1007                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
1008     }
1009 #endif
1010         mci_writel(host, CMDARG, arg);
1011         wmb();
1012         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1013         if(cmd & SDMMC_CMD_UPD_CLK)
1014                 timeout = jiffies + msecs_to_jiffies(50);
1015         else
1016                 timeout = jiffies + msecs_to_jiffies(500);
1017         while (time_before(jiffies, timeout)) {
1018                 cmd_status = mci_readl(host, CMD);
1019                 if (!(cmd_status & SDMMC_CMD_START))
1020                         return ;
1021         }
1022         dev_err(&slot->mmc->class_dev,
1023                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1024                 cmd, arg, cmd_status);
1025 }
1026
1027 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1028 {
1029         struct dw_mci *host = slot->host;
1030         unsigned int tempck,clock = slot->clock;
1031         u32 div;
1032         u32 clk_en_a;
1033         u32 sdio_int;
1034
1035         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
1036                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
1037
1038         if (!clock) {
1039                 mci_writel(host, CLKENA, 0);
1040                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1041                 if(host->svi_flags == 0)
1042                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1043                 #else
1044                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1045                 #endif
1046         } else if (clock != host->current_speed || force_clkinit) {
1047                 div = host->bus_hz / clock;
1048                 if (host->bus_hz % clock && host->bus_hz > clock)
1049                         /*
1050                          * move the + 1 after the divide to prevent
1051                          * over-clocking the card.
1052                          */
1053                         div += 1;
1054
1055                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1056
1057                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1058                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1059                         dev_info(&slot->mmc->class_dev,
1060                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1061                                  slot->id, host->bus_hz, clock,
1062                                  tempck, div);
1063
1064                         host->set_speed = tempck;
1065                         host->set_div = div;
1066                 }
1067
1068                 /* disable clock */
1069                 mci_writel(host, CLKENA, 0);
1070                 mci_writel(host, CLKSRC, 0);
1071
1072                 /* inform CIU */
1073                 mci_send_cmd(slot,
1074                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1075
1076                 if(clock <= 400*1000){
1077                         MMC_DBG_BOOT_FUNC(host->mmc,
1078                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1079                                 clock * 2, mmc_hostname(host->mmc));
1080                         /* clk_mmc will change parents to 24MHz xtal*/
1081                         clk_set_rate(host->clk_mmc, clock * 2);
1082
1083                         div = 0;
1084                         host->set_div = div;
1085                 }
1086                 else
1087                 {
1088                         MMC_DBG_BOOT_FUNC(host->mmc,
1089                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1090                                 mmc_hostname(host->mmc));
1091                         if(div > 1)
1092                         {
1093                                 MMC_DBG_ERR_FUNC(host->mmc,
1094                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1095                                         mmc_hostname(host->mmc));
1096                                  div = 1;
1097                                  host->set_div = div;
1098                                  host->bus_hz = host->set_speed * 2;
1099                                  MMC_DBG_BOOT_FUNC(host->mmc,
1100                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1101                                         div, host->bus_hz, mmc_hostname(host->mmc));
1102                         }
1103                         /* BUG may be here, come on,  Linux BSP engineer looks!
1104                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1105                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1106                            some oops happened like that:
1107                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1108                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1109                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1110                            mmc0: new high speed DDR MMC card at address 0001
1111                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1112                            ....
1113                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1114                            mmcblk0: retrying using single block read
1115                            mmcblk0: error -110 sending status command, retrying
1116
1117                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1118                          */
1119                         if ((div == 0) &&
1120                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1121                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1122                                 /*  Fixup DDR MMC */
1123                                 div = 1;
1124                                 host->set_div = div;
1125                                 host->bus_hz = host->set_speed * 2;
1126                                 MMC_DBG_BOOT_FUNC(host->mmc,
1127                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1128                                         div, host->bus_hz, mmc_hostname(host->mmc));
1129                         }
1130
1131                         if (host->verid < DW_MMC_240A)
1132                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1133                         else
1134                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1135
1136
1137
1138                 }
1139
1140                 /* set clock to desired speed */
1141                 mci_writel(host, CLKDIV, div);
1142
1143                 /* inform CIU */
1144                 mci_send_cmd(slot,
1145                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1146
1147                 /* enable clock; only low power if no SDIO */
1148                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1149
1150                 if (host->verid < DW_MMC_240A)
1151                     sdio_int = SDMMC_INT_SDIO(slot->id);
1152                 else
1153                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1154
1155                 if (!(mci_readl(host, INTMASK) & sdio_int))
1156                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1157                 mci_writel(host, CLKENA, clk_en_a);
1158
1159                 /* inform CIU */
1160                 mci_send_cmd(slot,
1161                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1162                 /* keep the clock with reflecting clock dividor */
1163                 slot->__clk_old = clock << div;
1164         }
1165
1166         host->current_speed = clock;
1167
1168     if(slot->ctype != slot->pre_ctype)
1169         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
1170             host->set_speed,
1171             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
1172             mmc_hostname(host->mmc));
1173     slot->pre_ctype = slot->ctype;
1174
1175         /* Set the current slot bus width */
1176         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1177 }
1178
1179 extern struct mmc_card *this_card;
1180 static void dw_mci_wait_unbusy(struct dw_mci *host)
1181 {
1182
1183         unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1184         unsigned long   time_loop;
1185         unsigned int    status;
1186         u32 se_flag = 0;
1187
1188         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1189
1190         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1191                 if (host->cmd && (host->cmd->opcode == MMC_ERASE)) {
1192                 /* Special care for (secure)erase timeout calculation */
1193                         if(this_card){
1194                                 if((host->cmd->arg & (0x1 << 31)) == 1) /* secure erase */
1195                                         se_flag = 0x1;
1196
1197                                 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1) ;
1198                                         se_flag ? (timeout = (this_card->ext_csd.hc_erase_timeout) *
1199                                                         300000 * (this_card->ext_csd.sec_erase_mult)) :
1200                                                         (timeout = (this_card->ext_csd.hc_erase_timeout) * 300000);
1201                         }
1202                 }
1203
1204                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1205                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1206         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1207                 timeout = SDMMC_DATA_TIMEOUT_SD;
1208         }
1209
1210         time_loop = jiffies + msecs_to_jiffies(timeout);
1211         do {
1212                 status = mci_readl(host, STATUS);
1213                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1214                         break;
1215         } while (time_before(jiffies, time_loop));
1216 }
1217
1218
1219
1220 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1221 /*
1222 *   result:
1223 *   0--status is busy.
1224 *   1--status is unbusy.
1225 */
1226 int dw_mci_card_busy(struct mmc_host *mmc)
1227 {
1228         struct dw_mci_slot *slot = mmc_priv(mmc);
1229         struct dw_mci *host = slot->host;
1230
1231         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1232                                 host->svi_flags, mmc_hostname(host->mmc));
1233
1234         /* svi toggle*/
1235         if(host->svi_flags == 0){
1236                 /*first svi*/
1237                 host->svi_flags = 1;
1238                 return host->svi_flags;
1239
1240         }else{
1241                 host->svi_flags = 0;
1242                 return host->svi_flags;
1243         }
1244
1245
1246 }
1247 #endif
1248 static void __dw_mci_start_request(struct dw_mci *host,
1249                                    struct dw_mci_slot *slot,
1250                                    struct mmc_command *cmd)
1251 {
1252         struct mmc_request *mrq;
1253         struct mmc_data *data;
1254         u32 cmdflags;
1255
1256         mrq = slot->mrq;
1257         if (host->pdata->select_slot)
1258                 host->pdata->select_slot(slot->id);
1259
1260         host->cur_slot = slot;
1261         host->mrq = mrq;
1262
1263         dw_mci_wait_unbusy(host);
1264
1265         host->pending_events = 0;
1266         host->completed_events = 0;
1267         host->data_status = 0;
1268
1269         data = cmd->data;
1270         if (data) {
1271                 dw_mci_set_timeout(host);
1272                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1273                 mci_writel(host, BLKSIZ, data->blksz);
1274         }
1275
1276         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1277
1278         /* this is the first command, send the initialization clock */
1279         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1280                 cmdflags |= SDMMC_CMD_INIT;
1281
1282         if (data) {
1283                 dw_mci_submit_data(host, data);
1284                 wmb();
1285         }
1286
1287         dw_mci_start_command(host, cmd, cmdflags);
1288
1289         if (mrq->stop)
1290                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1291 }
1292
1293 static void dw_mci_start_request(struct dw_mci *host,
1294                                  struct dw_mci_slot *slot)
1295 {
1296         struct mmc_request *mrq = slot->mrq;
1297         struct mmc_command *cmd;
1298
1299         MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1300                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1301
1302         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1303         __dw_mci_start_request(host, slot, cmd);
1304 }
1305
1306 /* must be called with host->lock held */
1307 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1308                                  struct mmc_request *mrq)
1309 {
1310         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1311                  host->state);
1312
1313         slot->mrq = mrq;
1314
1315         if (host->state == STATE_IDLE) {
1316                 host->state = STATE_SENDING_CMD;
1317                 dw_mci_start_request(host, slot);
1318         } else {
1319                 list_add_tail(&slot->queue_node, &host->queue);
1320         }
1321 }
1322
1323 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1324 {
1325         struct dw_mci_slot *slot = mmc_priv(mmc);
1326         struct dw_mci *host = slot->host;
1327
1328         WARN_ON(slot->mrq);
1329
1330         /*
1331          * The check for card presence and queueing of the request must be
1332          * atomic, otherwise the card could be removed in between and the
1333          * request wouldn't fail until another card was inserted.
1334          */
1335         spin_lock_bh(&host->lock);
1336
1337         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1338                 spin_unlock_bh(&host->lock);
1339                 mrq->cmd->error = -ENOMEDIUM;
1340                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1341                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1342
1343                 mmc_request_done(mmc, mrq);
1344                 return;
1345         }
1346
1347         MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1348                                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1349
1350         dw_mci_queue_request(host, slot, mrq);
1351
1352         spin_unlock_bh(&host->lock);
1353 }
1354
1355 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1356 {
1357         struct dw_mci_slot *slot = mmc_priv(mmc);
1358         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1359         struct dw_mci *host = slot->host;
1360         #endif
1361         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1362         u32 regs;
1363
1364         #ifdef SDMMC_WAIT_FOR_UNBUSY
1365         unsigned long   time_loop;
1366         bool ret = true;
1367
1368         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1369         if(host->svi_flags == 1)
1370                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1371         else
1372                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1373         #else
1374                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1375         #endif
1376
1377         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1378                 printk("%d..%s:  no card. [%s]\n", \
1379                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1380                 goto EXIT_POWER;
1381         }
1382
1383         while (ret) {
1384                 ret = time_before(jiffies, time_loop);
1385                 regs = mci_readl(slot->host, STATUS);
1386                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1387                         break;
1388         };
1389
1390         if(false == ret)
1391         {
1392                 printk("slot->flags = %lu ", slot->flags);
1393                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1394                 if(host->svi_flags != 1)
1395                 #endif
1396                         dump_stack();
1397                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1398                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1399         }
1400         #endif
1401
1402         switch (ios->bus_width) {
1403         case MMC_BUS_WIDTH_4:
1404                 slot->ctype = SDMMC_CTYPE_4BIT;
1405                 break;
1406         case MMC_BUS_WIDTH_8:
1407                 slot->ctype = SDMMC_CTYPE_8BIT;
1408                 break;
1409         default:
1410                 /* set default 1 bit mode */
1411                 slot->ctype = SDMMC_CTYPE_1BIT;
1412                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1413         }
1414
1415         regs = mci_readl(slot->host, UHS_REG);
1416
1417         /* DDR mode set */
1418         if (ios->timing == MMC_TIMING_UHS_DDR50)
1419                 regs |= ((0x1 << slot->id) << 16);
1420         else
1421                 regs &= ~((0x1 << slot->id) << 16);
1422
1423         mci_writel(slot->host, UHS_REG, regs);
1424         slot->host->timing = ios->timing;
1425
1426         /*
1427          * Use mirror of ios->clock to prevent race with mmc
1428          * core ios update when finding the minimum.
1429          */
1430         slot->clock = ios->clock;
1431
1432         if (drv_data && drv_data->set_ios)
1433                 drv_data->set_ios(slot->host, ios);
1434
1435         /* Slot specific timing and width adjustment */
1436         dw_mci_setup_bus(slot, false);
1437                 //return -EAGAIN;
1438
1439 EXIT_POWER:
1440         switch (ios->power_mode) {
1441                 case MMC_POWER_UP:
1442                         set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1443                         /* Power up slot */
1444                         if (slot->host->pdata->setpower)
1445                                 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1446                         regs = mci_readl(slot->host, PWREN);
1447                         regs |= (1 << slot->id);
1448                         mci_writel(slot->host, PWREN, regs);
1449                         break;
1450                 case MMC_POWER_OFF:
1451                         /* Power down slot */
1452                         if(slot->host->pdata->setpower)
1453                                 slot->host->pdata->setpower(slot->id, 0);
1454                         regs = mci_readl(slot->host, PWREN);
1455                         regs &= ~(1 << slot->id);
1456                         mci_writel(slot->host, PWREN, regs);
1457                         break;
1458                 default:
1459                         break;
1460         }
1461 }
1462
1463 static int dw_mci_get_ro(struct mmc_host *mmc)
1464 {
1465         int read_only;
1466         struct dw_mci_slot *slot = mmc_priv(mmc);
1467         struct dw_mci_board *brd = slot->host->pdata;
1468
1469         /* Use platform get_ro function, else try on board write protect */
1470         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1471                 read_only = 0;
1472         else if(brd->get_ro)
1473                 read_only = brd->get_ro(slot->id);
1474         else if(gpio_is_valid(slot->wp_gpio))
1475                 read_only = gpio_get_value(slot->wp_gpio);
1476         else
1477                 read_only =
1478                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1479
1480         dev_dbg(&mmc->class_dev, "card is %s\n",
1481                 read_only ? "read-only" : "read-write");
1482
1483         return read_only;
1484 }
1485
1486 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1487 {
1488         struct dw_mci_slot *slot = mmc_priv(mmc);
1489         struct dw_mci *host = slot->host;
1490         /*struct dw_mci_board *brd = slot->host->pdata;*/
1491
1492         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1493                 return 0;
1494
1495         spin_lock_bh(&host->lock);
1496
1497         if(val)
1498                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1499         else
1500                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1501
1502         spin_unlock_bh(&host->lock);
1503
1504         if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1505                 if(__clk_is_enabled(host->hclk_mmc) == false)
1506                         clk_prepare_enable(host->hclk_mmc);
1507                 if(__clk_is_enabled(host->clk_mmc) == false)
1508                         clk_prepare_enable(host->clk_mmc);
1509         }else{
1510                 if(__clk_is_enabled(host->clk_mmc) == true)
1511                         clk_disable_unprepare(slot->host->clk_mmc);
1512                 if(__clk_is_enabled(host->hclk_mmc) == true)
1513                         clk_disable_unprepare(slot->host->hclk_mmc);
1514         }
1515
1516         mmc_detect_change(slot->mmc, 20);
1517         return 0;
1518 }
1519
1520
1521
1522 static int dw_mci_get_cd(struct mmc_host *mmc)
1523 {
1524         int present;
1525         struct dw_mci_slot *slot = mmc_priv(mmc);
1526         struct dw_mci_board *brd = slot->host->pdata;
1527         struct dw_mci *host = slot->host;
1528         int gpio_cd = mmc_gpio_get_cd(mmc);
1529         int gpio_val;
1530
1531         if (cpu_is_rk312x() &&
1532                 soc_is_rk3126() &&
1533                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1534                 gpio_cd = slot->cd_gpio;
1535                 if (gpio_is_valid(gpio_cd)) {
1536                         gpio_val = gpio_get_value_cansleep(gpio_cd);
1537                         msleep(10);
1538                         if (gpio_val == gpio_get_value_cansleep(gpio_cd)) {
1539                                 gpio_cd = gpio_get_value_cansleep(gpio_cd) == 0 ? 1 : 0;
1540                                 if (gpio_cd == 0) {
1541                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1542                                         grf_writel((0x1 << 24) | (1 << 8), RK312X_GRF_SOC_CON0);
1543                                         dw_mci_ctrl_all_reset(host);
1544                                 } else {
1545                                         /* Really card detected: SHOULD disable force_jtag */
1546                                         grf_writel((0x1 << 24) | (0 << 8), RK312X_GRF_SOC_CON0);
1547                                 }
1548                         } else {
1549                                 /* Jitter */
1550                                 return slot->last_detect_state;
1551                         }
1552                 } else {
1553                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1554                 }
1555         }
1556
1557         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1558                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1559
1560         /* Use platform get_cd function, else try onboard card detect */
1561         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1562                 present = 1;
1563         else if (brd->get_cd)
1564                 present = !brd->get_cd(slot->id);
1565         else if (!IS_ERR_VALUE(gpio_cd))
1566                 present = gpio_cd;
1567         else
1568                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1569                         == 0 ? 1 : 0;
1570
1571         spin_lock_bh(&host->lock);
1572         if (present) {
1573                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1574                 dev_dbg(&mmc->class_dev, "card is present\n");
1575         } else {
1576                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1577                 dev_dbg(&mmc->class_dev, "card is not present\n");
1578         }
1579         spin_unlock_bh(&host->lock);
1580
1581         return present;
1582 }
1583
1584
1585 /*
1586  * Dts Should caps emmc controller with poll-hw-reset
1587  */
1588 static void dw_mci_hw_reset(struct mmc_host *mmc)
1589 {
1590         struct dw_mci_slot *slot = mmc_priv(mmc);
1591         struct dw_mci *host = slot->host;
1592         u32 regs;
1593
1594         #if 0
1595         u32 cmd_flags;
1596         unsigned long timeout;
1597         bool ret = true;
1598
1599         /* (1) CMD12 to end any transfer in process */
1600         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1601                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1602
1603         if(host->mmc->hold_reg_flag)
1604                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1605         mci_writel(host, CMDARG, 0);
1606         wmb();
1607         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1608         wmb();
1609         timeout = jiffies + msecs_to_jiffies(500);
1610         while(ret){
1611                 ret = time_before(jiffies, timeout);
1612                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1613                         break;
1614         }
1615
1616         if(false == ret)
1617                 MMC_DBG_ERR_FUNC(host->mmc,
1618                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1619                         __func__, mmc_hostname(host->mmc));
1620
1621         /* (2) wait DTO, even if no response is sent back by card */
1622         ret = true;
1623         timeout = jiffies + msecs_to_jiffies(5);
1624         while(ret){
1625                 ret = time_before(jiffies, timeout);
1626                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1627                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1628                         break;
1629                 }
1630         }
1631         #endif
1632
1633         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1634
1635         /* Software reset - BMOD[0] for IDMA only */
1636         regs = mci_readl(host, BMOD);
1637         regs |= SDMMC_IDMAC_SWRESET;
1638         mci_writel(host, BMOD, regs);
1639         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1640         regs = mci_readl(host, BMOD);
1641         if(regs & SDMMC_IDMAC_SWRESET)
1642                 MMC_DBG_WARN_FUNC(host->mmc,
1643                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1644                         __func__, mmc_hostname(host->mmc));
1645
1646         /* DMA reset - CTRL[2] */
1647         regs = mci_readl(host, CTRL);
1648         regs |= SDMMC_CTRL_DMA_RESET;
1649         mci_writel(host, CTRL, regs);
1650         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1651         regs = mci_readl(host, CTRL);
1652         if(regs & SDMMC_CTRL_DMA_RESET)
1653                 MMC_DBG_WARN_FUNC(host->mmc,
1654                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1655                         __func__, mmc_hostname(host->mmc));
1656
1657         /* FIFO reset - CTRL[1] */
1658         regs = mci_readl(host, CTRL);
1659         regs |= SDMMC_CTRL_FIFO_RESET;
1660         mci_writel(host, CTRL, regs);
1661         mdelay(1); /* no timing limited, 1ms is random value */
1662         regs = mci_readl(host, CTRL);
1663         if(regs & SDMMC_CTRL_FIFO_RESET)
1664                 MMC_DBG_WARN_FUNC(host->mmc,
1665                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1666                         __func__, mmc_hostname(host->mmc));
1667
1668         /* (4) CARD_RESET
1669         According to eMMC spec
1670         tRstW >= 1us ;   RST_n pulse width
1671         tRSCA >= 200us ; RST_n to Command time
1672         tRSTH >= 1us ;   RST_n high period
1673         */
1674         mci_writel(slot->host, PWREN, 0x0);
1675         mci_writel(slot->host, RST_N, 0x0);
1676         dsb();
1677         udelay(10); /* 10us for bad quality eMMc. */
1678
1679         mci_writel(slot->host, PWREN, 0x1);
1680         mci_writel(slot->host, RST_N, 0x1);
1681         dsb();
1682         usleep_range(500, 1000); /* at least 500(> 200us) */
1683 }
1684
1685 /*
1686  * Disable lower power mode.
1687  *
1688  * Low power mode will stop the card clock when idle.  According to the
1689  * description of the CLKENA register we should disable low power mode
1690  * for SDIO cards if we need SDIO interrupts to work.
1691  *
1692  * This function is fast if low power mode is already disabled.
1693  */
1694 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1695 {
1696         struct dw_mci *host = slot->host;
1697         u32 clk_en_a;
1698         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1699
1700         clk_en_a = mci_readl(host, CLKENA);
1701
1702         if (clk_en_a & clken_low_pwr) {
1703                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1704                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1705                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1706         }
1707 }
1708
1709 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1710 {
1711         struct dw_mci_slot *slot = mmc_priv(mmc);
1712         struct dw_mci *host = slot->host;
1713         unsigned long flags;
1714         u32 int_mask;
1715         u32 sdio_int;
1716
1717         spin_lock_irqsave(&host->slock, flags);
1718
1719         /* Enable/disable Slot Specific SDIO interrupt */
1720         int_mask = mci_readl(host, INTMASK);
1721
1722         if (host->verid < DW_MMC_240A)
1723                 sdio_int = SDMMC_INT_SDIO(slot->id);
1724         else
1725                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1726
1727         if (enb) {
1728                 /*
1729                  * Turn off low power mode if it was enabled.  This is a bit of
1730                  * a heavy operation and we disable / enable IRQs a lot, so
1731                  * we'll leave low power mode disabled and it will get
1732                  * re-enabled again in dw_mci_setup_bus().
1733                  */
1734                 dw_mci_disable_low_power(slot);
1735
1736                 mci_writel(host, INTMASK,
1737                            (int_mask | sdio_int));
1738         } else {
1739                 mci_writel(host, INTMASK,
1740                            (int_mask & ~sdio_int));
1741         }
1742
1743         spin_unlock_irqrestore(&host->slock, flags);
1744 }
1745
1746 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1747 enum{
1748         IO_DOMAIN_12 = 1200,
1749         IO_DOMAIN_18 = 1800,
1750         IO_DOMAIN_33 = 3300,
1751 };
1752 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1753 {
1754         switch(voltage){
1755                 case IO_DOMAIN_33:
1756                         voltage = 0;
1757                         break;
1758                 case IO_DOMAIN_18:
1759                         voltage = 1;
1760                         break;
1761                 case IO_DOMAIN_12:
1762                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Not support io domain voltage [%s]\n",
1763                                                         __FUNCTION__, mmc_hostname(host->mmc));
1764                         break;
1765                 default:
1766                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Err io domain voltage [%s]\n",
1767                                                         __FUNCTION__, mmc_hostname(host->mmc));
1768                         break;
1769         }
1770
1771         if(cpu_is_rk3288()){
1772                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1773                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1774                 else
1775                         return ;
1776         }else{
1777                 MMC_DBG_ERR_FUNC(host->mmc,"%s : unknown chip [%s]\n",
1778                                         __FUNCTION__, mmc_hostname(host->mmc));
1779         }
1780 }
1781
1782 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1783                                                 struct mmc_ios *ios)
1784 {
1785         int ret;
1786         unsigned int value,uhs_reg;
1787
1788         /*
1789          * Signal Voltage Switching is only applicable for Host Controllers
1790          * v3.00 and above.
1791          */
1792         if (host->verid < DW_MMC_240A)
1793                 return 0;
1794
1795         uhs_reg = mci_readl(host, UHS_REG);
1796         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1797                 __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1798
1799         switch (ios->signal_voltage) {
1800         case MMC_SIGNAL_VOLTAGE_330:
1801                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1802                 if (host->vmmc) {
1803                         ret = io_domain_regulator_set_voltage(host->vmmc, 3300000, 3300000);
1804                         /* regulator_put(host->vmmc); //to be done in remove function. */
1805
1806                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1807                             __func__, regulator_get_voltage(host->vmmc), ret);
1808                         if (ret) {
1809                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 3.3V signalling voltage "
1810                                                 " failed\n", mmc_hostname(host->mmc));
1811                                 return -EIO;
1812                         }
1813                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1814                 }
1815                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__,
1816                                         __FUNCTION__, mmc_hostname(host->mmc));
1817
1818                 /* set High-power mode */
1819                 value = mci_readl(host, CLKENA);
1820                 value &= ~SDMMC_CLKEN_LOW_PWR;
1821                 mci_writel(host,CLKENA , value);
1822                 /* SDMMC_UHS_REG */
1823                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1824                 mci_writel(host,UHS_REG , uhs_reg);
1825
1826                 /* Wait for 5ms */
1827                 usleep_range(5000, 5500);
1828
1829                 /* 3.3V regulator output should be stable within 5 ms */
1830                 uhs_reg = mci_readl(host, UHS_REG);
1831                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1832                         return 0;
1833
1834                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 3.3V regulator output did not became stable\n",
1835                                 mmc_hostname(host->mmc));
1836
1837                 return -EAGAIN;
1838         case MMC_SIGNAL_VOLTAGE_180:
1839                 if (host->vmmc) {
1840                         ret = io_domain_regulator_set_voltage(host->vmmc,1800000, 1800000);
1841                         /* regulator_put(host->vmmc);//to be done in remove function. */
1842
1843                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1844                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1845                         if (ret) {
1846                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.8V signalling voltage "
1847                                                 " failed\n", mmc_hostname(host->mmc));
1848                                 return -EIO;
1849                         }
1850                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1851                 }
1852
1853                 /*
1854                  * Enable 1.8V Signal Enable in the Host Control2
1855                  * register
1856                  */
1857                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1858
1859                 /* Wait for 5ms */
1860                 usleep_range(5000, 5500);
1861                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__,
1862                                         __FUNCTION__,mmc_hostname(host->mmc));
1863
1864                 /* 1.8V regulator output should be stable within 5 ms */
1865                 uhs_reg = mci_readl(host, UHS_REG);
1866                 if(uhs_reg & SDMMC_UHS_VOLT_REG_18)
1867                         return 0;
1868
1869                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 1.8V regulator output did not became stable\n",
1870                                 mmc_hostname(host->mmc));
1871
1872                 return -EAGAIN;
1873         case MMC_SIGNAL_VOLTAGE_120:
1874                 if (host->vmmc) {
1875                         ret = io_domain_regulator_set_voltage(host->vmmc, 1200000, 1200000);
1876                         if (ret) {
1877                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.2V signalling voltage "
1878                                                 " failed\n", mmc_hostname(host->mmc));
1879                                 return -EIO;
1880                         }
1881                 }
1882                 return 0;
1883         default:
1884                 /* No signal voltage switch required */
1885                 return 0;
1886         }
1887 }
1888
1889
1890 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
1891         struct mmc_ios *ios)
1892 {
1893         struct dw_mci_slot *slot = mmc_priv(mmc);
1894         struct dw_mci *host = slot->host;
1895         int err;
1896
1897         if (host->verid < DW_MMC_240A)
1898                 return 0;
1899
1900         err = dw_mci_do_start_signal_voltage_switch(host, ios);
1901         return err;
1902 }
1903
1904 #endif
1905
1906 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1907 {
1908         struct dw_mci_slot *slot = mmc_priv(mmc);
1909         struct dw_mci *host = slot->host;
1910         const struct dw_mci_drv_data *drv_data = host->drv_data;
1911         struct dw_mci_tuning_data tuning_data;
1912         int err = -ENOSYS;
1913
1914         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
1915         if(cpu_is_rk3036() || cpu_is_rk312x())
1916                 return err;
1917
1918         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1919                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1920                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1921                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1922                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1923                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1924                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1925                 } else {
1926                         return -EINVAL;
1927                 }
1928         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1929                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1930                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1931         } else {
1932                 dev_err(host->dev,
1933                         "Undefined command(%d) for tuning\n", opcode);
1934                 return -EINVAL;
1935         }
1936
1937
1938         /* Recommend sample phase and delayline
1939            Fixme: Mix-use these three controllers will cause
1940            con_id mismatch.
1941          */
1942         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
1943             tuning_data.con_id = 3;
1944         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1945             tuning_data.con_id = 1;
1946         else
1947             tuning_data.con_id = 0;
1948
1949         /* 0: driver, from host->devices
1950            1: sample, from devices->host
1951          */
1952         tuning_data.tuning_type = 1;
1953
1954         if (drv_data && drv_data->execute_tuning)
1955                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1956
1957         return err;
1958 }
1959
1960 static const struct mmc_host_ops dw_mci_ops = {
1961         .request                = dw_mci_request,
1962         .pre_req                = dw_mci_pre_req,
1963         .post_req               = dw_mci_post_req,
1964         .set_ios                = dw_mci_set_ios,
1965         .get_ro                 = dw_mci_get_ro,
1966         .get_cd                 = dw_mci_get_cd,
1967         .set_sdio_status    = dw_mci_set_sdio_status,
1968         .hw_reset       = dw_mci_hw_reset,
1969         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1970         .execute_tuning         = dw_mci_execute_tuning,
1971         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1972         .start_signal_voltage_switch    = dw_mci_start_signal_voltage_switch,
1973         .card_busy  = dw_mci_card_busy,
1974         #endif
1975 };
1976
1977 #if 0
1978 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
1979 {
1980         unsigned long flags;
1981
1982     if(!host)
1983         return;
1984
1985         local_irq_save(flags);
1986         if(host->irq_state != irqflag)
1987         {
1988             host->irq_state = irqflag;
1989             if(irqflag)
1990             {
1991                 enable_irq(host->irq);
1992             }
1993             else
1994             {
1995                 disable_irq(host->irq);
1996             }
1997         }
1998         local_irq_restore(flags);
1999 }
2000 #endif
2001
2002 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2003         __releases(&host->lock)
2004         __acquires(&host->lock)
2005 {
2006         if(DW_MCI_SEND_STATUS == host->dir_status){
2007             #if 0
2008             if( MMC_BUS_TEST_W != host->cmd->opcode){
2009                 if(host->data_status & SDMMC_INT_DCRC)
2010                     host->data->error = -EILSEQ;
2011                 else if(host->data_status & SDMMC_INT_EBE)
2012                     host->data->error = -ETIMEDOUT;
2013             } else {
2014                 dw_mci_wait_unbusy(host);
2015             }
2016             #else
2017             dw_mci_wait_unbusy(host);
2018             #endif
2019         }
2020 }
2021
2022 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2023         __releases(&host->lock)
2024         __acquires(&host->lock)
2025 {
2026         struct dw_mci_slot *slot;
2027         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2028
2029         WARN_ON(host->cmd || host->data);
2030
2031         del_timer_sync(&host->dto_timer);
2032         dw_mci_deal_data_end(host, mrq);
2033
2034         if(mrq->cmd)
2035                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
2036                         mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
2037         if(mrq->data)
2038                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
2039                         mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
2040
2041         host->cur_slot->mrq = NULL;
2042         host->mrq = NULL;
2043         if (!list_empty(&host->queue)) {
2044                 slot = list_entry(host->queue.next,
2045                                   struct dw_mci_slot, queue_node);
2046                 list_del(&slot->queue_node);
2047                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2048                          mmc_hostname(slot->mmc));
2049                 host->state = STATE_SENDING_CMD;
2050                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
2051                 dw_mci_start_request(host, slot);
2052         } else {
2053                 dev_vdbg(host->dev, "list empty\n");
2054                 host->state = STATE_IDLE;
2055         }
2056
2057         spin_unlock(&host->lock);
2058         mmc_request_done(prev_mmc, mrq);
2059         spin_lock(&host->lock);
2060 }
2061
2062 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2063 {
2064         u32 status = host->cmd_status;
2065
2066         host->cmd_status = 0;
2067
2068         /* Read the response from the card (up to 16 bytes) */
2069         if (cmd->flags & MMC_RSP_PRESENT) {
2070                 if (cmd->flags & MMC_RSP_136) {
2071                         cmd->resp[3] = mci_readl(host, RESP0);
2072                         cmd->resp[2] = mci_readl(host, RESP1);
2073                         cmd->resp[1] = mci_readl(host, RESP2);
2074                         cmd->resp[0] = mci_readl(host, RESP3);
2075
2076             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
2077                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
2078                 } else {
2079                         cmd->resp[0] = mci_readl(host, RESP0);
2080                         cmd->resp[1] = 0;
2081                         cmd->resp[2] = 0;
2082                         cmd->resp[3] = 0;
2083             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
2084                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2085                 }
2086         }
2087
2088         if (status & SDMMC_INT_RTO)
2089         {
2090             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2091                 host->cmd_rto += 1;
2092
2093                 cmd->error = -ETIMEDOUT;
2094                 del_timer_sync(&host->dto_timer);
2095         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2096                 del_timer_sync(&host->dto_timer);
2097                 cmd->error = -EILSEQ;
2098         }else if (status & SDMMC_INT_RESP_ERR){
2099                 del_timer_sync(&host->dto_timer);
2100                 cmd->error = -EIO;
2101         }else{
2102                 cmd->error = 0;
2103         }
2104         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",
2105                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2106
2107         if (cmd->error) {
2108                 del_timer_sync(&host->dto_timer);
2109             if(MMC_SEND_STATUS != cmd->opcode)
2110                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2111                         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
2112                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2113                         host->cmd_rto = 0;
2114                 }
2115
2116                 /* newer ip versions need a delay between retries */
2117                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2118                         mdelay(20);
2119         }
2120
2121 }
2122
2123 static void dw_mci_tasklet_func(unsigned long priv)
2124 {
2125         struct dw_mci *host = (struct dw_mci *)priv;
2126         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2127         struct mmc_data *data;
2128         struct mmc_command *cmd;
2129         enum dw_mci_state state;
2130         enum dw_mci_state prev_state;
2131         u32 status, cmd_flags;
2132         unsigned long timeout = 0;
2133         bool ret = true;
2134
2135         spin_lock(&host->lock);
2136
2137         state = host->state;
2138         data = host->data;
2139
2140         do {
2141                 prev_state = state;
2142
2143                 switch (state) {
2144                 case STATE_IDLE:
2145                         break;
2146
2147                 case STATE_SENDING_CMD:
2148                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2149                                                 &host->pending_events))
2150                                 break;
2151
2152                         cmd = host->cmd;
2153                         host->cmd = NULL;
2154                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2155                         dw_mci_command_complete(host, cmd);
2156                         if (cmd == host->mrq->sbc && !cmd->error) {
2157                                 prev_state = state = STATE_SENDING_CMD;
2158                                 __dw_mci_start_request(host, host->cur_slot,
2159                                                        host->mrq->cmd);
2160                                 goto unlock;
2161                         }
2162
2163                         if (cmd->data && cmd->error) {
2164                                 del_timer_sync(&host->dto_timer); /* delete the timer for INT_DTO */
2165                                 dw_mci_stop_dma(host);
2166                                 #if 1
2167                                 if (data->stop) {
2168                                         send_stop_cmd(host, data);
2169                                         state = STATE_SENDING_STOP;
2170                                         break;
2171                                 }else{
2172                                         host->data = NULL;
2173                                 }
2174                                 #else
2175                                 send_stop_abort(host, data);
2176                                 state = STATE_SENDING_STOP;
2177                                 break;
2178                                 #endif
2179                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2180                         }
2181
2182                         if (!host->mrq->data || cmd->error) {
2183                                 dw_mci_request_end(host, host->mrq);
2184                                 goto unlock;
2185                         }
2186
2187                         prev_state = state = STATE_SENDING_DATA;
2188                         /* fall through */
2189
2190                 case STATE_SENDING_DATA:
2191                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
2192                                 dw_mci_stop_dma(host);
2193                                 #if 1
2194                                 if (data->stop){
2195                                         send_stop_cmd(host, data);
2196                                 }else{
2197                                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
2198                                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
2199                                                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
2200
2201                                         mci_writel(host, CMDARG, 0);
2202                                         wmb();
2203                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
2204                                                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2205
2206                                         if(host->mmc->hold_reg_flag)
2207                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2208
2209                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2210                                         wmb();
2211                                         timeout = jiffies + msecs_to_jiffies(500);
2212
2213                                         while(ret){
2214                                                 ret = time_before(jiffies, timeout);
2215                                                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2216                                                         break;
2217                                         }
2218                                         if(false == ret)
2219                                                 MMC_DBG_ERR_FUNC(host->mmc,
2220                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2221                                                         __func__, mmc_hostname(host->mmc));
2222                                 }
2223                                 #else
2224                                 send_stop_abort(host, data);
2225                                 #endif
2226                                 state = STATE_DATA_ERROR;
2227                                 break;
2228                         }
2229
2230                         MMC_DBG_CMD_FUNC(host->mmc,
2231                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
2232                         prev_state,state, mmc_hostname(host->mmc));
2233
2234                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2235                                                 &host->pending_events))
2236                                 break;
2237                         MMC_DBG_INFO_FUNC(host->mmc,
2238                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
2239                                           prev_state,state,mmc_hostname(host->mmc));
2240
2241                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2242                         prev_state = state = STATE_DATA_BUSY;
2243                         /* fall through */
2244
2245                 case STATE_DATA_BUSY:
2246                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2247                                                 &host->pending_events))
2248                                 break;
2249
2250                         dw_mci_deal_data_end(host, host->mrq);
2251                         del_timer_sync(&host->dto_timer); //delete the timer for INT_DTO
2252                         MMC_DBG_INFO_FUNC(host->mmc,
2253                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
2254                                           prev_state,state,mmc_hostname(host->mmc));
2255
2256                         host->data = NULL;
2257                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2258                         status = host->data_status;
2259
2260                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2261                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2262                                 MMC_DBG_ERR_FUNC(host->mmc,
2263                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
2264                             prev_state,state, status, mmc_hostname(host->mmc));
2265
2266                         if (status & SDMMC_INT_DRTO) {
2267                                         data->error = -ETIMEDOUT;
2268                                 } else if (status & SDMMC_INT_DCRC) {
2269                                         data->error = -EILSEQ;
2270                                 } else if (status & SDMMC_INT_EBE &&
2271                                 host->dir_status == DW_MCI_SEND_STATUS){
2272                                         /*
2273                                          * No data CRC status was returned.
2274                                          * The number of bytes transferred will
2275                                          * be exaggerated in PIO mode.
2276                                          */
2277                                         data->bytes_xfered = 0;
2278                                         data->error = -ETIMEDOUT;
2279                                 } else {
2280                                         dev_err(host->dev,
2281                                                 "data FIFO error "
2282                                                 "(status=%08x)\n",
2283                                                 status);
2284                                         data->error = -EIO;
2285                                 }
2286                                 /*
2287                                  * After an error, there may be data lingering
2288                                  * in the FIFO, so reset it - doing so
2289                                  * generates a block interrupt, hence setting
2290                                  * the scatter-gather pointer to NULL.
2291                                  */
2292                                 dw_mci_fifo_reset(host);
2293                         } else {
2294                                 data->bytes_xfered = data->blocks * data->blksz;
2295                                 data->error = 0;
2296                         }
2297
2298                         if (!data->stop) {
2299                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2300                                       prev_state,state,mmc_hostname(host->mmc));
2301                                 dw_mci_request_end(host, host->mrq);
2302                                 goto unlock;
2303                         }
2304                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2305                                                 prev_state,state,mmc_hostname(host->mmc));
2306
2307                         if (host->mrq->sbc && !data->error) {
2308                                 data->stop->error = 0;
2309
2310                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2311                                                 prev_state,state,mmc_hostname(host->mmc));
2312
2313                                 dw_mci_request_end(host, host->mrq);
2314                                 goto unlock;
2315                         }
2316
2317                         prev_state = state = STATE_SENDING_STOP;
2318                         if (!data->error)
2319                             send_stop_cmd(host, data);
2320                         #if 0
2321                         if (data->stop && !data->error) {
2322                                 /* stop command for open-ended transfer*/
2323
2324                                 send_stop_abort(host, data);
2325                         }
2326                         #endif
2327                         /* fall through */
2328                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2329                                                 prev_state,state,mmc_hostname(host->mmc));
2330
2331                 case STATE_SENDING_STOP:
2332                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2333                                 break;
2334
2335                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2336                                                 prev_state, state, mmc_hostname(host->mmc));
2337
2338                         /* CMD error in data command */
2339                         if (host->mrq->cmd->error && host->mrq->data) {
2340                                 dw_mci_fifo_reset(host);
2341                         }
2342
2343                         host->cmd = NULL;
2344                         host->data = NULL;
2345                         #if 1
2346                         dw_mci_command_complete(host, host->mrq->stop);
2347                         #else
2348                         if (host->mrq->stop)
2349                                 dw_mci_command_complete(host, host->mrq->stop);
2350                         else
2351                                 host->cmd_status = 0;
2352                         #endif
2353
2354                         dw_mci_request_end(host, host->mrq);
2355                         goto unlock;
2356
2357                 case STATE_DATA_ERROR:
2358                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2359                                                 &host->pending_events))
2360                                 break;
2361
2362                         state = STATE_DATA_BUSY;
2363                         break;
2364                 }
2365         } while (state != prev_state);
2366
2367         host->state = state;
2368 unlock:
2369         spin_unlock(&host->lock);
2370
2371 }
2372
2373 /* push final bytes to part_buf, only use during push */
2374 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2375 {
2376         memcpy((void *)&host->part_buf, buf, cnt);
2377         host->part_buf_count = cnt;
2378 }
2379
2380 /* append bytes to part_buf, only use during push */
2381 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2382 {
2383         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2384         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2385         host->part_buf_count += cnt;
2386         return cnt;
2387 }
2388
2389 /* pull first bytes from part_buf, only use during pull */
2390 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2391 {
2392         cnt = min(cnt, (int)host->part_buf_count);
2393         if (cnt) {
2394                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2395                        cnt);
2396                 host->part_buf_count -= cnt;
2397                 host->part_buf_start += cnt;
2398         }
2399         return cnt;
2400 }
2401
2402 /* pull final bytes from the part_buf, assuming it's just been filled */
2403 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2404 {
2405         memcpy(buf, &host->part_buf, cnt);
2406         host->part_buf_start = cnt;
2407         host->part_buf_count = (1 << host->data_shift) - cnt;
2408 }
2409
2410 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2411 {
2412         struct mmc_data *data = host->data;
2413         int init_cnt = cnt;
2414
2415         /* try and push anything in the part_buf */
2416         if (unlikely(host->part_buf_count)) {
2417                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2418                 buf += len;
2419                 cnt -= len;
2420                 if (host->part_buf_count == 2) {
2421                         mci_writew(host, DATA(host->data_offset),
2422                                         host->part_buf16);
2423                         host->part_buf_count = 0;
2424                 }
2425         }
2426 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2427         if (unlikely((unsigned long)buf & 0x1)) {
2428                 while (cnt >= 2) {
2429                         u16 aligned_buf[64];
2430                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2431                         int items = len >> 1;
2432                         int i;
2433                         /* memcpy from input buffer into aligned buffer */
2434                         memcpy(aligned_buf, buf, len);
2435                         buf += len;
2436                         cnt -= len;
2437                         /* push data from aligned buffer into fifo */
2438                         for (i = 0; i < items; ++i)
2439                                 mci_writew(host, DATA(host->data_offset),
2440                                                 aligned_buf[i]);
2441                 }
2442         } else
2443 #endif
2444         {
2445                 u16 *pdata = buf;
2446                 for (; cnt >= 2; cnt -= 2)
2447                         mci_writew(host, DATA(host->data_offset), *pdata++);
2448                 buf = pdata;
2449         }
2450         /* put anything remaining in the part_buf */
2451         if (cnt) {
2452                 dw_mci_set_part_bytes(host, buf, cnt);
2453                  /* Push data if we have reached the expected data length */
2454                 if ((data->bytes_xfered + init_cnt) ==
2455                     (data->blksz * data->blocks))
2456                         mci_writew(host, DATA(host->data_offset),
2457                                    host->part_buf16);
2458         }
2459 }
2460
2461 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2462 {
2463 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2464         if (unlikely((unsigned long)buf & 0x1)) {
2465                 while (cnt >= 2) {
2466                         /* pull data from fifo into aligned buffer */
2467                         u16 aligned_buf[64];
2468                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2469                         int items = len >> 1;
2470                         int i;
2471                         for (i = 0; i < items; ++i)
2472                                 aligned_buf[i] = mci_readw(host,
2473                                                 DATA(host->data_offset));
2474                         /* memcpy from aligned buffer into output buffer */
2475                         memcpy(buf, aligned_buf, len);
2476                         buf += len;
2477                         cnt -= len;
2478                 }
2479         } else
2480 #endif
2481         {
2482                 u16 *pdata = buf;
2483                 for (; cnt >= 2; cnt -= 2)
2484                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2485                 buf = pdata;
2486         }
2487         if (cnt) {
2488                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2489                 dw_mci_pull_final_bytes(host, buf, cnt);
2490         }
2491 }
2492
2493 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2494 {
2495         struct mmc_data *data = host->data;
2496         int init_cnt = cnt;
2497
2498         /* try and push anything in the part_buf */
2499         if (unlikely(host->part_buf_count)) {
2500                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2501                 buf += len;
2502                 cnt -= len;
2503                 if (host->part_buf_count == 4) {
2504                         mci_writel(host, DATA(host->data_offset),
2505                                         host->part_buf32);
2506                         host->part_buf_count = 0;
2507                 }
2508         }
2509 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2510         if (unlikely((unsigned long)buf & 0x3)) {
2511                 while (cnt >= 4) {
2512                         u32 aligned_buf[32];
2513                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2514                         int items = len >> 2;
2515                         int i;
2516                         /* memcpy from input buffer into aligned buffer */
2517                         memcpy(aligned_buf, buf, len);
2518                         buf += len;
2519                         cnt -= len;
2520                         /* push data from aligned buffer into fifo */
2521                         for (i = 0; i < items; ++i)
2522                                 mci_writel(host, DATA(host->data_offset),
2523                                                 aligned_buf[i]);
2524                 }
2525         } else
2526 #endif
2527         {
2528                 u32 *pdata = buf;
2529                 for (; cnt >= 4; cnt -= 4)
2530                         mci_writel(host, DATA(host->data_offset), *pdata++);
2531                 buf = pdata;
2532         }
2533         /* put anything remaining in the part_buf */
2534         if (cnt) {
2535                 dw_mci_set_part_bytes(host, buf, cnt);
2536                  /* Push data if we have reached the expected data length */
2537                 if ((data->bytes_xfered + init_cnt) ==
2538                     (data->blksz * data->blocks))
2539                         mci_writel(host, DATA(host->data_offset),
2540                                    host->part_buf32);
2541         }
2542 }
2543
2544 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2545 {
2546 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2547         if (unlikely((unsigned long)buf & 0x3)) {
2548                 while (cnt >= 4) {
2549                         /* pull data from fifo into aligned buffer */
2550                         u32 aligned_buf[32];
2551                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2552                         int items = len >> 2;
2553                         int i;
2554                         for (i = 0; i < items; ++i)
2555                                 aligned_buf[i] = mci_readl(host,
2556                                                 DATA(host->data_offset));
2557                         /* memcpy from aligned buffer into output buffer */
2558                         memcpy(buf, aligned_buf, len);
2559                         buf += len;
2560                         cnt -= len;
2561                 }
2562         } else
2563 #endif
2564         {
2565                 u32 *pdata = buf;
2566                 for (; cnt >= 4; cnt -= 4)
2567                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2568                 buf = pdata;
2569         }
2570         if (cnt) {
2571                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2572                 dw_mci_pull_final_bytes(host, buf, cnt);
2573         }
2574 }
2575
2576 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2577 {
2578         struct mmc_data *data = host->data;
2579         int init_cnt = cnt;
2580
2581         /* try and push anything in the part_buf */
2582         if (unlikely(host->part_buf_count)) {
2583                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2584                 buf += len;
2585                 cnt -= len;
2586
2587                 if (host->part_buf_count == 8) {
2588                         mci_writeq(host, DATA(host->data_offset),
2589                                         host->part_buf);
2590                         host->part_buf_count = 0;
2591                 }
2592         }
2593 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2594         if (unlikely((unsigned long)buf & 0x7)) {
2595                 while (cnt >= 8) {
2596                         u64 aligned_buf[16];
2597                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2598                         int items = len >> 3;
2599                         int i;
2600                         /* memcpy from input buffer into aligned buffer */
2601                         memcpy(aligned_buf, buf, len);
2602                         buf += len;
2603                         cnt -= len;
2604                         /* push data from aligned buffer into fifo */
2605                         for (i = 0; i < items; ++i)
2606                                 mci_writeq(host, DATA(host->data_offset),
2607                                                 aligned_buf[i]);
2608                 }
2609         } else
2610 #endif
2611         {
2612                 u64 *pdata = buf;
2613                 for (; cnt >= 8; cnt -= 8)
2614                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2615                 buf = pdata;
2616         }
2617         /* put anything remaining in the part_buf */
2618         if (cnt) {
2619                 dw_mci_set_part_bytes(host, buf, cnt);
2620                 /* Push data if we have reached the expected data length */
2621                 if ((data->bytes_xfered + init_cnt) ==
2622                     (data->blksz * data->blocks))
2623                         mci_writeq(host, DATA(host->data_offset),
2624                                    host->part_buf);
2625         }
2626 }
2627
2628 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2629 {
2630 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2631         if (unlikely((unsigned long)buf & 0x7)) {
2632                 while (cnt >= 8) {
2633                         /* pull data from fifo into aligned buffer */
2634                         u64 aligned_buf[16];
2635                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2636                         int items = len >> 3;
2637                         int i;
2638                         for (i = 0; i < items; ++i)
2639                                 aligned_buf[i] = mci_readq(host,
2640                                                 DATA(host->data_offset));
2641                         /* memcpy from aligned buffer into output buffer */
2642                         memcpy(buf, aligned_buf, len);
2643                         buf += len;
2644                         cnt -= len;
2645                 }
2646         } else
2647 #endif
2648         {
2649                 u64 *pdata = buf;
2650                 for (; cnt >= 8; cnt -= 8)
2651                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2652                 buf = pdata;
2653         }
2654         if (cnt) {
2655                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2656                 dw_mci_pull_final_bytes(host, buf, cnt);
2657         }
2658 }
2659
2660 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2661 {
2662         int len;
2663
2664         /* get remaining partial bytes */
2665         len = dw_mci_pull_part_bytes(host, buf, cnt);
2666         if (unlikely(len == cnt))
2667                 return;
2668         buf += len;
2669         cnt -= len;
2670
2671         /* get the rest of the data */
2672         host->pull_data(host, buf, cnt);
2673 }
2674
2675 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2676 {
2677         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2678         void *buf;
2679         unsigned int offset;
2680         struct mmc_data *data = host->data;
2681         int shift = host->data_shift;
2682         u32 status;
2683         unsigned int len;
2684         unsigned int remain, fcnt;
2685
2686         if(!host->mmc->bus_refs){
2687                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2688                 goto host_put;
2689         }
2690         do {
2691                 if (!sg_miter_next(sg_miter))
2692                         goto done;
2693
2694                 host->sg = sg_miter->piter.sg;
2695                 buf = sg_miter->addr;
2696                 remain = sg_miter->length;
2697                 offset = 0;
2698
2699                 do {
2700                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2701                                         << shift) + host->part_buf_count;
2702                         len = min(remain, fcnt);
2703                         if (!len)
2704                                 break;
2705                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2706                         data->bytes_xfered += len;
2707                         offset += len;
2708                         remain -= len;
2709                 } while (remain);
2710
2711                 sg_miter->consumed = offset;
2712                 status = mci_readl(host, MINTSTS);
2713                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2714         /* if the RXDR is ready read again */
2715         } while ((status & SDMMC_INT_RXDR) ||
2716                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2717
2718         if (!remain) {
2719                 if (!sg_miter_next(sg_miter))
2720                         goto done;
2721                 sg_miter->consumed = 0;
2722         }
2723         sg_miter_stop(sg_miter);
2724         return;
2725
2726 done:
2727         sg_miter_stop(sg_miter);
2728 host_put:
2729         host->sg = NULL;
2730         smp_wmb();
2731         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2732 }
2733
2734 static void dw_mci_write_data_pio(struct dw_mci *host)
2735 {
2736         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2737         void *buf;
2738         unsigned int offset;
2739         struct mmc_data *data = host->data;
2740         int shift = host->data_shift;
2741         u32 status;
2742         unsigned int len;
2743         unsigned int fifo_depth = host->fifo_depth;
2744         unsigned int remain, fcnt;
2745
2746         if(!host->mmc->bus_refs){
2747                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2748                 goto host_put;
2749         }
2750
2751         do {
2752                 if (!sg_miter_next(sg_miter))
2753                         goto done;
2754
2755                 host->sg = sg_miter->piter.sg;
2756                 buf = sg_miter->addr;
2757                 remain = sg_miter->length;
2758                 offset = 0;
2759
2760                 do {
2761                         fcnt = ((fifo_depth -
2762                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2763                                         << shift) - host->part_buf_count;
2764                         len = min(remain, fcnt);
2765                         if (!len)
2766                                 break;
2767                         host->push_data(host, (void *)(buf + offset), len);
2768                         data->bytes_xfered += len;
2769                         offset += len;
2770                         remain -= len;
2771                 } while (remain);
2772
2773                 sg_miter->consumed = offset;
2774                 status = mci_readl(host, MINTSTS);
2775                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2776         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2777
2778         if (!remain) {
2779                 if (!sg_miter_next(sg_miter))
2780                         goto done;
2781                 sg_miter->consumed = 0;
2782         }
2783         sg_miter_stop(sg_miter);
2784         return;
2785
2786 done:
2787         sg_miter_stop(sg_miter);
2788 host_put:
2789         host->sg = NULL;
2790         smp_wmb();
2791         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2792 }
2793
2794 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2795 {
2796         u32 multi, unit = SZ_2M;
2797
2798         if (!host->cmd_status)
2799             host->cmd_status = status;
2800
2801         if (!host->cmd)
2802                 goto cmd_exit;
2803
2804         if ((MMC_STOP_TRANSMISSION != host->cmd->opcode)) {
2805                 multi = (mci_readl(host, BYTCNT) / unit) +
2806                         ((mci_readl(host, BYTCNT) % unit) ? 1 :0 ) +
2807                         ((host->cmd->retries > 2) ? 2 : host->cmd->retries);
2808                 /* Max limit time: 8s for dto */
2809                 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(4000 * multi));
2810         }
2811
2812 cmd_exit:
2813         smp_wmb();
2814         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2815         tasklet_schedule(&host->tasklet);
2816 }
2817
2818 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2819 {
2820         struct dw_mci *host = dev_id;
2821         u32 pending, sdio_int;
2822         int i;
2823
2824         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2825
2826         /*
2827         * DTO fix - version 2.10a and below, and only if internal DMA
2828         * is configured.
2829         */
2830         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2831                         if (!pending &&
2832                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2833                                 pending |= SDMMC_INT_DATA_OVER;
2834         }
2835
2836         if (pending) {
2837                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2838                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2839                         host->cmd_status = pending;
2840                         smp_wmb();
2841                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
2842                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
2843
2844                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2845                 }
2846
2847                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2848                         /* if there is an error report DATA_ERROR */
2849                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2850                         host->data_status = pending;
2851                         smp_wmb();
2852                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2853
2854                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
2855                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
2856                         tasklet_schedule(&host->tasklet);
2857                 }
2858
2859                 if (pending & SDMMC_INT_DATA_OVER) {
2860                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2861                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2862                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2863                         if (!host->data_status)
2864                                 host->data_status = pending;
2865                         smp_wmb();
2866                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2867                                 if (host->sg != NULL)
2868                                         dw_mci_read_data_pio(host, true);
2869                         }
2870                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2871                         tasklet_schedule(&host->tasklet);
2872                 }
2873
2874                 if (pending & SDMMC_INT_RXDR) {
2875                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2876                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2877                                 dw_mci_read_data_pio(host, false);
2878                 }
2879
2880                 if (pending & SDMMC_INT_TXDR) {
2881                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2882                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2883                                 dw_mci_write_data_pio(host);
2884                 }
2885
2886                 if (pending & SDMMC_INT_VSI) {
2887                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
2888                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
2889                         dw_mci_cmd_interrupt(host, pending);
2890                 }
2891
2892                 if (pending & SDMMC_INT_CMD_DONE) {
2893                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
2894                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2895                         dw_mci_cmd_interrupt(host, pending);
2896                 }
2897
2898                 if (pending & SDMMC_INT_CD) {
2899                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2900                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
2901                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
2902                         queue_work(host->card_workqueue, &host->card_work);
2903                 }
2904
2905                 if (pending & SDMMC_INT_HLE) {
2906                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
2907                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
2908
2909                 }
2910
2911                 /* Handle SDIO Interrupts */
2912                 for (i = 0; i < host->num_slots; i++) {
2913                         struct dw_mci_slot *slot = host->slot[i];
2914
2915                         if (host->verid < DW_MMC_240A)
2916                                 sdio_int = SDMMC_INT_SDIO(i);
2917                         else
2918                                 sdio_int = SDMMC_INT_SDIO(i + 8);
2919
2920                         if (pending & sdio_int) {
2921                                 mci_writel(host, RINTSTS, sdio_int);
2922                                 mmc_signal_sdio_irq(slot->mmc);
2923                         }
2924                 }
2925
2926         }
2927
2928 #ifdef CONFIG_MMC_DW_IDMAC
2929         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
2930         if(!(cpu_is_rk3036() || cpu_is_rk312x())){
2931                 /* Handle DMA interrupts */
2932                 pending = mci_readl(host, IDSTS);
2933                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2934                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2935                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2936                         host->dma_ops->complete((void *)host);
2937                 }
2938         }
2939 #endif
2940
2941         return IRQ_HANDLED;
2942 }
2943
2944 static void dw_mci_work_routine_card(struct work_struct *work)
2945 {
2946         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2947         int i;
2948
2949         for (i = 0; i < host->num_slots; i++) {
2950                 struct dw_mci_slot *slot = host->slot[i];
2951                 struct mmc_host *mmc = slot->mmc;
2952                 struct mmc_request *mrq;
2953                 int present;
2954
2955                 present = dw_mci_get_cd(mmc);
2956                 while (present != slot->last_detect_state) {
2957                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
2958                                 present ? "inserted" : "removed");
2959                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
2960                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
2961
2962                         rk_send_wakeup_key();//wake up system
2963                         spin_lock_bh(&host->lock);
2964
2965                         del_timer(&host->dto_timer); /* delete the timer for INT_DTO */
2966                         /* Card change detected */
2967                         slot->last_detect_state = present;
2968
2969                         /* Clean up queue if present */
2970                         mrq = slot->mrq;
2971                         if (mrq) {
2972                                 if (mrq == host->mrq) {
2973                                         host->data = NULL;
2974                                         host->cmd = NULL;
2975
2976                                         switch (host->state) {
2977                                         case STATE_IDLE:
2978                                                 break;
2979                                         case STATE_SENDING_CMD:
2980                                                 mrq->cmd->error = -ENOMEDIUM;
2981                                                 if (!mrq->data)
2982                                                         break;
2983                                                 /* fall through */
2984                                         case STATE_SENDING_DATA:
2985                                                 mrq->data->error = -ENOMEDIUM;
2986                                                 dw_mci_stop_dma(host);
2987                                                 break;
2988                                         case STATE_DATA_BUSY:
2989                                         case STATE_DATA_ERROR:
2990                                                 if (mrq->data->error == -EINPROGRESS)
2991                                                         mrq->data->error = -ENOMEDIUM;
2992                                                 if (!mrq->stop)
2993                                                         break;
2994                                                 /* fall through */
2995                                         case STATE_SENDING_STOP:
2996                                                 mrq->stop->error = -ENOMEDIUM;
2997                                                 break;
2998                                         }
2999
3000                                         dw_mci_request_end(host, mrq);
3001                                 } else {
3002                                         list_del(&slot->queue_node);
3003                                         mrq->cmd->error = -ENOMEDIUM;
3004                                         if (mrq->data)
3005                                                 mrq->data->error = -ENOMEDIUM;
3006                                         if (mrq->stop)
3007                                                 mrq->stop->error = -ENOMEDIUM;
3008
3009                                         MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",
3010                                                         mrq->cmd->opcode, mmc_hostname(mmc));
3011
3012                                         spin_unlock(&host->lock);
3013                                         mmc_request_done(slot->mmc, mrq);
3014                                         spin_lock(&host->lock);
3015                                 }
3016                         }
3017
3018                         /* Power down slot */
3019                         if (present == 0) {
3020                                 /* Clear down the FIFO */
3021                                 dw_mci_fifo_reset(host);
3022 #ifdef CONFIG_MMC_DW_IDMAC
3023                                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3024                                         dw_mci_idmac_reset(host);
3025 #endif
3026
3027                         }
3028
3029                         spin_unlock_bh(&host->lock);
3030
3031                         present = dw_mci_get_cd(mmc);
3032                 }
3033
3034                 mmc_detect_change(slot->mmc,
3035                 msecs_to_jiffies(host->pdata->detect_delay_ms));
3036         }
3037 }
3038
3039 #ifdef CONFIG_OF
3040 /* given a slot id, find out the device node representing that slot */
3041 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3042 {
3043         struct device_node *np;
3044         const __be32 *addr;
3045         int len;
3046
3047         if (!dev || !dev->of_node)
3048                 return NULL;
3049
3050         for_each_child_of_node(dev->of_node, np) {
3051                 addr = of_get_property(np, "reg", &len);
3052                 if (!addr || (len < sizeof(int)))
3053                         continue;
3054                 if (be32_to_cpup(addr) == slot)
3055                         return np;
3056         }
3057         return NULL;
3058 }
3059
3060 static struct dw_mci_of_slot_quirks {
3061         char *quirk;
3062         int id;
3063 } of_slot_quirks[] = {
3064         {
3065                 .quirk  = "disable-wp",
3066                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3067         },
3068 };
3069
3070 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3071 {
3072         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3073         int quirks = 0;
3074         int idx;
3075
3076         /* get quirks */
3077         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3078                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3079                         quirks |= of_slot_quirks[idx].id;
3080
3081         return quirks;
3082 }
3083
3084 /* find out bus-width for a given slot */
3085 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3086 {
3087         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3088         u32 bus_wd = 1;
3089
3090         if (!np)
3091                 return 1;
3092
3093         if (of_property_read_u32(np, "bus-width", &bus_wd))
3094                 dev_err(dev, "bus-width property not found, assuming width"
3095                                " as 1\n");
3096         return bus_wd;
3097 }
3098
3099
3100 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3101 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3102 {
3103         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3104         int gpio;
3105
3106         if (!np)
3107                 return -EINVAL;
3108
3109         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3110
3111         /* Having a missing entry is valid; return silently */
3112         if (!gpio_is_valid(gpio))
3113                 return -EINVAL;
3114
3115         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3116                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3117                 return -EINVAL;
3118         }
3119
3120     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3121
3122         return gpio;
3123 }
3124
3125
3126 /* find the write protect gpio for a given slot; or -1 if none specified */
3127 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3128 {
3129         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3130         int gpio;
3131
3132         if (!np)
3133                 return -EINVAL;
3134
3135         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3136
3137         /* Having a missing entry is valid; return silently */
3138         if (!gpio_is_valid(gpio))
3139                 return -EINVAL;
3140
3141         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3142                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3143                 return -EINVAL;
3144         }
3145
3146         return gpio;
3147 }
3148
3149 /* find the cd gpio for a given slot */
3150 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3151                                         struct mmc_host *mmc)
3152 {
3153         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3154         int gpio;
3155
3156         if (!np)
3157                 return;
3158
3159         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3160
3161         /* Having a missing entry is valid; return silently */
3162         if (!gpio_is_valid(gpio))
3163                 return;
3164
3165         if (mmc_gpio_request_cd(mmc, gpio, 0))
3166                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3167 }
3168
3169 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3170 {
3171         struct mmc_host *mmc = dev_id;
3172         struct dw_mci_slot *slot = mmc_priv(mmc);
3173         struct dw_mci *host = slot->host;
3174
3175         #if 0
3176         if (mmc->ops->card_event)
3177                 mmc->ops->card_event(mmc);
3178
3179         mmc_detect_change(mmc, msecs_to_jiffies(200));
3180         #endif
3181
3182         /* wakeup system whether gpio debounce or not */
3183         rk_send_wakeup_key();
3184         queue_work(host->card_workqueue, &host->card_work);
3185         return IRQ_HANDLED;
3186 }
3187
3188 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3189                                         struct mmc_host *mmc)
3190 {
3191         struct dw_mci_slot *slot = mmc_priv(mmc);
3192         struct dw_mci *host = slot->host;
3193         int irq;
3194         int ret;
3195
3196         /* Having a missing entry is valid; return silently */
3197         if (!gpio_is_valid(gpio))
3198                 return;
3199
3200         irq = gpio_to_irq(gpio);
3201         if (irq >= 0) {
3202                 ret = devm_request_threaded_irq(&mmc->class_dev, irq,
3203                                                 NULL, dw_mci_gpio_cd_irqt,
3204                                                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3205                                                 "dw_mci_cd", mmc);
3206                 if (ret < 0) {
3207                         irq = ret;
3208                         dev_err(host->dev, "Request cd-gpio %d interrupt error!\n", gpio);
3209                 } else{
3210                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3211                         enable_irq_wake(irq);
3212                 }
3213         } else {
3214                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3215         }
3216 }
3217
3218 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3219                                         struct mmc_host *mmc)
3220 {
3221         if (!gpio_is_valid(gpio))
3222                 return;
3223
3224         if (gpio_to_irq(gpio) >= 0) {
3225                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3226                 devm_gpio_free(&mmc->class_dev, gpio);
3227         }
3228 }
3229 #else /* CONFIG_OF */
3230 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3231 {
3232         return 0;
3233 }
3234 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3235 {
3236         return 1;
3237 }
3238 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3239 {
3240         return NULL;
3241 }
3242 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3243 {
3244         return -EINVAL;
3245 }
3246 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3247                                         struct mmc_host *mmc)
3248 {
3249         return;
3250 }
3251 #endif /* CONFIG_OF */
3252
3253 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3254 {
3255         struct mmc_host *mmc;
3256         struct dw_mci_slot *slot;
3257         const struct dw_mci_drv_data *drv_data = host->drv_data;
3258         int ctrl_id, ret;
3259         u32 freq[2];
3260         u8 bus_width;
3261
3262         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3263         if (!mmc)
3264                 return -ENOMEM;
3265
3266         slot = mmc_priv(mmc);
3267         slot->id = id;
3268         slot->mmc = mmc;
3269         slot->host = host;
3270         host->slot[id] = slot;
3271         host->mmc = mmc;
3272
3273         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3274
3275         mmc->ops = &dw_mci_ops;
3276
3277         if (of_property_read_u32_array(host->dev->of_node,
3278                                        "clock-freq-min-max", freq, 2)) {
3279                 mmc->f_min = DW_MCI_FREQ_MIN;
3280                 mmc->f_max = DW_MCI_FREQ_MAX;
3281
3282                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3283                         mmc->f_min, mmc->f_max, mmc_hostname(mmc));
3284         } else {
3285                 mmc->f_min = freq[0];
3286                 mmc->f_max = freq[1];
3287
3288                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3289                         mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
3290         }
3291
3292         printk("%s : Rockchip specific MHSC: %s\n", mmc_hostname(mmc), RK_SDMMC_DRIVER_VERSION);
3293
3294         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3295                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3296         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3297                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3298         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3299                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3300         /* Fixup for tSD */
3301         if (of_find_property(host->dev->of_node, "supports-tSD", NULL))
3302                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_TSD;
3303
3304
3305         /* We assume only low-level chip use gpio_cd */
3306         if (cpu_is_rk312x() &&
3307                 soc_is_rk3126() &&
3308                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3309                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3310                 if (gpio_is_valid(slot->cd_gpio)) {
3311                         /* Request gpio int for card detection */
3312                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3313                 } else {
3314                         slot->cd_gpio = -ENODEV;
3315                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3316                 }
3317         }
3318
3319         if (host->pdata->get_ocr)
3320                 mmc->ocr_avail = host->pdata->get_ocr(id);
3321         else
3322         {
3323                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
3324                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
3325                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
3326                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
3327         }
3328
3329         /*
3330          * Start with slot power disabled, it will be enabled when a card
3331          * is detected.
3332          */
3333         if (host->pdata->setpower)
3334                 host->pdata->setpower(id, 0);
3335
3336         if (host->pdata->caps)
3337                 mmc->caps = host->pdata->caps;
3338
3339         if (host->pdata->pm_caps)
3340                 mmc->pm_caps = host->pdata->pm_caps;
3341
3342         if (host->dev->of_node) {
3343                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3344                 if (ctrl_id < 0)
3345                         ctrl_id = 0;
3346         } else {
3347                 ctrl_id = to_platform_device(host->dev)->id;
3348         }
3349         if (drv_data && drv_data->caps)
3350                 mmc->caps |= drv_data->caps[ctrl_id];
3351         if (drv_data && drv_data->hold_reg_flag)
3352                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3353
3354         /* set the compatibility of driver. */
3355         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3356                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3357
3358         if (host->pdata->caps2)
3359                 mmc->caps2 = host->pdata->caps2;
3360
3361         if (host->pdata->get_bus_wd)
3362                 bus_width = host->pdata->get_bus_wd(slot->id);
3363         else if (host->dev->of_node)
3364                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3365         else
3366                 bus_width = 1;
3367
3368         switch (bus_width) {
3369                 case 8:
3370                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3371                 case 4:
3372                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3373         }
3374
3375         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3376                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3377         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3378                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3379         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3380                 mmc->caps |= MMC_CAP_HW_RESET;
3381         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3382                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3383         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3384                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3385         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3386                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3387         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3388                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3389
3390         /*Assign pm_caps pass to pm_flags*/
3391         mmc->pm_flags = mmc->pm_caps;
3392
3393         if (host->pdata->blk_settings) {
3394                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3395                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3396                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3397                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3398                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3399         } else {
3400                 /* Useful defaults if platform data is unset. */
3401 #ifdef CONFIG_MMC_DW_IDMAC
3402                 mmc->max_segs = host->ring_size;
3403                 mmc->max_blk_size = 65536;
3404                 mmc->max_blk_count = host->ring_size;
3405                 mmc->max_seg_size = 0x1000;
3406                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3407                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3408                         /* fixup for external dmac setting */
3409                         mmc->max_segs = 64;
3410                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3411                         mmc->max_blk_count = 65535;
3412                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3413                         mmc->max_seg_size = mmc->max_req_size;
3414                 }
3415 #else
3416                 mmc->max_segs = 64;
3417                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3418                 mmc->max_blk_count = 512;
3419                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3420                 mmc->max_seg_size = mmc->max_req_size;
3421 #endif /* CONFIG_MMC_DW_IDMAC */
3422
3423         }
3424         /* pwr_en */
3425         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3426
3427         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3428         {
3429                 host->vmmc = NULL;
3430         }else{
3431
3432                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3433                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3434                 else
3435                         host->vmmc = NULL;
3436
3437                 if (IS_ERR(host->vmmc)) {
3438                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3439                         host->vmmc = NULL;
3440                 }else{
3441                         ret = regulator_enable(host->vmmc);
3442                         if (ret) {
3443                                 dev_err(host->dev,
3444                                         "failed to enable regulator: %d\n", ret);
3445                                 host->vmmc = NULL;
3446                                 goto err_setup_bus;
3447                         }
3448                 }
3449         }
3450
3451         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3452
3453         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3454                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3455
3456         ret = mmc_add_host(mmc);
3457         if (ret)
3458                 goto err_setup_bus;
3459
3460         /* Pinctrl set default iomux state to fucntion port.
3461          * Fixme: DON'T TOUCH EMMC SETTING!
3462          */
3463         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3464         {
3465                 host->pinctrl = devm_pinctrl_get(host->dev);
3466                 if(IS_ERR(host->pinctrl)){
3467                         printk("%s: Warning : No pinctrl used!\n",mmc_hostname(host->mmc));
3468                 }else{
3469                         host->pins_idle= pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_IDLE);
3470                         if(IS_ERR(host->pins_default)){
3471                                 printk("%s: Warning : No IDLE pinctrl matched!\n", mmc_hostname(host->mmc));
3472                         }
3473                         else
3474                         {
3475                                 if(pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3476                                         printk("%s: Warning :  Idle pinctrl setting failed!\n", mmc_hostname(host->mmc));
3477                         }
3478
3479                         host->pins_default = pinctrl_lookup_state(host->pinctrl,PINCTRL_STATE_DEFAULT);
3480                         if(IS_ERR(host->pins_default)){
3481                                 printk("%s: Warning : No default pinctrl matched!\n", mmc_hostname(host->mmc));
3482                         }
3483                         else
3484                         {
3485                                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3486                                         printk("%s: Warning :  Default pinctrl setting failed!\n", mmc_hostname(host->mmc));
3487                         }
3488                 }
3489         }
3490
3491
3492 #if defined(CONFIG_DEBUG_FS)
3493         dw_mci_init_debugfs(slot);
3494 #endif
3495
3496         /* Card initially undetected */
3497         slot->last_detect_state = 1;
3498
3499         return 0;
3500
3501 err_setup_bus:
3502         if (gpio_is_valid(slot->cd_gpio))
3503                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3504         mmc_free_host(mmc);
3505         return -EINVAL;
3506 }
3507
3508 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3509 {
3510         /* Shutdown detect IRQ */
3511         if (slot->host->pdata->exit)
3512                 slot->host->pdata->exit(id);
3513
3514         /* Debugfs stuff is cleaned up by mmc core */
3515         mmc_remove_host(slot->mmc);
3516         slot->host->slot[id] = NULL;
3517         mmc_free_host(slot->mmc);
3518 }
3519
3520 static void dw_mci_init_dma(struct dw_mci *host)
3521 {
3522         /* Alloc memory for sg translation */
3523         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3524                                           &host->sg_dma, GFP_KERNEL);
3525         if (!host->sg_cpu) {
3526                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3527                         __func__);
3528                 goto no_dma;
3529         }
3530
3531         /* Determine which DMA interface to use */
3532 #if defined(CONFIG_MMC_DW_IDMAC)
3533         if(cpu_is_rk3036() || cpu_is_rk312x()){
3534                 host->dma_ops = &dw_mci_edmac_ops;
3535                 dev_info(host->dev, "Using external DMA controller.\n");
3536         }else{
3537                 host->dma_ops = &dw_mci_idmac_ops;
3538                 dev_info(host->dev, "Using internal DMA controller.\n");
3539         }
3540 #endif
3541
3542         if (!host->dma_ops)
3543                 goto no_dma;
3544
3545         if (host->dma_ops->init && host->dma_ops->start &&
3546             host->dma_ops->stop && host->dma_ops->cleanup) {
3547                 if (host->dma_ops->init(host)) {
3548                         dev_err(host->dev, "%s: Unable to initialize "
3549                                 "DMA Controller.\n", __func__);
3550                         goto no_dma;
3551                 }
3552         } else {
3553                 dev_err(host->dev, "DMA initialization not found.\n");
3554                 goto no_dma;
3555         }
3556
3557         host->use_dma = 1;
3558         return;
3559
3560 no_dma:
3561         dev_info(host->dev, "Using PIO mode.\n");
3562         host->use_dma = 0;
3563         return;
3564 }
3565
3566 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3567 {
3568         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3569         u32 ctrl;
3570
3571         ctrl = mci_readl(host, CTRL);
3572         ctrl |= reset;
3573         mci_writel(host, CTRL, ctrl);
3574
3575         /* wait till resets clear */
3576         do {
3577                 ctrl = mci_readl(host, CTRL);
3578                 if (!(ctrl & reset))
3579                         return true;
3580         } while (time_before(jiffies, timeout));
3581
3582         dev_err(host->dev,
3583                 "Timeout resetting block (ctrl reset %#x)\n",
3584                 ctrl & reset);
3585
3586         return false;
3587 }
3588
3589 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3590 {
3591         /*
3592          * Reseting generates a block interrupt, hence setting
3593          * the scatter-gather pointer to NULL.
3594          */
3595         if (host->sg) {
3596                 sg_miter_stop(&host->sg_miter);
3597                 host->sg = NULL;
3598         }
3599
3600         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3601 }
3602
3603 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3604 {
3605         return dw_mci_ctrl_reset(host,
3606                                  SDMMC_CTRL_FIFO_RESET |
3607                                  SDMMC_CTRL_RESET |
3608                                  SDMMC_CTRL_DMA_RESET);
3609 }
3610
3611 #ifdef CONFIG_OF
3612 /*
3613 static struct dw_mci_of_quirks {
3614         char *quirk;
3615         int id;
3616 } of_quirks[] = {
3617         {
3618                 .quirk  = "broken-cd",
3619                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3620         },
3621 };
3622 */
3623 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3624 {
3625         struct dw_mci_board *pdata;
3626         struct device *dev = host->dev;
3627         struct device_node *np = dev->of_node;
3628         const struct dw_mci_drv_data *drv_data = host->drv_data;
3629         int  ret;
3630         u32 clock_frequency;
3631
3632         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3633         if (!pdata) {
3634                 dev_err(dev, "could not allocate memory for pdata\n");
3635                 return ERR_PTR(-ENOMEM);
3636         }
3637
3638         /* find out number of slots supported */
3639         if (of_property_read_u32(dev->of_node, "num-slots",
3640                                 &pdata->num_slots)) {
3641                 dev_info(dev, "num-slots property not found, "
3642                                 "assuming 1 slot is available\n");
3643                 pdata->num_slots = 1;
3644         }
3645 #if 0
3646         /* get quirks */
3647         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3648                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3649                         pdata->quirks |= of_quirks[idx].id;
3650 #endif
3651
3652         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3653                 dev_info(dev, "fifo-depth property not found, using "
3654                                 "value of FIFOTH register as default\n");
3655
3656         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
3657
3658         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
3659                 pdata->bus_hz = clock_frequency;
3660
3661         if (drv_data && drv_data->parse_dt) {
3662                 ret = drv_data->parse_dt(host);
3663                 if (ret)
3664                         return ERR_PTR(ret);
3665         }
3666
3667         if (of_find_property(np, "keep-power-in-suspend", NULL))
3668                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
3669
3670         if (of_find_property(np, "enable-sdio-wakeup", NULL))
3671                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3672
3673         if (of_find_property(np, "supports-highspeed", NULL))
3674                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3675
3676     if (of_find_property(np, "supports-UHS_SDR104", NULL))
3677                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3678
3679     if (of_find_property(np, "supports-DDR_MODE", NULL))
3680                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
3681
3682     if (of_find_property(np, "caps2-mmc-hs200", NULL))
3683                 pdata->caps2 |= MMC_CAP2_HS200;
3684
3685         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
3686                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
3687
3688         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
3689                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
3690
3691         if (of_get_property(np, "cd-inverted", NULL))
3692                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
3693         if (of_get_property(np, "bootpart-no-access", NULL))
3694                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
3695
3696         return pdata;
3697 }
3698
3699 #else /* CONFIG_OF */
3700 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3701 {
3702         return ERR_PTR(-EINVAL);
3703 }
3704 #endif /* CONFIG_OF */
3705
3706 static void dw_mci_dealwith_timeout(struct dw_mci *host)
3707 {
3708         u32 ret, i, regs;
3709         u32 sdio_int;
3710
3711         switch(host->state){
3712                 case STATE_IDLE:
3713                         break;
3714                 case STATE_SENDING_DATA:
3715                 case STATE_DATA_BUSY:
3716                         host->data_status |= (SDMMC_INT_DCRC|SDMMC_INT_EBE);
3717                         mci_writel(host, RINTSTS, SDMMC_INT_DRTO);  // clear interrupt
3718                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3719                         host->state = STATE_DATA_BUSY;
3720                         if (!dw_mci_ctrl_all_reset(host)) {
3721                                 ret = -ENODEV;
3722                                 return ;
3723                         }
3724
3725                         /* NO requirement to reclaim slave chn using external dmac */
3726                         #ifdef CONFIG_MMC_DW_IDMAC
3727                         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3728                                 if (host->use_dma && host->dma_ops->init)
3729                                         host->dma_ops->init(host);
3730                         #endif
3731
3732                         /*
3733                          * Restore the initial value at FIFOTH register
3734                          * And Invalidate the prev_blksz with zero
3735                          */
3736                         mci_writel(host, FIFOTH, host->fifoth_val);
3737                         host->prev_blksz = 0;
3738                         mci_writel(host, TMOUT, 0xFFFFFFFF);
3739                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3740                         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
3741                                         | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
3742                         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
3743                                 regs |= SDMMC_INT_CD;
3744
3745                         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
3746                                 if (host->verid < DW_MMC_240A)
3747                                         sdio_int = SDMMC_INT_SDIO(0);
3748                                 else
3749                                         sdio_int = SDMMC_INT_SDIO(8);
3750
3751                                 if (mci_readl(host, INTMASK) & sdio_int)
3752                                         regs |= sdio_int;
3753                         }
3754
3755                         mci_writel(host, INTMASK, regs);
3756                         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3757                         for (i = 0; i < host->num_slots; i++) {
3758                                 struct dw_mci_slot *slot = host->slot[i];
3759                                 if (!slot)
3760                                         continue;
3761                                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3762                                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3763                                         dw_mci_setup_bus(slot, true);
3764                                 }
3765                         }
3766                         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3767                         tasklet_schedule(&host->tasklet);
3768                         break;
3769                 default:
3770                         break;
3771     }
3772 }
3773 static void dw_mci_dto_timeout(unsigned long host_data)
3774 {
3775         struct dw_mci *host = (struct dw_mci *) host_data;
3776
3777         disable_irq(host->irq);
3778
3779         dev_err(host->dev, "data_over interrupt timeout!\n");
3780         host->data_status = SDMMC_INT_EBE;
3781         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3782         dw_mci_dealwith_timeout(host);
3783
3784         enable_irq(host->irq);
3785 }
3786
3787
3788 void resume_rescan_enable(struct work_struct *work)
3789 {
3790         struct dw_mci *host =
3791                 container_of(work, struct dw_mci, resume_rescan.work);
3792         host->mmc->rescan_disable = 0;
3793         mmc_detect_change(host->mmc, 10);
3794 }
3795
3796
3797 int dw_mci_probe(struct dw_mci *host)
3798 {
3799         const struct dw_mci_drv_data *drv_data = host->drv_data;
3800         int width, i, ret = 0;
3801         u32 fifo_size;
3802         int init_slots = 0;
3803         u32 regs;
3804
3805         if (!host->pdata) {
3806                 host->pdata = dw_mci_parse_dt(host);
3807                 if (IS_ERR(host->pdata)) {
3808                         dev_err(host->dev, "platform data not available\n");
3809                         return -EINVAL;
3810                 }
3811         }
3812
3813         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
3814                 dev_err(host->dev,
3815                         "Platform data must supply select_slot function\n");
3816                 return -ENODEV;
3817         }
3818
3819         /*
3820          * In 2.40a spec, Data offset is changed.
3821          * Need to check the version-id and set data-offset for DATA register.
3822          */
3823         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3824         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3825
3826         if (host->verid < DW_MMC_240A)
3827                 host->data_offset = DATA_OFFSET;
3828         else
3829                 host->data_offset = DATA_240A_OFFSET;
3830
3831         //hclk enable
3832         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
3833         if (IS_ERR(host->hclk_mmc)) {
3834                 dev_err(host->dev, "failed to get hclk_mmc\n");
3835                 ret = PTR_ERR(host->hclk_mmc);
3836                 goto err_hclk_mmc;
3837         }
3838
3839         clk_prepare_enable(host->hclk_mmc);
3840
3841         //mmc clk enable
3842         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
3843         if (IS_ERR(host->clk_mmc)) {
3844                 dev_err(host->dev, "failed to get clk mmc_per\n");
3845                 ret = PTR_ERR(host->clk_mmc);
3846                 goto err_clk_mmc;
3847         }
3848
3849         host->bus_hz = host->pdata->bus_hz;
3850         if (!host->bus_hz) {
3851                 dev_err(host->dev,"Platform data must supply bus speed\n");
3852                 ret = -ENODEV;
3853                 goto err_clk_mmc;
3854         }
3855
3856         if (host->verid < DW_MMC_240A)
3857                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
3858         else
3859                 //rockchip: fix divider 2 in clksum before controlller
3860                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
3861
3862         if(ret < 0) {
3863             dev_err(host->dev, "failed to set clk mmc\n");
3864             goto err_clk_mmc;
3865         }
3866         clk_prepare_enable(host->clk_mmc);
3867
3868         if (drv_data && drv_data->setup_clock) {
3869         ret = drv_data->setup_clock(host);
3870         if (ret) {
3871             dev_err(host->dev,
3872                 "implementation specific clock setup failed\n");
3873             goto err_clk_mmc;
3874         }
3875     }
3876
3877         host->quirks = host->pdata->quirks;
3878         host->irq_state = true;
3879         host->set_speed = 0;
3880         host->set_div = 0;
3881         host->svi_flags = 0;
3882
3883         spin_lock_init(&host->lock);
3884         spin_lock_init(&host->slock);
3885
3886         INIT_LIST_HEAD(&host->queue);
3887         INIT_DELAYED_WORK(&host->resume_rescan, resume_rescan_enable);
3888         /*
3889          * Get the host data width - this assumes that HCON has been set with
3890          * the correct values.
3891          */
3892         i = (mci_readl(host, HCON) >> 7) & 0x7;
3893         if (!i) {
3894                 host->push_data = dw_mci_push_data16;
3895                 host->pull_data = dw_mci_pull_data16;
3896                 width = 16;
3897                 host->data_shift = 1;
3898         } else if (i == 2) {
3899                 host->push_data = dw_mci_push_data64;
3900                 host->pull_data = dw_mci_pull_data64;
3901                 width = 64;
3902                 host->data_shift = 3;
3903         } else {
3904                 /* Check for a reserved value, and warn if it is */
3905                 WARN((i != 1),
3906                      "HCON reports a reserved host data width!\n"
3907                      "Defaulting to 32-bit access.\n");
3908                 host->push_data = dw_mci_push_data32;
3909                 host->pull_data = dw_mci_pull_data32;
3910                 width = 32;
3911                 host->data_shift = 2;
3912         }
3913
3914         /* Reset all blocks */
3915         if (!dw_mci_ctrl_all_reset(host))
3916                 return -ENODEV;
3917
3918         host->dma_ops = host->pdata->dma_ops;
3919         dw_mci_init_dma(host);
3920
3921         /* Clear the interrupts for the host controller */
3922         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3923         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3924
3925         /* Put in max timeout */
3926         mci_writel(host, TMOUT, 0xFFFFFFFF);
3927
3928         /*
3929          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3930          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3931          */
3932         if (!host->pdata->fifo_depth) {
3933                 /*
3934                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3935                  * have been overwritten by the bootloader, just like we're
3936                  * about to do, so if you know the value for your hardware, you
3937                  * should put it in the platform data.
3938                  */
3939                 fifo_size = mci_readl(host, FIFOTH);
3940                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3941         } else {
3942                 fifo_size = host->pdata->fifo_depth;
3943         }
3944         host->fifo_depth = fifo_size;
3945         host->fifoth_val =
3946                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3947         mci_writel(host, FIFOTH, host->fifoth_val);
3948
3949         /* disable clock to CIU */
3950         mci_writel(host, CLKENA, 0);
3951         mci_writel(host, CLKSRC, 0);
3952
3953         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3954         host->card_workqueue = alloc_workqueue("dw-mci-card",
3955                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
3956         if (!host->card_workqueue) {
3957                 ret = -ENOMEM;
3958                 goto err_dmaunmap;
3959         }
3960         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
3961         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3962                                host->irq_flags, "dw-mci", host);
3963         if (ret)
3964                 goto err_workqueue;
3965
3966         if (host->pdata->num_slots)
3967                 host->num_slots = host->pdata->num_slots;
3968         else
3969                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
3970
3971         setup_timer(&host->dto_timer, dw_mci_dto_timeout, (unsigned long)host);
3972         /* We need at least one slot to succeed */
3973         for (i = 0; i < host->num_slots; i++) {
3974                 ret = dw_mci_init_slot(host, i);
3975                 if (ret)
3976                         dev_dbg(host->dev, "slot %d init failed\n", i);
3977                 else
3978                         init_slots++;
3979         }
3980
3981         /*
3982          * Enable interrupts for command done, data over, data empty, card det,
3983          * receive ready and error such as transmit, receive timeout, crc error
3984          */
3985         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3986         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
3987                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
3988         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3989             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
3990             regs |= SDMMC_INT_CD;
3991
3992         mci_writel(host, INTMASK, regs);
3993
3994         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
3995
3996         dev_info(host->dev, "DW MMC controller at irq %d, "
3997                  "%d bit host data width, "
3998                  "%u deep fifo\n",
3999                  host->irq, width, fifo_size);
4000
4001         if (init_slots) {
4002                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4003         } else {
4004                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4005                                         "but failed on all\n", host->num_slots);
4006                 goto err_workqueue;
4007         }
4008
4009
4010         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4011                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4012
4013         return 0;
4014
4015 err_workqueue:
4016         destroy_workqueue(host->card_workqueue);
4017
4018 err_dmaunmap:
4019         if (host->use_dma && host->dma_ops->exit)
4020                 host->dma_ops->exit(host);
4021
4022         if (host->vmmc){
4023                 regulator_disable(host->vmmc);
4024                 regulator_put(host->vmmc);
4025         }
4026
4027 err_clk_mmc:
4028     if (!IS_ERR(host->clk_mmc))
4029                 clk_disable_unprepare(host->clk_mmc);
4030 err_hclk_mmc:
4031     if (!IS_ERR(host->hclk_mmc))
4032                 clk_disable_unprepare(host->hclk_mmc);
4033
4034         return ret;
4035 }
4036 EXPORT_SYMBOL(dw_mci_probe);
4037
4038 void dw_mci_remove(struct dw_mci *host)
4039 {
4040         struct mmc_host *mmc = host->mmc;
4041         struct dw_mci_slot *slot = mmc_priv(mmc);
4042         int i;
4043
4044         del_timer_sync(&host->dto_timer);
4045         cancel_delayed_work(&host->resume_rescan);
4046
4047         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4048         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4049
4050         for(i = 0; i < host->num_slots; i++){
4051                 dev_dbg(host->dev, "remove slot %d\n", i);
4052                 if(host->slot[i])
4053                         dw_mci_cleanup_slot(host->slot[i], i);
4054         }
4055
4056         /* disable clock to CIU */
4057         mci_writel(host, CLKENA, 0);
4058         mci_writel(host, CLKSRC, 0);
4059
4060         destroy_workqueue(host->card_workqueue);
4061
4062         if(host->use_dma && host->dma_ops->exit)
4063                 host->dma_ops->exit(host);
4064
4065         if (gpio_is_valid(slot->cd_gpio))
4066                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4067
4068         if(host->vmmc){
4069                 regulator_disable(host->vmmc);
4070                 regulator_put(host->vmmc);
4071         }
4072         if(!IS_ERR(host->clk_mmc))
4073                 clk_disable_unprepare(host->clk_mmc);
4074
4075         if(!IS_ERR(host->hclk_mmc))
4076                 clk_disable_unprepare(host->hclk_mmc);
4077 }
4078 EXPORT_SYMBOL(dw_mci_remove);
4079
4080
4081
4082 #ifdef CONFIG_PM_SLEEP
4083 /*
4084  * TODO: we should probably disable the clock to the card in the suspend path.
4085  */
4086 int dw_mci_suspend(struct dw_mci *host)
4087 {
4088         if(host->vmmc)
4089                 regulator_disable(host->vmmc);
4090
4091         /*only for sdmmc controller*/
4092         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4093                 host->mmc->rescan_disable = 1;
4094                 if (cancel_delayed_work_sync(&host->mmc->detect))
4095                         wake_unlock(&host->mmc->detect_wake_lock);
4096
4097                 disable_irq(host->irq);
4098                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4099                         MMC_DBG_ERR_FUNC(host->mmc, "Idle pinctrl setting failed! [%s]",
4100                                                 mmc_hostname(host->mmc));
4101
4102                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
4103                 mci_writel(host, INTMASK, 0x00);
4104                 mci_writel(host, CTRL, 0x00);
4105
4106                 /* Soc rk3126 already in gpio_cd mode */
4107                 if (!(cpu_is_rk312x() && soc_is_rk3126())) {
4108                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4109                         enable_irq_wake(host->mmc->slot.cd_irq);
4110                 }
4111         }
4112         return 0;
4113 }
4114 EXPORT_SYMBOL(dw_mci_suspend);
4115
4116 int dw_mci_resume(struct dw_mci *host)
4117 {
4118         int i, ret, retry_cnt = 0;
4119         u32 regs;
4120         struct dw_mci_slot *slot;
4121
4122         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4123                 slot = mmc_priv(host->mmc);
4124                 if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4125                         return 0;
4126         }
4127
4128         /*only for sdmmc controller*/
4129         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4130                 /* Soc rk3126 already in gpio_cd mode */
4131                 if (!(cpu_is_rk312x() && soc_is_rk3126())) {
4132                         disable_irq_wake(host->mmc->slot.cd_irq);
4133                         mmc_gpio_free_cd(host->mmc);
4134                 }
4135                 if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4136                         MMC_DBG_ERR_FUNC(host->mmc, "Default pinctrl setting failed! [%s]",
4137                                                 mmc_hostname(host->mmc));
4138                 host->mmc->rescan_disable = 1;
4139                 /* Disable jtag*/
4140                 if(cpu_is_rk3288())
4141                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4142                 else if(cpu_is_rk3036())
4143                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4144                 else if(cpu_is_rk312x())
4145                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4146                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4147         }
4148         if(host->vmmc){
4149                 ret = regulator_enable(host->vmmc);
4150                 if (ret){
4151                         dev_err(host->dev,
4152                                 "failed to enable regulator: %d\n", ret);
4153                         return ret;
4154                 }
4155         }
4156
4157         if(!dw_mci_ctrl_all_reset(host)){
4158                 ret = -ENODEV;
4159                 return ret;
4160         }
4161
4162         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
4163                 if(host->use_dma && host->dma_ops->init)
4164                         host->dma_ops->init(host);
4165
4166         /*
4167          * Restore the initial value at FIFOTH register
4168          * And Invalidate the prev_blksz with zero
4169          */
4170         mci_writel(host, FIFOTH, host->fifoth_val);
4171         host->prev_blksz = 0;
4172         /* Put in max timeout */
4173         mci_writel(host, TMOUT, 0xFFFFFFFF);
4174
4175         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4176         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_RXDR | SDMMC_INT_VSI |
4177                    DW_MCI_ERROR_FLAGS;
4178         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4179             regs |= SDMMC_INT_CD;
4180         mci_writel(host, INTMASK, regs);
4181         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4182         /*only for sdmmc controller*/
4183         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)&& (!retry_cnt)){
4184                 enable_irq(host->irq);
4185         }
4186
4187         for(i = 0; i < host->num_slots; i++){
4188                 struct dw_mci_slot *slot = host->slot[i];
4189                 if(!slot)
4190                         continue;
4191                 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4192                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4193                         dw_mci_setup_bus(slot, true);
4194                 }
4195         }
4196         schedule_delayed_work(&host->resume_rescan, msecs_to_jiffies(2000));
4197         return 0;
4198 }
4199 EXPORT_SYMBOL(dw_mci_resume);
4200 #endif /* CONFIG_PM_SLEEP */
4201
4202 static int __init dw_mci_init(void)
4203 {
4204         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4205         return 0;
4206 }
4207
4208 static void __exit dw_mci_exit(void)
4209 {
4210 }
4211
4212 module_init(dw_mci_init);
4213 module_exit(dw_mci_exit);
4214
4215 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4216 MODULE_AUTHOR("NXP Semiconductor VietNam");
4217 MODULE_AUTHOR("Imagination Technologies Ltd");
4218 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4219 MODULE_AUTHOR("Rockchip Electronics£¬Bangwang Xie < xbw@rock-chips.com> ");
4220 MODULE_LICENSE("GPL v2");