drivers/mmc/host/rk_sdmmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/blkdev.h>
  17 #include <linux/clk.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/device.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ioport.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <linux/stat.h>
  31 #include <linux/delay.h>
  32 #include <linux/irq.h>
  33 #include <linux/suspend.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/mmc.h>
  36 #include <linux/mmc/sd.h>
  37 #include <linux/mmc/card.h>
  38 #include <linux/mmc/sdio.h>
  39 #include <linux/mmc/rk_mmc.h>
  40 #include <linux/bitops.h>
  41 #include <linux/regulator/consumer.h>
  42 #include <linux/workqueue.h>
  43 #include <linux/of.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/mmc/slot-gpio.h>
  46 #include <linux/clk-private.h>
  47 #include <linux/rockchip/cpu.h>
  48 #include <linux/rfkill-wlan.h>
  49 #include <linux/mfd/syscon.h>
  50 #include <linux/regmap.h>
  51 #include <linux/log2.h>
  52 #include "rk_sdmmc.h"
  53 #include "rk_sdmmc_dbg.h"
  54 #include <linux/regulator/rockchip_io_vol_domain.h>
  55 #include "../../clk/rockchip/clk-ops.h"
  56
  57 #define RK_SDMMC_DRIVER_VERSION "Ver 1.13 2014-09-05"
  58
  59 /* Common flag combinations */
  60 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  61                                  /*SDMMC_INT_HTO | */SDMMC_INT_SBE  | \
  62                                  SDMMC_INT_EBE)
  63 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  64                                  SDMMC_INT_RESP_ERR)
  65 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  66                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  67 #define DW_MCI_SEND_STATUS      1
  68 #define DW_MCI_RECV_STATUS      2
  69 #define DW_MCI_DMA_THRESHOLD    16
  70
  71 #define DW_MCI_FREQ_MAX 50000000//200000000     /* unit: HZ */
  72 #define DW_MCI_FREQ_MIN 300000//400000          /* unit: HZ */
  73
  74 /*max is 250ms showed in Spec; Maybe adapt the value for the sick card.*/
  75 #define SDMMC_DATA_TIMEOUT_SD   500
  76 #define SDMMC_DATA_TIMEOUT_SDIO 250
  77 #define SDMMC_DATA_TIMEOUT_EMMC 2500
  78
  79 #define SDMMC_CMD_RTO_MAX_HOLD  200
  80 #define SDMMC_WAIT_FOR_UNBUSY   2500
  81
  82 #define DW_REGS_SIZE    (0x0098 + 4)
  83 #define DW_REGS_NUM     (0x0098 / 4)
  84
  85 #ifdef CONFIG_MMC_DW_IDMAC
  86 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  87                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  88                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  89                                  SDMMC_IDMAC_INT_TI)
  90
  91 struct idmac_desc {
  92         u32             des0;   /* Control Descriptor */
  93 #define IDMAC_DES0_DIC  BIT(1)
  94 #define IDMAC_DES0_LD   BIT(2)
  95 #define IDMAC_DES0_FD   BIT(3)
  96 #define IDMAC_DES0_CH   BIT(4)
  97 #define IDMAC_DES0_ER   BIT(5)
  98 #define IDMAC_DES0_CES  BIT(30)
  99 #define IDMAC_DES0_OWN  BIT(31)
 100
 101         u32             des1;   /* Buffer sizes */
 102 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 103         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
 104
 105         u32             des2;   /* buffer 1 physical address */
 106
 107         u32             des3;   /* buffer 2 physical address */
 108 };
 109 #endif /* CONFIG_MMC_DW_IDMAC */
 110
 111 static const u8 tuning_blk_pattern_4bit[] = {
 112         0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
 113         0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
 114         0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
 115         0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
 116         0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
 117         0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
 118         0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
 119         0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
 120 };
 121
 122 static const u8 tuning_blk_pattern_8bit[] = {
 123         0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
 124         0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
 125         0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
 126         0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
 127         0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
 128         0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
 129         0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
 130         0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
 131         0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
 132         0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
 133         0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
 134         0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
 135         0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
 136         0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
 137         0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
 138         0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
 139 };
 140
 141
 142 static struct sdmmc_reg dw_mci_regs[] =
 143 {
 144   { 0x0000, "CTRL" },
 145   { 0x0004, "PWREN" },
 146   { 0x0008, "CLKDIV" },
 147   { 0x000C, "CLKSRC" },
 148   { 0x0010, "CLKENA" },
 149   { 0x0014, "TMOUT" },
 150   { 0x0018, "CTYPE" },
 151   { 0x001C, "BLKSIZ" },
 152   { 0x0020, "BYTCNT" },
 153   { 0x0024, "INTMASK" },
 154   { 0x0028, "CMDARG" },
 155   { 0x002C, "CMD" },
 156   { 0x0030, "RESP0" },
 157   { 0x0034, "RESP1" },
 158   { 0x0038, "RESP2" },
 159   { 0x003C, "RESP3" },
 160   { 0x0040, "MINSTS" },
 161   { 0x0044, "RINTSTS" },
 162   { 0x0048, "STATUS" },
 163   { 0x004C, "FIFOTH" },
 164   { 0x0050, "CDETECT" },
 165   { 0x0054, "WRTPRT" },
 166   { 0x0058, "GPIO" },
 167   { 0x005C, "TCBCNT" },
 168   { 0x0060, "TBBCNT" },
 169   { 0x0064, "DEBNCE" },
 170   { 0x0068, "USRID" },
 171   { 0x006C, "VERID" },
 172   { 0x0070, "HCON" },
 173   { 0x0074, "UHS_REG" },
 174   { 0x0078, "RST_n" },
 175   { 0x0080, "BMOD" },
 176   { 0x0084, "PLDMND" },
 177   { 0x0088, "DBADDR" },
 178   { 0x008C, "IDSTS" },
 179   { 0x0090, "IDINTEN" },
 180   { 0x0094, "DSCADDR" },
 181   { 0x0098, "BUFADDR" },
 182   { 0x0100, "CARDTHRCTL" },
 183   { 0x0104, "BackEndPwr" },
 184   { 0, 0 }
 185 };
 186
 187 static inline bool dw_mci_fifo_reset(struct dw_mci *host);
 188 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
 189 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 190 static void dw_mci_disable_low_power(struct dw_mci_slot *slot);
 191
 192 /*printk the all register of current host*/
 193 #if 0
 194 static int dw_mci_regs_printk(struct dw_mci *host)
 195 {
 196     struct sdmmc_reg *regs = dw_mci_regs;
 197
 198     while( regs->name != 0 ){
 199         printk("%s: (0x%04x) = 0x%08x\n", regs->name, regs->addr, mci_readreg(host,regs->addr));
 200         regs++;
 201     }
 202     printk("=======printk %s-register end =========\n", mmc_hostname(host->mmc));
 203     return 0;
 204 }
 205 #endif
 206
 207 #if defined(CONFIG_DEBUG_FS)
 208 static int dw_mci_req_show(struct seq_file *s, void *v)
 209 {
 210         struct dw_mci_slot *slot = s->private;
 211         struct mmc_request *mrq;
 212         struct mmc_command *cmd;
 213         struct mmc_command *stop;
 214         struct mmc_data *data;
 215
 216         /* Make sure we get a consistent snapshot */
 217         spin_lock_bh(&slot->host->lock);
 218         mrq = slot->mrq;
 219
 220         if (mrq) {
 221                 cmd = mrq->cmd;
 222                 data = mrq->data;
 223                 stop = mrq->stop;
 224
 225                 if (cmd)
 226                         seq_printf(s,
 227                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 228                                    cmd->opcode, cmd->arg, cmd->flags,
 229                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 230                                    cmd->resp[2], cmd->error);
 231                 if (data)
 232                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 233                                    data->bytes_xfered, data->blocks,
 234                                    data->blksz, data->flags, data->error);
 235                 if (stop)
 236                         seq_printf(s,
 237                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 238                                    stop->opcode, stop->arg, stop->flags,
 239                                    stop->resp[0], stop->resp[1], stop->resp[2],
 240                                    stop->resp[2], stop->error);
 241         }
 242
 243         spin_unlock_bh(&slot->host->lock);
 244
 245         return 0;
 246 }
 247
 248 static int dw_mci_req_open(struct inode *inode, struct file *file)
 249 {
 250         return single_open(file, dw_mci_req_show, inode->i_private);
 251 }
 252
 253 static const struct file_operations dw_mci_req_fops = {
 254         .owner          = THIS_MODULE,
 255         .open           = dw_mci_req_open,
 256         .read           = seq_read,
 257         .llseek         = seq_lseek,
 258         .release        = single_release,
 259 };
 260
 261 static int dw_mci_regs_show(struct seq_file *s, void *v)
 262 {
 263         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 264         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 265         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 266         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 267         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 268         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 269
 270         return 0;
 271 }
 272
 273 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 274 {
 275         return single_open(file, dw_mci_regs_show, inode->i_private);
 276 }
 277
 278 static const struct file_operations dw_mci_regs_fops = {
 279         .owner          = THIS_MODULE,
 280         .open           = dw_mci_regs_open,
 281         .read           = seq_read,
 282         .llseek         = seq_lseek,
 283         .release        = single_release,
 284 };
 285
 286 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 287 {
 288         struct mmc_host *mmc = slot->mmc;
 289         struct dw_mci *host = slot->host;
 290         struct dentry *root;
 291         struct dentry *node;
 292
 293         root = mmc->debugfs_root;
 294         if (!root)
 295                 return;
 296
 297         node = debugfs_create_file("regs", S_IRUSR, root, host,
 298                                    &dw_mci_regs_fops);
 299         if (!node)
 300                 goto err;
 301
 302         node = debugfs_create_file("req", S_IRUSR, root, slot,
 303                                    &dw_mci_req_fops);
 304         if (!node)
 305                 goto err;
 306
 307         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 308         if (!node)
 309                 goto err;
 310
 311         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 312                                   (u32 *)&host->pending_events);
 313         if (!node)
 314                 goto err;
 315
 316         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 317                                   (u32 *)&host->completed_events);
 318         if (!node)
 319                 goto err;
 320
 321         return;
 322
 323 err:
 324         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 325 }
 326 #endif /* defined(CONFIG_DEBUG_FS) */
 327
 328 static void dw_mci_set_timeout(struct dw_mci *host)
 329 {
 330         /* timeout (maximum) */
 331         mci_writel(host, TMOUT, 0xffffffff);
 332 }
 333
 334 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 335 {
 336         struct mmc_data *data;
 337         struct dw_mci_slot *slot = mmc_priv(mmc);
 338         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 339         u32 cmdr;
 340         cmd->error = -EINPROGRESS;
 341
 342         cmdr = cmd->opcode;
 343
 344         if (cmdr == MMC_STOP_TRANSMISSION)
 345                 cmdr |= SDMMC_CMD_STOP;
 346         else
 347                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 348
 349         if (cmd->flags & MMC_RSP_PRESENT) {
 350                 /* We expect a response, so set this bit */
 351                 cmdr |= SDMMC_CMD_RESP_EXP;
 352                 if (cmd->flags & MMC_RSP_136)
 353                         cmdr |= SDMMC_CMD_RESP_LONG;
 354         }
 355
 356         if (cmd->flags & MMC_RSP_CRC)
 357                 cmdr |= SDMMC_CMD_RESP_CRC;
 358
 359         data = cmd->data;
 360         if (data) {
 361                 cmdr |= SDMMC_CMD_DAT_EXP;
 362                 if (data->flags & MMC_DATA_STREAM)
 363                         cmdr |= SDMMC_CMD_STRM_MODE;
 364                 if (data->flags & MMC_DATA_WRITE)
 365                         cmdr |= SDMMC_CMD_DAT_WR;
 366         }
 367
 368         if (drv_data && drv_data->prepare_command)
 369                 drv_data->prepare_command(slot->host, &cmdr);
 370
 371         return cmdr;
 372 }
 373
 374 #if 0
 375 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 376 {
 377         struct mmc_command *stop;
 378         u32 cmdr;
 379
 380         if (!cmd->data)
 381                 return 0;
 382
 383         stop = &host->stop_abort;
 384         cmdr = cmd->opcode;
 385         memset(stop, 0, sizeof(struct mmc_command));
 386
 387         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 388             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 389             cmdr == MMC_WRITE_BLOCK ||
 390             cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
 391                 stop->opcode = MMC_STOP_TRANSMISSION;
 392                 stop->arg = 0;
 393                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 394         } else if (cmdr == SD_IO_RW_EXTENDED) {
 395                 stop->opcode = SD_IO_RW_DIRECT;
 396                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 397                              ((cmd->arg >> 28) & 0x7);
 398                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 399         } else {
 400                 return 0;
 401         }
 402
 403         cmdr = stop->opcode | SDMMC_CMD_STOP |
 404                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 405
 406         return cmdr;
 407 }
 408 #endif
 409 static void dw_mci_start_command(struct dw_mci *host,
 410                                  struct mmc_command *cmd, u32 cmd_flags)
 411 {
 412         struct dw_mci_slot *slot = host->slot[0];
 413         /*temporality fix slot[0] due to host->num_slots equal to 1*/
 414
 415         host->pre_cmd = host->cmd;
 416         host->cmd = cmd;
 417         dev_vdbg(host->dev,
 418                 "start command: ARGR=0x%08x CMDR=0x%08x\n",
 419                 cmd->arg, cmd_flags);
 420
 421         if(SD_SWITCH_VOLTAGE == cmd->opcode){
 422                 /*confirm non-low-power mode*/
 423                 mci_writel(host, CMDARG, 0);
 424                 dw_mci_disable_low_power(slot);
 425
 426                 MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s before start cmd=11,[%s]",
 427                         __LINE__, __FUNCTION__,mmc_hostname(host->mmc));
 428
 429                 cmd_flags |= SDMMC_CMD_VOLT_SWITCH;
 430         }
 431
 432         mci_writel(host, CMDARG, cmd->arg);
 433         wmb();
 434
 435         /* fix the value to 1 in some Soc,for example RK3188. */
 436         if(host->mmc->hold_reg_flag)
 437                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
 438
 439         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 440         wmb();
 441 }
 442
 443 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 444 {
 445         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 446 }
 447
 448 /* DMA interface functions */
 449 static void dw_mci_stop_dma(struct dw_mci *host)
 450 {
 451         if (host->using_dma) {
 452                 /* Fixme: No need to terminate edma, may cause flush op */
 453                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 454                         host->dma_ops->stop(host);
 455                 host->dma_ops->cleanup(host);
 456         }
 457
 458         /* Data transfer was stopped by the interrupt handler */
 459         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 460 }
 461
 462 static int dw_mci_get_dma_dir(struct mmc_data *data)
 463 {
 464         if (data->flags & MMC_DATA_WRITE)
 465                 return DMA_TO_DEVICE;
 466         else
 467                 return DMA_FROM_DEVICE;
 468 }
 469
 470 #ifdef CONFIG_MMC_DW_IDMAC
 471 static void dw_mci_dma_cleanup(struct dw_mci *host)
 472 {
 473         struct mmc_data *data = host->data;
 474
 475         if (data)
 476                 if (!data->host_cookie)
 477                         dma_unmap_sg(host->dev,
 478                                      data->sg,
 479                                      data->sg_len,
 480                                      dw_mci_get_dma_dir(data));
 481 }
 482
 483 static void dw_mci_idmac_reset(struct dw_mci *host)
 484 {
 485         u32 bmod = mci_readl(host, BMOD);
 486         /* Software reset of DMA */
 487         bmod |= SDMMC_IDMAC_SWRESET;
 488         mci_writel(host, BMOD, bmod);
 489 }
 490
 491 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 492 {
 493         u32 temp;
 494
 495         /* Disable and reset the IDMAC interface */
 496         temp = mci_readl(host, CTRL);
 497         temp &= ~SDMMC_CTRL_USE_IDMAC;
 498         temp |= SDMMC_CTRL_DMA_RESET;
 499         mci_writel(host, CTRL, temp);
 500
 501         /* Stop the IDMAC running */
 502         temp = mci_readl(host, BMOD);
 503         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 504         temp |= SDMMC_IDMAC_SWRESET;
 505         mci_writel(host, BMOD, temp);
 506 }
 507
 508 static void dw_mci_idmac_complete_dma(void *arg)
 509 {
 510         struct dw_mci *host = arg;
 511         struct mmc_data *data = host->data;
 512
 513         dev_vdbg(host->dev, "DMA complete\n");
 514
 515         /*
 516         MMC_DBG_CMD_FUNC(host->mmc," DMA complete cmd=%d(arg=0x%x), blocks=%d,blksz=%d[%s]", \
 517                 host->mrq->cmd->opcode,host->mrq->cmd->arg,
 518                 data->blocks,data->blksz,mmc_hostname(host->mmc));
 519         */
 520
 521         host->dma_ops->cleanup(host);
 522
 523         /*
 524          * If the card was removed, data will be NULL. No point in trying to
 525          * send the stop command or waiting for NBUSY in this case.
 526          */
 527         if(data){
 528                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 529                 tasklet_schedule(&host->tasklet);
 530         }
 531 }
 532
 533 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 534                                     unsigned int sg_len)
 535 {
 536         int i;
 537         struct idmac_desc *desc = host->sg_cpu;
 538
 539         for (i = 0; i < sg_len; i++, desc++) {
 540                 unsigned int length = sg_dma_len(&data->sg[i]);
 541                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 542
 543                 /* Set the OWN bit and disable interrupts for this descriptor */
 544                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 545
 546                 /* Buffer length */
 547                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 548
 549                 /* Physical address to DMA to/from */
 550                 desc->des2 = mem_addr;
 551         }
 552
 553         /* Set first descriptor */
 554         desc = host->sg_cpu;
 555         desc->des0 |= IDMAC_DES0_FD;
 556
 557         /* Set last descriptor */
 558         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 559         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 560         desc->des0 |= IDMAC_DES0_LD;
 561
 562         wmb();
 563 }
 564
 565 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 566 {
 567         u32 temp;
 568
 569         dw_mci_translate_sglist(host, host->data, sg_len);
 570
 571         /* Select IDMAC interface */
 572         temp = mci_readl(host, CTRL);
 573         temp |= SDMMC_CTRL_USE_IDMAC;
 574         mci_writel(host, CTRL, temp);
 575
 576         wmb();
 577
 578         /* Enable the IDMAC */
 579         temp = mci_readl(host, BMOD);
 580         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 581         mci_writel(host, BMOD, temp);
 582
 583         /* Start it running */
 584         mci_writel(host, PLDMND, 1);
 585 }
 586
 587 static int dw_mci_idmac_init(struct dw_mci *host)
 588 {
 589         struct idmac_desc *p;
 590         int i;
 591
 592         /* Number of descriptors in the ring buffer */
 593         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 594
 595         /* Forward link the descriptor list */
 596         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 597                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 598
 599         /* Set the last descriptor as the end-of-ring descriptor */
 600         p->des3 = host->sg_dma;
 601         p->des0 = IDMAC_DES0_ER;
 602
 603         dw_mci_idmac_reset(host);
 604
 605         /* Mask out interrupts - get Tx & Rx complete only */
 606         mci_writel(host, IDSTS, IDMAC_INT_CLR);
 607         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 608                    SDMMC_IDMAC_INT_TI);
 609
 610         /* Set the descriptor base address */
 611         mci_writel(host, DBADDR, host->sg_dma);
 612         return 0;
 613 }
 614
 615 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 616         .init = dw_mci_idmac_init,
 617         .start = dw_mci_idmac_start_dma,
 618         .stop = dw_mci_idmac_stop_dma,
 619         .complete = dw_mci_idmac_complete_dma,
 620         .cleanup = dw_mci_dma_cleanup,
 621 };
 622
 623
 624 static void dw_mci_edma_cleanup(struct dw_mci *host)
 625 {
 626         struct mmc_data *data = host->data;
 627
 628         if (data)
 629                 if (!data->host_cookie)
 630                         dma_unmap_sg(host->dev,
 631                                         data->sg, data->sg_len,
 632                                         dw_mci_get_dma_dir(data));
 633 }
 634
 635 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 636 {
 637         dmaengine_terminate_all(host->dms->ch);
 638 }
 639
 640 static void dw_mci_edmac_complete_dma(void *arg)
 641 {
 642         struct dw_mci *host = arg;
 643         struct mmc_data *data = host->data;
 644
 645         dev_vdbg(host->dev, "DMA complete\n");
 646
 647         if(data)
 648                 if(data->flags & MMC_DATA_READ)
 649                         /* Invalidate cache after read */
 650                         dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 651                                 data->sg_len, DMA_FROM_DEVICE);
 652
 653         host->dma_ops->cleanup(host);
 654
 655         /*
 656          * If the card was removed, data will be NULL. No point in trying to
 657          * send the stop command or waiting for NBUSY in this case.
 658          */
 659         if (data) {
 660                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 661                 tasklet_schedule(&host->tasklet);
 662         }
 663 }
 664
 665 static void dw_mci_edmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 666 {
 667         struct dma_slave_config slave_config;
 668         struct dma_async_tx_descriptor *desc = NULL;
 669         struct scatterlist *sgl = host->data->sg;
 670         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 671         u32 sg_elems = host->data->sg_len;
 672         u32 fifoth_val, mburst;
 673         u32 burst_limit = 0;
 674         u32 idx, rx_wmark, tx_wmark;
 675         int ret = 0;
 676
 677         /* Set external dma config: burst size, burst width*/
 678         slave_config.dst_addr = (dma_addr_t)(host->phy_regs + host->data_offset);
 679         slave_config.src_addr = slave_config.dst_addr;
 680         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 681         slave_config.src_addr_width = slave_config.dst_addr_width;
 682
 683         /* Match FIFO dma burst MSIZE with external dma config*/
 684         fifoth_val = mci_readl(host, FIFOTH);
 685         mburst = mszs[(fifoth_val >> 28) & 0x7];
 686
 687         /* edmac limit burst to 16, but work around for rk3036 to 8 */
 688         if (unlikely(cpu_is_rk3036()))
 689                 burst_limit = 8;
 690         else
 691                 burst_limit = 16;
 692
 693         if (mburst > burst_limit) {
 694                 mburst = burst_limit;
 695                 idx = (ilog2(mburst) > 0) ? (ilog2(mburst) - 1) : 0;
 696
 697                 rx_wmark = mszs[idx] - 1;
 698                 tx_wmark = (host->fifo_depth) / 2;
 699                 fifoth_val = SDMMC_SET_FIFOTH(idx, rx_wmark, tx_wmark);
 700
 701                 mci_writel(host, FIFOTH, fifoth_val);
 702         }
 703
 704         slave_config.dst_maxburst = mburst;
 705         slave_config.src_maxburst = slave_config.dst_maxburst;
 706
 707         if(host->data->flags & MMC_DATA_WRITE){
 708                 slave_config.direction = DMA_MEM_TO_DEV;
 709                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 710                 if(ret){
 711                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 712                         return;
 713                 }
 714
 715                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 716                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 717                 if (!desc) {
 718                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 719                         return;
 720                 }
 721                 /* Set dw_mci_edmac_complete_dma as callback */
 722                 desc->callback = dw_mci_edmac_complete_dma;
 723                 desc->callback_param = (void *)host;
 724                 dmaengine_submit(desc);
 725
 726                 /* Flush cache before write */
 727                 dma_sync_sg_for_device(mmc_dev(host->mmc), sgl,
 728                                 sg_elems, DMA_TO_DEVICE);
 729                 dma_async_issue_pending(host->dms->ch);
 730         } else {
 731                 /* MMC_DATA_READ*/
 732                 slave_config.direction = DMA_DEV_TO_MEM;
 733                 ret = dmaengine_slave_config(host->dms->ch, &slave_config);
 734                 if (ret) {
 735                         dev_err(host->dev, "error in dw_mci edma configuration.\n");
 736                         return;
 737                 }
 738                 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, sg_len,
 739                                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 740                 if (!desc) {
 741                         dev_err(host->dev, "We cannot prepare for the dw_mci slave edma!\n");
 742                         return;
 743                 }
 744                 /* set dw_mci_edmac_complete_dma as callback */
 745                 desc->callback = dw_mci_edmac_complete_dma;
 746                 desc->callback_param = (void *)host;
 747                 dmaengine_submit(desc);
 748                 dma_async_issue_pending(host->dms->ch);
 749         }
 750 }
 751
 752 static int dw_mci_edmac_init(struct dw_mci *host)
 753 {
 754         /* Request external dma channel, SHOULD decide chn in dts */
 755         host->dms = NULL;
 756         host->dms = (struct dw_mci_dma_slave *)kmalloc
 757                                 (sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 758         if (NULL == host->dms) {
 759                 dev_err(host->dev, "No enough memory to alloc dms.\n");
 760                 goto err_exit;
 761         }
 762
 763         host->dms->ch = dma_request_slave_channel(host->dev, "dw_mci");
 764         if (!host->dms->ch) {
 765                 dev_err(host->dev, "Failed to get external DMA channel: channel id = %d\n",
 766                                 host->dms->ch->chan_id);
 767                 goto err_exit;
 768         }
 769
 770         return 0;
 771
 772 err_exit:
 773         if (NULL != host->dms) {
 774                 kfree(host->dms);
 775                 host->dms = NULL;
 776         }
 777         return -ENXIO;
 778
 779 }
 780
 781 static void dw_mci_edmac_exit(struct dw_mci *host)
 782 {
 783         if (NULL != host->dms) {
 784                 if (NULL != host->dms->ch) {
 785                         dma_release_channel(host->dms->ch);
 786                         host->dms->ch = NULL;
 787                 }
 788                 kfree(host->dms);
 789                 host->dms = NULL;
 790         }
 791 }
 792
 793 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 794         .init = dw_mci_edmac_init,
 795         .exit = dw_mci_edmac_exit,
 796         .start = dw_mci_edmac_start_dma,
 797         .stop = dw_mci_edmac_stop_dma,
 798         .complete = dw_mci_edmac_complete_dma,
 799         .cleanup = dw_mci_edma_cleanup,
 800 };
 801 #endif /* CONFIG_MMC_DW_IDMAC */
 802
 803 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 804                                    struct mmc_data *data,
 805                                    bool next)
 806 {
 807         struct scatterlist *sg;
 808         unsigned int i, sg_len;
 809
 810         if (!next && data->host_cookie)
 811                 return data->host_cookie;
 812
 813         /*
 814          * We don't do DMA on "complex" transfers, i.e. with
 815          * non-word-aligned buffers or lengths. Also, we don't bother
 816          * with all the DMA setup overhead for short transfers.
 817          */
 818         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 819                 return -EINVAL;
 820
 821         if (data->blksz & 3)
 822                 return -EINVAL;
 823
 824         for_each_sg(data->sg, sg, data->sg_len, i) {
 825                 if (sg->offset & 3 || sg->length & 3)
 826                         return -EINVAL;
 827         }
 828
 829         sg_len = dma_map_sg(host->dev,
 830                             data->sg,
 831                             data->sg_len,
 832                             dw_mci_get_dma_dir(data));
 833         if (sg_len == 0)
 834                 return -EINVAL;
 835
 836         if (next)
 837                 data->host_cookie = sg_len;
 838
 839         return sg_len;
 840 }
 841
 842 static void dw_mci_pre_req(struct mmc_host *mmc,
 843                            struct mmc_request *mrq,
 844                            bool is_first_req)
 845 {
 846         struct dw_mci_slot *slot = mmc_priv(mmc);
 847         struct mmc_data *data = mrq->data;
 848
 849         if (!slot->host->use_dma || !data)
 850                 return;
 851
 852         if (data->host_cookie) {
 853                 data->host_cookie = 0;
 854                 return;
 855         }
 856
 857         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 858                 data->host_cookie = 0;
 859 }
 860
 861 static void dw_mci_post_req(struct mmc_host *mmc,
 862                             struct mmc_request *mrq,
 863                             int err)
 864 {
 865         struct dw_mci_slot *slot = mmc_priv(mmc);
 866         struct mmc_data *data = mrq->data;
 867
 868         if (!slot->host->use_dma || !data)
 869                 return;
 870
 871         if (data->host_cookie)
 872                 dma_unmap_sg(slot->host->dev,
 873                              data->sg,
 874                              data->sg_len,
 875                              dw_mci_get_dma_dir(data));
 876         data->host_cookie = 0;
 877 }
 878
 879 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 880 {
 881 #ifdef CONFIG_MMC_DW_IDMAC
 882         unsigned int blksz = data->blksz;
 883         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 884         u32 fifo_width = 1 << host->data_shift;
 885         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 886         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 887         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 888
 889         tx_wmark = (host->fifo_depth) / 2;
 890         tx_wmark_invers = host->fifo_depth - tx_wmark;
 891
 892         /*
 893          * MSIZE is '1',
 894          * if blksz is not a multiple of the FIFO width
 895          */
 896         if (blksz % fifo_width) {
 897                 msize = 0;
 898                 rx_wmark = 1;
 899                 goto done;
 900         }
 901
 902         do {
 903                 if (!((blksz_depth % mszs[idx]) ||
 904                      (tx_wmark_invers % mszs[idx]))) {
 905                         msize = idx;
 906                         rx_wmark = mszs[idx] - 1;
 907                         break;
 908                 }
 909         } while (--idx > 0);
 910         /*
 911          * If idx is '0', it won't be tried
 912          * Thus, initial values are uesed
 913          */
 914 done:
 915         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 916         mci_writel(host, FIFOTH, fifoth_val);
 917
 918 #endif
 919 }
 920
 921 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 922 {
 923         unsigned int blksz = data->blksz;
 924         u32 blksz_depth, fifo_depth;
 925         u16 thld_size;
 926
 927         WARN_ON(!(data->flags & MMC_DATA_READ));
 928
 929         if (host->timing != MMC_TIMING_MMC_HS200 &&
 930             host->timing != MMC_TIMING_UHS_SDR104)
 931                 goto disable;
 932
 933         blksz_depth = blksz / (1 << host->data_shift);
 934         fifo_depth = host->fifo_depth;
 935
 936         if (blksz_depth > fifo_depth)
 937                 goto disable;
 938
 939         /*
 940          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 941          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 942          * Currently just choose blksz.
 943          */
 944         thld_size = blksz;
 945         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 946         return;
 947
 948 disable:
 949         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 950 }
 951
 952 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 953 {
 954         int sg_len;
 955         unsigned long flags;
 956         u32 temp;
 957
 958         host->using_dma = 0;
 959
 960         /* If we don't have a channel, we can't do DMA */
 961         if (!host->use_dma)
 962                 return -ENODEV;
 963
 964         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 965         if (sg_len < 0) {
 966                 /* Fixme: No need terminate edma, may cause flush op */
 967                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
 968                         host->dma_ops->stop(host);
 969                 return sg_len;
 970         }
 971
 972         host->using_dma = 1;
 973
 974         dev_vdbg(host->dev,
 975                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 976                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 977                  sg_len);
 978
 979         /*
 980          * Decide the MSIZE and RX/TX Watermark.
 981          * If current block size is same with previous size,
 982          * no need to update fifoth.
 983          */
 984         if (host->prev_blksz != data->blksz)
 985                 dw_mci_adjust_fifoth(host, data);
 986
 987         /* Reset DMA FIFO*/
 988         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET); //dange to fifo-reset; noted by xbw,at 2014-03-28
 989
 990         /* Enable the DMA interface */
 991         temp = mci_readl(host, CTRL);
 992         temp |= SDMMC_CTRL_DMA_ENABLE;
 993         mci_writel(host, CTRL, temp);
 994
 995         /* Disable RX/TX IRQs, let DMA handle it */
 996         spin_lock_irqsave(&host->slock, flags);
 997         temp = mci_readl(host, INTMASK);
 998         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 999         mci_writel(host, INTMASK, temp);
1000         spin_unlock_irqrestore(&host->slock, flags);
1001
1002         host->dma_ops->start(host, sg_len);
1003
1004         return 0;
1005 }
1006
1007 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1008 {
1009         u32 temp;
1010         unsigned long flag;
1011
1012         data->error = -EINPROGRESS;
1013
1014         //WARN_ON(host->data);
1015         host->sg = NULL;
1016         host->data = data;
1017
1018         /* Reset FIFO*/
1019         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);// | SDMMC_CTRL_FIFO_RESET);//dange to fifo-reset; noted by xbw,at 2014-03-28
1020
1021         if (data->flags & MMC_DATA_READ) {
1022                 host->dir_status = DW_MCI_RECV_STATUS;
1023                 dw_mci_ctrl_rd_thld(host, data);
1024         } else {
1025                 host->dir_status = DW_MCI_SEND_STATUS;
1026         }
1027
1028     MMC_DBG_INFO_FUNC(host->mmc," dw_mci_submit_data,blocks=%d,blksz=%d [%s]",\
1029          data->blocks, data->blksz, mmc_hostname(host->mmc));
1030
1031         if (dw_mci_submit_data_dma(host, data)) {
1032                 int flags = SG_MITER_ATOMIC;
1033                 if (host->data->flags & MMC_DATA_READ)
1034                         flags |= SG_MITER_TO_SG;
1035                 else
1036                         flags |= SG_MITER_FROM_SG;
1037
1038                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1039                 host->sg = data->sg;
1040                 host->part_buf_start = 0;
1041                 host->part_buf_count = 0;
1042
1043                 spin_lock_irqsave(&host->slock, flag);
1044                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1045                 temp = mci_readl(host, INTMASK);
1046                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1047                 mci_writel(host, INTMASK, temp);
1048                 spin_unlock_irqrestore(&host->slock, flag);
1049
1050                 temp = mci_readl(host, CTRL);
1051                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1052                 mci_writel(host, CTRL, temp);
1053
1054                 /*
1055                  * Use the initial fifoth_val for PIO mode.
1056                  * If next issued data may be transfered by DMA mode,
1057                  * prev_blksz should be invalidated.
1058                  */
1059                 mci_writel(host, FIFOTH, host->fifoth_val);
1060                 host->prev_blksz = 0;
1061         } else {
1062                 /*
1063                  * Keep the current block size.
1064                  * It will be used to decide whether to update
1065                  * fifoth register next time.
1066                  */
1067                 host->prev_blksz = data->blksz;
1068         }
1069 }
1070
1071 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1072 {
1073         struct dw_mci *host = slot->host;
1074         unsigned long timeout = jiffies + msecs_to_jiffies(500);//msecs_to_jiffies(5000);
1075         unsigned int cmd_status = 0;
1076 #ifdef SDMMC_WAIT_FOR_UNBUSY
1077         bool ret = true;
1078         timeout = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1079
1080     if(test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1081         while (ret) {
1082                 ret =  time_before(jiffies, timeout);
1083                 cmd_status = mci_readl(host, STATUS);
1084                 if (!(cmd_status & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1085                         break;
1086         } ;
1087         if(false == ret)
1088             printk("%d..%s:  wait for unbusy timeout.......[%s]\n", \
1089                 __LINE__, __FUNCTION__, mmc_hostname(host->mmc));
1090     }
1091 #endif
1092         mci_writel(host, CMDARG, arg);
1093         wmb();
1094         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1095         if(cmd & SDMMC_CMD_UPD_CLK)
1096                 timeout = jiffies + msecs_to_jiffies(50);
1097         else
1098                 timeout = jiffies + msecs_to_jiffies(500);
1099         while (time_before(jiffies, timeout)) {
1100                 cmd_status = mci_readl(host, CMD);
1101                 if (!(cmd_status & SDMMC_CMD_START))
1102                         return ;
1103         }
1104         dev_err(&slot->mmc->class_dev,
1105                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1106                 cmd, arg, cmd_status);
1107 }
1108
1109 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1110 {
1111         struct dw_mci *host = slot->host;
1112         unsigned int tempck,clock = slot->clock;
1113         u32 div;
1114         u32 clk_en_a;
1115         u32 sdio_int;
1116
1117         MMC_DBG_INFO_FUNC(host->mmc,"%d..%s: clock=%d, current_speed=%d, bus_hz=%d,forc=%d[%s]\n",
1118                 __LINE__, __FUNCTION__, clock, host->current_speed,host->bus_hz,force_clkinit,mmc_hostname(host->mmc));
1119
1120         if (!clock) {
1121                 mci_writel(host, CLKENA, 0);
1122                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1123                 if(host->svi_flags == 0)
1124                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1125                 #else
1126                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1127                 #endif
1128         } else if (clock != host->current_speed || force_clkinit) {
1129                 div = host->bus_hz / clock;
1130                 if (host->bus_hz % clock && host->bus_hz > clock)
1131                         /*
1132                          * move the + 1 after the divide to prevent
1133                          * over-clocking the card.
1134                          */
1135                         div += 1;
1136
1137                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1138
1139                 if ((clock << div) != slot->__clk_old || force_clkinit) {
1140                     tempck = div ? ((host->bus_hz / div) >> 1) :host->bus_hz;
1141                         dev_info(&slot->mmc->class_dev,
1142                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1143                                  slot->id, host->bus_hz, clock,
1144                                  tempck, div);
1145
1146                         host->set_speed = tempck;
1147                         host->set_div = div;
1148                 }
1149
1150                 /* disable clock */
1151                 mci_writel(host, CLKENA, 0);
1152                 mci_writel(host, CLKSRC, 0);
1153
1154                 /* inform CIU */
1155                 mci_send_cmd(slot,
1156                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1157
1158                 if(clock <= 400*1000){
1159                         MMC_DBG_BOOT_FUNC(host->mmc,
1160                                 "dw_mci_setup_bus: argue clk_mmc workaround out %dHz for init[%s]",
1161                                 clock * 2, mmc_hostname(host->mmc));
1162                         /* clk_mmc will change parents to 24MHz xtal*/
1163                         clk_set_rate(host->clk_mmc, clock * 2);
1164
1165                         div = 0;
1166                         host->set_div = div;
1167                 }
1168                 else
1169                 {
1170                         MMC_DBG_BOOT_FUNC(host->mmc,
1171                                 "dw_mci_setup_bus: argue clk_mmc workaround out normal clock [%s]",
1172                                 mmc_hostname(host->mmc));
1173                         if(div > 1)
1174                         {
1175                                 MMC_DBG_ERR_FUNC(host->mmc,
1176                                         "dw_mci_setup_bus: div SHOULD NOT LARGER THAN ONE! [%s]",
1177                                         mmc_hostname(host->mmc));
1178                                  div = 1;
1179                                  host->set_div = div;
1180                                  host->bus_hz = host->set_speed * 2;
1181                                  MMC_DBG_BOOT_FUNC(host->mmc,
1182                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1183                                         div, host->bus_hz, mmc_hostname(host->mmc));
1184                         }
1185                         /* BUG may be here, come on,  Linux BSP engineer looks!
1186                            FIXME:  HS-DDR eMMC, div SHOULD be ONE, but we here cannot fetch eMMC bus mode!!!!!!!!
1187                            WRONG dts set clk = 50M, and calc div be zero. Controller denied this setting!
1188                            some oops happened like that:
1189                            mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)
1190                            rk_sdmmc: BOOT dw_mci_setup_bus: argue clk_mmc workaround out normal clock [mmc0]
1191                            rk_sdmmc: BOOT Bus speed=50000000Hz,Bus width=8bits.[mmc0]
1192                            mmc0: new high speed DDR MMC card at address 0001
1193                            mmcblk0: mmc0:0001 M8G1GC 7.28 GiB
1194                            ....
1195                            mmcblk0: error -84 transferring data, sector 606208, nr 32, cmd response 0x900, card status 0xb00
1196                            mmcblk0: retrying using single block read
1197                            mmcblk0: error -110 sending status command, retrying
1198
1199                            We assume all eMMC in RK platform with 3.10 kernel, at least version 4.5
1200                          */
1201                         if ((div == 0) &&
1202                                 (host->mmc->caps & (MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR)) &&
1203                                 !(host->mmc->caps2 & MMC_CAP2_HS200)) {
1204                                 /*  Fixup DDR MMC */
1205                                 div = 1;
1206                                 host->set_div = div;
1207                                 host->bus_hz = host->set_speed * 2;
1208                                 MMC_DBG_BOOT_FUNC(host->mmc,
1209                                         "dw_mci_setup_bus: workaround div = %d, host->bus_hz = %d [%s]",
1210                                         div, host->bus_hz, mmc_hostname(host->mmc));
1211                         }
1212
1213                         if (host->verid < DW_MMC_240A)
1214                                 clk_set_rate(host->clk_mmc,(host->bus_hz));
1215                         else
1216                                 clk_set_rate(host->clk_mmc,(host->bus_hz) * 2);
1217
1218
1219
1220                 }
1221
1222                 /* set clock to desired speed */
1223                 mci_writel(host, CLKDIV, div);
1224
1225                 /* inform CIU */
1226                 mci_send_cmd(slot,
1227                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1228
1229                 /* enable clock; only low power if no SDIO */
1230                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1231
1232                 if (host->verid < DW_MMC_240A)
1233                     sdio_int = SDMMC_INT_SDIO(slot->id);
1234                 else
1235                     sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1236
1237                 if (!(mci_readl(host, INTMASK) & sdio_int))
1238                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1239                 mci_writel(host, CLKENA, clk_en_a);
1240
1241                 /* inform CIU */
1242                 mci_send_cmd(slot,
1243                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
1244                 /* keep the clock with reflecting clock dividor */
1245                 slot->__clk_old = clock << div;
1246         }
1247
1248         host->current_speed = clock;
1249
1250     if(slot->ctype != slot->pre_ctype)
1251         MMC_DBG_BOOT_FUNC(host->mmc, "Bus speed=%dHz,Bus width=%s.[%s]",
1252             host->set_speed,
1253             (slot->ctype == SDMMC_CTYPE_4BIT)?"4bits":"8bits",
1254             mmc_hostname(host->mmc));
1255     slot->pre_ctype = slot->ctype;
1256
1257         /* Set the current slot bus width */
1258         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1259 }
1260
1261 extern struct mmc_card *this_card;
1262 static void dw_mci_wait_unbusy(struct dw_mci *host)
1263 {
1264
1265         unsigned int    timeout= SDMMC_DATA_TIMEOUT_SDIO;
1266         unsigned long   time_loop;
1267         unsigned int    status;
1268         u32 se_flag = 0;
1269
1270         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_wait_unbusy, status=0x%x ", mci_readl(host, STATUS));
1271
1272         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC) {
1273                 if (host->cmd && (host->cmd->opcode == MMC_ERASE)) {
1274                 /* Special care for (secure)erase timeout calculation */
1275                         if(this_card){
1276                                 if((host->cmd->arg & (0x1 << 31)) == 1) /* secure erase */
1277                                         se_flag = 0x1;
1278
1279                                 if (((this_card->ext_csd.erase_group_def) & 0x1) == 1)
1280                                         se_flag ? (timeout = (this_card->ext_csd.hc_erase_timeout) *
1281                                                         300000 * (this_card->ext_csd.sec_erase_mult)) :
1282                                                         (timeout = (this_card->ext_csd.hc_erase_timeout) * 300000);
1283                         }
1284                 }
1285
1286                 if(timeout < SDMMC_DATA_TIMEOUT_EMMC)
1287                         timeout = SDMMC_DATA_TIMEOUT_EMMC;
1288         } else if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
1289                 timeout = SDMMC_DATA_TIMEOUT_SD;
1290         }
1291
1292         time_loop = jiffies + msecs_to_jiffies(timeout);
1293         do {
1294                 status = mci_readl(host, STATUS);
1295                 if (!(status & (SDMMC_STAUTS_DATA_BUSY | SDMMC_STAUTS_MC_BUSY)))
1296                         break;
1297         } while (time_before(jiffies, time_loop));
1298 }
1299
1300
1301
1302 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1303 /*
1304 *   result:
1305 *   0--status is busy.
1306 *   1--status is unbusy.
1307 */
1308 int dw_mci_card_busy(struct mmc_host *mmc)
1309 {
1310         struct dw_mci_slot *slot = mmc_priv(mmc);
1311         struct dw_mci *host = slot->host;
1312
1313         MMC_DBG_INFO_FUNC(host->mmc, "dw_mci_card_busy: svi_flags = %d [%s]", \
1314                                 host->svi_flags, mmc_hostname(host->mmc));
1315
1316         /* svi toggle*/
1317         if(host->svi_flags == 0){
1318                 /*first svi*/
1319                 host->svi_flags = 1;
1320                 return host->svi_flags;
1321
1322         }else{
1323                 host->svi_flags = 0;
1324                 return host->svi_flags;
1325         }
1326
1327
1328 }
1329 #endif
1330 static void __dw_mci_start_request(struct dw_mci *host,
1331                                    struct dw_mci_slot *slot,
1332                                    struct mmc_command *cmd)
1333 {
1334         struct mmc_request *mrq;
1335         struct mmc_data *data;
1336         u32 cmdflags;
1337
1338         mrq = slot->mrq;
1339         if (host->pdata->select_slot)
1340                 host->pdata->select_slot(slot->id);
1341
1342         host->cur_slot = slot;
1343         host->mrq = mrq;
1344
1345         dw_mci_wait_unbusy(host);
1346
1347         host->pending_events = 0;
1348         host->completed_events = 0;
1349         host->data_status = 0;
1350
1351         data = cmd->data;
1352         if (data) {
1353                 dw_mci_set_timeout(host);
1354                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1355                 mci_writel(host, BLKSIZ, data->blksz);
1356         }
1357
1358         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1359
1360         /* this is the first command, send the initialization clock */
1361         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1362                 cmdflags |= SDMMC_CMD_INIT;
1363
1364         if (data) {
1365                 dw_mci_submit_data(host, data);
1366                 wmb();
1367         }
1368
1369         dw_mci_start_command(host, cmd, cmdflags);
1370
1371         if (mrq->stop)
1372                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1373 }
1374
1375 static void dw_mci_start_request(struct dw_mci *host,
1376                                  struct dw_mci_slot *slot)
1377 {
1378         struct mmc_request *mrq = slot->mrq;
1379         struct mmc_command *cmd;
1380
1381         MMC_DBG_INFO_FUNC(host->mmc, " Begin to start the new request. cmd=%d(arg=0x%x)[%s]", \
1382                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1383
1384         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1385         __dw_mci_start_request(host, slot, cmd);
1386 }
1387
1388 /* must be called with host->lock held */
1389 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1390                                  struct mmc_request *mrq)
1391 {
1392         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1393                  host->state);
1394
1395         slot->mrq = mrq;
1396
1397         if (host->state == STATE_IDLE) {
1398                 host->state = STATE_SENDING_CMD;
1399                 dw_mci_start_request(host, slot);
1400         } else {
1401                 list_add_tail(&slot->queue_node, &host->queue);
1402         }
1403 }
1404
1405 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1406 {
1407         struct dw_mci_slot *slot = mmc_priv(mmc);
1408         struct dw_mci *host = slot->host;
1409
1410         WARN_ON(slot->mrq);
1411
1412         /*
1413          * The check for card presence and queueing of the request must be
1414          * atomic, otherwise the card could be removed in between and the
1415          * request wouldn't fail until another card was inserted.
1416          */
1417         spin_lock_bh(&host->lock);
1418
1419         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1420                 spin_unlock_bh(&host->lock);
1421                 mrq->cmd->error = -ENOMEDIUM;
1422                 MMC_DBG_CMD_FUNC(host->mmc, "%d..%s: no card,so reqeuest done, cmd=%d [%s]",\
1423                     __LINE__, __FUNCTION__, mrq->cmd->opcode, mmc_hostname(host->mmc));
1424
1425                 mmc_request_done(mmc, mrq);
1426                 return;
1427         }
1428
1429         MMC_DBG_CMD_FUNC(host->mmc, "======>\n    pull a new request from MMC-frame to dw_mci_queue. cmd=%d(arg=0x%x)[%s]", \
1430                                 mrq->cmd->opcode, mrq->cmd->arg, mmc_hostname(host->mmc));
1431
1432         dw_mci_queue_request(host, slot, mrq);
1433
1434         spin_unlock_bh(&host->lock);
1435 }
1436
1437 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1438 {
1439         struct dw_mci_slot *slot = mmc_priv(mmc);
1440         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1441         struct dw_mci *host = slot->host;
1442         #endif
1443         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1444         u32 regs;
1445
1446         #ifdef SDMMC_WAIT_FOR_UNBUSY
1447         unsigned long   time_loop;
1448         bool ret = true;
1449
1450         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1451         if(host->svi_flags == 1)
1452                 time_loop = jiffies + msecs_to_jiffies(SDMMC_DATA_TIMEOUT_SD);
1453         else
1454                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1455         #else
1456                 time_loop = jiffies + msecs_to_jiffies(SDMMC_WAIT_FOR_UNBUSY);
1457         #endif
1458
1459         if(!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)){
1460                 printk("%d..%s:  no card. [%s]\n", \
1461                         __LINE__, __FUNCTION__, mmc_hostname(mmc));
1462                 goto EXIT_POWER;
1463         }
1464
1465         while (ret) {
1466                 ret = time_before(jiffies, time_loop);
1467                 regs = mci_readl(slot->host, STATUS);
1468                 if (!(regs & (SDMMC_STAUTS_DATA_BUSY|SDMMC_STAUTS_MC_BUSY)))
1469                         break;
1470         };
1471
1472         if(false == ret)
1473         {
1474                 printk("slot->flags = %lu ", slot->flags);
1475                 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1476                 if(host->svi_flags != 1)
1477                 #endif
1478                         dump_stack();
1479                 printk("%d..%s:  wait for unbusy timeout....... STATUS = 0x%x [%s]\n", \
1480                         __LINE__, __FUNCTION__, regs, mmc_hostname(mmc));
1481         }
1482         #endif
1483
1484         switch (ios->bus_width) {
1485         case MMC_BUS_WIDTH_4:
1486                 slot->ctype = SDMMC_CTYPE_4BIT;
1487                 break;
1488         case MMC_BUS_WIDTH_8:
1489                 slot->ctype = SDMMC_CTYPE_8BIT;
1490                 break;
1491         default:
1492                 /* set default 1 bit mode */
1493                 slot->ctype = SDMMC_CTYPE_1BIT;
1494                 slot->pre_ctype = SDMMC_CTYPE_1BIT;
1495         }
1496
1497         regs = mci_readl(slot->host, UHS_REG);
1498
1499         /* DDR mode set */
1500         if (ios->timing == MMC_TIMING_UHS_DDR50)
1501                 regs |= ((0x1 << slot->id) << 16);
1502         else
1503                 regs &= ~((0x1 << slot->id) << 16);
1504
1505         mci_writel(slot->host, UHS_REG, regs);
1506         slot->host->timing = ios->timing;
1507
1508         /*
1509          * Use mirror of ios->clock to prevent race with mmc
1510          * core ios update when finding the minimum.
1511          */
1512         slot->clock = ios->clock;
1513
1514         if (drv_data && drv_data->set_ios)
1515                 drv_data->set_ios(slot->host, ios);
1516
1517         /* Slot specific timing and width adjustment */
1518         dw_mci_setup_bus(slot, false);
1519                 //return -EAGAIN;
1520
1521 EXIT_POWER:
1522         switch (ios->power_mode) {
1523                 case MMC_POWER_UP:
1524                         set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1525                         /* Power up slot */
1526                         if (slot->host->pdata->setpower)
1527                                 slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
1528                         regs = mci_readl(slot->host, PWREN);
1529                         regs |= (1 << slot->id);
1530                         mci_writel(slot->host, PWREN, regs);
1531                         break;
1532                 case MMC_POWER_OFF:
1533                         /* Power down slot */
1534                         if(slot->host->pdata->setpower)
1535                                 slot->host->pdata->setpower(slot->id, 0);
1536                         regs = mci_readl(slot->host, PWREN);
1537                         regs &= ~(1 << slot->id);
1538                         mci_writel(slot->host, PWREN, regs);
1539                         break;
1540                 default:
1541                         break;
1542         }
1543 }
1544
1545 static int dw_mci_get_ro(struct mmc_host *mmc)
1546 {
1547         int read_only;
1548         struct dw_mci_slot *slot = mmc_priv(mmc);
1549         struct dw_mci_board *brd = slot->host->pdata;
1550
1551         /* Use platform get_ro function, else try on board write protect */
1552         if(slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
1553                 read_only = 0;
1554         else if(brd->get_ro)
1555                 read_only = brd->get_ro(slot->id);
1556         else if(gpio_is_valid(slot->wp_gpio))
1557                 read_only = gpio_get_value(slot->wp_gpio);
1558         else
1559                 read_only =
1560                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1561
1562         dev_dbg(&mmc->class_dev, "card is %s\n",
1563                 read_only ? "read-only" : "read-write");
1564
1565         return read_only;
1566 }
1567
1568 static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
1569 {
1570         struct dw_mci_slot *slot = mmc_priv(mmc);
1571         struct dw_mci *host = slot->host;
1572         /*struct dw_mci_board *brd = slot->host->pdata;*/
1573
1574         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
1575                 return 0;
1576
1577         spin_lock_bh(&host->lock);
1578
1579         if(val)
1580                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1581         else
1582                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1583
1584         spin_unlock_bh(&host->lock);
1585
1586         if (test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1587                 if (__clk_is_enabled(host->hclk_mmc) == false)
1588                         clk_prepare_enable(host->hclk_mmc);
1589                 if (__clk_is_enabled(host->clk_mmc) == false)
1590                         clk_prepare_enable(host->clk_mmc);
1591         } else {
1592                 if (__clk_is_enabled(host->clk_mmc) == true)
1593                         clk_disable_unprepare(slot->host->clk_mmc);
1594                 if (__clk_is_enabled(host->hclk_mmc) == true)
1595                         clk_disable_unprepare(slot->host->hclk_mmc);
1596         }
1597
1598         mmc_detect_change(slot->mmc, 20);
1599         return 0;
1600 }
1601
1602
1603
1604 static int dw_mci_get_cd(struct mmc_host *mmc)
1605 {
1606         int present;
1607         struct dw_mci_slot *slot = mmc_priv(mmc);
1608         struct dw_mci_board *brd = slot->host->pdata;
1609         struct dw_mci *host = slot->host;
1610         int gpio_cd = mmc_gpio_get_cd(mmc);
1611         int force_jtag_bit, force_jtag_reg;
1612         int gpio_val;
1613         int irq;
1614
1615         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
1616                 (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
1617                 gpio_cd = slot->cd_gpio;
1618                 irq = gpio_to_irq(gpio_cd);
1619                 if (gpio_is_valid(gpio_cd)) {
1620                         gpio_val = gpio_get_value(gpio_cd);
1621                         if (soc_is_rk3036()) {
1622                                 force_jtag_bit = 11;
1623                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1624                         } else if (soc_is_rk3126() || soc_is_rk3126b()) {
1625                                 force_jtag_reg = RK312X_GRF_SOC_CON0;
1626                                 force_jtag_bit = 8;
1627                         }
1628                         msleep(10);
1629                         if (gpio_val == gpio_get_value(gpio_cd)) {
1630                                 gpio_cd = (gpio_val == 0 ? 1 : 0);
1631                                 if (gpio_cd == 0) {
1632                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
1633                                         /* Enable force_jtag wihtout card in slot, ONLY for NCD-package */
1634                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (1 << force_jtag_bit),
1635                                                         force_jtag_reg);
1636
1637                                         dw_mci_ctrl_all_reset(host);
1638                                 } else {
1639                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
1640                                         /* Really card detected: SHOULD disable force_jtag */
1641                                         grf_writel((0x1 << (force_jtag_bit + 16)) | (0 << force_jtag_bit),
1642                                                         force_jtag_reg);
1643                                 }
1644                         } else {
1645                                 /* Jitter */
1646                                 gpio_val = gpio_get_value(gpio_cd);
1647                                 (gpio_val == 0) ?
1648                                         irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
1649                                         irq_set_irq_type(irq, IRQF_TRIGGER_LOW  | IRQF_ONESHOT);
1650                                 return slot->last_detect_state;
1651                         }
1652                 } else {
1653                         dev_err(host->dev, "dw_mci_get_cd: invalid gpio_cd!\n");
1654                 }
1655         }
1656
1657         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
1658                 return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1659
1660         /* Use platform get_cd function, else try onboard card detect */
1661         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1662                 present = 1;
1663         else if (brd->get_cd)
1664                 present = !brd->get_cd(slot->id);
1665         else if (!IS_ERR_VALUE(gpio_cd))
1666                 present = gpio_cd;
1667         else
1668                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1669                         == 0 ? 1 : 0;
1670
1671         spin_lock_bh(&host->lock);
1672         if (present) {
1673                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1674                 dev_dbg(&mmc->class_dev, "card is present\n");
1675         } else {
1676                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1677                 dev_dbg(&mmc->class_dev, "card is not present\n");
1678         }
1679         spin_unlock_bh(&host->lock);
1680
1681         return present;
1682 }
1683
1684
1685 /*
1686  * Dts Should caps emmc controller with poll-hw-reset
1687  */
1688 static void dw_mci_hw_reset(struct mmc_host *mmc)
1689 {
1690         struct dw_mci_slot *slot = mmc_priv(mmc);
1691         struct dw_mci *host = slot->host;
1692         u32 regs;
1693
1694         #if 0
1695         u32 cmd_flags;
1696         unsigned long timeout;
1697         bool ret = true;
1698
1699         /* (1) CMD12 to end any transfer in process */
1700         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
1701                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
1702
1703         if(host->mmc->hold_reg_flag)
1704                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
1705         mci_writel(host, CMDARG, 0);
1706         wmb();
1707         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
1708         wmb();
1709         timeout = jiffies + msecs_to_jiffies(500);
1710         while(ret){
1711                 ret = time_before(jiffies, timeout);
1712                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
1713                         break;
1714         }
1715
1716         if(false == ret)
1717                 MMC_DBG_ERR_FUNC(host->mmc,
1718                         "%s dw_mci_hw_reset: STOP_TRANSMISSION failed!!! [%s]\n",
1719                         __func__, mmc_hostname(host->mmc));
1720
1721         /* (2) wait DTO, even if no response is sent back by card */
1722         ret = true;
1723         timeout = jiffies + msecs_to_jiffies(5);
1724         while(ret){
1725                 ret = time_before(jiffies, timeout);
1726                 if(!(mci_readl(host, MINTSTS) & SDMMC_INT_DATA_OVER)){
1727                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1728                         break;
1729                 }
1730         }
1731         #endif
1732
1733         /* (3) Reset following: DONNOT CHANGE RESET ORDER!*/
1734
1735         /* Software reset - BMOD[0] for IDMA only */
1736         regs = mci_readl(host, BMOD);
1737         regs |= SDMMC_IDMAC_SWRESET;
1738         mci_writel(host, BMOD, regs);
1739         udelay(1); /* Auto cleared after 1 cycle, 1us is enough for hclk_mmc */
1740         regs = mci_readl(host, BMOD);
1741         if(regs & SDMMC_IDMAC_SWRESET)
1742                 MMC_DBG_WARN_FUNC(host->mmc,
1743                         "%s dw_mci_hw_reset: SDMMC_IDMAC_SWRESET failed!!! [%s]\n",
1744                         __func__, mmc_hostname(host->mmc));
1745
1746         /* DMA reset - CTRL[2] */
1747         regs = mci_readl(host, CTRL);
1748         regs |= SDMMC_CTRL_DMA_RESET;
1749         mci_writel(host, CTRL, regs);
1750         udelay(1); /* Auto cleared after 2 AHB clocks, 1us is enough plus mci_readl access */
1751         regs = mci_readl(host, CTRL);
1752         if(regs & SDMMC_CTRL_DMA_RESET)
1753                 MMC_DBG_WARN_FUNC(host->mmc,
1754                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1755                         __func__, mmc_hostname(host->mmc));
1756
1757         /* FIFO reset - CTRL[1] */
1758         regs = mci_readl(host, CTRL);
1759         regs |= SDMMC_CTRL_FIFO_RESET;
1760         mci_writel(host, CTRL, regs);
1761         mdelay(1); /* no timing limited, 1ms is random value */
1762         regs = mci_readl(host, CTRL);
1763         if(regs & SDMMC_CTRL_FIFO_RESET)
1764                 MMC_DBG_WARN_FUNC(host->mmc,
1765                         "%s dw_mci_hw_reset: SDMMC_CTRL_DMA_RESET failed!!! [%s]\n",
1766                         __func__, mmc_hostname(host->mmc));
1767
1768         /* (4) CARD_RESET
1769         According to eMMC spec
1770         tRstW >= 1us ;   RST_n pulse width
1771         tRSCA >= 200us ; RST_n to Command time
1772         tRSTH >= 1us ;   RST_n high period
1773         */
1774         mci_writel(slot->host, PWREN, 0x0);
1775         mci_writel(slot->host, RST_N, 0x0);
1776         dsb(sy);
1777         udelay(10); /* 10us for bad quality eMMc. */
1778
1779         mci_writel(slot->host, PWREN, 0x1);
1780         mci_writel(slot->host, RST_N, 0x1);
1781         dsb(sy);
1782         usleep_range(500, 1000); /* at least 500(> 200us) */
1783 }
1784
1785 /*
1786  * Disable lower power mode.
1787  *
1788  * Low power mode will stop the card clock when idle.  According to the
1789  * description of the CLKENA register we should disable low power mode
1790  * for SDIO cards if we need SDIO interrupts to work.
1791  *
1792  * This function is fast if low power mode is already disabled.
1793  */
1794 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1795 {
1796         struct dw_mci *host = slot->host;
1797         u32 clk_en_a;
1798         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1799
1800         clk_en_a = mci_readl(host, CLKENA);
1801
1802         if (clk_en_a & clken_low_pwr) {
1803                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1804                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1805                              SDMMC_CMD_PRV_DAT_WAIT, 0);
1806         }
1807 }
1808
1809 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1810 {
1811         struct dw_mci_slot *slot = mmc_priv(mmc);
1812         struct dw_mci *host = slot->host;
1813         unsigned long flags;
1814         u32 int_mask;
1815         u32 sdio_int;
1816
1817         spin_lock_irqsave(&host->slock, flags);
1818
1819         /* Enable/disable Slot Specific SDIO interrupt */
1820         int_mask = mci_readl(host, INTMASK);
1821
1822         if (host->verid < DW_MMC_240A)
1823                 sdio_int = SDMMC_INT_SDIO(slot->id);
1824         else
1825                 sdio_int = SDMMC_INT_SDIO((slot->id) + 8);
1826
1827         if (enb) {
1828                 /*
1829                  * Turn off low power mode if it was enabled.  This is a bit of
1830                  * a heavy operation and we disable / enable IRQs a lot, so
1831                  * we'll leave low power mode disabled and it will get
1832                  * re-enabled again in dw_mci_setup_bus().
1833                  */
1834                 dw_mci_disable_low_power(slot);
1835
1836                 mci_writel(host, INTMASK,
1837                            (int_mask | sdio_int));
1838         } else {
1839                 mci_writel(host, INTMASK,
1840                            (int_mask & ~sdio_int));
1841         }
1842
1843         spin_unlock_irqrestore(&host->slock, flags);
1844 }
1845
1846 #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
1847 enum{
1848         IO_DOMAIN_12 = 1200,
1849         IO_DOMAIN_18 = 1800,
1850         IO_DOMAIN_33 = 3300,
1851 };
1852 static void dw_mci_do_grf_io_domain_switch(struct dw_mci *host, u32 voltage)
1853 {
1854         switch(voltage){
1855                 case IO_DOMAIN_33:
1856                         voltage = 0;
1857                         break;
1858                 case IO_DOMAIN_18:
1859                         voltage = 1;
1860                         break;
1861                 case IO_DOMAIN_12:
1862                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Not support io domain voltage [%s]\n",
1863                                                         __FUNCTION__, mmc_hostname(host->mmc));
1864                         break;
1865                 default:
1866                         MMC_DBG_ERR_FUNC(host->mmc,"%s : Err io domain voltage [%s]\n",
1867                                                         __FUNCTION__, mmc_hostname(host->mmc));
1868                         break;
1869         }
1870
1871         if (cpu_is_rk3288()) {
1872                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1873                         grf_writel((voltage << 7) | (1 << 23), RK3288_GRF_IO_VSEL);
1874                 else
1875                         return ;
1876         } else if (host->cid == DW_MCI_TYPE_RK3368) {
1877                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
1878                          regmap_write(host->grf, 0x900, (voltage << 6) | (1 << 22));
1879                 else
1880                         return;
1881         } else {
1882                 MMC_DBG_ERR_FUNC(host->mmc,"%s : unknown chip [%s]\n",
1883                                         __FUNCTION__, mmc_hostname(host->mmc));
1884         }
1885 }
1886
1887 static int dw_mci_do_start_signal_voltage_switch(struct dw_mci *host,
1888                                                 struct mmc_ios *ios)
1889 {
1890         int ret;
1891         unsigned int value,uhs_reg;
1892
1893         /*
1894          * Signal Voltage Switching is only applicable for Host Controllers
1895          * v3.00 and above.
1896          */
1897         if (host->verid < DW_MMC_240A)
1898                 return 0;
1899
1900         uhs_reg = mci_readl(host, UHS_REG);
1901         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: vol=%d.[%s]\n",
1902                 __LINE__, __FUNCTION__,ios->signal_voltage, mmc_hostname(host->mmc));
1903
1904         switch (ios->signal_voltage) {
1905         case MMC_SIGNAL_VOLTAGE_330:
1906                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1907                 if (host->vmmc) {
1908                         if (cpu_is_rk3288())
1909                                 ret = io_domain_regulator_set_voltage(
1910                                                 host->vmmc, 3300000, 3300000);
1911                         else
1912                                 ret = regulator_set_voltage(host->vmmc, 3300000, 3300000);
1913
1914                         /* regulator_put(host->vmmc); //to be done in remove function. */
1915
1916                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%s   =%dmV  set 3.3end, ret=%d  \n",
1917                             __func__, regulator_get_voltage(host->vmmc), ret);
1918                         if (ret) {
1919                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 3.3V signalling voltage "
1920                                                 " failed\n", mmc_hostname(host->mmc));
1921                                 return -EIO;
1922                         }
1923                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_33);
1924                 }
1925                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: [%s]\n",__LINE__,
1926                                         __FUNCTION__, mmc_hostname(host->mmc));
1927
1928                 /* set High-power mode */
1929                 value = mci_readl(host, CLKENA);
1930                 value &= ~SDMMC_CLKEN_LOW_PWR;
1931                 mci_writel(host,CLKENA , value);
1932                 /* SDMMC_UHS_REG */
1933                 uhs_reg &= ~SDMMC_UHS_VOLT_REG_18;
1934                 mci_writel(host,UHS_REG , uhs_reg);
1935
1936                 /* Wait for 5ms */
1937                 usleep_range(5000, 5500);
1938
1939                 /* 3.3V regulator output should be stable within 5 ms */
1940                 uhs_reg = mci_readl(host, UHS_REG);
1941                 if( !(uhs_reg & SDMMC_UHS_VOLT_REG_18))
1942                         return 0;
1943
1944                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 3.3V regulator output did not became stable\n",
1945                                 mmc_hostname(host->mmc));
1946
1947                 return -EAGAIN;
1948         case MMC_SIGNAL_VOLTAGE_180:
1949                 if (host->vmmc) {
1950                         if (cpu_is_rk3288())
1951                                 ret = io_domain_regulator_set_voltage(
1952                                                         host->vmmc,
1953                                                         1800000, 1800000);
1954                         else
1955                                 ret = regulator_set_voltage(
1956                                                         host->vmmc,
1957                                                         1800000, 1800000);
1958                         /* regulator_put(host->vmmc);//to be done in remove function. */
1959
1960                         MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s   =%dmV  set 1.8end, ret=%d . \n",
1961                             __LINE__, __func__, regulator_get_voltage(host->vmmc), ret);
1962                         if (ret) {
1963                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.8V signalling voltage "
1964                                                 " failed\n", mmc_hostname(host->mmc));
1965                                 return -EIO;
1966                         }
1967                         dw_mci_do_grf_io_domain_switch(host, IO_DOMAIN_18);
1968                 }
1969
1970                 /*
1971                  * Enable 1.8V Signal Enable in the Host Control2
1972                  * register
1973                  */
1974                 mci_writel(host,UHS_REG , uhs_reg | SDMMC_UHS_VOLT_REG_18);
1975
1976                 /* Wait for 5ms */
1977                 usleep_range(5000, 5500);
1978                 MMC_DBG_SW_VOL_FUNC(host->mmc,"%d..%s: .[%s]\n",__LINE__,
1979                                         __FUNCTION__,mmc_hostname(host->mmc));
1980
1981                 /* 1.8V regulator output should be stable within 5 ms */
1982                 uhs_reg = mci_readl(host, UHS_REG);
1983                 if(uhs_reg & SDMMC_UHS_VOLT_REG_18)
1984                         return 0;
1985
1986                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: 1.8V regulator output did not became stable\n",
1987                                 mmc_hostname(host->mmc));
1988
1989                 return -EAGAIN;
1990         case MMC_SIGNAL_VOLTAGE_120:
1991                 if (host->vmmc) {
1992                         if (cpu_is_rk3288())
1993                                 ret = io_domain_regulator_set_voltage(
1994                                                         host->vmmc,
1995                                                         1200000, 1200000);
1996                         else
1997                                 ret = regulator_set_voltage(host->vmmc,
1998                                                         1200000, 1200000);
1999                         if (ret) {
2000                                 MMC_DBG_SW_VOL_FUNC(host->mmc, "%s: Switching to 1.2V signalling voltage "
2001                                                 " failed\n", mmc_hostname(host->mmc));
2002                                 return -EIO;
2003                         }
2004                 }
2005                 return 0;
2006         default:
2007                 /* No signal voltage switch required */
2008                 return 0;
2009         }
2010 }
2011
2012
2013 static int dw_mci_start_signal_voltage_switch(struct mmc_host *mmc,
2014         struct mmc_ios *ios)
2015 {
2016         struct dw_mci_slot *slot = mmc_priv(mmc);
2017         struct dw_mci *host = slot->host;
2018         int err;
2019
2020         if (host->verid < DW_MMC_240A)
2021                 return 0;
2022
2023         err = dw_mci_do_start_signal_voltage_switch(host, ios);
2024         return err;
2025 }
2026
2027 #endif
2028
2029 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
2030 {
2031         struct dw_mci_slot *slot = mmc_priv(mmc);
2032         struct dw_mci *host = slot->host;
2033         const struct dw_mci_drv_data *drv_data = host->drv_data;
2034         struct dw_mci_tuning_data tuning_data;
2035         int err = -ENOSYS;
2036
2037         /* Fixme: 3036/3126 doesn't support 1.8 io domain, no sense exe tuning */
2038         if(cpu_is_rk3036() || cpu_is_rk312x())
2039                 return err;
2040
2041         if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2042                 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
2043                         tuning_data.blk_pattern = tuning_blk_pattern_8bit;
2044                         tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
2045                 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
2046                         tuning_data.blk_pattern = tuning_blk_pattern_4bit;
2047                         tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
2048                 } else {
2049                         return -EINVAL;
2050                 }
2051         } else if (opcode == MMC_SEND_TUNING_BLOCK) {
2052                 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
2053                 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
2054         } else {
2055                 dev_err(host->dev,
2056                         "Undefined command(%d) for tuning\n", opcode);
2057                 return -EINVAL;
2058         }
2059
2060
2061         /* Recommend sample phase and delayline
2062            Fixme: Mix-use these three controllers will cause
2063            con_id mismatch.
2064          */
2065         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
2066             tuning_data.con_id = 3;
2067         else if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2068             tuning_data.con_id = 1;
2069         else
2070             tuning_data.con_id = 0;
2071
2072         /* 0: driver, from host->devices
2073            1: sample, from devices->host
2074          */
2075         tuning_data.tuning_type = 1;
2076
2077         if (drv_data && drv_data->execute_tuning)
2078                 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
2079
2080         return err;
2081 }
2082
2083 static void dw_mci_post_tmo(struct mmc_host *mmc)
2084 {
2085         struct dw_mci_slot *slot = mmc_priv(mmc);
2086         struct dw_mci *host = slot->host;
2087         struct mmc_data *data;
2088         u32 ret, i, regs, cmd_flags;
2089         u32 sdio_int;
2090         unsigned long timeout = 0;
2091         bool ret_timeout = true;
2092
2093         host->cur_slot->mrq = NULL;
2094         host->mrq = NULL;
2095         host->state = STATE_IDLE;
2096
2097         data = host->data;
2098
2099         printk("[%s] -- Timeout recovery procedure start --\n",
2100                 mmc_hostname(host->mmc));
2101
2102         if (data && (data->stop)) {
2103                 send_stop_cmd(host, data);
2104         } else {
2105                 mci_writel(host, CMDARG, 0);
2106                 wmb();
2107                 cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC |
2108                         SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2109
2110                 if (host->mmc->hold_reg_flag)
2111                         cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2112
2113                 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2114                 wmb();
2115                 timeout = jiffies + msecs_to_jiffies(500);
2116
2117                 while(ret_timeout) {
2118                         ret_timeout = time_before(jiffies, timeout);
2119                         if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2120                                 break;
2121                 }
2122
2123                 if (false == ret_timeout)
2124                         MMC_DBG_ERR_FUNC(host->mmc, "stop recovery failed![%s]",
2125                                         mmc_hostname(host->mmc));
2126         }
2127
2128         if (!dw_mci_ctrl_all_reset(host)) {
2129                 ret = -ENODEV;
2130                 return ;
2131         }
2132
2133 #ifdef CONFIG_MMC_DW_IDMAC
2134         if (host->use_dma && host->dma_ops->init)
2135                 host->dma_ops->init(host);
2136 #endif
2137
2138         /*
2139         * Restore the initial value at FIFOTH register
2140         * And Invalidate the prev_blksz with zero
2141         */
2142         mci_writel(host, FIFOTH, host->fifoth_val);
2143         host->prev_blksz = 0;
2144         mci_writel(host, TMOUT, 0xFFFFFFFF);
2145         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2146         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR
2147                         | SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
2148         if (!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
2149                 regs |= SDMMC_INT_CD;
2150
2151         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)) {
2152                 if (host->verid < DW_MMC_240A)
2153                         sdio_int = SDMMC_INT_SDIO(0);
2154                 else
2155                         sdio_int = SDMMC_INT_SDIO(8);
2156
2157                 if (mci_readl(host, INTMASK) & sdio_int)
2158                         regs |= sdio_int;
2159         }
2160
2161         mci_writel(host, INTMASK, regs);
2162         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2163         for (i = 0; i < host->num_slots; i++) {
2164                 struct dw_mci_slot *slot = host->slot[i];
2165                 if (!slot)
2166                         continue;
2167                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2168                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2169                         dw_mci_setup_bus(slot, true);
2170                 }
2171         }
2172         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2173
2174         printk("[%s] -- Timeout recovery procedure finished --\n",
2175                 mmc_hostname(host->mmc));
2176
2177 }
2178
2179 static const struct mmc_host_ops dw_mci_ops = {
2180         .request                = dw_mci_request,
2181         .pre_req                = dw_mci_pre_req,
2182         .post_req               = dw_mci_post_req,
2183         .set_ios                = dw_mci_set_ios,
2184         .get_ro                 = dw_mci_get_ro,
2185         .get_cd                 = dw_mci_get_cd,
2186         .set_sdio_status    = dw_mci_set_sdio_status,
2187         .hw_reset       = dw_mci_hw_reset,
2188         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
2189         .execute_tuning         = dw_mci_execute_tuning,
2190         .post_tmo               = dw_mci_post_tmo,
2191         #ifdef CONFIG_MMC_DW_ROCKCHIP_SWITCH_VOLTAGE
2192         .start_signal_voltage_switch    = dw_mci_start_signal_voltage_switch,
2193         .card_busy  = dw_mci_card_busy,
2194         #endif
2195 };
2196
2197 #if 0
2198 static void dw_mci_enable_irq(struct dw_mci *host, bool irqflag)
2199 {
2200         unsigned long flags;
2201
2202     if(!host)
2203         return;
2204
2205         local_irq_save(flags);
2206         if(host->irq_state != irqflag)
2207         {
2208             host->irq_state = irqflag;
2209             if(irqflag)
2210             {
2211                 enable_irq(host->irq);
2212             }
2213             else
2214             {
2215                 disable_irq(host->irq);
2216             }
2217         }
2218         local_irq_restore(flags);
2219 }
2220 #endif
2221
2222 static void dw_mci_deal_data_end(struct dw_mci *host, struct mmc_request *mrq)
2223         __releases(&host->lock)
2224         __acquires(&host->lock)
2225 {
2226         if(DW_MCI_SEND_STATUS == host->dir_status){
2227             #if 0
2228             if( MMC_BUS_TEST_W != host->cmd->opcode){
2229                 if(host->data_status & SDMMC_INT_DCRC)
2230                     host->data->error = -EILSEQ;
2231                 else if(host->data_status & SDMMC_INT_EBE)
2232                     host->data->error = -ETIMEDOUT;
2233             } else {
2234                 dw_mci_wait_unbusy(host);
2235             }
2236             #else
2237             dw_mci_wait_unbusy(host);
2238             #endif
2239         }
2240 }
2241
2242 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
2243         __releases(&host->lock)
2244         __acquires(&host->lock)
2245 {
2246         struct dw_mci_slot *slot;
2247         struct mmc_host *prev_mmc = host->cur_slot->mmc;
2248
2249         //WARN_ON(host->cmd || host->data);
2250
2251         dw_mci_deal_data_end(host, mrq);
2252
2253         if(mrq->cmd)
2254                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, cmderr=%d, host->state=%d [%s]",\
2255                         mrq->cmd->opcode,mrq->cmd->error, host->state,mmc_hostname(host->mmc));
2256         if(mrq->data)
2257                 MMC_DBG_CMD_FUNC(host->mmc, " reqeust end--reqeuest done, cmd=%d, dataerr=%d, host->state=%d [%s]",\
2258                         mrq->cmd->opcode,mrq->data->error, host->state, mmc_hostname(host->mmc));
2259
2260         host->cur_slot->mrq = NULL;
2261         host->mrq = NULL;
2262         if (!list_empty(&host->queue)) {
2263                 slot = list_entry(host->queue.next,
2264                                   struct dw_mci_slot, queue_node);
2265                 list_del(&slot->queue_node);
2266                 dev_vdbg(host->dev, "list not empty: %s is next\n",
2267                          mmc_hostname(slot->mmc));
2268                 host->state = STATE_SENDING_CMD;
2269                 MMC_DBG_CMD_FUNC(host->mmc, " list is not empty. run the request in list. [%s]", mmc_hostname(host->mmc));
2270                 dw_mci_start_request(host, slot);
2271         } else {
2272                 dev_vdbg(host->dev, "list empty\n");
2273                 host->state = STATE_IDLE;
2274         }
2275
2276         spin_unlock(&host->lock);
2277         mmc_request_done(prev_mmc, mrq);
2278         spin_lock(&host->lock);
2279 }
2280
2281 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
2282 {
2283         u32 status = host->cmd_status;
2284
2285         host->cmd_status = 0;
2286
2287         /* Read the response from the card (up to 16 bytes) */
2288         if (cmd->flags & MMC_RSP_PRESENT) {
2289                 if (cmd->flags & MMC_RSP_136) {
2290                         cmd->resp[3] = mci_readl(host, RESP0);
2291                         cmd->resp[2] = mci_readl(host, RESP1);
2292                         cmd->resp[1] = mci_readl(host, RESP2);
2293                         cmd->resp[0] = mci_readl(host, RESP3);
2294
2295             MMC_DBG_INFO_FUNC(host->mmc,"Line%d: command complete cmd=%d,resp[3]=0x%x, resp[2]=0x%x,resp[1]=0x%x,resp[0]=0x%x.[%s]", \
2296                     __LINE__,cmd->opcode,cmd->resp[3], cmd->resp[2], cmd->resp[1], cmd->resp[0], mmc_hostname(host->mmc));
2297                 } else {
2298                         cmd->resp[0] = mci_readl(host, RESP0);
2299                         cmd->resp[1] = 0;
2300                         cmd->resp[2] = 0;
2301                         cmd->resp[3] = 0;
2302             MMC_DBG_INFO_FUNC(host->mmc, "Line%d: command complete cmd=%d,resp[0]=0x%x. [%s]",\
2303                     __LINE__,cmd->opcode, cmd->resp[0], mmc_hostname(host->mmc));
2304                 }
2305         }
2306
2307         if (status & SDMMC_INT_RTO)
2308         {
2309             if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
2310                 host->cmd_rto += 1;
2311
2312                 cmd->error = -ETIMEDOUT;
2313         }else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)){
2314                 cmd->error = -EILSEQ;
2315         }else if (status & SDMMC_INT_RESP_ERR){
2316                 cmd->error = -EIO;
2317         }else{
2318                 cmd->error = 0;
2319         }
2320         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",
2321                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2322
2323         if (cmd->error) {
2324             if(MMC_SEND_STATUS != cmd->opcode)
2325                 if(host->cmd_rto >= SDMMC_CMD_RTO_MAX_HOLD){
2326                         MMC_DBG_CMD_FUNC(host->mmc, " command complete, cmd=%d,cmdError=%d [%s]",\
2327                                 cmd->opcode, cmd->error,mmc_hostname(host->mmc));
2328                         host->cmd_rto = 0;
2329                 }
2330
2331                 /* newer ip versions need a delay between retries */
2332                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
2333                         mdelay(20);
2334         }
2335
2336 }
2337
2338 static void dw_mci_tasklet_func(unsigned long priv)
2339 {
2340         struct dw_mci *host = (struct dw_mci *)priv;
2341         struct dw_mci_slot *slot = mmc_priv(host->mmc);
2342         struct mmc_data *data;
2343         struct mmc_command *cmd;
2344         enum dw_mci_state state;
2345         enum dw_mci_state prev_state;
2346         u32 status, cmd_flags;
2347         unsigned long timeout = 0;
2348         bool ret = true;
2349
2350         spin_lock(&host->lock);
2351
2352         state = host->state;
2353         data = host->data;
2354
2355         do {
2356                 prev_state = state;
2357
2358                 switch (state) {
2359                 case STATE_IDLE:
2360                         break;
2361
2362                 case STATE_SENDING_CMD:
2363                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2364                                                 &host->pending_events))
2365                                 break;
2366
2367                         cmd = host->cmd;
2368                         host->cmd = NULL;
2369                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2370                         dw_mci_command_complete(host, cmd);
2371                         if (cmd == host->mrq->sbc && !cmd->error) {
2372                                 prev_state = state = STATE_SENDING_CMD;
2373                                 __dw_mci_start_request(host, host->cur_slot,
2374                                                        host->mrq->cmd);
2375                                 goto unlock;
2376                         }
2377
2378                         if (cmd->data && cmd->error) {
2379                                 dw_mci_stop_dma(host);
2380                                 #if 1
2381                                 if (data->stop) {
2382                                         send_stop_cmd(host, data);
2383                                         state = STATE_SENDING_STOP;
2384                                         break;
2385                                 }else{
2386                                        /*  host->data = NULL; */
2387                                 }
2388                                 #else
2389                                 send_stop_abort(host, data);
2390                                 state = STATE_SENDING_STOP;
2391                                 break;
2392                                 #endif
2393                                 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2394                         }
2395
2396                         if (!host->mrq->data || cmd->error) {
2397                                 dw_mci_request_end(host, host->mrq);
2398                                 goto unlock;
2399                         }
2400
2401                         prev_state = state = STATE_SENDING_DATA;
2402                         /* fall through */
2403
2404                 case STATE_SENDING_DATA:
2405                         if (test_and_clear_bit(EVENT_DATA_ERROR, &host->pending_events)) {
2406                                 dw_mci_stop_dma(host);
2407                                 #if 1
2408                                 if (data->stop){
2409                                         send_stop_cmd(host, data);
2410                                 }else{
2411                                         /*single block read/write, send stop cmd manually to prevent host controller halt*/
2412                                         MMC_DBG_INFO_FUNC(host->mmc, "%s status 1 0x%08x [%s]\n",
2413                                                         __func__, mci_readl(host, STATUS), mmc_hostname(host->mmc));
2414
2415                                         mci_writel(host, CMDARG, 0);
2416                                         wmb();
2417                                         cmd_flags = SDMMC_CMD_STOP | SDMMC_CMD_RESP_CRC
2418                                                         | SDMMC_CMD_RESP_EXP | MMC_STOP_TRANSMISSION;
2419
2420                                         if(host->mmc->hold_reg_flag)
2421                                                 cmd_flags |= SDMMC_CMD_USE_HOLD_REG;
2422
2423                                         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
2424                                         wmb();
2425                                         timeout = jiffies + msecs_to_jiffies(500);
2426
2427                                         while(ret){
2428                                                 ret = time_before(jiffies, timeout);
2429                                                 if(!(mci_readl(host, CMD) & SDMMC_CMD_START))
2430                                                         break;
2431                                         }
2432                                         if(false == ret)
2433                                                 MMC_DBG_ERR_FUNC(host->mmc,
2434                                                         "%s EVENT_DATA_ERROR recovery failed!!! [%s]\n",
2435                                                         __func__, mmc_hostname(host->mmc));
2436                                 }
2437                                 #else
2438                                 send_stop_abort(host, data);
2439                                 #endif
2440                                 state = STATE_DATA_ERROR;
2441                                 break;
2442                         }
2443
2444                         MMC_DBG_CMD_FUNC(host->mmc,
2445                                 "Pre-state[%d]-->NowState[%d]: STATE_SENDING_DATA, wait for EVENT_XFER_COMPLETE.[%s]",\
2446                         prev_state,state, mmc_hostname(host->mmc));
2447
2448                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2449                                                 &host->pending_events))
2450                                 break;
2451                         MMC_DBG_INFO_FUNC(host->mmc,
2452                                 "Pre-state[%d]-->NowState[%d]:  STATE_SENDING_DATA, wait for EVENT_DATA_COMPLETE. [%s]",\
2453                                           prev_state,state,mmc_hostname(host->mmc));
2454
2455                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2456                         prev_state = state = STATE_DATA_BUSY;
2457                         /* fall through */
2458
2459                 case STATE_DATA_BUSY:
2460                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2461                                                 &host->pending_events))
2462                                 break;
2463
2464                         dw_mci_deal_data_end(host, host->mrq);
2465                         MMC_DBG_INFO_FUNC(host->mmc,
2466                                 "Pre-state[%d]-->NowState[%d]: STATE_DATA_BUSY, after EVENT_DATA_COMPLETE. [%s]", \
2467                                           prev_state,state,mmc_hostname(host->mmc));
2468
2469                         /* host->data = NULL; */
2470                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2471                         status = host->data_status;
2472
2473                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
2474                             if((SDMMC_CTYPE_1BIT != slot->ctype)&&(MMC_SEND_EXT_CSD == host->mrq->cmd->opcode))
2475                                 MMC_DBG_ERR_FUNC(host->mmc,
2476                                         "Pre-state[%d]-->NowState[%d]: DW_MCI_DATA_ERROR_FLAGS,datastatus=0x%x [%s]",\
2477                             prev_state,state, status, mmc_hostname(host->mmc));
2478
2479                         if (status & SDMMC_INT_DRTO) {
2480                                         data->error = -ETIMEDOUT;
2481                                 } else if (status & SDMMC_INT_DCRC) {
2482                                         data->error = -EILSEQ;
2483                                 } else if (status & SDMMC_INT_EBE &&
2484                                 host->dir_status == DW_MCI_SEND_STATUS){
2485                                         /*
2486                                          * No data CRC status was returned.
2487                                          * The number of bytes transferred will
2488                                          * be exaggerated in PIO mode.
2489                                          */
2490                                         data->bytes_xfered = 0;
2491                                         data->error = -ETIMEDOUT;
2492                                 } else {
2493                                         dev_err(host->dev,
2494                                                 "data FIFO error "
2495                                                 "(status=%08x)\n",
2496                                                 status);
2497                                         data->error = -EIO;
2498                                 }
2499                                 /*
2500                                  * After an error, there may be data lingering
2501                                  * in the FIFO, so reset it - doing so
2502                                  * generates a block interrupt, hence setting
2503                                  * the scatter-gather pointer to NULL.
2504                                  */
2505                                 dw_mci_fifo_reset(host);
2506                         } else {
2507                                 data->bytes_xfered = data->blocks * data->blksz;
2508                                 data->error = 0;
2509                         }
2510
2511                         if (!data->stop) {
2512                                 MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: no stop and no dataerr, exit. [%s]", \
2513                                       prev_state,state,mmc_hostname(host->mmc));
2514                                 dw_mci_request_end(host, host->mrq);
2515                                 goto unlock;
2516                         }
2517                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to stop . [%s]", \
2518                                                 prev_state,state,mmc_hostname(host->mmc));
2519
2520                         if (host->mrq->sbc && !data->error) {
2521                                 data->stop->error = 0;
2522
2523                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: have stop and sbc, exit. [%s]", \
2524                                                 prev_state,state,mmc_hostname(host->mmc));
2525
2526                                 dw_mci_request_end(host, host->mrq);
2527                                 goto unlock;
2528                         }
2529
2530                         prev_state = state = STATE_SENDING_STOP;
2531                         if (!data->error)
2532                             send_stop_cmd(host, data);
2533                         #if 0
2534                         if (data->stop && !data->error) {
2535                                 /* stop command for open-ended transfer*/
2536
2537                                 send_stop_abort(host, data);
2538                         }
2539                         #endif
2540                         /* fall through */
2541                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to STATE_SENDING_STOP . [%s]", \
2542                                                 prev_state,state,mmc_hostname(host->mmc));
2543
2544                 case STATE_SENDING_STOP:
2545                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE, &host->pending_events))
2546                                 break;
2547
2548                         MMC_DBG_CMD_FUNC(host->mmc, "Pre-state[%d]-->NowState[%d]: begin to send cmd12 . [%s]", \
2549                                                 prev_state, state, mmc_hostname(host->mmc));
2550
2551                         /* CMD error in data command */
2552                         if (host->mrq->cmd->error && host->mrq->data) {
2553                                 dw_mci_fifo_reset(host);
2554                         }
2555
2556                         /*host->cmd = NULL;
2557                         host->data = NULL; */
2558                         #if 1
2559                         dw_mci_command_complete(host, host->mrq->stop);
2560                         #else
2561                         if (host->mrq->stop)
2562                                 dw_mci_command_complete(host, host->mrq->stop);
2563                         else
2564                                 host->cmd_status = 0;
2565                         #endif
2566
2567                         dw_mci_request_end(host, host->mrq);
2568                         goto unlock;
2569
2570                 case STATE_DATA_ERROR:
2571                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2572                                                 &host->pending_events))
2573                                 break;
2574
2575                         state = STATE_DATA_BUSY;
2576                         break;
2577                 }
2578         } while (state != prev_state);
2579
2580         host->state = state;
2581 unlock:
2582         spin_unlock(&host->lock);
2583
2584 }
2585
2586 /* push final bytes to part_buf, only use during push */
2587 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2588 {
2589         memcpy((void *)&host->part_buf, buf, cnt);
2590         host->part_buf_count = cnt;
2591 }
2592
2593 /* append bytes to part_buf, only use during push */
2594 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2595 {
2596         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2597         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2598         host->part_buf_count += cnt;
2599         return cnt;
2600 }
2601
2602 /* pull first bytes from part_buf, only use during pull */
2603 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2604 {
2605         cnt = min(cnt, (int)host->part_buf_count);
2606         if (cnt) {
2607                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2608                        cnt);
2609                 host->part_buf_count -= cnt;
2610                 host->part_buf_start += cnt;
2611         }
2612         return cnt;
2613 }
2614
2615 /* pull final bytes from the part_buf, assuming it's just been filled */
2616 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2617 {
2618         memcpy(buf, &host->part_buf, cnt);
2619         host->part_buf_start = cnt;
2620         host->part_buf_count = (1 << host->data_shift) - cnt;
2621 }
2622
2623 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2624 {
2625         struct mmc_data *data = host->data;
2626         int init_cnt = cnt;
2627
2628         /* try and push anything in the part_buf */
2629         if (unlikely(host->part_buf_count)) {
2630                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2631                 buf += len;
2632                 cnt -= len;
2633                 if (host->part_buf_count == 2) {
2634                         mci_writew(host, DATA(host->data_offset),
2635                                         host->part_buf16);
2636                         host->part_buf_count = 0;
2637                 }
2638         }
2639 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2640         if (unlikely((unsigned long)buf & 0x1)) {
2641                 while (cnt >= 2) {
2642                         u16 aligned_buf[64];
2643                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2644                         int items = len >> 1;
2645                         int i;
2646                         /* memcpy from input buffer into aligned buffer */
2647                         memcpy(aligned_buf, buf, len);
2648                         buf += len;
2649                         cnt -= len;
2650                         /* push data from aligned buffer into fifo */
2651                         for (i = 0; i < items; ++i)
2652                                 mci_writew(host, DATA(host->data_offset),
2653                                                 aligned_buf[i]);
2654                 }
2655         } else
2656 #endif
2657         {
2658                 u16 *pdata = buf;
2659                 for (; cnt >= 2; cnt -= 2)
2660                         mci_writew(host, DATA(host->data_offset), *pdata++);
2661                 buf = pdata;
2662         }
2663         /* put anything remaining in the part_buf */
2664         if (cnt) {
2665                 dw_mci_set_part_bytes(host, buf, cnt);
2666                  /* Push data if we have reached the expected data length */
2667                 if ((data->bytes_xfered + init_cnt) ==
2668                     (data->blksz * data->blocks))
2669                         mci_writew(host, DATA(host->data_offset),
2670                                    host->part_buf16);
2671         }
2672 }
2673
2674 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2675 {
2676 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2677         if (unlikely((unsigned long)buf & 0x1)) {
2678                 while (cnt >= 2) {
2679                         /* pull data from fifo into aligned buffer */
2680                         u16 aligned_buf[64];
2681                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2682                         int items = len >> 1;
2683                         int i;
2684                         for (i = 0; i < items; ++i)
2685                                 aligned_buf[i] = mci_readw(host,
2686                                                 DATA(host->data_offset));
2687                         /* memcpy from aligned buffer into output buffer */
2688                         memcpy(buf, aligned_buf, len);
2689                         buf += len;
2690                         cnt -= len;
2691                 }
2692         } else
2693 #endif
2694         {
2695                 u16 *pdata = buf;
2696                 for (; cnt >= 2; cnt -= 2)
2697                         *pdata++ = mci_readw(host, DATA(host->data_offset));
2698                 buf = pdata;
2699         }
2700         if (cnt) {
2701                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
2702                 dw_mci_pull_final_bytes(host, buf, cnt);
2703         }
2704 }
2705
2706 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2707 {
2708         struct mmc_data *data = host->data;
2709         int init_cnt = cnt;
2710
2711         /* try and push anything in the part_buf */
2712         if (unlikely(host->part_buf_count)) {
2713                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2714                 buf += len;
2715                 cnt -= len;
2716                 if (host->part_buf_count == 4) {
2717                         mci_writel(host, DATA(host->data_offset),
2718                                         host->part_buf32);
2719                         host->part_buf_count = 0;
2720                 }
2721         }
2722 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2723         if (unlikely((unsigned long)buf & 0x3)) {
2724                 while (cnt >= 4) {
2725                         u32 aligned_buf[32];
2726                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2727                         int items = len >> 2;
2728                         int i;
2729                         /* memcpy from input buffer into aligned buffer */
2730                         memcpy(aligned_buf, buf, len);
2731                         buf += len;
2732                         cnt -= len;
2733                         /* push data from aligned buffer into fifo */
2734                         for (i = 0; i < items; ++i)
2735                                 mci_writel(host, DATA(host->data_offset),
2736                                                 aligned_buf[i]);
2737                 }
2738         } else
2739 #endif
2740         {
2741                 u32 *pdata = buf;
2742                 for (; cnt >= 4; cnt -= 4)
2743                         mci_writel(host, DATA(host->data_offset), *pdata++);
2744                 buf = pdata;
2745         }
2746         /* put anything remaining in the part_buf */
2747         if (cnt) {
2748                 dw_mci_set_part_bytes(host, buf, cnt);
2749                  /* Push data if we have reached the expected data length */
2750                 if ((data->bytes_xfered + init_cnt) ==
2751                     (data->blksz * data->blocks))
2752                         mci_writel(host, DATA(host->data_offset),
2753                                    host->part_buf32);
2754         }
2755 }
2756
2757 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2758 {
2759 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2760         if (unlikely((unsigned long)buf & 0x3)) {
2761                 while (cnt >= 4) {
2762                         /* pull data from fifo into aligned buffer */
2763                         u32 aligned_buf[32];
2764                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2765                         int items = len >> 2;
2766                         int i;
2767                         for (i = 0; i < items; ++i)
2768                                 aligned_buf[i] = mci_readl(host,
2769                                                 DATA(host->data_offset));
2770                         /* memcpy from aligned buffer into output buffer */
2771                         memcpy(buf, aligned_buf, len);
2772                         buf += len;
2773                         cnt -= len;
2774                 }
2775         } else
2776 #endif
2777         {
2778                 u32 *pdata = buf;
2779                 for (; cnt >= 4; cnt -= 4)
2780                         *pdata++ = mci_readl(host, DATA(host->data_offset));
2781                 buf = pdata;
2782         }
2783         if (cnt) {
2784                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
2785                 dw_mci_pull_final_bytes(host, buf, cnt);
2786         }
2787 }
2788
2789 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2790 {
2791         struct mmc_data *data = host->data;
2792         int init_cnt = cnt;
2793
2794         /* try and push anything in the part_buf */
2795         if (unlikely(host->part_buf_count)) {
2796                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2797                 buf += len;
2798                 cnt -= len;
2799
2800                 if (host->part_buf_count == 8) {
2801                         mci_writeq(host, DATA(host->data_offset),
2802                                         host->part_buf);
2803                         host->part_buf_count = 0;
2804                 }
2805         }
2806 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2807         if (unlikely((unsigned long)buf & 0x7)) {
2808                 while (cnt >= 8) {
2809                         u64 aligned_buf[16];
2810                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2811                         int items = len >> 3;
2812                         int i;
2813                         /* memcpy from input buffer into aligned buffer */
2814                         memcpy(aligned_buf, buf, len);
2815                         buf += len;
2816                         cnt -= len;
2817                         /* push data from aligned buffer into fifo */
2818                         for (i = 0; i < items; ++i)
2819                                 mci_writeq(host, DATA(host->data_offset),
2820                                                 aligned_buf[i]);
2821                 }
2822         } else
2823 #endif
2824         {
2825                 u64 *pdata = buf;
2826                 for (; cnt >= 8; cnt -= 8)
2827                         mci_writeq(host, DATA(host->data_offset), *pdata++);
2828                 buf = pdata;
2829         }
2830         /* put anything remaining in the part_buf */
2831         if (cnt) {
2832                 dw_mci_set_part_bytes(host, buf, cnt);
2833                 /* Push data if we have reached the expected data length */
2834                 if ((data->bytes_xfered + init_cnt) ==
2835                     (data->blksz * data->blocks))
2836                         mci_writeq(host, DATA(host->data_offset),
2837                                    host->part_buf);
2838         }
2839 }
2840
2841 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2842 {
2843 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2844         if (unlikely((unsigned long)buf & 0x7)) {
2845                 while (cnt >= 8) {
2846                         /* pull data from fifo into aligned buffer */
2847                         u64 aligned_buf[16];
2848                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2849                         int items = len >> 3;
2850                         int i;
2851                         for (i = 0; i < items; ++i)
2852                                 aligned_buf[i] = mci_readq(host,
2853                                                 DATA(host->data_offset));
2854                         /* memcpy from aligned buffer into output buffer */
2855                         memcpy(buf, aligned_buf, len);
2856                         buf += len;
2857                         cnt -= len;
2858                 }
2859         } else
2860 #endif
2861         {
2862                 u64 *pdata = buf;
2863                 for (; cnt >= 8; cnt -= 8)
2864                         *pdata++ = mci_readq(host, DATA(host->data_offset));
2865                 buf = pdata;
2866         }
2867         if (cnt) {
2868                 host->part_buf = mci_readq(host, DATA(host->data_offset));
2869                 dw_mci_pull_final_bytes(host, buf, cnt);
2870         }
2871 }
2872
2873 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2874 {
2875         int len;
2876
2877         /* get remaining partial bytes */
2878         len = dw_mci_pull_part_bytes(host, buf, cnt);
2879         if (unlikely(len == cnt))
2880                 return;
2881         buf += len;
2882         cnt -= len;
2883
2884         /* get the rest of the data */
2885         host->pull_data(host, buf, cnt);
2886 }
2887
2888 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2889 {
2890         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2891         void *buf;
2892         unsigned int offset;
2893         struct mmc_data *data = host->data;
2894         int shift = host->data_shift;
2895         u32 status;
2896         unsigned int len;
2897         unsigned int remain, fcnt;
2898
2899         if(!host->mmc->bus_refs){
2900                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2901                 goto host_put;
2902         }
2903         do {
2904                 if (!sg_miter_next(sg_miter))
2905                         goto done;
2906
2907                 host->sg = sg_miter->piter.sg;
2908                 buf = sg_miter->addr;
2909                 remain = sg_miter->length;
2910                 offset = 0;
2911
2912                 do {
2913                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2914                                         << shift) + host->part_buf_count;
2915                         len = min(remain, fcnt);
2916                         if (!len)
2917                                 break;
2918                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2919                         data->bytes_xfered += len;
2920                         offset += len;
2921                         remain -= len;
2922                 } while (remain);
2923
2924                 sg_miter->consumed = offset;
2925                 status = mci_readl(host, MINTSTS);
2926                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2927         /* if the RXDR is ready read again */
2928         } while ((status & SDMMC_INT_RXDR) ||
2929                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2930
2931         if (!remain) {
2932                 if (!sg_miter_next(sg_miter))
2933                         goto done;
2934                 sg_miter->consumed = 0;
2935         }
2936         sg_miter_stop(sg_miter);
2937         return;
2938
2939 done:
2940         sg_miter_stop(sg_miter);
2941 host_put:
2942         host->sg = NULL;
2943         smp_wmb();
2944         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2945 }
2946
2947 static void dw_mci_write_data_pio(struct dw_mci *host)
2948 {
2949         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2950         void *buf;
2951         unsigned int offset;
2952         struct mmc_data *data = host->data;
2953         int shift = host->data_shift;
2954         u32 status;
2955         unsigned int len;
2956         unsigned int fifo_depth = host->fifo_depth;
2957         unsigned int remain, fcnt;
2958
2959         if(!host->mmc->bus_refs){
2960                 printk("Note: %s host->mmc->bus_refs is 0!!!\n", __func__);
2961                 goto host_put;
2962         }
2963
2964         do {
2965                 if (!sg_miter_next(sg_miter))
2966                         goto done;
2967
2968                 host->sg = sg_miter->piter.sg;
2969                 buf = sg_miter->addr;
2970                 remain = sg_miter->length;
2971                 offset = 0;
2972
2973                 do {
2974                         fcnt = ((fifo_depth -
2975                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2976                                         << shift) - host->part_buf_count;
2977                         len = min(remain, fcnt);
2978                         if (!len)
2979                                 break;
2980                         host->push_data(host, (void *)(buf + offset), len);
2981                         data->bytes_xfered += len;
2982                         offset += len;
2983                         remain -= len;
2984                 } while (remain);
2985
2986                 sg_miter->consumed = offset;
2987                 status = mci_readl(host, MINTSTS);
2988                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2989         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2990
2991         if (!remain) {
2992                 if (!sg_miter_next(sg_miter))
2993                         goto done;
2994                 sg_miter->consumed = 0;
2995         }
2996         sg_miter_stop(sg_miter);
2997         return;
2998
2999 done:
3000         sg_miter_stop(sg_miter);
3001 host_put:
3002         host->sg = NULL;
3003         smp_wmb();
3004         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
3005 }
3006
3007 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
3008 {
3009         if (!host->cmd_status)
3010             host->cmd_status = status;
3011
3012         if (!host->cmd)
3013                 goto cmd_exit;
3014
3015 cmd_exit:
3016         smp_wmb();
3017         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3018         tasklet_schedule(&host->tasklet);
3019 }
3020
3021 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
3022 {
3023         struct dw_mci *host = dev_id;
3024         u32 pending, sdio_int;
3025         int i;
3026
3027         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3028
3029         /*
3030         * DTO fix - version 2.10a and below, and only if internal DMA
3031         * is configured.
3032         */
3033         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
3034                         if (!pending &&
3035                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
3036                                 pending |= SDMMC_INT_DATA_OVER;
3037         }
3038
3039         if (pending) {
3040                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
3041                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
3042                         host->cmd_status = pending;
3043                         smp_wmb();
3044                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s cmd_status INT=0x%x,[%s]",
3045                                           __LINE__, __FUNCTION__,host->cmd_status,mmc_hostname(host->mmc));
3046
3047                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3048                 }
3049
3050                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
3051                         /* if there is an error report DATA_ERROR */
3052                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
3053                         host->data_status = pending;
3054                         smp_wmb();
3055                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
3056
3057                         MMC_DBG_INFO_FUNC(host->mmc,"Line%d..%s data_status INT=0x%x,[%s]",
3058                                           __LINE__, __FUNCTION__,host->data_status,mmc_hostname(host->mmc));
3059                         tasklet_schedule(&host->tasklet);
3060                 }
3061
3062                 if (pending & SDMMC_INT_DATA_OVER) {
3063                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
3064                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_DATA_OVER, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
3065                         if (!host->data_status)
3066                                 host->data_status = pending;
3067                         smp_wmb();
3068                         if (host->dir_status == DW_MCI_RECV_STATUS) {
3069                                 if (host->sg != NULL)
3070                                         dw_mci_read_data_pio(host, true);
3071                         }
3072                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3073                         tasklet_schedule(&host->tasklet);
3074                 }
3075
3076                 if (pending & SDMMC_INT_RXDR) {
3077                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
3078                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
3079                                 dw_mci_read_data_pio(host, false);
3080                 }
3081
3082                 if (pending & SDMMC_INT_TXDR) {
3083                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
3084                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
3085                                 dw_mci_write_data_pio(host);
3086                 }
3087
3088                 if (pending & SDMMC_INT_VSI) {
3089                         MMC_DBG_SW_VOL_FUNC(host->mmc, "SDMMC_INT_VSI, INT-pending=0x%x. [%s]",pending,mmc_hostname(host->mmc));
3090                         mci_writel(host, RINTSTS, SDMMC_INT_VSI);
3091                         dw_mci_cmd_interrupt(host, pending);
3092                 }
3093
3094                 if (pending & SDMMC_INT_CMD_DONE) {
3095                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_CMD_DONE, CMD = 0x%x, INT-pending=0x%x. [%s]",mci_readl(host, CMD),pending,mmc_hostname(host->mmc));
3096                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
3097                         dw_mci_cmd_interrupt(host, pending);
3098                 }
3099
3100                 if (pending & SDMMC_INT_CD) {
3101                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
3102                         MMC_DBG_INFO_FUNC(host->mmc, "SDMMC_INT_CD, INT-pending=0x%x. [%s]", pending, mmc_hostname(host->mmc));
3103                         wake_lock_timeout(&host->mmc->detect_wake_lock, 5 * HZ);
3104                         queue_work(host->card_workqueue, &host->card_work);
3105                 }
3106
3107                 if (pending & SDMMC_INT_HLE) {
3108                         mci_writel(host, RINTSTS, SDMMC_INT_HLE);
3109                         MMC_DBG_CMD_FUNC(host->mmc, "SDMMC_INT_HLE INT-pending=0x%x. [%s]\n",pending,mmc_hostname(host->mmc));
3110
3111                 }
3112
3113                 /* Handle SDIO Interrupts */
3114                 for (i = 0; i < host->num_slots; i++) {
3115                         struct dw_mci_slot *slot = host->slot[i];
3116
3117                         if (host->verid < DW_MMC_240A)
3118                                 sdio_int = SDMMC_INT_SDIO(i);
3119                         else
3120                                 sdio_int = SDMMC_INT_SDIO(i + 8);
3121
3122                         if (pending & sdio_int) {
3123                                 mci_writel(host, RINTSTS, sdio_int);
3124                                 mmc_signal_sdio_irq(slot->mmc);
3125                         }
3126                 }
3127
3128         }
3129
3130 #ifdef CONFIG_MMC_DW_IDMAC
3131         /* External DMA Soc platform NOT need to ack interrupt IDSTS */
3132         if(!(cpu_is_rk3036() || cpu_is_rk312x())){
3133                 /* Handle DMA interrupts */
3134                 pending = mci_readl(host, IDSTS);
3135                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
3136                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
3137                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3138                         host->dma_ops->complete((void *)host);
3139                 }
3140         }
3141 #endif
3142
3143         return IRQ_HANDLED;
3144 }
3145
3146 static void dw_mci_work_routine_card(struct work_struct *work)
3147 {
3148         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
3149         int i;
3150
3151         for (i = 0; i < host->num_slots; i++) {
3152                 struct dw_mci_slot *slot = host->slot[i];
3153                 struct mmc_host *mmc = slot->mmc;
3154                 struct mmc_request *mrq;
3155                 int present;
3156
3157                 present = dw_mci_get_cd(mmc);
3158
3159                 /* Card insert, switch data line to uart function, and vice verse.
3160             eONLY audi chip need switched by software, using udbg tag in dts!
3161                  */
3162                 if (!(IS_ERR(host->pins_udbg)) && !(IS_ERR(host->pins_default))) {
3163                          if (present) {
3164                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3165                                         dev_err(host->dev, "%s: Default pinctrl setting failed!\n",
3166                                                 mmc_hostname(host->mmc));
3167                          } else {
3168                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3169                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3170                                                 mmc_hostname(host->mmc));
3171                         }
3172                 }
3173
3174                 while (present != slot->last_detect_state) {
3175                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
3176                                 present ? "inserted" : "removed");
3177                         MMC_DBG_BOOT_FUNC(mmc, "  The card is %s.  ===!!!!!!==[%s]\n",
3178                                 present ? "inserted" : "removed.", mmc_hostname(mmc));
3179
3180                         dw_mci_ctrl_all_reset(host);
3181                         /* Stop edma when rountine card triggered */
3182                         if(cpu_is_rk3036() || cpu_is_rk312x())
3183                                 if(host->dma_ops && host->dma_ops->stop)
3184                                         host->dma_ops->stop(host);
3185                         rk_send_wakeup_key();//wake up system
3186                         spin_lock_bh(&host->lock);
3187
3188                         /* Card change detected */
3189                         slot->last_detect_state = present;
3190
3191                         /* Clean up queue if present */
3192                         mrq = slot->mrq;
3193                         if (mrq) {
3194                                 if (mrq == host->mrq) {
3195                                         host->data = NULL;
3196                                         host->cmd = NULL;
3197
3198                                         switch (host->state) {
3199                                         case STATE_IDLE:
3200                                                 break;
3201                                         case STATE_SENDING_CMD:
3202                                                 mrq->cmd->error = -ENOMEDIUM;
3203                                                 if (!mrq->data)
3204                                                         break;
3205                                                 /* fall through */
3206                                         case STATE_SENDING_DATA:
3207                                                 mrq->data->error = -ENOMEDIUM;
3208                                                 dw_mci_stop_dma(host);
3209                                                 break;
3210                                         case STATE_DATA_BUSY:
3211                                         case STATE_DATA_ERROR:
3212                                                 if (mrq->data->error == -EINPROGRESS)
3213                                                         mrq->data->error = -ENOMEDIUM;
3214                                                 if (!mrq->stop)
3215                                                         break;
3216                                                 /* fall through */
3217                                         case STATE_SENDING_STOP:
3218                                                 mrq->stop->error = -ENOMEDIUM;
3219                                                 break;
3220                                         }
3221
3222                                         dw_mci_request_end(host, mrq);
3223                                 } else {
3224                                         list_del(&slot->queue_node);
3225                                         mrq->cmd->error = -ENOMEDIUM;
3226                                         if (mrq->data)
3227                                                 mrq->data->error = -ENOMEDIUM;
3228                                         if (mrq->stop)
3229                                                 mrq->stop->error = -ENOMEDIUM;
3230
3231                                         MMC_DBG_CMD_FUNC(host->mmc, "dw_mci_work--reqeuest done, cmd=%d [%s]",
3232                                                         mrq->cmd->opcode, mmc_hostname(mmc));
3233
3234                                         spin_unlock(&host->lock);
3235                                         mmc_request_done(slot->mmc, mrq);
3236                                         spin_lock(&host->lock);
3237                                 }
3238                         }
3239
3240                         /* Power down slot */
3241                         if (present == 0) {
3242                                 /* Clear down the FIFO */
3243                                 dw_mci_fifo_reset(host);
3244 #ifdef CONFIG_MMC_DW_IDMAC
3245                                 if(!(cpu_is_rk3036() || cpu_is_rk312x()))
3246                                         dw_mci_idmac_reset(host);
3247 #endif
3248
3249                         }
3250
3251                         spin_unlock_bh(&host->lock);
3252
3253                         present = dw_mci_get_cd(mmc);
3254                 }
3255
3256                 mmc_detect_change(slot->mmc,
3257                 msecs_to_jiffies(host->pdata->detect_delay_ms));
3258         }
3259 }
3260
3261 #ifdef CONFIG_OF
3262 /* given a slot id, find out the device node representing that slot */
3263 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3264 {
3265         struct device_node *np;
3266         const __be32 *addr;
3267         int len;
3268
3269         if (!dev || !dev->of_node)
3270                 return NULL;
3271
3272         for_each_child_of_node(dev->of_node, np) {
3273                 addr = of_get_property(np, "reg", &len);
3274                 if (!addr || (len < sizeof(int)))
3275                         continue;
3276                 if (be32_to_cpup(addr) == slot)
3277                         return np;
3278         }
3279         return NULL;
3280 }
3281
3282 static struct dw_mci_of_slot_quirks {
3283         char *quirk;
3284         int id;
3285 } of_slot_quirks[] = {
3286         {
3287                 .quirk  = "disable-wp",
3288                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
3289         },
3290 };
3291
3292 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3293 {
3294         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3295         int quirks = 0;
3296         int idx;
3297
3298         /* get quirks */
3299         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
3300                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
3301                         quirks |= of_slot_quirks[idx].id;
3302
3303         return quirks;
3304 }
3305
3306 /* find out bus-width for a given slot */
3307 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3308 {
3309         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3310         u32 bus_wd = 1;
3311
3312         if (!np)
3313                 return 1;
3314
3315         if (of_property_read_u32(np, "bus-width", &bus_wd))
3316                 dev_err(dev, "bus-width property not found, assuming width"
3317                                " as 1\n");
3318         return bus_wd;
3319 }
3320
3321
3322 /* find the pwr-en gpio for a given slot; or -1 if none specified */
3323 static int dw_mci_of_get_pwr_en_gpio(struct device *dev, u8 slot)
3324 {
3325         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3326         int gpio;
3327
3328         if (!np)
3329                 return -EINVAL;
3330
3331         gpio = of_get_named_gpio(np, "pwr-gpios", 0);
3332
3333         /* Having a missing entry is valid; return silently */
3334         if (!gpio_is_valid(gpio))
3335                 return -EINVAL;
3336
3337         if (devm_gpio_request(dev, gpio, "dw-mci-pwr_en")) {
3338                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3339                 return -EINVAL;
3340         }
3341
3342     gpio_direction_output(gpio, 0);//set 0 to pwr-en
3343
3344         return gpio;
3345 }
3346
3347
3348 /* find the write protect gpio for a given slot; or -1 if none specified */
3349 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3350 {
3351         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
3352         int gpio;
3353
3354         if (!np)
3355                 return -EINVAL;
3356
3357         gpio = of_get_named_gpio(np, "wp-gpios", 0);
3358
3359         /* Having a missing entry is valid; return silently */
3360         if (!gpio_is_valid(gpio))
3361                 return -EINVAL;
3362
3363         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
3364                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3365                 return -EINVAL;
3366         }
3367
3368         return gpio;
3369 }
3370
3371 /* find the cd gpio for a given slot */
3372 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3373                                         struct mmc_host *mmc)
3374 {
3375         struct device_node *np = dev->of_node;//dw_mci_of_find_slot_node(dev, slot);
3376         int gpio;
3377
3378         if (!np)
3379                 return;
3380
3381         gpio = of_get_named_gpio(np, "cd-gpios", 0);
3382
3383         /* Having a missing entry is valid; return silently */
3384         if (!gpio_is_valid(gpio))
3385                 return;
3386
3387         if (mmc_gpio_request_cd(mmc, gpio, 0))
3388                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
3389 }
3390
3391 static irqreturn_t dw_mci_gpio_cd_irqt(int irq, void *dev_id)
3392 {
3393         struct mmc_host *mmc = dev_id;
3394         struct dw_mci_slot *slot = mmc_priv(mmc);
3395         struct dw_mci *host = slot->host;
3396         int gpio_cd = slot->cd_gpio;
3397
3398         (gpio_get_value(gpio_cd)  == 0) ?
3399                 irq_set_irq_type(irq, IRQF_TRIGGER_HIGH  | IRQF_ONESHOT) :
3400                 irq_set_irq_type(irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
3401
3402         /* wakeup system whether gpio debounce or not */
3403         rk_send_wakeup_key();
3404
3405         /* no need to trigger detect flow when rescan is disabled.
3406            This case happended in dpm, that we just wakeup system and
3407            let suspend_post notify callback handle it.
3408          */
3409         if(mmc->rescan_disable == 0)
3410                 queue_work(host->card_workqueue, &host->card_work);
3411         else
3412                 printk("%s: rescan been disabled!\n", __FUNCTION__);
3413
3414         return IRQ_HANDLED;
3415 }
3416
3417 static void dw_mci_of_set_cd_gpio_irq(struct device *dev, u32 gpio,
3418                                         struct mmc_host *mmc)
3419 {
3420         struct dw_mci_slot *slot = mmc_priv(mmc);
3421         struct dw_mci *host = slot->host;
3422         int irq;
3423         int ret;
3424
3425         /* Having a missing entry is valid; return silently */
3426         if (!gpio_is_valid(gpio))
3427                 return;
3428
3429         irq = gpio_to_irq(gpio);
3430         if (irq >= 0) {
3431                 ret = devm_request_threaded_irq(&mmc->class_dev, irq,
3432                                                 NULL, dw_mci_gpio_cd_irqt,
3433                                                 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3434                                                 "dw_mci_cd", mmc);
3435                 if (ret < 0) {
3436                         irq = ret;
3437                         dev_err(host->dev, "Request cd-gpio %d interrupt error!\n", gpio);
3438                 } else{
3439                         /* enable wakeup event for gpio-cd in idle or deep suspend*/
3440                         enable_irq_wake(irq);
3441                 }
3442         } else {
3443                 dev_err(host->dev, "Cannot convert gpio %d to irq!\n", gpio);
3444         }
3445 }
3446
3447 static void dw_mci_of_free_cd_gpio_irq(struct device *dev, u32 gpio,
3448                                         struct mmc_host *mmc)
3449 {
3450         if (!gpio_is_valid(gpio))
3451                 return;
3452
3453         if (gpio_to_irq(gpio) >= 0) {
3454                 devm_free_irq(&mmc->class_dev, gpio_to_irq(gpio), mmc);
3455                 devm_gpio_free(&mmc->class_dev, gpio);
3456         }
3457 }
3458 #else /* CONFIG_OF */
3459 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
3460 {
3461         return 0;
3462 }
3463 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
3464 {
3465         return 1;
3466 }
3467 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
3468 {
3469         return NULL;
3470 }
3471 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
3472 {
3473         return -EINVAL;
3474 }
3475 static void dw_mci_of_get_cd_gpio(struct device *dev, u8 slot,
3476                                         struct mmc_host *mmc)
3477 {
3478         return;
3479 }
3480 #endif /* CONFIG_OF */
3481
3482 /* @host: dw_mci host prvdata
3483  * Init pinctrl for each platform. Usually we assign
3484  * "defalut" tag for functional usage, "idle" tag for gpio
3485  * state and "udbg" tag for uart_dbg if any.
3486  */
3487 static void dw_mci_init_pinctrl(struct dw_mci *host)
3488 {
3489         /* Fixme: DON'T TOUCH EMMC SETTING! */
3490         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
3491                 return;
3492
3493         /* Get pinctrl for DTS */
3494         host->pinctrl = devm_pinctrl_get(host->dev);
3495         if (IS_ERR(host->pinctrl)) {
3496                 dev_err(host->dev, "%s: No pinctrl used!\n",
3497                         mmc_hostname(host->mmc));
3498                 return;
3499         }
3500
3501         /* Lookup idle state */
3502         host->pins_idle = pinctrl_lookup_state(host->pinctrl,
3503                                                 PINCTRL_STATE_IDLE);
3504         if (IS_ERR(host->pins_idle)) {
3505                 dev_err(host->dev, "%s: No idle tag found!\n",
3506                         mmc_hostname(host->mmc));
3507         } else {
3508                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
3509                         dev_err(host->dev, "%s: Idle pinctrl setting failed!\n",
3510                                 mmc_hostname(host->mmc));
3511         }
3512
3513         /* Lookup default state */
3514         host->pins_default = pinctrl_lookup_state(host->pinctrl,
3515                                                         PINCTRL_STATE_DEFAULT);
3516         if (IS_ERR(host->pins_default)) {
3517                 dev_err(host->dev, "%s: No default pinctrl found!\n",
3518                         mmc_hostname(host->mmc));
3519         } else {
3520                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
3521                         dev_err(host->dev, "%s:  Default pinctrl setting failed!\n",
3522                                 mmc_hostname(host->mmc));
3523         }
3524
3525         /* Sd card data0/1 may be used for uart_dbg, so were data2/3 for Jtag */
3526         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3527                 host->pins_udbg = pinctrl_lookup_state(host->pinctrl, "udbg");
3528                 if (IS_ERR(host->pins_udbg)) {
3529                         dev_warn(host->dev, "%s: No udbg pinctrl found!\n",
3530                                         mmc_hostname(host->mmc));
3531                 } else {
3532                         if (!dw_mci_get_cd(host->mmc))
3533                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
3534                                         dev_err(host->dev, "%s: Udbg pinctrl setting failed!\n",
3535                                                 mmc_hostname(host->mmc));
3536                 }
3537         }
3538 }
3539
3540 static int dw_mci_pm_notify(struct notifier_block *notify_block,
3541                                         unsigned long mode, void *unused)
3542 {
3543         struct mmc_host *host = container_of(
3544                 notify_block, struct mmc_host, pm_notify);
3545         unsigned long flags;
3546
3547         switch (mode) {
3548         case PM_HIBERNATION_PREPARE:
3549         case PM_SUSPEND_PREPARE:
3550                 dev_err(host->parent, "dw_mci_pm_notify:  suspend prepare\n");
3551                 spin_lock_irqsave(&host->lock, flags);
3552                 host->rescan_disable = 1;
3553                 spin_unlock_irqrestore(&host->lock, flags);
3554                 if (cancel_delayed_work(&host->detect))
3555                         wake_unlock(&host->detect_wake_lock);
3556                 break;
3557
3558         case PM_POST_SUSPEND:
3559         case PM_POST_HIBERNATION:
3560         case PM_POST_RESTORE:
3561                 dev_err(host->parent, "dw_mci_pm_notify:  post suspend\n");
3562                 spin_lock_irqsave(&host->lock, flags);
3563                 host->rescan_disable = 0;
3564                 spin_unlock_irqrestore(&host->lock, flags);
3565                 mmc_detect_change(host, 10);
3566         }
3567
3568         return 0;
3569 }
3570
3571 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
3572 {
3573         struct mmc_host *mmc;
3574         struct dw_mci_slot *slot;
3575         const struct dw_mci_drv_data *drv_data = host->drv_data;
3576         int ctrl_id, ret;
3577         u32 freq[2];
3578         u8 bus_width;
3579
3580         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
3581         if (!mmc)
3582                 return -ENOMEM;
3583
3584         slot = mmc_priv(mmc);
3585         slot->id = id;
3586         slot->mmc = mmc;
3587         slot->host = host;
3588         host->slot[id] = slot;
3589         host->mmc = mmc;
3590
3591         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
3592
3593         mmc->ops = &dw_mci_ops;
3594
3595         if (of_property_read_u32_array(host->dev->of_node,
3596                                        "clock-freq-min-max", freq, 2)) {
3597                 mmc->f_min = DW_MCI_FREQ_MIN;
3598                 mmc->f_max = DW_MCI_FREQ_MAX;
3599
3600                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3601                         mmc->f_min, mmc->f_max, mmc_hostname(mmc));
3602         } else {
3603                 mmc->f_min = freq[0];
3604                 mmc->f_max = freq[1];
3605
3606                 printk("%d..%s: fmin=%d, fmax=%d [%s]\n", __LINE__, __FUNCTION__,
3607                         mmc->f_min, mmc->f_max,  mmc_hostname(mmc));
3608         }
3609
3610         printk("%s : Rockchip specific MHSC: %s\n", mmc_hostname(mmc), RK_SDMMC_DRIVER_VERSION);
3611
3612         if (of_find_property(host->dev->of_node, "supports-sd", NULL))
3613                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SD;
3614         if (of_find_property(host->dev->of_node, "supports-sdio", NULL))
3615                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_SDIO;
3616         if (of_find_property(host->dev->of_node, "supports-emmc", NULL))
3617                 mmc->restrict_caps |= RESTRICT_CARD_TYPE_EMMC;
3618
3619         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
3620                 mmc->pm_notify.notifier_call = dw_mci_pm_notify;
3621                 if (register_pm_notifier(&mmc->pm_notify)) {
3622                         printk(KERN_ERR "dw_mci: register_pm_notifier failed\n");
3623                         goto err_pm_notifier;
3624                 }
3625         }
3626
3627         if (host->cid == DW_MCI_TYPE_RK3368) {
3628                 if (IS_ERR(host->grf))
3629                         pr_err("rk_sdmmc: dts couldn't find grf regmap for 3368\n");
3630                 else
3631                         /* Disable force_jtag */
3632                         regmap_write(host->grf, 0x43c, (1<<13)<<16 | (0 << 13));
3633         } else if (cpu_is_rk3288()) {
3634                 grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
3635         }
3636
3637
3638         /* We assume only low-level chip use gpio_cd */
3639         if ((soc_is_rk3126() || soc_is_rk3126b() || soc_is_rk3036()) &&
3640                 (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)) {
3641                 slot->cd_gpio = of_get_named_gpio(host->dev->of_node, "cd-gpios", 0);
3642                 if (gpio_is_valid(slot->cd_gpio)) {
3643                         /* Request gpio int for card detection */
3644                         dw_mci_of_set_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3645                 } else {
3646                         slot->cd_gpio = -ENODEV;
3647                         dev_err(host->dev, "failed to get your cd-gpios!\n");
3648                 }
3649         }
3650
3651         if (host->pdata->get_ocr)
3652                 mmc->ocr_avail = host->pdata->get_ocr(id);
3653         else
3654         {
3655                 mmc->ocr_avail =  MMC_VDD_27_28| MMC_VDD_28_29| MMC_VDD_29_30| MMC_VDD_30_31
3656                         | MMC_VDD_31_32| MMC_VDD_32_33| MMC_VDD_33_34| MMC_VDD_34_35| MMC_VDD_35_36
3657                         | MMC_VDD_26_27| MMC_VDD_25_26| MMC_VDD_24_25| MMC_VDD_23_24
3658                         | MMC_VDD_22_23| MMC_VDD_21_22| MMC_VDD_20_21| MMC_VDD_165_195;
3659         }
3660
3661         /*
3662          * Start with slot power disabled, it will be enabled when a card
3663          * is detected.
3664          */
3665         if (host->pdata->setpower)
3666                 host->pdata->setpower(id, 0);
3667
3668         if (host->pdata->caps)
3669                 mmc->caps = host->pdata->caps;
3670
3671         if (host->pdata->pm_caps)
3672                 mmc->pm_caps = host->pdata->pm_caps;
3673
3674         if (host->dev->of_node) {
3675                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
3676                 if (ctrl_id < 0)
3677                         ctrl_id = 0;
3678         } else {
3679                 ctrl_id = to_platform_device(host->dev)->id;
3680         }
3681         if (drv_data && drv_data->caps)
3682                 mmc->caps |= drv_data->caps[ctrl_id];
3683         if (drv_data && drv_data->hold_reg_flag)
3684                 mmc->hold_reg_flag |= drv_data->hold_reg_flag[ctrl_id];
3685
3686         /* set the compatibility of driver. */
3687         mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50
3688                         | MMC_CAP_UHS_SDR104 | MMC_CAP_ERASE ;
3689
3690         if (host->pdata->caps2)
3691                 mmc->caps2 = host->pdata->caps2;
3692
3693         if (host->pdata->get_bus_wd)
3694                 bus_width = host->pdata->get_bus_wd(slot->id);
3695         else if (host->dev->of_node)
3696                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
3697         else
3698                 bus_width = 1;
3699
3700         switch (bus_width) {
3701                 case 8:
3702                         mmc->caps |= MMC_CAP_8_BIT_DATA;
3703                 case 4:
3704                         mmc->caps |= MMC_CAP_4_BIT_DATA;
3705         }
3706
3707         if (of_find_property(host->dev->of_node, "cap-power-off-card", NULL))
3708                 mmc->caps |= MMC_CAP_POWER_OFF_CARD;
3709         if (of_find_property(host->dev->of_node, "cap-sdio-irq", NULL))
3710                 mmc->caps |= MMC_CAP_SDIO_IRQ;
3711         if (of_find_property(host->dev->of_node, "poll-hw-reset", NULL))
3712                 mmc->caps |= MMC_CAP_HW_RESET;
3713         if (of_find_property(host->dev->of_node, "full-pwr-cycle", NULL))
3714                 mmc->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
3715         if (of_find_property(host->dev->of_node, "keep-power-in-suspend", NULL))
3716                 mmc->pm_caps |= MMC_PM_KEEP_POWER;
3717         if (of_find_property(host->dev->of_node, "ignore-pm-notify", NULL))
3718                 mmc->pm_caps |= MMC_PM_IGNORE_PM_NOTIFY;
3719         if (of_find_property(host->dev->of_node, "enable-sdio-wakeup", NULL))
3720                 mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
3721
3722         /*Assign pm_caps pass to pm_flags*/
3723         mmc->pm_flags = mmc->pm_caps;
3724
3725         if (host->pdata->blk_settings) {
3726                 mmc->max_segs = host->pdata->blk_settings->max_segs;
3727                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
3728                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
3729                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
3730                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
3731         } else {
3732                 /* Useful defaults if platform data is unset. */
3733 #ifdef CONFIG_MMC_DW_IDMAC
3734                 mmc->max_segs = host->ring_size;
3735                 mmc->max_blk_size = 65536;
3736                 mmc->max_blk_count = host->ring_size;
3737                 mmc->max_seg_size = 0x1000;
3738                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
3739                 if(cpu_is_rk3036() || cpu_is_rk312x()){
3740                         /* fixup for external dmac setting */
3741                         mmc->max_segs = 64;
3742                         mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3743                         mmc->max_blk_count = 65535;
3744                         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3745                         mmc->max_seg_size = mmc->max_req_size;
3746                 }
3747 #else
3748                 mmc->max_segs = 64;
3749                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
3750                 mmc->max_blk_count = 512;
3751                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
3752                 mmc->max_seg_size = mmc->max_req_size;
3753 #endif /* CONFIG_MMC_DW_IDMAC */
3754
3755         }
3756         /* pwr_en */
3757         slot->pwr_en_gpio = dw_mci_of_get_pwr_en_gpio(host->dev, slot->id);
3758
3759         if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
3760         {
3761                 host->vmmc = NULL;
3762         }else{
3763
3764                 if(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
3765                         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
3766                 else
3767                         host->vmmc = NULL;
3768
3769                 if (IS_ERR(host->vmmc)) {
3770                         pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
3771                         host->vmmc = NULL;
3772                 }else{
3773                         ret = regulator_enable(host->vmmc);
3774                         if (ret) {
3775                                 dev_err(host->dev,
3776                                         "failed to enable regulator: %d\n", ret);
3777                                 host->vmmc = NULL;
3778                                 goto err_setup_bus;
3779                         }
3780                 }
3781         }
3782
3783         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
3784
3785         if (mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
3786                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
3787
3788         dw_mci_init_pinctrl(host);
3789         ret = mmc_add_host(mmc);
3790         if (ret)
3791                 goto err_setup_bus;
3792
3793 #if defined(CONFIG_DEBUG_FS)
3794         dw_mci_init_debugfs(slot);
3795 #endif
3796
3797         /* Card initially undetected */
3798         slot->last_detect_state = 1;
3799
3800         return 0;
3801 err_pm_notifier:
3802         unregister_pm_notifier(&mmc->pm_notify);
3803
3804 err_setup_bus:
3805         if (gpio_is_valid(slot->cd_gpio))
3806                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio,host->mmc);
3807         mmc_free_host(mmc);
3808         return -EINVAL;
3809 }
3810
3811 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
3812 {
3813         /* Shutdown detect IRQ */
3814         if (slot->host->pdata->exit)
3815                 slot->host->pdata->exit(id);
3816
3817         /* Debugfs stuff is cleaned up by mmc core */
3818         mmc_remove_host(slot->mmc);
3819         slot->host->slot[id] = NULL;
3820         mmc_free_host(slot->mmc);
3821 }
3822
3823 static void dw_mci_init_dma(struct dw_mci *host)
3824 {
3825         /* Alloc memory for sg translation */
3826         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
3827                                           &host->sg_dma, GFP_KERNEL);
3828         if (!host->sg_cpu) {
3829                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
3830                         __func__);
3831                 goto no_dma;
3832         }
3833         #ifdef CONFIG_ARM64
3834         memset(host->sg_cpu, 0, PAGE_SIZE);
3835         #endif
3836
3837         /* Determine which DMA interface to use */
3838 #if defined(CONFIG_MMC_DW_IDMAC)
3839         if(cpu_is_rk3036() || cpu_is_rk312x()){
3840                 host->dma_ops = &dw_mci_edmac_ops;
3841                 dev_info(host->dev, "Using external DMA controller.\n");
3842         }else{
3843                 host->dma_ops = &dw_mci_idmac_ops;
3844                 dev_info(host->dev, "Using internal DMA controller.\n");
3845         }
3846 #endif
3847
3848         if (!host->dma_ops)
3849                 goto no_dma;
3850
3851         if (host->dma_ops->init && host->dma_ops->start &&
3852             host->dma_ops->stop && host->dma_ops->cleanup) {
3853                 if (host->dma_ops->init(host)) {
3854                         dev_err(host->dev, "%s: Unable to initialize "
3855                                 "DMA Controller.\n", __func__);
3856                         goto no_dma;
3857                 }
3858         } else {
3859                 dev_err(host->dev, "DMA initialization not found.\n");
3860                 goto no_dma;
3861         }
3862
3863         host->use_dma = 1;
3864         return;
3865
3866 no_dma:
3867         dev_info(host->dev, "Using PIO mode.\n");
3868         host->use_dma = 0;
3869         return;
3870 }
3871
3872 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
3873 {
3874         unsigned long timeout = jiffies + msecs_to_jiffies(500);
3875         u32 ctrl;
3876
3877         ctrl = mci_readl(host, CTRL);
3878         ctrl |= reset;
3879         mci_writel(host, CTRL, ctrl);
3880
3881         /* wait till resets clear */
3882         do {
3883                 ctrl = mci_readl(host, CTRL);
3884                 if (!(ctrl & reset))
3885                         return true;
3886         } while (time_before(jiffies, timeout));
3887
3888         dev_err(host->dev,
3889                 "Timeout resetting block (ctrl reset %#x)\n",
3890                 ctrl & reset);
3891
3892         return false;
3893 }
3894
3895 static inline bool dw_mci_fifo_reset(struct dw_mci *host)
3896 {
3897         /*
3898          * Reseting generates a block interrupt, hence setting
3899          * the scatter-gather pointer to NULL.
3900          */
3901         if (host->sg) {
3902                 sg_miter_stop(&host->sg_miter);
3903                 host->sg = NULL;
3904         }
3905
3906         return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
3907 }
3908
3909 static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
3910 {
3911         return dw_mci_ctrl_reset(host,
3912                                  SDMMC_CTRL_FIFO_RESET |
3913                                  SDMMC_CTRL_RESET |
3914                                  SDMMC_CTRL_DMA_RESET);
3915 }
3916
3917 static void dw_mci_rst_pre_suspend(struct dw_mci *host)
3918 {
3919         u32 index;
3920         u32 *buffer;
3921
3922         buffer = host->regs_buffer;
3923
3924         for (index = 0; index < DW_REGS_NUM ; index++){
3925                 *buffer = mci_readreg(host, index*4);
3926                 MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
3927                         dw_mci_regs[index].name, *buffer);
3928                 buffer++;
3929         }
3930
3931         *buffer = mci_readl(host,CDTHRCTL);
3932         MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
3933 }
3934
3935 static void dw_mci_rst_post_resume(struct dw_mci *host)
3936 {
3937         u32 index;
3938         u32 *buffer;
3939
3940         buffer = host->regs_buffer;
3941
3942         for (index = 0; index < DW_REGS_NUM; index++){
3943                 mci_writereg(host, index*4, *buffer);
3944                 buffer++;
3945         }
3946         mci_writel(host, CDTHRCTL, *buffer);
3947 }
3948
3949 static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
3950         .pre_suspend = dw_mci_rst_pre_suspend,
3951         .post_resume = dw_mci_rst_post_resume,
3952 };
3953
3954 #ifdef CONFIG_OF
3955 /*
3956 static struct dw_mci_of_quirks {
3957         char *quirk;
3958         int id;
3959 } of_quirks[] = {
3960         {
3961                 .quirk  = "broken-cd",
3962                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
3963         },
3964 };
3965 */
3966 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3967 {
3968         struct dw_mci_board *pdata;
3969         struct device *dev = host->dev;
3970         struct device_node *np = dev->of_node;
3971         const struct dw_mci_drv_data *drv_data = host->drv_data;
3972         int  ret;
3973         u32 clock_frequency;
3974
3975         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3976         if (!pdata) {
3977                 dev_err(dev, "could not allocate memory for pdata\n");
3978                 return ERR_PTR(-ENOMEM);
3979         }
3980
3981         /* find out number of slots supported */
3982         if (of_property_read_u32(dev->of_node, "num-slots",
3983                                 &pdata->num_slots)) {
3984                 dev_info(dev, "num-slots property not found, "
3985                                 "assuming 1 slot is available\n");
3986                 pdata->num_slots = 1;
3987         }
3988 #if 0
3989         /* get quirks */
3990         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
3991                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
3992                         pdata->quirks |= of_quirks[idx].id;
3993 #endif
3994
3995         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
3996                 dev_info(dev, "fifo-depth property not found, using "
3997                                 "value of FIFOTH register as default\n");
3998
3999         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
4000
4001         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
4002                 pdata->bus_hz = clock_frequency;
4003
4004         if (drv_data && drv_data->parse_dt) {
4005                 ret = drv_data->parse_dt(host);
4006                 if (ret)
4007                         return ERR_PTR(ret);
4008         }
4009
4010         if (of_find_property(np, "keep-power-in-suspend", NULL))
4011                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
4012
4013         if (of_find_property(np, "enable-sdio-wakeup", NULL))
4014                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
4015
4016         if (of_find_property(np, "supports-highspeed", NULL))
4017                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
4018
4019     if (of_find_property(np, "supports-UHS_SDR104", NULL))
4020                 pdata->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
4021
4022     if (of_find_property(np, "supports-DDR_MODE", NULL))
4023                 pdata->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_1_2V_DDR;
4024
4025     if (of_find_property(np, "caps2-mmc-hs200", NULL))
4026                 pdata->caps2 |= MMC_CAP2_HS200;
4027
4028         if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
4029                 pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
4030
4031         if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
4032                 pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
4033
4034         if (of_get_property(np, "cd-inverted", NULL))
4035                 pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
4036         if (of_get_property(np, "bootpart-no-access", NULL))
4037                 pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
4038
4039         if (of_get_property(np, "controller-power-down", NULL)) {
4040                 host->regs_buffer = (u32 *)devm_kzalloc(host->dev,
4041                                                 DW_REGS_SIZE, GFP_KERNEL);
4042                 if (!host->regs_buffer) {
4043                         dev_err(host->dev,
4044                                 "could not allocate memory for regs_buffer\n");
4045                         return ERR_PTR(-ENOMEM);
4046                 }
4047
4048                 host->rst_ops = &dw_mci_pdrst_ops;
4049                 mmc_assume_removable = 0;
4050         }
4051
4052         return pdata;
4053 }
4054
4055 #else /* CONFIG_OF */
4056 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
4057 {
4058         return ERR_PTR(-EINVAL);
4059 }
4060 #endif /* CONFIG_OF */
4061
4062 int dw_mci_probe(struct dw_mci *host)
4063 {
4064         const struct dw_mci_drv_data *drv_data = host->drv_data;
4065         int width, i, ret = 0;
4066         u32 fifo_size;
4067         int init_slots = 0;
4068         u32 regs;
4069
4070         if (!host->pdata) {
4071                 host->pdata = dw_mci_parse_dt(host);
4072                 if (IS_ERR(host->pdata)) {
4073                         dev_err(host->dev, "platform data not available\n");
4074                         return -EINVAL;
4075                 }
4076         }
4077
4078         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4079                 dev_err(host->dev,
4080                         "Platform data must supply select_slot function\n");
4081                 return -ENODEV;
4082         }
4083
4084         /*
4085          * In 2.40a spec, Data offset is changed.
4086          * Need to check the version-id and set data-offset for DATA register.
4087          */
4088         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4089         dev_info(host->dev, "Version ID is %04x\n", host->verid);
4090
4091         if (host->verid < DW_MMC_240A)
4092                 host->data_offset = DATA_OFFSET;
4093         else
4094                 host->data_offset = DATA_240A_OFFSET;
4095
4096         //hpclk enable
4097         host->hpclk_mmc= devm_clk_get(host->dev, "hpclk_mmc");
4098         if (IS_ERR(host->hpclk_mmc)) {
4099                 dev_err(host->dev, "failed to get hpclk_mmc\n");
4100         } else {
4101                 clk_prepare_enable(host->hpclk_mmc);
4102         }
4103
4104         //hclk enable
4105         host->hclk_mmc= devm_clk_get(host->dev, "hclk_mmc");
4106         if (IS_ERR(host->hclk_mmc)) {
4107                 dev_err(host->dev, "failed to get hclk_mmc\n");
4108                 ret = PTR_ERR(host->hclk_mmc);
4109                 goto err_hclk_mmc;
4110         }
4111
4112         clk_prepare_enable(host->hclk_mmc);
4113
4114         //mmc clk enable
4115         host->clk_mmc = devm_clk_get(host->dev, "clk_mmc");
4116         if (IS_ERR(host->clk_mmc)) {
4117                 dev_err(host->dev, "failed to get clk mmc_per\n");
4118                 ret = PTR_ERR(host->clk_mmc);
4119                 goto err_clk_mmc;
4120         }
4121
4122         host->bus_hz = host->pdata->bus_hz;
4123         if (!host->bus_hz) {
4124                 dev_err(host->dev,"Platform data must supply bus speed\n");
4125                 ret = -ENODEV;
4126                 goto err_clk_mmc;
4127         }
4128
4129         if (host->verid < DW_MMC_240A)
4130                 ret = clk_set_rate(host->clk_mmc, host->bus_hz);
4131         else
4132                 //rockchip: fix divider 2 in clksum before controlller
4133                 ret = clk_set_rate(host->clk_mmc, host->bus_hz * 2);
4134
4135         if(ret < 0) {
4136             dev_err(host->dev, "failed to set clk mmc\n");
4137             goto err_clk_mmc;
4138         }
4139         clk_prepare_enable(host->clk_mmc);
4140
4141         if (drv_data && drv_data->setup_clock) {
4142         ret = drv_data->setup_clock(host);
4143         if (ret) {
4144             dev_err(host->dev,
4145                 "implementation specific clock setup failed\n");
4146             goto err_clk_mmc;
4147         }
4148     }
4149
4150         host->quirks = host->pdata->quirks;
4151         host->irq_state = true;
4152         host->set_speed = 0;
4153         host->set_div = 0;
4154         host->svi_flags = 0;
4155
4156         spin_lock_init(&host->lock);
4157         spin_lock_init(&host->slock);
4158
4159         INIT_LIST_HEAD(&host->queue);
4160         /*
4161          * Get the host data width - this assumes that HCON has been set with
4162          * the correct values.
4163          */
4164         i = (mci_readl(host, HCON) >> 7) & 0x7;
4165         if (!i) {
4166                 host->push_data = dw_mci_push_data16;
4167                 host->pull_data = dw_mci_pull_data16;
4168                 width = 16;
4169                 host->data_shift = 1;
4170         } else if (i == 2) {
4171                 host->push_data = dw_mci_push_data64;
4172                 host->pull_data = dw_mci_pull_data64;
4173                 width = 64;
4174                 host->data_shift = 3;
4175         } else {
4176                 /* Check for a reserved value, and warn if it is */
4177                 WARN((i != 1),
4178                      "HCON reports a reserved host data width!\n"
4179                      "Defaulting to 32-bit access.\n");
4180                 host->push_data = dw_mci_push_data32;
4181                 host->pull_data = dw_mci_pull_data32;
4182                 width = 32;
4183                 host->data_shift = 2;
4184         }
4185
4186         /* Reset all blocks */
4187         if (!dw_mci_ctrl_all_reset(host))
4188                 return -ENODEV;
4189
4190         host->dma_ops = host->pdata->dma_ops;
4191         dw_mci_init_dma(host);
4192
4193         /* Clear the interrupts for the host controller */
4194         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4195         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4196
4197         /* Put in max timeout */
4198         mci_writel(host, TMOUT, 0xFFFFFFFF);
4199
4200         /*
4201          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
4202          *                          Tx Mark = fifo_size / 2 DMA Size = 8
4203          */
4204         if (!host->pdata->fifo_depth) {
4205                 /*
4206                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
4207                  * have been overwritten by the bootloader, just like we're
4208                  * about to do, so if you know the value for your hardware, you
4209                  * should put it in the platform data.
4210                  */
4211                 fifo_size = mci_readl(host, FIFOTH);
4212                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
4213         } else {
4214                 fifo_size = host->pdata->fifo_depth;
4215         }
4216         host->fifo_depth = fifo_size;
4217         host->fifoth_val =
4218                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
4219         mci_writel(host, FIFOTH, host->fifoth_val);
4220
4221         /* disable clock to CIU */
4222         mci_writel(host, CLKENA, 0);
4223         mci_writel(host, CLKSRC, 0);
4224
4225         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
4226         host->card_workqueue = alloc_workqueue("dw-mci-card",
4227                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
4228         if (!host->card_workqueue) {
4229                 ret = -ENOMEM;
4230                 goto err_dmaunmap;
4231         }
4232         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
4233         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
4234                                host->irq_flags, "dw-mci", host);
4235         if (ret)
4236                 goto err_workqueue;
4237
4238         if (host->pdata->num_slots)
4239                 host->num_slots = host->pdata->num_slots;
4240         else
4241                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
4242
4243         /* We need at least one slot to succeed */
4244         for (i = 0; i < host->num_slots; i++) {
4245                 ret = dw_mci_init_slot(host, i);
4246                 if (ret)
4247                         dev_dbg(host->dev, "slot %d init failed\n", i);
4248                 else
4249                         init_slots++;
4250         }
4251
4252         /*
4253          * Enable interrupts for command done, data over, data empty, card det,
4254          * receive ready and error such as transmit, receive timeout, crc error
4255          */
4256         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4257         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR | SDMMC_INT_VSI |
4258                SDMMC_INT_RXDR | DW_MCI_ERROR_FLAGS;
4259         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO)
4260             && !(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC))
4261             regs |= SDMMC_INT_CD;
4262
4263         mci_writel(host, INTMASK, regs);
4264
4265         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
4266
4267         dev_info(host->dev, "DW MMC controller at irq %d, "
4268                  "%d bit host data width, "
4269                  "%u deep fifo\n",
4270                  host->irq, width, fifo_size);
4271
4272         if (init_slots) {
4273                 dev_info(host->dev, "%d slots initialized\n", init_slots);
4274         } else {
4275                 dev_dbg(host->dev, "attempted to initialize %d slots, "
4276                                         "but failed on all\n", host->num_slots);
4277                 goto err_workqueue;
4278         }
4279
4280
4281         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4282                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
4283
4284         return 0;
4285
4286 err_workqueue:
4287         destroy_workqueue(host->card_workqueue);
4288
4289 err_dmaunmap:
4290         if (host->use_dma && host->dma_ops->exit)
4291                 host->dma_ops->exit(host);
4292
4293         if (host->vmmc){
4294                 regulator_disable(host->vmmc);
4295                 regulator_put(host->vmmc);
4296         }
4297
4298 err_clk_mmc:
4299         if (!IS_ERR(host->clk_mmc))
4300                 clk_disable_unprepare(host->clk_mmc);
4301 err_hclk_mmc:
4302         if (!IS_ERR(host->hclk_mmc))
4303                 clk_disable_unprepare(host->hclk_mmc);
4304         return ret;
4305 }
4306 EXPORT_SYMBOL(dw_mci_probe);
4307
4308 void dw_mci_remove(struct dw_mci *host)
4309 {
4310         struct mmc_host *mmc = host->mmc;
4311         struct dw_mci_slot *slot = mmc_priv(mmc);
4312         int i;
4313
4314         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4315         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
4316
4317         for(i = 0; i < host->num_slots; i++){
4318                 dev_dbg(host->dev, "remove slot %d\n", i);
4319                 if(host->slot[i])
4320                         dw_mci_cleanup_slot(host->slot[i], i);
4321         }
4322
4323         /* disable clock to CIU */
4324         mci_writel(host, CLKENA, 0);
4325         mci_writel(host, CLKSRC, 0);
4326
4327         destroy_workqueue(host->card_workqueue);
4328         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)
4329                 unregister_pm_notifier(&host->mmc->pm_notify);
4330
4331         if (host->use_dma && host->dma_ops->exit)
4332                 host->dma_ops->exit(host);
4333
4334         if (gpio_is_valid(slot->cd_gpio))
4335                 dw_mci_of_free_cd_gpio_irq(host->dev, slot->cd_gpio, host->mmc);
4336
4337         if (host->vmmc){
4338                 regulator_disable(host->vmmc);
4339                 regulator_put(host->vmmc);
4340         }
4341         if (!IS_ERR(host->clk_mmc))
4342                 clk_disable_unprepare(host->clk_mmc);
4343
4344         if (!IS_ERR(host->hclk_mmc))
4345                 clk_disable_unprepare(host->hclk_mmc);
4346         if (!IS_ERR(host->hpclk_mmc))
4347                 clk_disable_unprepare(host->hpclk_mmc);
4348 }
4349 EXPORT_SYMBOL(dw_mci_remove);
4350
4351
4352
4353 #ifdef CONFIG_PM_SLEEP
4354 /*
4355  * TODO: we should probably disable the clock to the card in the suspend path.
4356  */
4357 extern int get_wifi_chip_type(void);
4358 int dw_mci_suspend(struct dw_mci *host)
4359 {
4360         int present = dw_mci_get_cd(host->mmc);
4361
4362         if((host->mmc->restrict_caps &
4363                 RESTRICT_CARD_TYPE_SDIO) &&
4364                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4365                 get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4366                 return 0;
4367
4368         if(host->vmmc)
4369                 regulator_disable(host->vmmc);
4370
4371         /* Only for sdmmc controller */
4372         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4373                 disable_irq(host->irq);
4374                 if (present) {
4375                         if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4376                                 MMC_DBG_ERR_FUNC(host->mmc,
4377                                         "Idle pinctrl setting failed! [%s]",
4378                                         mmc_hostname(host->mmc));
4379                 }
4380
4381                 /* Soc rk3126/3036 already in gpio_cd mode */
4382                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4383                         dw_mci_of_get_cd_gpio(host->dev, 0, host->mmc);
4384                         enable_irq_wake(host->mmc->slot.cd_irq);
4385                 }
4386         }
4387
4388         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4389         mci_writel(host, INTMASK, 0x00);
4390         mci_writel(host, CTRL, 0x00);
4391
4392         if (host->rst_ops &&
4393                 host->rst_ops->pre_suspend)
4394                 host->rst_ops->pre_suspend(host);
4395
4396         return 0;
4397 }
4398 EXPORT_SYMBOL(dw_mci_suspend);
4399
4400 int dw_mci_resume(struct dw_mci *host)
4401 {
4402         int i, ret;
4403         u32 regs;
4404         struct dw_mci_slot *slot;
4405         int present = dw_mci_get_cd(host->mmc);
4406
4407         if (host->rst_ops &&
4408                 host->rst_ops->post_resume)
4409                 host->rst_ops->post_resume(host);
4410
4411
4412         if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
4413                 (get_wifi_chip_type() == WIFI_ESP8089 ||
4414                         get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
4415                 return 0;
4416
4417         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) {
4418                 slot = mmc_priv(host->mmc);
4419                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags))
4420                         return 0;
4421         }
4422
4423         /*only for sdmmc controller*/
4424         if (host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD) {
4425                 /* Soc rk3126/3036 already in gpio_cd mode */
4426                 if (!soc_is_rk3126() && !soc_is_rk3126b() && !soc_is_rk3036()) {
4427                         disable_irq_wake(host->mmc->slot.cd_irq);
4428                         mmc_gpio_free_cd(host->mmc);
4429                 }
4430
4431                 if (!present) {
4432                         if (!IS_ERR(host->pins_udbg)) {
4433                                 if (pinctrl_select_state(host->pinctrl, host->pins_idle) < 0)
4434                                         MMC_DBG_ERR_FUNC(host->mmc,
4435                                                 "Idle pinctrl setting failed! [%s]",
4436                                                 mmc_hostname(host->mmc));
4437                                 if (pinctrl_select_state(host->pinctrl, host->pins_udbg) < 0)
4438                                         MMC_DBG_ERR_FUNC(host->mmc,
4439                                                 "Udbg pinctrl setting failed! [%s]",
4440                                                 mmc_hostname(host->mmc));
4441                         } else {
4442                                 if (pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4443                                         MMC_DBG_ERR_FUNC(host->mmc,
4444                                                 "Default pinctrl setting failed! [%s]",
4445                                                 mmc_hostname(host->mmc));
4446                         }
4447                 } else {
4448                         if(pinctrl_select_state(host->pinctrl, host->pins_default) < 0)
4449                                 MMC_DBG_ERR_FUNC(host->mmc,
4450                                         "Default pinctrl setting failed! [%s]",
4451                                         mmc_hostname(host->mmc));
4452                 }
4453
4454                 /* Disable jtag*/
4455                 if(cpu_is_rk3288())
4456                         grf_writel(((1 << 12) << 16) | (0 << 12), RK3288_GRF_SOC_CON0);
4457                 else if(cpu_is_rk3036())
4458                         grf_writel(((1 << 11) << 16) | (0 << 11), RK3036_GRF_SOC_CON0);
4459                 else if(cpu_is_rk312x())
4460                         /* RK3036_GRF_SOC_CON0 is compatible with rk312x, tmp setting */
4461                         grf_writel(((1 << 8) << 16) | (0 << 8), RK3036_GRF_SOC_CON0);
4462         }
4463         if(host->vmmc){
4464                 ret = regulator_enable(host->vmmc);
4465                 if (ret){
4466                         dev_err(host->dev,
4467                                 "failed to enable regulator: %d\n", ret);
4468                         return ret;
4469                 }
4470         }
4471
4472         if(!dw_mci_ctrl_all_reset(host)){
4473                 ret = -ENODEV;
4474                 return ret;
4475         }
4476
4477         if(!(cpu_is_rk3036() || cpu_is_rk312x()))
4478                 if(host->use_dma && host->dma_ops->init)
4479                         host->dma_ops->init(host);
4480
4481         /*
4482          * Restore the initial value at FIFOTH register
4483          * And Invalidate the prev_blksz with zero
4484          */
4485         mci_writel(host, FIFOTH, host->fifoth_val);
4486         host->prev_blksz = 0;
4487         /* Put in max timeout */
4488         mci_writel(host, TMOUT, 0xFFFFFFFF);
4489
4490         mci_writel(host, RINTSTS, 0xFFFFFFFF);
4491         regs = SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | SDMMC_INT_TXDR |
4492                 SDMMC_INT_RXDR | SDMMC_INT_VSI | DW_MCI_ERROR_FLAGS;
4493
4494         if(!(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
4495             regs |= SDMMC_INT_CD;
4496
4497         mci_writel(host, INTMASK, regs);
4498         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
4499
4500         /*only for sdmmc controller*/
4501         if((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SD)){
4502                 enable_irq(host->irq);
4503         }
4504
4505         for(i = 0; i < host->num_slots; i++){
4506                 struct dw_mci_slot *slot = host->slot[i];
4507                 if(!slot)
4508                         continue;
4509                 if(slot->mmc->pm_flags & MMC_PM_KEEP_POWER){
4510                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
4511                         dw_mci_setup_bus(slot, true);
4512                 }
4513         }
4514
4515         return 0;
4516 }
4517 EXPORT_SYMBOL(dw_mci_resume);
4518 #endif /* CONFIG_PM_SLEEP */
4519
4520 static int __init dw_mci_init(void)
4521 {
4522         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
4523         return 0;
4524 }
4525
4526 static void __exit dw_mci_exit(void)
4527 {
4528 }
4529
4530 module_init(dw_mci_init);
4531 module_exit(dw_mci_exit);
4532
4533 MODULE_DESCRIPTION("Rockchip specific DW Multimedia Card Interface driver");
4534 MODULE_AUTHOR("NXP Semiconductor VietNam");
4535 MODULE_AUTHOR("Imagination Technologies Ltd");
4536 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
4537 MODULE_AUTHOR("Bangwang Xie <xbw@rock-chips.com>");
4538 MODULE_LICENSE("GPL v2");