2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_device.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/core.h>
34 #include <linux/mmc/mmc.h>
36 #include <linux/semaphore.h>
37 #include <linux/gpio.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSCONFIG 0x0010
48 #define OMAP_HSMMC_SYSSTATUS 0x0014
49 #define OMAP_HSMMC_CON 0x002C
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_HCTL 0x0128
59 #define OMAP_HSMMC_SYSCTL 0x012C
60 #define OMAP_HSMMC_STAT 0x0130
61 #define OMAP_HSMMC_IE 0x0134
62 #define OMAP_HSMMC_ISE 0x0138
63 #define OMAP_HSMMC_CAPA 0x0140
65 #define VS18 (1 << 26)
66 #define VS30 (1 << 25)
67 #define SDVS18 (0x5 << 9)
68 #define SDVS30 (0x6 << 9)
69 #define SDVS33 (0x7 << 9)
70 #define SDVS_MASK 0x00000E00
71 #define SDVSCLR 0xFFFFF1FF
72 #define SDVSDET 0x00000400
79 #define CLKD_MASK 0x0000FFC0
81 #define DTO_MASK 0x000F0000
83 #define INT_EN_MASK 0x307F0033
84 #define BWR_ENABLE (1 << 4)
85 #define BRR_ENABLE (1 << 5)
86 #define DTO_ENABLE (1 << 20)
87 #define INIT_STREAM (1 << 1)
88 #define DP_SELECT (1 << 21)
93 #define FOUR_BIT (1 << 1)
99 #define CMD_TIMEOUT (1 << 16)
100 #define DATA_TIMEOUT (1 << 20)
101 #define CMD_CRC (1 << 17)
102 #define DATA_CRC (1 << 21)
103 #define CARD_ERR (1 << 28)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
110 #define RESETDONE (1 << 0)
112 #define MMC_AUTOSUSPEND_DELAY 100
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MIN_CLOCK 400000
115 #define OMAP_MMC_MAX_CLOCK 52000000
116 #define DRIVER_NAME "omap_hsmmc"
119 * One controller can have multiple slots, like on some omap boards using
120 * omap.c controller driver. Luckily this is not currently done on any known
121 * omap_hsmmc.c device.
123 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
126 * MMC Host controller read/write API's
128 #define OMAP_HSMMC_READ(base, reg) \
129 __raw_readl((base) + OMAP_HSMMC_##reg)
131 #define OMAP_HSMMC_WRITE(base, reg, val) \
132 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
134 struct omap_hsmmc_next {
135 unsigned int dma_len;
139 struct omap_hsmmc_host {
141 struct mmc_host *mmc;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
148 * vcc == configured supply
149 * vcc_aux == optional
150 * - MMC1, supply for DAT4..DAT7
151 * - MMC2/MMC2, external level shifter voltage supply, for
152 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
154 struct regulator *vcc;
155 struct regulator *vcc_aux;
157 resource_size_t mapbase;
158 spinlock_t irq_lock; /* Prevent races with irq handler */
159 unsigned int dma_len;
160 unsigned int dma_sg_idx;
161 unsigned char bus_mode;
162 unsigned char power_mode;
168 int dma_line_tx, dma_line_rx;
178 struct omap_hsmmc_next next_data;
180 struct omap_mmc_platform_data *pdata;
183 static int omap_hsmmc_card_detect(struct device *dev, int slot)
185 struct omap_mmc_platform_data *mmc = dev->platform_data;
187 /* NOTE: assumes card detect signal is active-low */
188 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
191 static int omap_hsmmc_get_wp(struct device *dev, int slot)
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
195 /* NOTE: assumes write protect signal is active-high */
196 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
199 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
203 /* NOTE: assumes card detect signal is active-low */
204 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
209 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
211 struct omap_mmc_platform_data *mmc = dev->platform_data;
213 disable_irq(mmc->slots[0].card_detect_irq);
217 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
221 enable_irq(mmc->slots[0].card_detect_irq);
227 #define omap_hsmmc_suspend_cdirq NULL
228 #define omap_hsmmc_resume_cdirq NULL
232 #ifdef CONFIG_REGULATOR
234 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
237 struct omap_hsmmc_host *host =
238 platform_get_drvdata(to_platform_device(dev));
242 * If we don't see a Vcc regulator, assume it's a fixed
243 * voltage always-on regulator.
248 * With DT, never turn OFF the regulator. This is because
249 * the pbias cell programming support is still missing when
250 * booting with Device tree
252 if (of_have_populated_dt() && !vdd)
255 if (mmc_slot(host).before_set_reg)
256 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
259 * Assume Vcc regulator is used only to power the card ... OMAP
260 * VDDS is used to power the pins, optionally with a transceiver to
261 * support cards using voltages other than VDDS (1.8V nominal). When a
262 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
264 * In some cases this regulator won't support enable/disable;
265 * e.g. it's a fixed rail for a WLAN chip.
267 * In other cases vcc_aux switches interface power. Example, for
268 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
269 * chips/cards need an interface voltage rail too.
272 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
273 /* Enable interface voltage rail, if needed */
274 if (ret == 0 && host->vcc_aux) {
275 ret = regulator_enable(host->vcc_aux);
277 ret = mmc_regulator_set_ocr(host->mmc,
281 /* Shut down the rail */
283 ret = regulator_disable(host->vcc_aux);
285 /* Then proceed to shut down the local regulator */
286 ret = mmc_regulator_set_ocr(host->mmc,
291 if (mmc_slot(host).after_set_reg)
292 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
297 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
299 struct regulator *reg;
302 mmc_slot(host).set_power = omap_hsmmc_set_power;
304 reg = regulator_get(host->dev, "vmmc");
306 dev_dbg(host->dev, "vmmc regulator missing\n");
309 ocr_value = mmc_regulator_get_ocrmask(reg);
310 if (!mmc_slot(host).ocr_mask) {
311 mmc_slot(host).ocr_mask = ocr_value;
313 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
314 dev_err(host->dev, "ocrmask %x is not supported\n",
315 mmc_slot(host).ocr_mask);
316 mmc_slot(host).ocr_mask = 0;
321 /* Allow an aux regulator */
322 reg = regulator_get(host->dev, "vmmc_aux");
323 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
325 /* For eMMC do not power off when not in sleep state */
326 if (mmc_slot(host).no_regulator_off_init)
329 * UGLY HACK: workaround regulator framework bugs.
330 * When the bootloader leaves a supply active, it's
331 * initialized with zero usecount ... and we can't
332 * disable it without first enabling it. Until the
333 * framework is fixed, we need a workaround like this
334 * (which is safe for MMC, but not in general).
336 if (regulator_is_enabled(host->vcc) > 0 ||
337 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
338 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
340 mmc_slot(host).set_power(host->dev, host->slot_id,
342 mmc_slot(host).set_power(host->dev, host->slot_id,
350 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
352 regulator_put(host->vcc);
353 regulator_put(host->vcc_aux);
354 mmc_slot(host).set_power = NULL;
357 static inline int omap_hsmmc_have_reg(void)
364 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
369 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373 static inline int omap_hsmmc_have_reg(void)
380 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
384 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
385 if (pdata->slots[0].cover)
386 pdata->slots[0].get_cover_state =
387 omap_hsmmc_get_cover_state;
389 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
390 pdata->slots[0].card_detect_irq =
391 gpio_to_irq(pdata->slots[0].switch_pin);
392 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
395 ret = gpio_direction_input(pdata->slots[0].switch_pin);
399 pdata->slots[0].switch_pin = -EINVAL;
401 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
402 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
403 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
406 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
410 pdata->slots[0].gpio_wp = -EINVAL;
415 gpio_free(pdata->slots[0].gpio_wp);
417 if (gpio_is_valid(pdata->slots[0].switch_pin))
419 gpio_free(pdata->slots[0].switch_pin);
423 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
425 if (gpio_is_valid(pdata->slots[0].gpio_wp))
426 gpio_free(pdata->slots[0].gpio_wp);
427 if (gpio_is_valid(pdata->slots[0].switch_pin))
428 gpio_free(pdata->slots[0].switch_pin);
432 * Start clock to the card
434 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
436 OMAP_HSMMC_WRITE(host->base, SYSCTL,
437 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
441 * Stop clock to the card
443 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
445 OMAP_HSMMC_WRITE(host->base, SYSCTL,
446 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
447 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
448 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
451 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
452 struct mmc_command *cmd)
454 unsigned int irq_mask;
457 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
459 irq_mask = INT_EN_MASK;
461 /* Disable timeout for erases */
462 if (cmd->opcode == MMC_ERASE)
463 irq_mask &= ~DTO_ENABLE;
465 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
466 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
467 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
470 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
472 OMAP_HSMMC_WRITE(host->base, ISE, 0);
473 OMAP_HSMMC_WRITE(host->base, IE, 0);
474 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
477 /* Calculate divisor for the given clock frequency */
478 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
483 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
491 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
493 struct mmc_ios *ios = &host->mmc->ios;
494 unsigned long regval;
495 unsigned long timeout;
497 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
499 omap_hsmmc_stop_clock(host);
501 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
502 regval = regval & ~(CLKD_MASK | DTO_MASK);
503 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
504 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
505 OMAP_HSMMC_WRITE(host->base, SYSCTL,
506 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
508 /* Wait till the ICS bit is set */
509 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
510 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
511 && time_before(jiffies, timeout))
514 omap_hsmmc_start_clock(host);
517 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
519 struct mmc_ios *ios = &host->mmc->ios;
522 con = OMAP_HSMMC_READ(host->base, CON);
523 switch (ios->bus_width) {
524 case MMC_BUS_WIDTH_8:
525 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
527 case MMC_BUS_WIDTH_4:
528 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
529 OMAP_HSMMC_WRITE(host->base, HCTL,
530 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
532 case MMC_BUS_WIDTH_1:
533 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
534 OMAP_HSMMC_WRITE(host->base, HCTL,
535 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
540 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
542 struct mmc_ios *ios = &host->mmc->ios;
545 con = OMAP_HSMMC_READ(host->base, CON);
546 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
547 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
549 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
555 * Restore the MMC host context, if it was lost as result of a
556 * power state change.
558 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
560 struct mmc_ios *ios = &host->mmc->ios;
561 struct omap_mmc_platform_data *pdata = host->pdata;
562 int context_loss = 0;
564 unsigned long timeout;
566 if (pdata->get_context_loss_count) {
567 context_loss = pdata->get_context_loss_count(host->dev);
568 if (context_loss < 0)
572 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
573 context_loss == host->context_loss ? "not " : "");
574 if (host->context_loss == context_loss)
577 /* Wait for hardware reset */
578 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
579 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
580 && time_before(jiffies, timeout))
583 /* Do software reset */
584 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
585 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
586 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
587 && time_before(jiffies, timeout))
590 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
591 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
593 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
594 if (host->power_mode != MMC_POWER_OFF &&
595 (1 << ios->vdd) <= MMC_VDD_23_24)
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
608 OMAP_HSMMC_WRITE(host->base, CAPA,
609 OMAP_HSMMC_READ(host->base, CAPA) | capa);
611 OMAP_HSMMC_WRITE(host->base, HCTL,
612 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
614 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
615 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
616 && time_before(jiffies, timeout))
619 omap_hsmmc_disable_irq(host);
621 /* Do not initialize card-specific things if the power is off */
622 if (host->power_mode == MMC_POWER_OFF)
625 omap_hsmmc_set_bus_width(host);
627 omap_hsmmc_set_clock(host);
629 omap_hsmmc_set_bus_mode(host);
632 host->context_loss = context_loss;
634 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
639 * Save the MMC host context (store the number of power state changes so far).
641 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
643 struct omap_mmc_platform_data *pdata = host->pdata;
646 if (pdata->get_context_loss_count) {
647 context_loss = pdata->get_context_loss_count(host->dev);
648 if (context_loss < 0)
650 host->context_loss = context_loss;
656 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
661 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
668 * Send init stream sequence to card
669 * before sending IDLE command
671 static void send_init_stream(struct omap_hsmmc_host *host)
674 unsigned long timeout;
676 if (host->protect_card)
679 disable_irq(host->irq);
681 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
682 OMAP_HSMMC_WRITE(host->base, CON,
683 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
684 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
686 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
687 while ((reg != CC) && time_before(jiffies, timeout))
688 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
690 OMAP_HSMMC_WRITE(host->base, CON,
691 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
693 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
694 OMAP_HSMMC_READ(host->base, STAT);
696 enable_irq(host->irq);
700 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
704 if (mmc_slot(host).get_cover_state)
705 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
710 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
713 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
714 struct omap_hsmmc_host *host = mmc_priv(mmc);
716 return sprintf(buf, "%s\n",
717 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
720 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
723 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
726 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
727 struct omap_hsmmc_host *host = mmc_priv(mmc);
729 return sprintf(buf, "%s\n", mmc_slot(host).name);
732 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
735 * Configure the response type and send the cmd.
738 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
739 struct mmc_data *data)
741 int cmdreg = 0, resptype = 0, cmdtype = 0;
743 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
744 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
747 omap_hsmmc_enable_irq(host, cmd);
749 host->response_busy = 0;
750 if (cmd->flags & MMC_RSP_PRESENT) {
751 if (cmd->flags & MMC_RSP_136)
753 else if (cmd->flags & MMC_RSP_BUSY) {
755 host->response_busy = 1;
761 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
762 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
763 * a val of 0x3, rest 0x0.
765 if (cmd == host->mrq->stop)
768 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
771 cmdreg |= DP_SELECT | MSBS | BCE;
772 if (data->flags & MMC_DATA_READ)
781 host->req_in_progress = 1;
783 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
784 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
788 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
790 if (data->flags & MMC_DATA_WRITE)
791 return DMA_TO_DEVICE;
793 return DMA_FROM_DEVICE;
796 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
800 spin_lock(&host->irq_lock);
801 host->req_in_progress = 0;
802 dma_ch = host->dma_ch;
803 spin_unlock(&host->irq_lock);
805 omap_hsmmc_disable_irq(host);
806 /* Do not complete the request if DMA is still in progress */
807 if (mrq->data && host->use_dma && dma_ch != -1)
810 mmc_request_done(host->mmc, mrq);
814 * Notify the transfer complete to MMC core
817 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
820 struct mmc_request *mrq = host->mrq;
822 /* TC before CC from CMD6 - don't know why, but it happens */
823 if (host->cmd && host->cmd->opcode == 6 &&
824 host->response_busy) {
825 host->response_busy = 0;
829 omap_hsmmc_request_done(host, mrq);
836 data->bytes_xfered += data->blocks * (data->blksz);
838 data->bytes_xfered = 0;
841 omap_hsmmc_request_done(host, data->mrq);
844 omap_hsmmc_start_command(host, data->stop, NULL);
848 * Notify the core about command completion
851 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
855 if (cmd->flags & MMC_RSP_PRESENT) {
856 if (cmd->flags & MMC_RSP_136) {
857 /* response type 2 */
858 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
859 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
860 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
861 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
863 /* response types 1, 1b, 3, 4, 5, 6 */
864 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
867 if ((host->data == NULL && !host->response_busy) || cmd->error)
868 omap_hsmmc_request_done(host, cmd->mrq);
872 * DMA clean up for command errors
874 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
878 host->data->error = errno;
880 spin_lock(&host->irq_lock);
881 dma_ch = host->dma_ch;
883 spin_unlock(&host->irq_lock);
885 if (host->use_dma && dma_ch != -1) {
886 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
888 omap_hsmmc_get_dma_dir(host, host->data));
889 omap_free_dma(dma_ch);
890 host->data->host_cookie = 0;
896 * Readable error output
898 #ifdef CONFIG_MMC_DEBUG
899 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
901 /* --- means reserved bit without definition at documentation */
902 static const char *omap_hsmmc_status_bits[] = {
903 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
904 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
905 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
906 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
912 len = sprintf(buf, "MMC IRQ 0x%x :", status);
915 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
916 if (status & (1 << i)) {
917 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
921 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
924 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
928 #endif /* CONFIG_MMC_DEBUG */
931 * MMC controller internal state machines reset
933 * Used to reset command or data internal state machines, using respectively
934 * SRC or SRD bit of SYSCTL register
935 * Can be called from interrupt context
937 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
941 unsigned long limit = (loops_per_jiffy *
942 msecs_to_jiffies(MMC_TIMEOUT_MS));
944 OMAP_HSMMC_WRITE(host->base, SYSCTL,
945 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
948 * OMAP4 ES2 and greater has an updated reset logic.
949 * Monitor a 0->1 transition first
951 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
952 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
958 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
962 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
963 dev_err(mmc_dev(host->mmc),
964 "Timeout waiting on controller reset in %s\n",
968 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
970 struct mmc_data *data;
971 int end_cmd = 0, end_trans = 0;
973 if (!host->req_in_progress) {
975 OMAP_HSMMC_WRITE(host->base, STAT, status);
976 /* Flush posted write */
977 status = OMAP_HSMMC_READ(host->base, STAT);
978 } while (status & INT_EN_MASK);
983 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
986 omap_hsmmc_dbg_report_irq(host, status);
987 if ((status & CMD_TIMEOUT) ||
988 (status & CMD_CRC)) {
990 if (status & CMD_TIMEOUT) {
991 omap_hsmmc_reset_controller_fsm(host,
993 host->cmd->error = -ETIMEDOUT;
995 host->cmd->error = -EILSEQ;
999 if (host->data || host->response_busy) {
1001 omap_hsmmc_dma_cleanup(host,
1003 host->response_busy = 0;
1004 omap_hsmmc_reset_controller_fsm(host, SRD);
1007 if ((status & DATA_TIMEOUT) ||
1008 (status & DATA_CRC)) {
1009 if (host->data || host->response_busy) {
1010 int err = (status & DATA_TIMEOUT) ?
1011 -ETIMEDOUT : -EILSEQ;
1014 omap_hsmmc_dma_cleanup(host, err);
1016 host->mrq->cmd->error = err;
1017 host->response_busy = 0;
1018 omap_hsmmc_reset_controller_fsm(host, SRD);
1022 if (status & CARD_ERR) {
1023 dev_dbg(mmc_dev(host->mmc),
1024 "Ignoring card err CMD%d\n", host->cmd->opcode);
1032 OMAP_HSMMC_WRITE(host->base, STAT, status);
1034 if (end_cmd || ((status & CC) && host->cmd))
1035 omap_hsmmc_cmd_done(host, host->cmd);
1036 if ((end_trans || (status & TC)) && host->mrq)
1037 omap_hsmmc_xfer_done(host, data);
1041 * MMC controller IRQ handler
1043 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1045 struct omap_hsmmc_host *host = dev_id;
1048 status = OMAP_HSMMC_READ(host->base, STAT);
1050 omap_hsmmc_do_irq(host, status);
1051 /* Flush posted write */
1052 status = OMAP_HSMMC_READ(host->base, STAT);
1053 } while (status & INT_EN_MASK);
1058 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1062 OMAP_HSMMC_WRITE(host->base, HCTL,
1063 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1064 for (i = 0; i < loops_per_jiffy; i++) {
1065 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1072 * Switch MMC interface voltage ... only relevant for MMC1.
1074 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1075 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1076 * Some chips, like eMMC ones, use internal transceivers.
1078 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1083 /* Disable the clocks */
1084 pm_runtime_put_sync(host->dev);
1085 if (host->got_dbclk)
1086 clk_disable(host->dbclk);
1088 /* Turn the power off */
1089 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1091 /* Turn the power ON with given VDD 1.8 or 3.0v */
1093 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1095 pm_runtime_get_sync(host->dev);
1096 if (host->got_dbclk)
1097 clk_enable(host->dbclk);
1102 OMAP_HSMMC_WRITE(host->base, HCTL,
1103 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1104 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1107 * If a MMC dual voltage card is detected, the set_ios fn calls
1108 * this fn with VDD bit set for 1.8V. Upon card removal from the
1109 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1111 * Cope with a bit of slop in the range ... per data sheets:
1112 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1113 * but recommended values are 1.71V to 1.89V
1114 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1115 * but recommended values are 2.7V to 3.3V
1117 * Board setup code shouldn't permit anything very out-of-range.
1118 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1119 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1121 if ((1 << vdd) <= MMC_VDD_23_24)
1126 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1127 set_sd_bus_power(host);
1131 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1135 /* Protect the card while the cover is open */
1136 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1138 if (!mmc_slot(host).get_cover_state)
1141 host->reqs_blocked = 0;
1142 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1143 if (host->protect_card) {
1144 dev_info(host->dev, "%s: cover is closed, "
1145 "card is now accessible\n",
1146 mmc_hostname(host->mmc));
1147 host->protect_card = 0;
1150 if (!host->protect_card) {
1151 dev_info(host->dev, "%s: cover is open, "
1152 "card is now inaccessible\n",
1153 mmc_hostname(host->mmc));
1154 host->protect_card = 1;
1160 * irq handler to notify the core about card insertion/removal
1162 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1164 struct omap_hsmmc_host *host = dev_id;
1165 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1168 if (host->suspended)
1171 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1173 if (slot->card_detect)
1174 carddetect = slot->card_detect(host->dev, host->slot_id);
1176 omap_hsmmc_protect_card(host);
1177 carddetect = -ENOSYS;
1181 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1183 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1187 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1188 struct mmc_data *data)
1192 if (data->flags & MMC_DATA_WRITE)
1193 sync_dev = host->dma_line_tx;
1195 sync_dev = host->dma_line_rx;
1199 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1200 struct mmc_data *data,
1201 struct scatterlist *sgl)
1203 int blksz, nblk, dma_ch;
1205 dma_ch = host->dma_ch;
1206 if (data->flags & MMC_DATA_WRITE) {
1207 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1208 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1209 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1210 sg_dma_address(sgl), 0, 0);
1212 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1213 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1214 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1215 sg_dma_address(sgl), 0, 0);
1218 blksz = host->data->blksz;
1219 nblk = sg_dma_len(sgl) / blksz;
1221 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1222 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1223 omap_hsmmc_get_dma_sync_dev(host, data),
1224 !(data->flags & MMC_DATA_WRITE));
1226 omap_start_dma(dma_ch);
1230 * DMA call back function
1232 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1234 struct omap_hsmmc_host *host = cb_data;
1235 struct mmc_data *data;
1236 int dma_ch, req_in_progress;
1238 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1239 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1244 spin_lock(&host->irq_lock);
1245 if (host->dma_ch < 0) {
1246 spin_unlock(&host->irq_lock);
1250 data = host->mrq->data;
1252 if (host->dma_sg_idx < host->dma_len) {
1253 /* Fire up the next transfer. */
1254 omap_hsmmc_config_dma_params(host, data,
1255 data->sg + host->dma_sg_idx);
1256 spin_unlock(&host->irq_lock);
1260 if (!data->host_cookie)
1261 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1262 omap_hsmmc_get_dma_dir(host, data));
1264 req_in_progress = host->req_in_progress;
1265 dma_ch = host->dma_ch;
1267 spin_unlock(&host->irq_lock);
1269 omap_free_dma(dma_ch);
1271 /* If DMA has finished after TC, complete the request */
1272 if (!req_in_progress) {
1273 struct mmc_request *mrq = host->mrq;
1276 mmc_request_done(host->mmc, mrq);
1280 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1281 struct mmc_data *data,
1282 struct omap_hsmmc_next *next)
1286 if (!next && data->host_cookie &&
1287 data->host_cookie != host->next_data.cookie) {
1288 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1289 " host->next_data.cookie %d\n",
1290 __func__, data->host_cookie, host->next_data.cookie);
1291 data->host_cookie = 0;
1294 /* Check if next job is already prepared */
1296 (!next && data->host_cookie != host->next_data.cookie)) {
1297 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1299 omap_hsmmc_get_dma_dir(host, data));
1302 dma_len = host->next_data.dma_len;
1303 host->next_data.dma_len = 0;
1311 next->dma_len = dma_len;
1312 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1314 host->dma_len = dma_len;
1320 * Routine to configure and start DMA for the MMC card
1322 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1323 struct mmc_request *req)
1325 int dma_ch = 0, ret = 0, i;
1326 struct mmc_data *data = req->data;
1328 /* Sanity check: all the SG entries must be aligned by block size. */
1329 for (i = 0; i < data->sg_len; i++) {
1330 struct scatterlist *sgl;
1333 if (sgl->length % data->blksz)
1336 if ((data->blksz % 4) != 0)
1337 /* REVISIT: The MMC buffer increments only when MSB is written.
1338 * Return error for blksz which is non multiple of four.
1342 BUG_ON(host->dma_ch != -1);
1344 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1345 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1347 dev_err(mmc_dev(host->mmc),
1348 "%s: omap_request_dma() failed with %d\n",
1349 mmc_hostname(host->mmc), ret);
1352 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1356 host->dma_ch = dma_ch;
1357 host->dma_sg_idx = 0;
1359 omap_hsmmc_config_dma_params(host, data, data->sg);
1364 static void set_data_timeout(struct omap_hsmmc_host *host,
1365 unsigned int timeout_ns,
1366 unsigned int timeout_clks)
1368 unsigned int timeout, cycle_ns;
1369 uint32_t reg, clkd, dto = 0;
1371 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1372 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1376 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1377 timeout = timeout_ns / cycle_ns;
1378 timeout += timeout_clks;
1380 while ((timeout & 0x80000000) == 0) {
1397 reg |= dto << DTO_SHIFT;
1398 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1402 * Configure block length for MMC/SD cards and initiate the transfer.
1405 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1408 host->data = req->data;
1410 if (req->data == NULL) {
1411 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1413 * Set an arbitrary 100ms data timeout for commands with
1416 if (req->cmd->flags & MMC_RSP_BUSY)
1417 set_data_timeout(host, 100000000U, 0);
1421 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1422 | (req->data->blocks << 16));
1423 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1425 if (host->use_dma) {
1426 ret = omap_hsmmc_start_dma_transfer(host, req);
1428 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1435 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1438 struct omap_hsmmc_host *host = mmc_priv(mmc);
1439 struct mmc_data *data = mrq->data;
1441 if (host->use_dma) {
1442 if (data->host_cookie)
1443 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1445 omap_hsmmc_get_dma_dir(host, data));
1446 data->host_cookie = 0;
1450 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1453 struct omap_hsmmc_host *host = mmc_priv(mmc);
1455 if (mrq->data->host_cookie) {
1456 mrq->data->host_cookie = 0;
1461 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1463 mrq->data->host_cookie = 0;
1467 * Request function. for read/write operation
1469 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1471 struct omap_hsmmc_host *host = mmc_priv(mmc);
1474 BUG_ON(host->req_in_progress);
1475 BUG_ON(host->dma_ch != -1);
1476 if (host->protect_card) {
1477 if (host->reqs_blocked < 3) {
1479 * Ensure the controller is left in a consistent
1480 * state by resetting the command and data state
1483 omap_hsmmc_reset_controller_fsm(host, SRD);
1484 omap_hsmmc_reset_controller_fsm(host, SRC);
1485 host->reqs_blocked += 1;
1487 req->cmd->error = -EBADF;
1489 req->data->error = -EBADF;
1490 req->cmd->retries = 0;
1491 mmc_request_done(mmc, req);
1493 } else if (host->reqs_blocked)
1494 host->reqs_blocked = 0;
1495 WARN_ON(host->mrq != NULL);
1497 err = omap_hsmmc_prepare_data(host, req);
1499 req->cmd->error = err;
1501 req->data->error = err;
1503 mmc_request_done(mmc, req);
1507 omap_hsmmc_start_command(host, req->cmd, req->data);
1510 /* Routine to configure clock values. Exposed API to core */
1511 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1513 struct omap_hsmmc_host *host = mmc_priv(mmc);
1514 int do_send_init_stream = 0;
1516 pm_runtime_get_sync(host->dev);
1518 if (ios->power_mode != host->power_mode) {
1519 switch (ios->power_mode) {
1521 mmc_slot(host).set_power(host->dev, host->slot_id,
1526 mmc_slot(host).set_power(host->dev, host->slot_id,
1528 host->vdd = ios->vdd;
1531 do_send_init_stream = 1;
1534 host->power_mode = ios->power_mode;
1537 /* FIXME: set registers based only on changes to ios */
1539 omap_hsmmc_set_bus_width(host);
1541 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1542 /* Only MMC1 can interface at 3V without some flavor
1543 * of external transceiver; but they all handle 1.8V.
1545 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1546 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1548 * With pbias cell programming missing, this
1549 * can't be allowed when booting with device
1552 (!of_have_populated_dt())) {
1554 * The mmc_select_voltage fn of the core does
1555 * not seem to set the power_mode to
1556 * MMC_POWER_UP upon recalculating the voltage.
1559 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1560 dev_dbg(mmc_dev(host->mmc),
1561 "Switch operation failed\n");
1565 omap_hsmmc_set_clock(host);
1567 if (do_send_init_stream)
1568 send_init_stream(host);
1570 omap_hsmmc_set_bus_mode(host);
1572 pm_runtime_put_autosuspend(host->dev);
1575 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1577 struct omap_hsmmc_host *host = mmc_priv(mmc);
1579 if (!mmc_slot(host).card_detect)
1581 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1584 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1586 struct omap_hsmmc_host *host = mmc_priv(mmc);
1588 if (!mmc_slot(host).get_ro)
1590 return mmc_slot(host).get_ro(host->dev, 0);
1593 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1595 struct omap_hsmmc_host *host = mmc_priv(mmc);
1597 if (mmc_slot(host).init_card)
1598 mmc_slot(host).init_card(card);
1601 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1603 u32 hctl, capa, value;
1605 /* Only MMC1 supports 3.0V */
1606 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1614 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1615 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1617 value = OMAP_HSMMC_READ(host->base, CAPA);
1618 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1620 /* Set the controller to AUTO IDLE mode */
1621 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1622 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1624 /* Set SD bus power bit */
1625 set_sd_bus_power(host);
1628 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1630 struct omap_hsmmc_host *host = mmc_priv(mmc);
1632 pm_runtime_get_sync(host->dev);
1637 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1639 struct omap_hsmmc_host *host = mmc_priv(mmc);
1641 pm_runtime_mark_last_busy(host->dev);
1642 pm_runtime_put_autosuspend(host->dev);
1647 static const struct mmc_host_ops omap_hsmmc_ops = {
1648 .enable = omap_hsmmc_enable_fclk,
1649 .disable = omap_hsmmc_disable_fclk,
1650 .post_req = omap_hsmmc_post_req,
1651 .pre_req = omap_hsmmc_pre_req,
1652 .request = omap_hsmmc_request,
1653 .set_ios = omap_hsmmc_set_ios,
1654 .get_cd = omap_hsmmc_get_cd,
1655 .get_ro = omap_hsmmc_get_ro,
1656 .init_card = omap_hsmmc_init_card,
1657 /* NYET -- enable_sdio_irq */
1660 #ifdef CONFIG_DEBUG_FS
1662 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1664 struct mmc_host *mmc = s->private;
1665 struct omap_hsmmc_host *host = mmc_priv(mmc);
1666 int context_loss = 0;
1668 if (host->pdata->get_context_loss_count)
1669 context_loss = host->pdata->get_context_loss_count(host->dev);
1671 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1672 mmc->index, host->context_loss, context_loss);
1674 if (host->suspended) {
1675 seq_printf(s, "host suspended, can't read registers\n");
1679 pm_runtime_get_sync(host->dev);
1681 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1682 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1683 seq_printf(s, "CON:\t\t0x%08x\n",
1684 OMAP_HSMMC_READ(host->base, CON));
1685 seq_printf(s, "HCTL:\t\t0x%08x\n",
1686 OMAP_HSMMC_READ(host->base, HCTL));
1687 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1688 OMAP_HSMMC_READ(host->base, SYSCTL));
1689 seq_printf(s, "IE:\t\t0x%08x\n",
1690 OMAP_HSMMC_READ(host->base, IE));
1691 seq_printf(s, "ISE:\t\t0x%08x\n",
1692 OMAP_HSMMC_READ(host->base, ISE));
1693 seq_printf(s, "CAPA:\t\t0x%08x\n",
1694 OMAP_HSMMC_READ(host->base, CAPA));
1696 pm_runtime_mark_last_busy(host->dev);
1697 pm_runtime_put_autosuspend(host->dev);
1702 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1704 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1707 static const struct file_operations mmc_regs_fops = {
1708 .open = omap_hsmmc_regs_open,
1710 .llseek = seq_lseek,
1711 .release = single_release,
1714 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1716 if (mmc->debugfs_root)
1717 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1718 mmc, &mmc_regs_fops);
1723 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1730 static u16 omap4_reg_offset = 0x100;
1732 static const struct of_device_id omap_mmc_of_match[] = {
1734 .compatible = "ti,omap2-hsmmc",
1737 .compatible = "ti,omap3-hsmmc",
1740 .compatible = "ti,omap4-hsmmc",
1741 .data = &omap4_reg_offset,
1745 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1747 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1749 struct omap_mmc_platform_data *pdata;
1750 struct device_node *np = dev->of_node;
1753 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1755 return NULL; /* out of memory */
1757 if (of_find_property(np, "ti,dual-volt", NULL))
1758 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1760 /* This driver only supports 1 slot */
1761 pdata->nr_slots = 1;
1762 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1763 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1765 if (of_find_property(np, "ti,non-removable", NULL)) {
1766 pdata->slots[0].nonremovable = true;
1767 pdata->slots[0].no_regulator_off_init = true;
1769 of_property_read_u32(np, "ti,bus-width", &bus_width);
1771 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1772 else if (bus_width == 8)
1773 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1775 if (of_find_property(np, "ti,needs-special-reset", NULL))
1776 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1781 static inline struct omap_mmc_platform_data
1782 *of_get_hsmmc_pdata(struct device *dev)
1788 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1790 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1791 struct mmc_host *mmc;
1792 struct omap_hsmmc_host *host = NULL;
1793 struct resource *res;
1795 const struct of_device_id *match;
1797 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1799 pdata = of_get_hsmmc_pdata(&pdev->dev);
1801 u16 *offsetp = match->data;
1802 pdata->reg_offset = *offsetp;
1806 if (pdata == NULL) {
1807 dev_err(&pdev->dev, "Platform Data is missing\n");
1811 if (pdata->nr_slots == 0) {
1812 dev_err(&pdev->dev, "No Slots\n");
1816 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1817 irq = platform_get_irq(pdev, 0);
1818 if (res == NULL || irq < 0)
1821 res->start += pdata->reg_offset;
1822 res->end += pdata->reg_offset;
1823 res = request_mem_region(res->start, resource_size(res), pdev->name);
1827 ret = omap_hsmmc_gpio_init(pdata);
1831 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1837 host = mmc_priv(mmc);
1839 host->pdata = pdata;
1840 host->dev = &pdev->dev;
1842 host->dev->dma_mask = &pdata->dma_mask;
1846 host->mapbase = res->start;
1847 host->base = ioremap(host->mapbase, SZ_4K);
1848 host->power_mode = MMC_POWER_OFF;
1849 host->next_data.cookie = 1;
1851 platform_set_drvdata(pdev, host);
1853 mmc->ops = &omap_hsmmc_ops;
1856 * If regulator_disable can only put vcc_aux to sleep then there is
1859 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1860 mmc_slot(host).no_off = 1;
1862 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1864 if (pdata->max_freq > 0)
1865 mmc->f_max = pdata->max_freq;
1867 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1869 spin_lock_init(&host->irq_lock);
1871 host->fclk = clk_get(&pdev->dev, "fck");
1872 if (IS_ERR(host->fclk)) {
1873 ret = PTR_ERR(host->fclk);
1878 omap_hsmmc_context_save(host);
1880 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1881 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1882 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1885 pm_runtime_enable(host->dev);
1886 pm_runtime_get_sync(host->dev);
1887 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1888 pm_runtime_use_autosuspend(host->dev);
1890 if (cpu_is_omap2430()) {
1891 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1893 * MMC can still work without debounce clock.
1895 if (IS_ERR(host->dbclk))
1896 dev_warn(mmc_dev(host->mmc),
1897 "Failed to get debounce clock\n");
1899 host->got_dbclk = 1;
1901 if (host->got_dbclk)
1902 if (clk_enable(host->dbclk) != 0)
1903 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1907 /* Since we do only SG emulation, we can have as many segs
1909 mmc->max_segs = 1024;
1911 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1912 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1913 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1914 mmc->max_seg_size = mmc->max_req_size;
1916 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1917 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1919 mmc->caps |= mmc_slot(host).caps;
1920 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1921 mmc->caps |= MMC_CAP_4_BIT_DATA;
1923 if (mmc_slot(host).nonremovable)
1924 mmc->caps |= MMC_CAP_NONREMOVABLE;
1926 mmc->pm_caps = mmc_slot(host).pm_caps;
1928 omap_hsmmc_conf_bus_power(host);
1930 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1932 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1935 host->dma_line_tx = res->start;
1937 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1939 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1942 host->dma_line_rx = res->start;
1944 /* Request IRQ for MMC operations */
1945 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1946 mmc_hostname(mmc), host);
1948 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1952 if (pdata->init != NULL) {
1953 if (pdata->init(&pdev->dev) != 0) {
1954 dev_dbg(mmc_dev(host->mmc),
1955 "Unable to configure MMC IRQs\n");
1956 goto err_irq_cd_init;
1960 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1961 ret = omap_hsmmc_reg_get(host);
1967 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1969 /* Request IRQ for card detect */
1970 if ((mmc_slot(host).card_detect_irq)) {
1971 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1974 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1975 mmc_hostname(mmc), host);
1977 dev_dbg(mmc_dev(host->mmc),
1978 "Unable to grab MMC CD IRQ\n");
1981 pdata->suspend = omap_hsmmc_suspend_cdirq;
1982 pdata->resume = omap_hsmmc_resume_cdirq;
1985 omap_hsmmc_disable_irq(host);
1987 omap_hsmmc_protect_card(host);
1991 if (mmc_slot(host).name != NULL) {
1992 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1996 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1997 ret = device_create_file(&mmc->class_dev,
1998 &dev_attr_cover_switch);
2003 omap_hsmmc_debugfs(mmc);
2004 pm_runtime_mark_last_busy(host->dev);
2005 pm_runtime_put_autosuspend(host->dev);
2010 mmc_remove_host(mmc);
2011 free_irq(mmc_slot(host).card_detect_irq, host);
2014 omap_hsmmc_reg_put(host);
2016 if (host->pdata->cleanup)
2017 host->pdata->cleanup(&pdev->dev);
2019 free_irq(host->irq, host);
2021 pm_runtime_mark_last_busy(host->dev);
2022 pm_runtime_put_autosuspend(host->dev);
2023 pm_runtime_disable(host->dev);
2024 clk_put(host->fclk);
2025 if (host->got_dbclk) {
2026 clk_disable(host->dbclk);
2027 clk_put(host->dbclk);
2030 iounmap(host->base);
2031 platform_set_drvdata(pdev, NULL);
2034 omap_hsmmc_gpio_free(pdata);
2036 release_mem_region(res->start, resource_size(res));
2040 static int omap_hsmmc_remove(struct platform_device *pdev)
2042 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2043 struct resource *res;
2046 pm_runtime_get_sync(host->dev);
2047 mmc_remove_host(host->mmc);
2049 omap_hsmmc_reg_put(host);
2050 if (host->pdata->cleanup)
2051 host->pdata->cleanup(&pdev->dev);
2052 free_irq(host->irq, host);
2053 if (mmc_slot(host).card_detect_irq)
2054 free_irq(mmc_slot(host).card_detect_irq, host);
2056 pm_runtime_put_sync(host->dev);
2057 pm_runtime_disable(host->dev);
2058 clk_put(host->fclk);
2059 if (host->got_dbclk) {
2060 clk_disable(host->dbclk);
2061 clk_put(host->dbclk);
2064 mmc_free_host(host->mmc);
2065 iounmap(host->base);
2066 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2069 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2071 release_mem_region(res->start, resource_size(res));
2072 platform_set_drvdata(pdev, NULL);
2078 static int omap_hsmmc_suspend(struct device *dev)
2081 struct platform_device *pdev = to_platform_device(dev);
2082 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2084 if (host && host->suspended)
2088 pm_runtime_get_sync(host->dev);
2089 host->suspended = 1;
2090 if (host->pdata->suspend) {
2091 ret = host->pdata->suspend(&pdev->dev,
2094 dev_dbg(mmc_dev(host->mmc),
2095 "Unable to handle MMC board"
2096 " level suspend\n");
2097 host->suspended = 0;
2101 ret = mmc_suspend_host(host->mmc);
2104 host->suspended = 0;
2105 if (host->pdata->resume) {
2106 ret = host->pdata->resume(&pdev->dev,
2109 dev_dbg(mmc_dev(host->mmc),
2110 "Unmask interrupt failed\n");
2115 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2116 omap_hsmmc_disable_irq(host);
2117 OMAP_HSMMC_WRITE(host->base, HCTL,
2118 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2120 if (host->got_dbclk)
2121 clk_disable(host->dbclk);
2125 pm_runtime_put_sync(host->dev);
2129 /* Routine to resume the MMC device */
2130 static int omap_hsmmc_resume(struct device *dev)
2133 struct platform_device *pdev = to_platform_device(dev);
2134 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2136 if (host && !host->suspended)
2140 pm_runtime_get_sync(host->dev);
2142 if (host->got_dbclk)
2143 clk_enable(host->dbclk);
2145 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2146 omap_hsmmc_conf_bus_power(host);
2148 if (host->pdata->resume) {
2149 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2151 dev_dbg(mmc_dev(host->mmc),
2152 "Unmask interrupt failed\n");
2155 omap_hsmmc_protect_card(host);
2157 /* Notify the core to resume the host */
2158 ret = mmc_resume_host(host->mmc);
2160 host->suspended = 0;
2162 pm_runtime_mark_last_busy(host->dev);
2163 pm_runtime_put_autosuspend(host->dev);
2171 #define omap_hsmmc_suspend NULL
2172 #define omap_hsmmc_resume NULL
2175 static int omap_hsmmc_runtime_suspend(struct device *dev)
2177 struct omap_hsmmc_host *host;
2179 host = platform_get_drvdata(to_platform_device(dev));
2180 omap_hsmmc_context_save(host);
2181 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2186 static int omap_hsmmc_runtime_resume(struct device *dev)
2188 struct omap_hsmmc_host *host;
2190 host = platform_get_drvdata(to_platform_device(dev));
2191 omap_hsmmc_context_restore(host);
2192 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2197 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2198 .suspend = omap_hsmmc_suspend,
2199 .resume = omap_hsmmc_resume,
2200 .runtime_suspend = omap_hsmmc_runtime_suspend,
2201 .runtime_resume = omap_hsmmc_runtime_resume,
2204 static struct platform_driver omap_hsmmc_driver = {
2205 .remove = omap_hsmmc_remove,
2207 .name = DRIVER_NAME,
2208 .owner = THIS_MODULE,
2209 .pm = &omap_hsmmc_dev_pm_ops,
2210 .of_match_table = of_match_ptr(omap_mmc_of_match),
2214 static int __init omap_hsmmc_init(void)
2216 /* Register the MMC driver */
2217 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2220 static void __exit omap_hsmmc_cleanup(void)
2222 /* Unregister MMC driver */
2223 platform_driver_unregister(&omap_hsmmc_driver);
2226 module_init(omap_hsmmc_init);
2227 module_exit(omap_hsmmc_cleanup);
2229 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2230 MODULE_LICENSE("GPL");
2231 MODULE_ALIAS("platform:" DRIVER_NAME);
2232 MODULE_AUTHOR("Texas Instruments Inc");