drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/omap-dmaengine.h>
  36 #include <linux/mmc/host.h>
  37 #include <linux/mmc/core.h>
  38 #include <linux/mmc/mmc.h>
  39 #include <linux/mmc/slot-gpio.h>
  40 #include <linux/io.h>
  41 #include <linux/irq.h>
  42 #include <linux/gpio.h>
  43 #include <linux/regulator/consumer.h>
  44 #include <linux/pinctrl/consumer.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/platform_data/hsmmc-omap.h>
  47
  48 /* OMAP HSMMC Host Controller Registers */
  49 #define OMAP_HSMMC_SYSSTATUS    0x0014
  50 #define OMAP_HSMMC_CON          0x002C
  51 #define OMAP_HSMMC_SDMASA       0x0100
  52 #define OMAP_HSMMC_BLK          0x0104
  53 #define OMAP_HSMMC_ARG          0x0108
  54 #define OMAP_HSMMC_CMD          0x010C
  55 #define OMAP_HSMMC_RSP10        0x0110
  56 #define OMAP_HSMMC_RSP32        0x0114
  57 #define OMAP_HSMMC_RSP54        0x0118
  58 #define OMAP_HSMMC_RSP76        0x011C
  59 #define OMAP_HSMMC_DATA         0x0120
  60 #define OMAP_HSMMC_PSTATE       0x0124
  61 #define OMAP_HSMMC_HCTL         0x0128
  62 #define OMAP_HSMMC_SYSCTL       0x012C
  63 #define OMAP_HSMMC_STAT         0x0130
  64 #define OMAP_HSMMC_IE           0x0134
  65 #define OMAP_HSMMC_ISE          0x0138
  66 #define OMAP_HSMMC_AC12         0x013C
  67 #define OMAP_HSMMC_CAPA         0x0140
  68
  69 #define VS18                    (1 << 26)
  70 #define VS30                    (1 << 25)
  71 #define HSS                     (1 << 21)
  72 #define SDVS18                  (0x5 << 9)
  73 #define SDVS30                  (0x6 << 9)
  74 #define SDVS33                  (0x7 << 9)
  75 #define SDVS_MASK               0x00000E00
  76 #define SDVSCLR                 0xFFFFF1FF
  77 #define SDVSDET                 0x00000400
  78 #define AUTOIDLE                0x1
  79 #define SDBP                    (1 << 8)
  80 #define DTO                     0xe
  81 #define ICE                     0x1
  82 #define ICS                     0x2
  83 #define CEN                     (1 << 2)
  84 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  85 #define CLKD_MASK               0x0000FFC0
  86 #define CLKD_SHIFT              6
  87 #define DTO_MASK                0x000F0000
  88 #define DTO_SHIFT               16
  89 #define INIT_STREAM             (1 << 1)
  90 #define ACEN_ACMD23             (2 << 2)
  91 #define DP_SELECT               (1 << 21)
  92 #define DDIR                    (1 << 4)
  93 #define DMAE                    0x1
  94 #define MSBS                    (1 << 5)
  95 #define BCE                     (1 << 1)
  96 #define FOUR_BIT                (1 << 1)
  97 #define HSPE                    (1 << 2)
  98 #define IWE                     (1 << 24)
  99 #define DDR                     (1 << 19)
 100 #define CLKEXTFREE              (1 << 16)
 101 #define CTPL                    (1 << 11)
 102 #define DW8                     (1 << 5)
 103 #define OD                      0x1
 104 #define STAT_CLEAR              0xFFFFFFFF
 105 #define INIT_STREAM_CMD         0x00000000
 106 #define DUAL_VOLT_OCR_BIT       7
 107 #define SRC                     (1 << 25)
 108 #define SRD                     (1 << 26)
 109 #define SOFTRESET               (1 << 1)
 110
 111 /* PSTATE */
 112 #define DLEV_DAT(x)             (1 << (20 + (x)))
 113
 114 /* Interrupt masks for IE and ISE register */
 115 #define CC_EN                   (1 << 0)
 116 #define TC_EN                   (1 << 1)
 117 #define BWR_EN                  (1 << 4)
 118 #define BRR_EN                  (1 << 5)
 119 #define CIRQ_EN                 (1 << 8)
 120 #define ERR_EN                  (1 << 15)
 121 #define CTO_EN                  (1 << 16)
 122 #define CCRC_EN                 (1 << 17)
 123 #define CEB_EN                  (1 << 18)
 124 #define CIE_EN                  (1 << 19)
 125 #define DTO_EN                  (1 << 20)
 126 #define DCRC_EN                 (1 << 21)
 127 #define DEB_EN                  (1 << 22)
 128 #define ACE_EN                  (1 << 24)
 129 #define CERR_EN                 (1 << 28)
 130 #define BADA_EN                 (1 << 29)
 131
 132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 133                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 134                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 135
 136 #define CNI     (1 << 7)
 137 #define ACIE    (1 << 4)
 138 #define ACEB    (1 << 3)
 139 #define ACCE    (1 << 2)
 140 #define ACTO    (1 << 1)
 141 #define ACNE    (1 << 0)
 142
 143 #define MMC_AUTOSUSPEND_DELAY   100
 144 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 145 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 146 #define OMAP_MMC_MIN_CLOCK      400000
 147 #define OMAP_MMC_MAX_CLOCK      52000000
 148 #define DRIVER_NAME             "omap_hsmmc"
 149
 150 #define VDD_1V8                 1800000         /* 180000 uV */
 151 #define VDD_3V0                 3000000         /* 300000 uV */
 152 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
 153
 154 /*
 155  * One controller can have multiple slots, like on some omap boards using
 156  * omap.c controller driver. Luckily this is not currently done on any known
 157  * omap_hsmmc.c device.
 158  */
 159 #define mmc_pdata(host)         host->pdata
 160
 161 /*
 162  * MMC Host controller read/write API's
 163  */
 164 #define OMAP_HSMMC_READ(base, reg)      \
 165         __raw_readl((base) + OMAP_HSMMC_##reg)
 166
 167 #define OMAP_HSMMC_WRITE(base, reg, val) \
 168         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 169
 170 struct omap_hsmmc_next {
 171         unsigned int    dma_len;
 172         s32             cookie;
 173 };
 174
 175 struct omap_hsmmc_host {
 176         struct  device          *dev;
 177         struct  mmc_host        *mmc;
 178         struct  mmc_request     *mrq;
 179         struct  mmc_command     *cmd;
 180         struct  mmc_data        *data;
 181         struct  clk             *fclk;
 182         struct  clk             *dbclk;
 183         /*
 184          * vcc == configured supply
 185          * vcc_aux == optional
 186          *   -  MMC1, supply for DAT4..DAT7
 187          *   -  MMC2/MMC2, external level shifter voltage supply, for
 188          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 189          */
 190         struct  regulator       *vcc;
 191         struct  regulator       *vcc_aux;
 192         struct  regulator       *pbias;
 193         bool                    pbias_enabled;
 194         void    __iomem         *base;
 195         resource_size_t         mapbase;
 196         spinlock_t              irq_lock; /* Prevent races with irq handler */
 197         unsigned int            dma_len;
 198         unsigned int            dma_sg_idx;
 199         unsigned char           bus_mode;
 200         unsigned char           power_mode;
 201         int                     suspended;
 202         u32                     con;
 203         u32                     hctl;
 204         u32                     sysctl;
 205         u32                     capa;
 206         int                     irq;
 207         int                     wake_irq;
 208         int                     use_dma, dma_ch;
 209         struct dma_chan         *tx_chan;
 210         struct dma_chan         *rx_chan;
 211         int                     response_busy;
 212         int                     context_loss;
 213         int                     protect_card;
 214         int                     reqs_blocked;
 215         int                     use_reg;
 216         int                     req_in_progress;
 217         unsigned long           clk_rate;
 218         unsigned int            flags;
 219 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 220 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 221 #define HSMMC_WAKE_IRQ_ENABLED  (1 << 2)
 222         struct omap_hsmmc_next  next_data;
 223         struct  omap_hsmmc_platform_data        *pdata;
 224
 225         /* return MMC cover switch state, can be NULL if not supported.
 226          *
 227          * possible return values:
 228          *   0 - closed
 229          *   1 - open
 230          */
 231         int (*get_cover_state)(struct device *dev);
 232
 233         /* Card detection IRQs */
 234         int card_detect_irq;
 235
 236         int (*card_detect)(struct device *dev);
 237 };
 238
 239 struct omap_mmc_of_data {
 240         u32 reg_offset;
 241         u8 controller_flags;
 242 };
 243
 244 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 245
 246 static int omap_hsmmc_card_detect(struct device *dev)
 247 {
 248         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 249
 250         return mmc_gpio_get_cd(host->mmc);
 251 }
 252
 253 static int omap_hsmmc_get_cover_state(struct device *dev)
 254 {
 255         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 256
 257         return mmc_gpio_get_cd(host->mmc);
 258 }
 259
 260 #ifdef CONFIG_REGULATOR
 261
 262 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
 263 {
 264         struct omap_hsmmc_host *host =
 265                 platform_get_drvdata(to_platform_device(dev));
 266         int ret = 0;
 267
 268         /*
 269          * If we don't see a Vcc regulator, assume it's a fixed
 270          * voltage always-on regulator.
 271          */
 272         if (!host->vcc)
 273                 return 0;
 274
 275         if (mmc_pdata(host)->before_set_reg)
 276                 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
 277
 278         if (host->pbias) {
 279                 if (host->pbias_enabled == 1) {
 280                         ret = regulator_disable(host->pbias);
 281                         if (!ret)
 282                                 host->pbias_enabled = 0;
 283                 }
 284                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
 285         }
 286
 287         /*
 288          * Assume Vcc regulator is used only to power the card ... OMAP
 289          * VDDS is used to power the pins, optionally with a transceiver to
 290          * support cards using voltages other than VDDS (1.8V nominal).  When a
 291          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 292          *
 293          * In some cases this regulator won't support enable/disable;
 294          * e.g. it's a fixed rail for a WLAN chip.
 295          *
 296          * In other cases vcc_aux switches interface power.  Example, for
 297          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 298          * chips/cards need an interface voltage rail too.
 299          */
 300         if (power_on) {
 301                 if (host->vcc)
 302                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 303                 /* Enable interface voltage rail, if needed */
 304                 if (ret == 0 && host->vcc_aux) {
 305                         ret = regulator_enable(host->vcc_aux);
 306                         if (ret < 0 && host->vcc)
 307                                 ret = mmc_regulator_set_ocr(host->mmc,
 308                                                         host->vcc, 0);
 309                 }
 310         } else {
 311                 /* Shut down the rail */
 312                 if (host->vcc_aux)
 313                         ret = regulator_disable(host->vcc_aux);
 314                 if (host->vcc) {
 315                         /* Then proceed to shut down the local regulator */
 316                         ret = mmc_regulator_set_ocr(host->mmc,
 317                                                 host->vcc, 0);
 318                 }
 319         }
 320
 321         if (host->pbias) {
 322                 if (vdd <= VDD_165_195)
 323                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
 324                                                                 VDD_1V8);
 325                 else
 326                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
 327                                                                 VDD_3V0);
 328                 if (ret < 0)
 329                         goto error_set_power;
 330
 331                 if (host->pbias_enabled == 0) {
 332                         ret = regulator_enable(host->pbias);
 333                         if (!ret)
 334                                 host->pbias_enabled = 1;
 335                 }
 336         }
 337
 338         if (mmc_pdata(host)->after_set_reg)
 339                 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
 340
 341 error_set_power:
 342         return ret;
 343 }
 344
 345 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 346 {
 347         struct regulator *reg;
 348         int ocr_value = 0;
 349
 350         reg = devm_regulator_get(host->dev, "vmmc");
 351         if (IS_ERR(reg)) {
 352                 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
 353                         PTR_ERR(reg));
 354                 return PTR_ERR(reg);
 355         } else {
 356                 host->vcc = reg;
 357                 ocr_value = mmc_regulator_get_ocrmask(reg);
 358                 if (!mmc_pdata(host)->ocr_mask) {
 359                         mmc_pdata(host)->ocr_mask = ocr_value;
 360                 } else {
 361                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
 362                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 363                                         mmc_pdata(host)->ocr_mask);
 364                                 mmc_pdata(host)->ocr_mask = 0;
 365                                 return -EINVAL;
 366                         }
 367                 }
 368         }
 369         mmc_pdata(host)->set_power = omap_hsmmc_set_power;
 370
 371         /* Allow an aux regulator */
 372         reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
 373         host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 374
 375         reg = devm_regulator_get_optional(host->dev, "pbias");
 376         host->pbias = IS_ERR(reg) ? NULL : reg;
 377
 378         /* For eMMC do not power off when not in sleep state */
 379         if (mmc_pdata(host)->no_regulator_off_init)
 380                 return 0;
 381         /*
 382          * To disable boot_on regulator, enable regulator
 383          * to increase usecount and then disable it.
 384          */
 385         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
 386             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 387                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
 388
 389                 mmc_pdata(host)->set_power(host->dev, 1, vdd);
 390                 mmc_pdata(host)->set_power(host->dev, 0, 0);
 391         }
 392
 393         return 0;
 394 }
 395
 396 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 397 {
 398         mmc_pdata(host)->set_power = NULL;
 399 }
 400
 401 static inline int omap_hsmmc_have_reg(void)
 402 {
 403         return 1;
 404 }
 405
 406 #else
 407
 408 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 409 {
 410         return -EINVAL;
 411 }
 412
 413 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 414 {
 415 }
 416
 417 static inline int omap_hsmmc_have_reg(void)
 418 {
 419         return 0;
 420 }
 421
 422 #endif
 423
 424 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id);
 425
 426 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
 427                                 struct omap_hsmmc_host *host,
 428                                 struct omap_hsmmc_platform_data *pdata)
 429 {
 430         int ret;
 431
 432         if (gpio_is_valid(pdata->switch_pin)) {
 433                 if (pdata->cover)
 434                         host->get_cover_state =
 435                                 omap_hsmmc_get_cover_state;
 436                 else
 437                         host->card_detect = omap_hsmmc_card_detect;
 438                 host->card_detect_irq =
 439                                 gpio_to_irq(pdata->switch_pin);
 440                 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_detect);
 441                 ret = mmc_gpio_request_cd(mmc, pdata->switch_pin, 0);
 442                 if (ret)
 443                         return ret;
 444         } else {
 445                 pdata->switch_pin = -EINVAL;
 446         }
 447
 448         if (gpio_is_valid(pdata->gpio_wp)) {
 449                 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
 450                 if (ret)
 451                         return ret;
 452         }
 453
 454         return 0;
 455 }
 456
 457 /*
 458  * Start clock to the card
 459  */
 460 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 461 {
 462         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 463                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 464 }
 465
 466 /*
 467  * Stop clock to the card
 468  */
 469 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 470 {
 471         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 472                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 473         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 474                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 475 }
 476
 477 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 478                                   struct mmc_command *cmd)
 479 {
 480         u32 irq_mask = INT_EN_MASK;
 481         unsigned long flags;
 482
 483         if (host->use_dma)
 484                 irq_mask &= ~(BRR_EN | BWR_EN);
 485
 486         /* Disable timeout for erases */
 487         if (cmd->opcode == MMC_ERASE)
 488                 irq_mask &= ~DTO_EN;
 489
 490         spin_lock_irqsave(&host->irq_lock, flags);
 491         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 492         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 493
 494         /* latch pending CIRQ, but don't signal MMC core */
 495         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 496                 irq_mask |= CIRQ_EN;
 497         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 498         spin_unlock_irqrestore(&host->irq_lock, flags);
 499 }
 500
 501 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 502 {
 503         u32 irq_mask = 0;
 504         unsigned long flags;
 505
 506         spin_lock_irqsave(&host->irq_lock, flags);
 507         /* no transfer running but need to keep cirq if enabled */
 508         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 509                 irq_mask |= CIRQ_EN;
 510         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 511         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 512         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 513         spin_unlock_irqrestore(&host->irq_lock, flags);
 514 }
 515
 516 /* Calculate divisor for the given clock frequency */
 517 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 518 {
 519         u16 dsor = 0;
 520
 521         if (ios->clock) {
 522                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 523                 if (dsor > CLKD_MAX)
 524                         dsor = CLKD_MAX;
 525         }
 526
 527         return dsor;
 528 }
 529
 530 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 531 {
 532         struct mmc_ios *ios = &host->mmc->ios;
 533         unsigned long regval;
 534         unsigned long timeout;
 535         unsigned long clkdiv;
 536
 537         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 538
 539         omap_hsmmc_stop_clock(host);
 540
 541         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 542         regval = regval & ~(CLKD_MASK | DTO_MASK);
 543         clkdiv = calc_divisor(host, ios);
 544         regval = regval | (clkdiv << 6) | (DTO << 16);
 545         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 546         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 547                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 548
 549         /* Wait till the ICS bit is set */
 550         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 551         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 552                 && time_before(jiffies, timeout))
 553                 cpu_relax();
 554
 555         /*
 556          * Enable High-Speed Support
 557          * Pre-Requisites
 558          *      - Controller should support High-Speed-Enable Bit
 559          *      - Controller should not be using DDR Mode
 560          *      - Controller should advertise that it supports High Speed
 561          *        in capabilities register
 562          *      - MMC/SD clock coming out of controller > 25MHz
 563          */
 564         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 565             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 566             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 567             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 568                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 569                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 570                         regval |= HSPE;
 571                 else
 572                         regval &= ~HSPE;
 573
 574                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 575         }
 576
 577         omap_hsmmc_start_clock(host);
 578 }
 579
 580 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 581 {
 582         struct mmc_ios *ios = &host->mmc->ios;
 583         u32 con;
 584
 585         con = OMAP_HSMMC_READ(host->base, CON);
 586         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
 587             ios->timing == MMC_TIMING_UHS_DDR50)
 588                 con |= DDR;     /* configure in DDR mode */
 589         else
 590                 con &= ~DDR;
 591         switch (ios->bus_width) {
 592         case MMC_BUS_WIDTH_8:
 593                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 594                 break;
 595         case MMC_BUS_WIDTH_4:
 596                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 597                 OMAP_HSMMC_WRITE(host->base, HCTL,
 598                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 599                 break;
 600         case MMC_BUS_WIDTH_1:
 601                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 602                 OMAP_HSMMC_WRITE(host->base, HCTL,
 603                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 604                 break;
 605         }
 606 }
 607
 608 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 609 {
 610         struct mmc_ios *ios = &host->mmc->ios;
 611         u32 con;
 612
 613         con = OMAP_HSMMC_READ(host->base, CON);
 614         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 615                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 616         else
 617                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 618 }
 619
 620 #ifdef CONFIG_PM
 621
 622 /*
 623  * Restore the MMC host context, if it was lost as result of a
 624  * power state change.
 625  */
 626 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 627 {
 628         struct mmc_ios *ios = &host->mmc->ios;
 629         u32 hctl, capa;
 630         unsigned long timeout;
 631
 632         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 633             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 634             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 635             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 636                 return 0;
 637
 638         host->context_loss++;
 639
 640         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 641                 if (host->power_mode != MMC_POWER_OFF &&
 642                     (1 << ios->vdd) <= MMC_VDD_23_24)
 643                         hctl = SDVS18;
 644                 else
 645                         hctl = SDVS30;
 646                 capa = VS30 | VS18;
 647         } else {
 648                 hctl = SDVS18;
 649                 capa = VS18;
 650         }
 651
 652         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 653                 hctl |= IWE;
 654
 655         OMAP_HSMMC_WRITE(host->base, HCTL,
 656                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 657
 658         OMAP_HSMMC_WRITE(host->base, CAPA,
 659                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 660
 661         OMAP_HSMMC_WRITE(host->base, HCTL,
 662                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 663
 664         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 665         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 666                 && time_before(jiffies, timeout))
 667                 ;
 668
 669         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 670         OMAP_HSMMC_WRITE(host->base, IE, 0);
 671         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 672
 673         /* Do not initialize card-specific things if the power is off */
 674         if (host->power_mode == MMC_POWER_OFF)
 675                 goto out;
 676
 677         omap_hsmmc_set_bus_width(host);
 678
 679         omap_hsmmc_set_clock(host);
 680
 681         omap_hsmmc_set_bus_mode(host);
 682
 683 out:
 684         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 685                 host->context_loss);
 686         return 0;
 687 }
 688
 689 /*
 690  * Save the MMC host context (store the number of power state changes so far).
 691  */
 692 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 693 {
 694         host->con =  OMAP_HSMMC_READ(host->base, CON);
 695         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 696         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 697         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 698 }
 699
 700 #else
 701
 702 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 703 {
 704         return 0;
 705 }
 706
 707 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 708 {
 709 }
 710
 711 #endif
 712
 713 /*
 714  * Send init stream sequence to card
 715  * before sending IDLE command
 716  */
 717 static void send_init_stream(struct omap_hsmmc_host *host)
 718 {
 719         int reg = 0;
 720         unsigned long timeout;
 721
 722         if (host->protect_card)
 723                 return;
 724
 725         disable_irq(host->irq);
 726
 727         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 728         OMAP_HSMMC_WRITE(host->base, CON,
 729                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 730         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 731
 732         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 733         while ((reg != CC_EN) && time_before(jiffies, timeout))
 734                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 735
 736         OMAP_HSMMC_WRITE(host->base, CON,
 737                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 738
 739         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 740         OMAP_HSMMC_READ(host->base, STAT);
 741
 742         enable_irq(host->irq);
 743 }
 744
 745 static inline
 746 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 747 {
 748         int r = 1;
 749
 750         if (host->get_cover_state)
 751                 r = host->get_cover_state(host->dev);
 752         return r;
 753 }
 754
 755 static ssize_t
 756 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 757                            char *buf)
 758 {
 759         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 760         struct omap_hsmmc_host *host = mmc_priv(mmc);
 761
 762         return sprintf(buf, "%s\n",
 763                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 764 }
 765
 766 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 767
 768 static ssize_t
 769 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 770                         char *buf)
 771 {
 772         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 773         struct omap_hsmmc_host *host = mmc_priv(mmc);
 774
 775         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 776 }
 777
 778 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 779
 780 /*
 781  * Configure the response type and send the cmd.
 782  */
 783 static void
 784 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 785         struct mmc_data *data)
 786 {
 787         int cmdreg = 0, resptype = 0, cmdtype = 0;
 788
 789         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 790                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 791         host->cmd = cmd;
 792
 793         omap_hsmmc_enable_irq(host, cmd);
 794
 795         host->response_busy = 0;
 796         if (cmd->flags & MMC_RSP_PRESENT) {
 797                 if (cmd->flags & MMC_RSP_136)
 798                         resptype = 1;
 799                 else if (cmd->flags & MMC_RSP_BUSY) {
 800                         resptype = 3;
 801                         host->response_busy = 1;
 802                 } else
 803                         resptype = 2;
 804         }
 805
 806         /*
 807          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 808          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 809          * a val of 0x3, rest 0x0.
 810          */
 811         if (cmd == host->mrq->stop)
 812                 cmdtype = 0x3;
 813
 814         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 815
 816         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 817             host->mrq->sbc) {
 818                 cmdreg |= ACEN_ACMD23;
 819                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 820         }
 821         if (data) {
 822                 cmdreg |= DP_SELECT | MSBS | BCE;
 823                 if (data->flags & MMC_DATA_READ)
 824                         cmdreg |= DDIR;
 825                 else
 826                         cmdreg &= ~(DDIR);
 827         }
 828
 829         if (host->use_dma)
 830                 cmdreg |= DMAE;
 831
 832         host->req_in_progress = 1;
 833
 834         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 835         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 836 }
 837
 838 static int
 839 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 840 {
 841         if (data->flags & MMC_DATA_WRITE)
 842                 return DMA_TO_DEVICE;
 843         else
 844                 return DMA_FROM_DEVICE;
 845 }
 846
 847 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 848         struct mmc_data *data)
 849 {
 850         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 851 }
 852
 853 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 854 {
 855         int dma_ch;
 856         unsigned long flags;
 857
 858         spin_lock_irqsave(&host->irq_lock, flags);
 859         host->req_in_progress = 0;
 860         dma_ch = host->dma_ch;
 861         spin_unlock_irqrestore(&host->irq_lock, flags);
 862
 863         omap_hsmmc_disable_irq(host);
 864         /* Do not complete the request if DMA is still in progress */
 865         if (mrq->data && host->use_dma && dma_ch != -1)
 866                 return;
 867         host->mrq = NULL;
 868         mmc_request_done(host->mmc, mrq);
 869 }
 870
 871 /*
 872  * Notify the transfer complete to MMC core
 873  */
 874 static void
 875 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 876 {
 877         if (!data) {
 878                 struct mmc_request *mrq = host->mrq;
 879
 880                 /* TC before CC from CMD6 - don't know why, but it happens */
 881                 if (host->cmd && host->cmd->opcode == 6 &&
 882                     host->response_busy) {
 883                         host->response_busy = 0;
 884                         return;
 885                 }
 886
 887                 omap_hsmmc_request_done(host, mrq);
 888                 return;
 889         }
 890
 891         host->data = NULL;
 892
 893         if (!data->error)
 894                 data->bytes_xfered += data->blocks * (data->blksz);
 895         else
 896                 data->bytes_xfered = 0;
 897
 898         if (data->stop && (data->error || !host->mrq->sbc))
 899                 omap_hsmmc_start_command(host, data->stop, NULL);
 900         else
 901                 omap_hsmmc_request_done(host, data->mrq);
 902 }
 903
 904 /*
 905  * Notify the core about command completion
 906  */
 907 static void
 908 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 909 {
 910         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 911             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 912                 host->cmd = NULL;
 913                 omap_hsmmc_start_dma_transfer(host);
 914                 omap_hsmmc_start_command(host, host->mrq->cmd,
 915                                                 host->mrq->data);
 916                 return;
 917         }
 918
 919         host->cmd = NULL;
 920
 921         if (cmd->flags & MMC_RSP_PRESENT) {
 922                 if (cmd->flags & MMC_RSP_136) {
 923                         /* response type 2 */
 924                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 925                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 926                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 927                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 928                 } else {
 929                         /* response types 1, 1b, 3, 4, 5, 6 */
 930                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 931                 }
 932         }
 933         if ((host->data == NULL && !host->response_busy) || cmd->error)
 934                 omap_hsmmc_request_done(host, host->mrq);
 935 }
 936
 937 /*
 938  * DMA clean up for command errors
 939  */
 940 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 941 {
 942         int dma_ch;
 943         unsigned long flags;
 944
 945         host->data->error = errno;
 946
 947         spin_lock_irqsave(&host->irq_lock, flags);
 948         dma_ch = host->dma_ch;
 949         host->dma_ch = -1;
 950         spin_unlock_irqrestore(&host->irq_lock, flags);
 951
 952         if (host->use_dma && dma_ch != -1) {
 953                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 954
 955                 dmaengine_terminate_all(chan);
 956                 dma_unmap_sg(chan->device->dev,
 957                         host->data->sg, host->data->sg_len,
 958                         omap_hsmmc_get_dma_dir(host, host->data));
 959
 960                 host->data->host_cookie = 0;
 961         }
 962         host->data = NULL;
 963 }
 964
 965 /*
 966  * Readable error output
 967  */
 968 #ifdef CONFIG_MMC_DEBUG
 969 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 970 {
 971         /* --- means reserved bit without definition at documentation */
 972         static const char *omap_hsmmc_status_bits[] = {
 973                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 974                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 975                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 976                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 977         };
 978         char res[256];
 979         char *buf = res;
 980         int len, i;
 981
 982         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 983         buf += len;
 984
 985         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 986                 if (status & (1 << i)) {
 987                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 988                         buf += len;
 989                 }
 990
 991         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 992 }
 993 #else
 994 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 995                                              u32 status)
 996 {
 997 }
 998 #endif  /* CONFIG_MMC_DEBUG */
 999
1000 /*
1001  * MMC controller internal state machines reset
1002  *
1003  * Used to reset command or data internal state machines, using respectively
1004  *  SRC or SRD bit of SYSCTL register
1005  * Can be called from interrupt context
1006  */
1007 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1008                                                    unsigned long bit)
1009 {
1010         unsigned long i = 0;
1011         unsigned long limit = MMC_TIMEOUT_US;
1012
1013         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1014                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1015
1016         /*
1017          * OMAP4 ES2 and greater has an updated reset logic.
1018          * Monitor a 0->1 transition first
1019          */
1020         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1021                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1022                                         && (i++ < limit))
1023                         udelay(1);
1024         }
1025         i = 0;
1026
1027         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1028                 (i++ < limit))
1029                 udelay(1);
1030
1031         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1032                 dev_err(mmc_dev(host->mmc),
1033                         "Timeout waiting on controller reset in %s\n",
1034                         __func__);
1035 }
1036
1037 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1038                                         int err, int end_cmd)
1039 {
1040         if (end_cmd) {
1041                 omap_hsmmc_reset_controller_fsm(host, SRC);
1042                 if (host->cmd)
1043                         host->cmd->error = err;
1044         }
1045
1046         if (host->data) {
1047                 omap_hsmmc_reset_controller_fsm(host, SRD);
1048                 omap_hsmmc_dma_cleanup(host, err);
1049         } else if (host->mrq && host->mrq->cmd)
1050                 host->mrq->cmd->error = err;
1051 }
1052
1053 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1054 {
1055         struct mmc_data *data;
1056         int end_cmd = 0, end_trans = 0;
1057         int error = 0;
1058
1059         data = host->data;
1060         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1061
1062         if (status & ERR_EN) {
1063                 omap_hsmmc_dbg_report_irq(host, status);
1064
1065                 if (status & (CTO_EN | CCRC_EN))
1066                         end_cmd = 1;
1067                 if (status & (CTO_EN | DTO_EN))
1068                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1069                 else if (status & (CCRC_EN | DCRC_EN))
1070                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1071
1072                 if (status & ACE_EN) {
1073                         u32 ac12;
1074                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1075                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1076                                 end_cmd = 1;
1077                                 if (ac12 & ACTO)
1078                                         error =  -ETIMEDOUT;
1079                                 else if (ac12 & (ACCE | ACEB | ACIE))
1080                                         error = -EILSEQ;
1081                                 host->mrq->sbc->error = error;
1082                                 hsmmc_command_incomplete(host, error, end_cmd);
1083                         }
1084                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1085                 }
1086                 if (host->data || host->response_busy) {
1087                         end_trans = !end_cmd;
1088                         host->response_busy = 0;
1089                 }
1090         }
1091
1092         OMAP_HSMMC_WRITE(host->base, STAT, status);
1093         if (end_cmd || ((status & CC_EN) && host->cmd))
1094                 omap_hsmmc_cmd_done(host, host->cmd);
1095         if ((end_trans || (status & TC_EN)) && host->mrq)
1096                 omap_hsmmc_xfer_done(host, data);
1097 }
1098
1099 /*
1100  * MMC controller IRQ handler
1101  */
1102 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1103 {
1104         struct omap_hsmmc_host *host = dev_id;
1105         int status;
1106
1107         status = OMAP_HSMMC_READ(host->base, STAT);
1108         while (status & (INT_EN_MASK | CIRQ_EN)) {
1109                 if (host->req_in_progress)
1110                         omap_hsmmc_do_irq(host, status);
1111
1112                 if (status & CIRQ_EN)
1113                         mmc_signal_sdio_irq(host->mmc);
1114
1115                 /* Flush posted write */
1116                 status = OMAP_HSMMC_READ(host->base, STAT);
1117         }
1118
1119         return IRQ_HANDLED;
1120 }
1121
1122 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1123 {
1124         struct omap_hsmmc_host *host = dev_id;
1125
1126         /* cirq is level triggered, disable to avoid infinite loop */
1127         spin_lock(&host->irq_lock);
1128         if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1129                 disable_irq_nosync(host->wake_irq);
1130                 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1131         }
1132         spin_unlock(&host->irq_lock);
1133         pm_request_resume(host->dev); /* no use counter */
1134
1135         return IRQ_HANDLED;
1136 }
1137
1138 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1139 {
1140         unsigned long i;
1141
1142         OMAP_HSMMC_WRITE(host->base, HCTL,
1143                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1144         for (i = 0; i < loops_per_jiffy; i++) {
1145                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1146                         break;
1147                 cpu_relax();
1148         }
1149 }
1150
1151 /*
1152  * Switch MMC interface voltage ... only relevant for MMC1.
1153  *
1154  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1155  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1156  * Some chips, like eMMC ones, use internal transceivers.
1157  */
1158 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1159 {
1160         u32 reg_val = 0;
1161         int ret;
1162
1163         /* Disable the clocks */
1164         pm_runtime_put_sync(host->dev);
1165         if (host->dbclk)
1166                 clk_disable_unprepare(host->dbclk);
1167
1168         /* Turn the power off */
1169         ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1170
1171         /* Turn the power ON with given VDD 1.8 or 3.0v */
1172         if (!ret)
1173                 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1174         pm_runtime_get_sync(host->dev);
1175         if (host->dbclk)
1176                 clk_prepare_enable(host->dbclk);
1177
1178         if (ret != 0)
1179                 goto err;
1180
1181         OMAP_HSMMC_WRITE(host->base, HCTL,
1182                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1183         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1184
1185         /*
1186          * If a MMC dual voltage card is detected, the set_ios fn calls
1187          * this fn with VDD bit set for 1.8V. Upon card removal from the
1188          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1189          *
1190          * Cope with a bit of slop in the range ... per data sheets:
1191          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1192          *    but recommended values are 1.71V to 1.89V
1193          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1194          *    but recommended values are 2.7V to 3.3V
1195          *
1196          * Board setup code shouldn't permit anything very out-of-range.
1197          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1198          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1199          */
1200         if ((1 << vdd) <= MMC_VDD_23_24)
1201                 reg_val |= SDVS18;
1202         else
1203                 reg_val |= SDVS30;
1204
1205         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1206         set_sd_bus_power(host);
1207
1208         return 0;
1209 err:
1210         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1211         return ret;
1212 }
1213
1214 /* Protect the card while the cover is open */
1215 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1216 {
1217         if (!host->get_cover_state)
1218                 return;
1219
1220         host->reqs_blocked = 0;
1221         if (host->get_cover_state(host->dev)) {
1222                 if (host->protect_card) {
1223                         dev_info(host->dev, "%s: cover is closed, "
1224                                          "card is now accessible\n",
1225                                          mmc_hostname(host->mmc));
1226                         host->protect_card = 0;
1227                 }
1228         } else {
1229                 if (!host->protect_card) {
1230                         dev_info(host->dev, "%s: cover is open, "
1231                                          "card is now inaccessible\n",
1232                                          mmc_hostname(host->mmc));
1233                         host->protect_card = 1;
1234                 }
1235         }
1236 }
1237
1238 /*
1239  * irq handler to notify the core about card insertion/removal
1240  */
1241 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1242 {
1243         struct omap_hsmmc_host *host = dev_id;
1244         int carddetect;
1245
1246         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1247
1248         if (host->card_detect)
1249                 carddetect = host->card_detect(host->dev);
1250         else {
1251                 omap_hsmmc_protect_card(host);
1252                 carddetect = -ENOSYS;
1253         }
1254
1255         if (carddetect)
1256                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1257         else
1258                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1259         return IRQ_HANDLED;
1260 }
1261
1262 static void omap_hsmmc_dma_callback(void *param)
1263 {
1264         struct omap_hsmmc_host *host = param;
1265         struct dma_chan *chan;
1266         struct mmc_data *data;
1267         int req_in_progress;
1268
1269         spin_lock_irq(&host->irq_lock);
1270         if (host->dma_ch < 0) {
1271                 spin_unlock_irq(&host->irq_lock);
1272                 return;
1273         }
1274
1275         data = host->mrq->data;
1276         chan = omap_hsmmc_get_dma_chan(host, data);
1277         if (!data->host_cookie)
1278                 dma_unmap_sg(chan->device->dev,
1279                              data->sg, data->sg_len,
1280                              omap_hsmmc_get_dma_dir(host, data));
1281
1282         req_in_progress = host->req_in_progress;
1283         host->dma_ch = -1;
1284         spin_unlock_irq(&host->irq_lock);
1285
1286         /* If DMA has finished after TC, complete the request */
1287         if (!req_in_progress) {
1288                 struct mmc_request *mrq = host->mrq;
1289
1290                 host->mrq = NULL;
1291                 mmc_request_done(host->mmc, mrq);
1292         }
1293 }
1294
1295 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1296                                        struct mmc_data *data,
1297                                        struct omap_hsmmc_next *next,
1298                                        struct dma_chan *chan)
1299 {
1300         int dma_len;
1301
1302         if (!next && data->host_cookie &&
1303             data->host_cookie != host->next_data.cookie) {
1304                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1305                        " host->next_data.cookie %d\n",
1306                        __func__, data->host_cookie, host->next_data.cookie);
1307                 data->host_cookie = 0;
1308         }
1309
1310         /* Check if next job is already prepared */
1311         if (next || data->host_cookie != host->next_data.cookie) {
1312                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1313                                      omap_hsmmc_get_dma_dir(host, data));
1314
1315         } else {
1316                 dma_len = host->next_data.dma_len;
1317                 host->next_data.dma_len = 0;
1318         }
1319
1320
1321         if (dma_len == 0)
1322                 return -EINVAL;
1323
1324         if (next) {
1325                 next->dma_len = dma_len;
1326                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1327         } else
1328                 host->dma_len = dma_len;
1329
1330         return 0;
1331 }
1332
1333 /*
1334  * Routine to configure and start DMA for the MMC card
1335  */
1336 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1337                                         struct mmc_request *req)
1338 {
1339         struct dma_slave_config cfg;
1340         struct dma_async_tx_descriptor *tx;
1341         int ret = 0, i;
1342         struct mmc_data *data = req->data;
1343         struct dma_chan *chan;
1344
1345         /* Sanity check: all the SG entries must be aligned by block size. */
1346         for (i = 0; i < data->sg_len; i++) {
1347                 struct scatterlist *sgl;
1348
1349                 sgl = data->sg + i;
1350                 if (sgl->length % data->blksz)
1351                         return -EINVAL;
1352         }
1353         if ((data->blksz % 4) != 0)
1354                 /* REVISIT: The MMC buffer increments only when MSB is written.
1355                  * Return error for blksz which is non multiple of four.
1356                  */
1357                 return -EINVAL;
1358
1359         BUG_ON(host->dma_ch != -1);
1360
1361         chan = omap_hsmmc_get_dma_chan(host, data);
1362
1363         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1364         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1365         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1366         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1367         cfg.src_maxburst = data->blksz / 4;
1368         cfg.dst_maxburst = data->blksz / 4;
1369
1370         ret = dmaengine_slave_config(chan, &cfg);
1371         if (ret)
1372                 return ret;
1373
1374         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1375         if (ret)
1376                 return ret;
1377
1378         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1379                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1380                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1381         if (!tx) {
1382                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1383                 /* FIXME: cleanup */
1384                 return -1;
1385         }
1386
1387         tx->callback = omap_hsmmc_dma_callback;
1388         tx->callback_param = host;
1389
1390         /* Does not fail */
1391         dmaengine_submit(tx);
1392
1393         host->dma_ch = 1;
1394
1395         return 0;
1396 }
1397
1398 static void set_data_timeout(struct omap_hsmmc_host *host,
1399                              unsigned int timeout_ns,
1400                              unsigned int timeout_clks)
1401 {
1402         unsigned int timeout, cycle_ns;
1403         uint32_t reg, clkd, dto = 0;
1404
1405         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1406         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1407         if (clkd == 0)
1408                 clkd = 1;
1409
1410         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1411         timeout = timeout_ns / cycle_ns;
1412         timeout += timeout_clks;
1413         if (timeout) {
1414                 while ((timeout & 0x80000000) == 0) {
1415                         dto += 1;
1416                         timeout <<= 1;
1417                 }
1418                 dto = 31 - dto;
1419                 timeout <<= 1;
1420                 if (timeout && dto)
1421                         dto += 1;
1422                 if (dto >= 13)
1423                         dto -= 13;
1424                 else
1425                         dto = 0;
1426                 if (dto > 14)
1427                         dto = 14;
1428         }
1429
1430         reg &= ~DTO_MASK;
1431         reg |= dto << DTO_SHIFT;
1432         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1433 }
1434
1435 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1436 {
1437         struct mmc_request *req = host->mrq;
1438         struct dma_chan *chan;
1439
1440         if (!req->data)
1441                 return;
1442         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1443                                 | (req->data->blocks << 16));
1444         set_data_timeout(host, req->data->timeout_ns,
1445                                 req->data->timeout_clks);
1446         chan = omap_hsmmc_get_dma_chan(host, req->data);
1447         dma_async_issue_pending(chan);
1448 }
1449
1450 /*
1451  * Configure block length for MMC/SD cards and initiate the transfer.
1452  */
1453 static int
1454 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1455 {
1456         int ret;
1457         host->data = req->data;
1458
1459         if (req->data == NULL) {
1460                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1461                 /*
1462                  * Set an arbitrary 100ms data timeout for commands with
1463                  * busy signal.
1464                  */
1465                 if (req->cmd->flags & MMC_RSP_BUSY)
1466                         set_data_timeout(host, 100000000U, 0);
1467                 return 0;
1468         }
1469
1470         if (host->use_dma) {
1471                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1472                 if (ret != 0) {
1473                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1474                         return ret;
1475                 }
1476         }
1477         return 0;
1478 }
1479
1480 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1481                                 int err)
1482 {
1483         struct omap_hsmmc_host *host = mmc_priv(mmc);
1484         struct mmc_data *data = mrq->data;
1485
1486         if (host->use_dma && data->host_cookie) {
1487                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1488
1489                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1490                              omap_hsmmc_get_dma_dir(host, data));
1491                 data->host_cookie = 0;
1492         }
1493 }
1494
1495 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1496                                bool is_first_req)
1497 {
1498         struct omap_hsmmc_host *host = mmc_priv(mmc);
1499
1500         if (mrq->data->host_cookie) {
1501                 mrq->data->host_cookie = 0;
1502                 return ;
1503         }
1504
1505         if (host->use_dma) {
1506                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1507
1508                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1509                                                 &host->next_data, c))
1510                         mrq->data->host_cookie = 0;
1511         }
1512 }
1513
1514 /*
1515  * Request function. for read/write operation
1516  */
1517 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1518 {
1519         struct omap_hsmmc_host *host = mmc_priv(mmc);
1520         int err;
1521
1522         BUG_ON(host->req_in_progress);
1523         BUG_ON(host->dma_ch != -1);
1524         if (host->protect_card) {
1525                 if (host->reqs_blocked < 3) {
1526                         /*
1527                          * Ensure the controller is left in a consistent
1528                          * state by resetting the command and data state
1529                          * machines.
1530                          */
1531                         omap_hsmmc_reset_controller_fsm(host, SRD);
1532                         omap_hsmmc_reset_controller_fsm(host, SRC);
1533                         host->reqs_blocked += 1;
1534                 }
1535                 req->cmd->error = -EBADF;
1536                 if (req->data)
1537                         req->data->error = -EBADF;
1538                 req->cmd->retries = 0;
1539                 mmc_request_done(mmc, req);
1540                 return;
1541         } else if (host->reqs_blocked)
1542                 host->reqs_blocked = 0;
1543         WARN_ON(host->mrq != NULL);
1544         host->mrq = req;
1545         host->clk_rate = clk_get_rate(host->fclk);
1546         err = omap_hsmmc_prepare_data(host, req);
1547         if (err) {
1548                 req->cmd->error = err;
1549                 if (req->data)
1550                         req->data->error = err;
1551                 host->mrq = NULL;
1552                 mmc_request_done(mmc, req);
1553                 return;
1554         }
1555         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1556                 omap_hsmmc_start_command(host, req->sbc, NULL);
1557                 return;
1558         }
1559
1560         omap_hsmmc_start_dma_transfer(host);
1561         omap_hsmmc_start_command(host, req->cmd, req->data);
1562 }
1563
1564 /* Routine to configure clock values. Exposed API to core */
1565 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1566 {
1567         struct omap_hsmmc_host *host = mmc_priv(mmc);
1568         int do_send_init_stream = 0;
1569
1570         pm_runtime_get_sync(host->dev);
1571
1572         if (ios->power_mode != host->power_mode) {
1573                 switch (ios->power_mode) {
1574                 case MMC_POWER_OFF:
1575                         mmc_pdata(host)->set_power(host->dev, 0, 0);
1576                         break;
1577                 case MMC_POWER_UP:
1578                         mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1579                         break;
1580                 case MMC_POWER_ON:
1581                         do_send_init_stream = 1;
1582                         break;
1583                 }
1584                 host->power_mode = ios->power_mode;
1585         }
1586
1587         /* FIXME: set registers based only on changes to ios */
1588
1589         omap_hsmmc_set_bus_width(host);
1590
1591         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1592                 /* Only MMC1 can interface at 3V without some flavor
1593                  * of external transceiver; but they all handle 1.8V.
1594                  */
1595                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1596                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1597                                 /*
1598                                  * The mmc_select_voltage fn of the core does
1599                                  * not seem to set the power_mode to
1600                                  * MMC_POWER_UP upon recalculating the voltage.
1601                                  * vdd 1.8v.
1602                                  */
1603                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1604                                 dev_dbg(mmc_dev(host->mmc),
1605                                                 "Switch operation failed\n");
1606                 }
1607         }
1608
1609         omap_hsmmc_set_clock(host);
1610
1611         if (do_send_init_stream)
1612                 send_init_stream(host);
1613
1614         omap_hsmmc_set_bus_mode(host);
1615
1616         pm_runtime_put_autosuspend(host->dev);
1617 }
1618
1619 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1620 {
1621         struct omap_hsmmc_host *host = mmc_priv(mmc);
1622
1623         if (!host->card_detect)
1624                 return -ENOSYS;
1625         return host->card_detect(host->dev);
1626 }
1627
1628 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1629 {
1630         struct omap_hsmmc_host *host = mmc_priv(mmc);
1631
1632         if (mmc_pdata(host)->init_card)
1633                 mmc_pdata(host)->init_card(card);
1634 }
1635
1636 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1637 {
1638         struct omap_hsmmc_host *host = mmc_priv(mmc);
1639         u32 irq_mask, con;
1640         unsigned long flags;
1641
1642         spin_lock_irqsave(&host->irq_lock, flags);
1643
1644         con = OMAP_HSMMC_READ(host->base, CON);
1645         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1646         if (enable) {
1647                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1648                 irq_mask |= CIRQ_EN;
1649                 con |= CTPL | CLKEXTFREE;
1650         } else {
1651                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1652                 irq_mask &= ~CIRQ_EN;
1653                 con &= ~(CTPL | CLKEXTFREE);
1654         }
1655         OMAP_HSMMC_WRITE(host->base, CON, con);
1656         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1657
1658         /*
1659          * if enable, piggy back detection on current request
1660          * but always disable immediately
1661          */
1662         if (!host->req_in_progress || !enable)
1663                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1664
1665         /* flush posted write */
1666         OMAP_HSMMC_READ(host->base, IE);
1667
1668         spin_unlock_irqrestore(&host->irq_lock, flags);
1669 }
1670
1671 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1672 {
1673         struct mmc_host *mmc = host->mmc;
1674         int ret;
1675
1676         /*
1677          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1678          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1679          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1680          * with functional clock disabled.
1681          */
1682         if (!host->dev->of_node || !host->wake_irq)
1683                 return -ENODEV;
1684
1685         /* Prevent auto-enabling of IRQ */
1686         irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1687         ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1688                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1689                                mmc_hostname(mmc), host);
1690         if (ret) {
1691                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1692                 goto err;
1693         }
1694
1695         /*
1696          * Some omaps don't have wake-up path from deeper idle states
1697          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1698          */
1699         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1700                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1701                 if (!p) {
1702                         ret = -ENODEV;
1703                         goto err_free_irq;
1704                 }
1705                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1706                         dev_info(host->dev, "missing default pinctrl state\n");
1707                         devm_pinctrl_put(p);
1708                         ret = -EINVAL;
1709                         goto err_free_irq;
1710                 }
1711
1712                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1713                         dev_info(host->dev, "missing idle pinctrl state\n");
1714                         devm_pinctrl_put(p);
1715                         ret = -EINVAL;
1716                         goto err_free_irq;
1717                 }
1718                 devm_pinctrl_put(p);
1719         }
1720
1721         OMAP_HSMMC_WRITE(host->base, HCTL,
1722                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1723         return 0;
1724
1725 err_free_irq:
1726         devm_free_irq(host->dev, host->wake_irq, host);
1727 err:
1728         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1729         host->wake_irq = 0;
1730         return ret;
1731 }
1732
1733 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1734 {
1735         u32 hctl, capa, value;
1736
1737         /* Only MMC1 supports 3.0V */
1738         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1739                 hctl = SDVS30;
1740                 capa = VS30 | VS18;
1741         } else {
1742                 hctl = SDVS18;
1743                 capa = VS18;
1744         }
1745
1746         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1747         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1748
1749         value = OMAP_HSMMC_READ(host->base, CAPA);
1750         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1751
1752         /* Set SD bus power bit */
1753         set_sd_bus_power(host);
1754 }
1755
1756 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1757 {
1758         struct omap_hsmmc_host *host = mmc_priv(mmc);
1759
1760         pm_runtime_get_sync(host->dev);
1761
1762         return 0;
1763 }
1764
1765 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1766 {
1767         struct omap_hsmmc_host *host = mmc_priv(mmc);
1768
1769         pm_runtime_mark_last_busy(host->dev);
1770         pm_runtime_put_autosuspend(host->dev);
1771
1772         return 0;
1773 }
1774
1775 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1776                                      unsigned int direction, int blk_size)
1777 {
1778         /* This controller can't do multiblock reads due to hw bugs */
1779         if (direction == MMC_DATA_READ)
1780                 return 1;
1781
1782         return blk_size;
1783 }
1784
1785 static struct mmc_host_ops omap_hsmmc_ops = {
1786         .enable = omap_hsmmc_enable_fclk,
1787         .disable = omap_hsmmc_disable_fclk,
1788         .post_req = omap_hsmmc_post_req,
1789         .pre_req = omap_hsmmc_pre_req,
1790         .request = omap_hsmmc_request,
1791         .set_ios = omap_hsmmc_set_ios,
1792         .get_cd = omap_hsmmc_get_cd,
1793         .get_ro = mmc_gpio_get_ro,
1794         .init_card = omap_hsmmc_init_card,
1795         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1796 };
1797
1798 #ifdef CONFIG_DEBUG_FS
1799
1800 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1801 {
1802         struct mmc_host *mmc = s->private;
1803         struct omap_hsmmc_host *host = mmc_priv(mmc);
1804
1805         seq_printf(s, "mmc%d:\n", mmc->index);
1806         seq_printf(s, "sdio irq mode\t%s\n",
1807                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1808
1809         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1810                 seq_printf(s, "sdio irq \t%s\n",
1811                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1812                            : "disabled");
1813         }
1814         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1815
1816         pm_runtime_get_sync(host->dev);
1817         seq_puts(s, "\nregs:\n");
1818         seq_printf(s, "CON:\t\t0x%08x\n",
1819                         OMAP_HSMMC_READ(host->base, CON));
1820         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1821                    OMAP_HSMMC_READ(host->base, PSTATE));
1822         seq_printf(s, "HCTL:\t\t0x%08x\n",
1823                         OMAP_HSMMC_READ(host->base, HCTL));
1824         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1825                         OMAP_HSMMC_READ(host->base, SYSCTL));
1826         seq_printf(s, "IE:\t\t0x%08x\n",
1827                         OMAP_HSMMC_READ(host->base, IE));
1828         seq_printf(s, "ISE:\t\t0x%08x\n",
1829                         OMAP_HSMMC_READ(host->base, ISE));
1830         seq_printf(s, "CAPA:\t\t0x%08x\n",
1831                         OMAP_HSMMC_READ(host->base, CAPA));
1832
1833         pm_runtime_mark_last_busy(host->dev);
1834         pm_runtime_put_autosuspend(host->dev);
1835
1836         return 0;
1837 }
1838
1839 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1840 {
1841         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1842 }
1843
1844 static const struct file_operations mmc_regs_fops = {
1845         .open           = omap_hsmmc_regs_open,
1846         .read           = seq_read,
1847         .llseek         = seq_lseek,
1848         .release        = single_release,
1849 };
1850
1851 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1852 {
1853         if (mmc->debugfs_root)
1854                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1855                         mmc, &mmc_regs_fops);
1856 }
1857
1858 #else
1859
1860 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1861 {
1862 }
1863
1864 #endif
1865
1866 #ifdef CONFIG_OF
1867 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1868         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1869         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1870 };
1871
1872 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1873         .reg_offset = 0x100,
1874 };
1875 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1876         .reg_offset = 0x100,
1877         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1878 };
1879
1880 static const struct of_device_id omap_mmc_of_match[] = {
1881         {
1882                 .compatible = "ti,omap2-hsmmc",
1883         },
1884         {
1885                 .compatible = "ti,omap3-pre-es3-hsmmc",
1886                 .data = &omap3_pre_es3_mmc_of_data,
1887         },
1888         {
1889                 .compatible = "ti,omap3-hsmmc",
1890         },
1891         {
1892                 .compatible = "ti,omap4-hsmmc",
1893                 .data = &omap4_mmc_of_data,
1894         },
1895         {
1896                 .compatible = "ti,am33xx-hsmmc",
1897                 .data = &am33xx_mmc_of_data,
1898         },
1899         {},
1900 };
1901 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1902
1903 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1904 {
1905         struct omap_hsmmc_platform_data *pdata;
1906         struct device_node *np = dev->of_node;
1907
1908         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1909         if (!pdata)
1910                 return ERR_PTR(-ENOMEM); /* out of memory */
1911
1912         if (of_find_property(np, "ti,dual-volt", NULL))
1913                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1914
1915         pdata->switch_pin = -EINVAL;
1916         pdata->gpio_wp = -EINVAL;
1917
1918         if (of_find_property(np, "ti,non-removable", NULL)) {
1919                 pdata->nonremovable = true;
1920                 pdata->no_regulator_off_init = true;
1921         }
1922
1923         if (of_find_property(np, "ti,needs-special-reset", NULL))
1924                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1925
1926         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1927                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1928
1929         return pdata;
1930 }
1931 #else
1932 static inline struct omap_hsmmc_platform_data
1933                         *of_get_hsmmc_pdata(struct device *dev)
1934 {
1935         return ERR_PTR(-EINVAL);
1936 }
1937 #endif
1938
1939 static int omap_hsmmc_probe(struct platform_device *pdev)
1940 {
1941         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1942         struct mmc_host *mmc;
1943         struct omap_hsmmc_host *host = NULL;
1944         struct resource *res;
1945         int ret, irq;
1946         const struct of_device_id *match;
1947         dma_cap_mask_t mask;
1948         unsigned tx_req, rx_req;
1949         const struct omap_mmc_of_data *data;
1950         void __iomem *base;
1951
1952         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1953         if (match) {
1954                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1955
1956                 if (IS_ERR(pdata))
1957                         return PTR_ERR(pdata);
1958
1959                 if (match->data) {
1960                         data = match->data;
1961                         pdata->reg_offset = data->reg_offset;
1962                         pdata->controller_flags |= data->controller_flags;
1963                 }
1964         }
1965
1966         if (pdata == NULL) {
1967                 dev_err(&pdev->dev, "Platform Data is missing\n");
1968                 return -ENXIO;
1969         }
1970
1971         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1972         irq = platform_get_irq(pdev, 0);
1973         if (res == NULL || irq < 0)
1974                 return -ENXIO;
1975
1976         base = devm_ioremap_resource(&pdev->dev, res);
1977         if (IS_ERR(base))
1978                 return PTR_ERR(base);
1979
1980         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1981         if (!mmc) {
1982                 ret = -ENOMEM;
1983                 goto err;
1984         }
1985
1986         ret = mmc_of_parse(mmc);
1987         if (ret)
1988                 goto err1;
1989
1990         host            = mmc_priv(mmc);
1991         host->mmc       = mmc;
1992         host->pdata     = pdata;
1993         host->dev       = &pdev->dev;
1994         host->use_dma   = 1;
1995         host->dma_ch    = -1;
1996         host->irq       = irq;
1997         host->mapbase   = res->start + pdata->reg_offset;
1998         host->base      = base + pdata->reg_offset;
1999         host->power_mode = MMC_POWER_OFF;
2000         host->next_data.cookie = 1;
2001         host->pbias_enabled = 0;
2002
2003         ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2004         if (ret)
2005                 goto err_gpio;
2006
2007         platform_set_drvdata(pdev, host);
2008
2009         if (pdev->dev.of_node)
2010                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2011
2012         mmc->ops        = &omap_hsmmc_ops;
2013
2014         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2015
2016         if (pdata->max_freq > 0)
2017                 mmc->f_max = pdata->max_freq;
2018         else if (mmc->f_max == 0)
2019                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2020
2021         spin_lock_init(&host->irq_lock);
2022
2023         host->fclk = devm_clk_get(&pdev->dev, "fck");
2024         if (IS_ERR(host->fclk)) {
2025                 ret = PTR_ERR(host->fclk);
2026                 host->fclk = NULL;
2027                 goto err1;
2028         }
2029
2030         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2031                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2032                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2033         }
2034
2035         pm_runtime_enable(host->dev);
2036         pm_runtime_get_sync(host->dev);
2037         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2038         pm_runtime_use_autosuspend(host->dev);
2039
2040         omap_hsmmc_context_save(host);
2041
2042         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2043         /*
2044          * MMC can still work without debounce clock.
2045          */
2046         if (IS_ERR(host->dbclk)) {
2047                 host->dbclk = NULL;
2048         } else if (clk_prepare_enable(host->dbclk) != 0) {
2049                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2050                 host->dbclk = NULL;
2051         }
2052
2053         /* Since we do only SG emulation, we can have as many segs
2054          * as we want. */
2055         mmc->max_segs = 1024;
2056
2057         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2058         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2059         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2060         mmc->max_seg_size = mmc->max_req_size;
2061
2062         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2063                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2064
2065         mmc->caps |= mmc_pdata(host)->caps;
2066         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2067                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2068
2069         if (mmc_pdata(host)->nonremovable)
2070                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2071
2072         mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2073
2074         omap_hsmmc_conf_bus_power(host);
2075
2076         if (!pdev->dev.of_node) {
2077                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2078                 if (!res) {
2079                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2080                         ret = -ENXIO;
2081                         goto err_irq;
2082                 }
2083                 tx_req = res->start;
2084
2085                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2086                 if (!res) {
2087                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2088                         ret = -ENXIO;
2089                         goto err_irq;
2090                 }
2091                 rx_req = res->start;
2092         }
2093
2094         dma_cap_zero(mask);
2095         dma_cap_set(DMA_SLAVE, mask);
2096
2097         host->rx_chan =
2098                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2099                                                  &rx_req, &pdev->dev, "rx");
2100
2101         if (!host->rx_chan) {
2102                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2103                 ret = -ENXIO;
2104                 goto err_irq;
2105         }
2106
2107         host->tx_chan =
2108                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2109                                                  &tx_req, &pdev->dev, "tx");
2110
2111         if (!host->tx_chan) {
2112                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2113                 ret = -ENXIO;
2114                 goto err_irq;
2115         }
2116
2117         /* Request IRQ for MMC operations */
2118         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2119                         mmc_hostname(mmc), host);
2120         if (ret) {
2121                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2122                 goto err_irq;
2123         }
2124
2125         if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2126                 ret = omap_hsmmc_reg_get(host);
2127                 if (ret)
2128                         goto err_irq;
2129                 host->use_reg = 1;
2130         }
2131
2132         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2133
2134         omap_hsmmc_disable_irq(host);
2135
2136         /*
2137          * For now, only support SDIO interrupt if we have a separate
2138          * wake-up interrupt configured from device tree. This is because
2139          * the wake-up interrupt is needed for idle state and some
2140          * platforms need special quirks. And we don't want to add new
2141          * legacy mux platform init code callbacks any longer as we
2142          * are moving to DT based booting anyways.
2143          */
2144         ret = omap_hsmmc_configure_wake_irq(host);
2145         if (!ret)
2146                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2147
2148         omap_hsmmc_protect_card(host);
2149
2150         mmc_add_host(mmc);
2151
2152         if (mmc_pdata(host)->name != NULL) {
2153                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2154                 if (ret < 0)
2155                         goto err_slot_name;
2156         }
2157         if (host->card_detect_irq && host->get_cover_state) {
2158                 ret = device_create_file(&mmc->class_dev,
2159                                         &dev_attr_cover_switch);
2160                 if (ret < 0)
2161                         goto err_slot_name;
2162         }
2163
2164         omap_hsmmc_debugfs(mmc);
2165         pm_runtime_mark_last_busy(host->dev);
2166         pm_runtime_put_autosuspend(host->dev);
2167
2168         return 0;
2169
2170 err_slot_name:
2171         mmc_remove_host(mmc);
2172         if (host->use_reg)
2173                 omap_hsmmc_reg_put(host);
2174 err_irq:
2175         if (host->tx_chan)
2176                 dma_release_channel(host->tx_chan);
2177         if (host->rx_chan)
2178                 dma_release_channel(host->rx_chan);
2179         pm_runtime_put_sync(host->dev);
2180         pm_runtime_disable(host->dev);
2181         if (host->dbclk)
2182                 clk_disable_unprepare(host->dbclk);
2183 err1:
2184 err_gpio:
2185         mmc_free_host(mmc);
2186 err:
2187         return ret;
2188 }
2189
2190 static int omap_hsmmc_remove(struct platform_device *pdev)
2191 {
2192         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2193
2194         pm_runtime_get_sync(host->dev);
2195         mmc_remove_host(host->mmc);
2196         if (host->use_reg)
2197                 omap_hsmmc_reg_put(host);
2198
2199         if (host->tx_chan)
2200                 dma_release_channel(host->tx_chan);
2201         if (host->rx_chan)
2202                 dma_release_channel(host->rx_chan);
2203
2204         pm_runtime_put_sync(host->dev);
2205         pm_runtime_disable(host->dev);
2206         if (host->dbclk)
2207                 clk_disable_unprepare(host->dbclk);
2208
2209         mmc_free_host(host->mmc);
2210
2211         return 0;
2212 }
2213
2214 #ifdef CONFIG_PM
2215 static int omap_hsmmc_suspend(struct device *dev)
2216 {
2217         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2218
2219         if (!host)
2220                 return 0;
2221
2222         pm_runtime_get_sync(host->dev);
2223
2224         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2225                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2226                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2227                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2228                 OMAP_HSMMC_WRITE(host->base, HCTL,
2229                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2230         }
2231
2232         /* do not wake up due to sdio irq */
2233         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2234             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2235                 disable_irq(host->wake_irq);
2236
2237         if (host->dbclk)
2238                 clk_disable_unprepare(host->dbclk);
2239
2240         pm_runtime_put_sync(host->dev);
2241         return 0;
2242 }
2243
2244 /* Routine to resume the MMC device */
2245 static int omap_hsmmc_resume(struct device *dev)
2246 {
2247         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2248
2249         if (!host)
2250                 return 0;
2251
2252         pm_runtime_get_sync(host->dev);
2253
2254         if (host->dbclk)
2255                 clk_prepare_enable(host->dbclk);
2256
2257         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2258                 omap_hsmmc_conf_bus_power(host);
2259
2260         omap_hsmmc_protect_card(host);
2261
2262         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2263             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2264                 enable_irq(host->wake_irq);
2265
2266         pm_runtime_mark_last_busy(host->dev);
2267         pm_runtime_put_autosuspend(host->dev);
2268         return 0;
2269 }
2270
2271 #else
2272 #define omap_hsmmc_suspend      NULL
2273 #define omap_hsmmc_resume       NULL
2274 #endif
2275
2276 static int omap_hsmmc_runtime_suspend(struct device *dev)
2277 {
2278         struct omap_hsmmc_host *host;
2279         unsigned long flags;
2280         int ret = 0;
2281
2282         host = platform_get_drvdata(to_platform_device(dev));
2283         omap_hsmmc_context_save(host);
2284         dev_dbg(dev, "disabled\n");
2285
2286         spin_lock_irqsave(&host->irq_lock, flags);
2287         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2288             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2289                 /* disable sdio irq handling to prevent race */
2290                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2291                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2292
2293                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2294                         /*
2295                          * dat1 line low, pending sdio irq
2296                          * race condition: possible irq handler running on
2297                          * multi-core, abort
2298                          */
2299                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2300                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2301                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2302                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2303                         pm_runtime_mark_last_busy(dev);
2304                         ret = -EBUSY;
2305                         goto abort;
2306                 }
2307
2308                 pinctrl_pm_select_idle_state(dev);
2309
2310                 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2311                 enable_irq(host->wake_irq);
2312                 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2313         } else {
2314                 pinctrl_pm_select_idle_state(dev);
2315         }
2316
2317 abort:
2318         spin_unlock_irqrestore(&host->irq_lock, flags);
2319         return ret;
2320 }
2321
2322 static int omap_hsmmc_runtime_resume(struct device *dev)
2323 {
2324         struct omap_hsmmc_host *host;
2325         unsigned long flags;
2326
2327         host = platform_get_drvdata(to_platform_device(dev));
2328         omap_hsmmc_context_restore(host);
2329         dev_dbg(dev, "enabled\n");
2330
2331         spin_lock_irqsave(&host->irq_lock, flags);
2332         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2333             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2334                 /* sdio irq flag can't change while in runtime suspend */
2335                 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2336                         disable_irq_nosync(host->wake_irq);
2337                         host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2338                 }
2339
2340                 pinctrl_pm_select_default_state(host->dev);
2341
2342                 /* irq lost, if pinmux incorrect */
2343                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2344                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2345                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2346         } else {
2347                 pinctrl_pm_select_default_state(host->dev);
2348         }
2349         spin_unlock_irqrestore(&host->irq_lock, flags);
2350         return 0;
2351 }
2352
2353 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2354         .suspend        = omap_hsmmc_suspend,
2355         .resume         = omap_hsmmc_resume,
2356         .runtime_suspend = omap_hsmmc_runtime_suspend,
2357         .runtime_resume = omap_hsmmc_runtime_resume,
2358 };
2359
2360 static struct platform_driver omap_hsmmc_driver = {
2361         .probe          = omap_hsmmc_probe,
2362         .remove         = omap_hsmmc_remove,
2363         .driver         = {
2364                 .name = DRIVER_NAME,
2365                 .pm = &omap_hsmmc_dev_pm_ops,
2366                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2367         },
2368 };
2369
2370 module_platform_driver(omap_hsmmc_driver);
2371 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2372 MODULE_LICENSE("GPL");
2373 MODULE_ALIAS("platform:" DRIVER_NAME);
2374 MODULE_AUTHOR("Texas Instruments Inc");