2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
37 #include <mach/hardware.h>
38 #include <plat/board.h>
42 /* OMAP HSMMC Host Controller Registers */
43 #define OMAP_HSMMC_SYSCONFIG 0x0010
44 #define OMAP_HSMMC_SYSSTATUS 0x0014
45 #define OMAP_HSMMC_CON 0x002C
46 #define OMAP_HSMMC_BLK 0x0104
47 #define OMAP_HSMMC_ARG 0x0108
48 #define OMAP_HSMMC_CMD 0x010C
49 #define OMAP_HSMMC_RSP10 0x0110
50 #define OMAP_HSMMC_RSP32 0x0114
51 #define OMAP_HSMMC_RSP54 0x0118
52 #define OMAP_HSMMC_RSP76 0x011C
53 #define OMAP_HSMMC_DATA 0x0120
54 #define OMAP_HSMMC_HCTL 0x0128
55 #define OMAP_HSMMC_SYSCTL 0x012C
56 #define OMAP_HSMMC_STAT 0x0130
57 #define OMAP_HSMMC_IE 0x0134
58 #define OMAP_HSMMC_ISE 0x0138
59 #define OMAP_HSMMC_CAPA 0x0140
61 #define VS18 (1 << 26)
62 #define VS30 (1 << 25)
63 #define SDVS18 (0x5 << 9)
64 #define SDVS30 (0x6 << 9)
65 #define SDVS33 (0x7 << 9)
66 #define SDVS_MASK 0x00000E00
67 #define SDVSCLR 0xFFFFF1FF
68 #define SDVSDET 0x00000400
75 #define CLKD_MASK 0x0000FFC0
77 #define DTO_MASK 0x000F0000
79 #define INT_EN_MASK 0x307F0033
80 #define BWR_ENABLE (1 << 4)
81 #define BRR_ENABLE (1 << 5)
82 #define DTO_ENABLE (1 << 20)
83 #define INIT_STREAM (1 << 1)
84 #define DP_SELECT (1 << 21)
89 #define FOUR_BIT (1 << 1)
95 #define CMD_TIMEOUT (1 << 16)
96 #define DATA_TIMEOUT (1 << 20)
97 #define CMD_CRC (1 << 17)
98 #define DATA_CRC (1 << 21)
99 #define CARD_ERR (1 << 28)
100 #define STAT_CLEAR 0xFFFFFFFF
101 #define INIT_STREAM_CMD 0x00000000
102 #define DUAL_VOLT_OCR_BIT 7
103 #define SRC (1 << 25)
104 #define SRD (1 << 26)
105 #define SOFTRESET (1 << 1)
106 #define RESETDONE (1 << 0)
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
113 #define OMAP_MMC1_DEVID 0
114 #define OMAP_MMC2_DEVID 1
115 #define OMAP_MMC3_DEVID 2
116 #define OMAP_MMC4_DEVID 3
117 #define OMAP_MMC5_DEVID 4
119 #define MMC_TIMEOUT_MS 20
120 #define OMAP_MMC_MASTER_CLOCK 96000000
121 #define DRIVER_NAME "mmci-omap-hs"
123 /* Timeouts for entering power saving states on inactivity, msec */
124 #define OMAP_MMC_DISABLED_TIMEOUT 100
125 #define OMAP_MMC_SLEEP_TIMEOUT 1000
126 #define OMAP_MMC_OFF_TIMEOUT 8000
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
136 * MMC Host controller read/write API's
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144 struct omap_hsmmc_host {
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
162 struct work_struct mmc_carddetect_work;
164 resource_size_t mapbase;
165 spinlock_t irq_lock; /* Prevent races with irq handler */
167 unsigned int dma_len;
168 unsigned int dma_sg_idx;
169 unsigned char bus_mode;
170 unsigned char power_mode;
176 int dma_line_tx, dma_line_rx;
188 struct omap_mmc_platform_data *pdata;
191 static int omap_hsmmc_card_detect(struct device *dev, int slot)
193 struct omap_mmc_platform_data *mmc = dev->platform_data;
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
199 static int omap_hsmmc_get_wp(struct device *dev, int slot)
201 struct omap_mmc_platform_data *mmc = dev->platform_data;
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
209 struct omap_mmc_platform_data *mmc = dev->platform_data;
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
219 struct omap_mmc_platform_data *mmc = dev->platform_data;
221 disable_irq(mmc->slots[0].card_detect_irq);
225 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
227 struct omap_mmc_platform_data *mmc = dev->platform_data;
229 enable_irq(mmc->slots[0].card_detect_irq);
235 #define omap_hsmmc_suspend_cdirq NULL
236 #define omap_hsmmc_resume_cdirq NULL
240 #ifdef CONFIG_REGULATOR
242 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
245 struct omap_hsmmc_host *host =
246 platform_get_drvdata(to_platform_device(dev));
249 if (mmc_slot(host).before_set_reg)
250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
253 ret = mmc_regulator_set_ocr(host->vcc, vdd);
255 ret = mmc_regulator_set_ocr(host->vcc, 0);
257 if (mmc_slot(host).after_set_reg)
258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
263 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
266 struct omap_hsmmc_host *host =
267 platform_get_drvdata(to_platform_device(dev));
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
277 if (mmc_slot(host).before_set_reg)
278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
294 ret = mmc_regulator_set_ocr(host->vcc, vdd);
295 /* Enable interface voltage rail, if needed */
296 if (ret == 0 && host->vcc_aux) {
297 ret = regulator_enable(host->vcc_aux);
299 ret = mmc_regulator_set_ocr(host->vcc, 0);
303 ret = regulator_disable(host->vcc_aux);
305 ret = mmc_regulator_set_ocr(host->vcc, 0);
308 if (mmc_slot(host).after_set_reg)
309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
314 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
315 int vdd, int cardsleep)
317 struct omap_hsmmc_host *host =
318 platform_get_drvdata(to_platform_device(dev));
319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
321 return regulator_set_mode(host->vcc, mode);
324 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
325 int vdd, int cardsleep)
327 struct omap_hsmmc_host *host =
328 platform_get_drvdata(to_platform_device(dev));
332 * If we don't see a Vcc regulator, assume it's a fixed
333 * voltage always-on regulator.
338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
341 return regulator_set_mode(host->vcc, mode);
344 /* VCC can be turned off if card is asleep */
346 err = mmc_regulator_set_ocr(host->vcc, 0);
348 err = mmc_regulator_set_ocr(host->vcc, vdd);
350 err = regulator_set_mode(host->vcc, mode);
354 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
355 return regulator_set_mode(host->vcc_aux, mode);
358 return regulator_disable(host->vcc_aux);
360 return regulator_enable(host->vcc_aux);
363 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
365 struct regulator *reg;
370 case OMAP_MMC1_DEVID:
371 /* On-chip level shifting via PBIAS0/PBIAS1 */
372 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
373 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
375 case OMAP_MMC2_DEVID:
376 case OMAP_MMC3_DEVID:
377 /* Off-chip level shifting, or none */
378 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
379 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
382 pr_err("MMC%d configuration not supported!\n", host->id);
386 reg = regulator_get(host->dev, "vmmc");
388 dev_dbg(host->dev, "vmmc regulator missing\n");
390 * HACK: until fixed.c regulator is usable,
391 * we don't require a main regulator
394 if (host->id == OMAP_MMC1_DEVID) {
400 ocr_value = mmc_regulator_get_ocrmask(reg);
401 if (!mmc_slot(host).ocr_mask) {
402 mmc_slot(host).ocr_mask = ocr_value;
404 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
405 pr_err("MMC%d ocrmask %x is not supported\n",
406 host->id, mmc_slot(host).ocr_mask);
407 mmc_slot(host).ocr_mask = 0;
411 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
413 /* Allow an aux regulator */
414 reg = regulator_get(host->dev, "vmmc_aux");
415 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
418 * UGLY HACK: workaround regulator framework bugs.
419 * When the bootloader leaves a supply active, it's
420 * initialized with zero usecount ... and we can't
421 * disable it without first enabling it. Until the
422 * framework is fixed, we need a workaround like this
423 * (which is safe for MMC, but not in general).
425 if (regulator_is_enabled(host->vcc) > 0) {
426 regulator_enable(host->vcc);
427 regulator_disable(host->vcc);
430 if (regulator_is_enabled(reg) > 0) {
431 regulator_enable(reg);
432 regulator_disable(reg);
440 mmc_slot(host).set_power = NULL;
441 mmc_slot(host).set_sleep = NULL;
445 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
447 regulator_put(host->vcc);
448 regulator_put(host->vcc_aux);
449 mmc_slot(host).set_power = NULL;
450 mmc_slot(host).set_sleep = NULL;
453 static inline int omap_hsmmc_have_reg(void)
460 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
465 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
469 static inline int omap_hsmmc_have_reg(void)
476 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
480 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
481 pdata->suspend = omap_hsmmc_suspend_cdirq;
482 pdata->resume = omap_hsmmc_resume_cdirq;
483 if (pdata->slots[0].cover)
484 pdata->slots[0].get_cover_state =
485 omap_hsmmc_get_cover_state;
487 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
488 pdata->slots[0].card_detect_irq =
489 gpio_to_irq(pdata->slots[0].switch_pin);
490 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
493 ret = gpio_direction_input(pdata->slots[0].switch_pin);
497 pdata->slots[0].switch_pin = -EINVAL;
499 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
500 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
501 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
504 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
508 pdata->slots[0].gpio_wp = -EINVAL;
513 gpio_free(pdata->slots[0].gpio_wp);
515 if (gpio_is_valid(pdata->slots[0].switch_pin))
517 gpio_free(pdata->slots[0].switch_pin);
521 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
523 if (gpio_is_valid(pdata->slots[0].gpio_wp))
524 gpio_free(pdata->slots[0].gpio_wp);
525 if (gpio_is_valid(pdata->slots[0].switch_pin))
526 gpio_free(pdata->slots[0].switch_pin);
530 * Stop clock to the card
532 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
534 OMAP_HSMMC_WRITE(host->base, SYSCTL,
535 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
536 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
537 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
540 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
541 struct mmc_command *cmd)
543 unsigned int irq_mask;
546 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
548 irq_mask = INT_EN_MASK;
550 /* Disable timeout for erases */
551 if (cmd->opcode == MMC_ERASE)
552 irq_mask &= ~DTO_ENABLE;
554 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
555 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
556 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
559 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
561 OMAP_HSMMC_WRITE(host->base, ISE, 0);
562 OMAP_HSMMC_WRITE(host->base, IE, 0);
563 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
569 * Restore the MMC host context, if it was lost as result of a
570 * power state change.
572 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
574 struct mmc_ios *ios = &host->mmc->ios;
575 struct omap_mmc_platform_data *pdata = host->pdata;
576 int context_loss = 0;
579 unsigned long timeout;
581 if (pdata->get_context_loss_count) {
582 context_loss = pdata->get_context_loss_count(host->dev);
583 if (context_loss < 0)
587 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
588 context_loss == host->context_loss ? "not " : "");
589 if (host->context_loss == context_loss)
592 /* Wait for hardware reset */
593 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
594 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
595 && time_before(jiffies, timeout))
598 /* Do software reset */
599 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
600 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
601 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
602 && time_before(jiffies, timeout))
605 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
606 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
608 if (host->id == OMAP_MMC1_DEVID) {
609 if (host->power_mode != MMC_POWER_OFF &&
610 (1 << ios->vdd) <= MMC_VDD_23_24)
620 OMAP_HSMMC_WRITE(host->base, HCTL,
621 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
623 OMAP_HSMMC_WRITE(host->base, CAPA,
624 OMAP_HSMMC_READ(host->base, CAPA) | capa);
626 OMAP_HSMMC_WRITE(host->base, HCTL,
627 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
629 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
630 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
631 && time_before(jiffies, timeout))
634 omap_hsmmc_disable_irq(host);
636 /* Do not initialize card-specific things if the power is off */
637 if (host->power_mode == MMC_POWER_OFF)
640 con = OMAP_HSMMC_READ(host->base, CON);
641 switch (ios->bus_width) {
642 case MMC_BUS_WIDTH_8:
643 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
645 case MMC_BUS_WIDTH_4:
646 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
647 OMAP_HSMMC_WRITE(host->base, HCTL,
648 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
650 case MMC_BUS_WIDTH_1:
651 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
652 OMAP_HSMMC_WRITE(host->base, HCTL,
653 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
658 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
662 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
669 OMAP_HSMMC_WRITE(host->base, SYSCTL,
670 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
671 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
672 OMAP_HSMMC_WRITE(host->base, SYSCTL,
673 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
675 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
676 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
677 && time_before(jiffies, timeout))
680 OMAP_HSMMC_WRITE(host->base, SYSCTL,
681 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
683 con = OMAP_HSMMC_READ(host->base, CON);
684 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
685 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
687 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
689 host->context_loss = context_loss;
691 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
696 * Save the MMC host context (store the number of power state changes so far).
698 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
700 struct omap_mmc_platform_data *pdata = host->pdata;
703 if (pdata->get_context_loss_count) {
704 context_loss = pdata->get_context_loss_count(host->dev);
705 if (context_loss < 0)
707 host->context_loss = context_loss;
713 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
718 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
725 * Send init stream sequence to card
726 * before sending IDLE command
728 static void send_init_stream(struct omap_hsmmc_host *host)
731 unsigned long timeout;
733 if (host->protect_card)
736 disable_irq(host->irq);
738 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
739 OMAP_HSMMC_WRITE(host->base, CON,
740 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
741 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
743 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
744 while ((reg != CC) && time_before(jiffies, timeout))
745 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
747 OMAP_HSMMC_WRITE(host->base, CON,
748 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
750 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
751 OMAP_HSMMC_READ(host->base, STAT);
753 enable_irq(host->irq);
757 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
761 if (mmc_slot(host).get_cover_state)
762 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
767 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
770 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
771 struct omap_hsmmc_host *host = mmc_priv(mmc);
773 return sprintf(buf, "%s\n",
774 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
777 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
780 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
783 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
784 struct omap_hsmmc_host *host = mmc_priv(mmc);
786 return sprintf(buf, "%s\n", mmc_slot(host).name);
789 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
792 * Configure the response type and send the cmd.
795 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
796 struct mmc_data *data)
798 int cmdreg = 0, resptype = 0, cmdtype = 0;
800 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
801 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
804 omap_hsmmc_enable_irq(host, cmd);
806 host->response_busy = 0;
807 if (cmd->flags & MMC_RSP_PRESENT) {
808 if (cmd->flags & MMC_RSP_136)
810 else if (cmd->flags & MMC_RSP_BUSY) {
812 host->response_busy = 1;
818 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
819 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
820 * a val of 0x3, rest 0x0.
822 if (cmd == host->mrq->stop)
825 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
828 cmdreg |= DP_SELECT | MSBS | BCE;
829 if (data->flags & MMC_DATA_READ)
838 host->req_in_progress = 1;
840 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
841 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
845 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
847 if (data->flags & MMC_DATA_WRITE)
848 return DMA_TO_DEVICE;
850 return DMA_FROM_DEVICE;
853 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
857 spin_lock(&host->irq_lock);
858 host->req_in_progress = 0;
859 dma_ch = host->dma_ch;
860 spin_unlock(&host->irq_lock);
862 omap_hsmmc_disable_irq(host);
863 /* Do not complete the request if DMA is still in progress */
864 if (mrq->data && host->use_dma && dma_ch != -1)
867 mmc_request_done(host->mmc, mrq);
871 * Notify the transfer complete to MMC core
874 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
877 struct mmc_request *mrq = host->mrq;
879 /* TC before CC from CMD6 - don't know why, but it happens */
880 if (host->cmd && host->cmd->opcode == 6 &&
881 host->response_busy) {
882 host->response_busy = 0;
886 omap_hsmmc_request_done(host, mrq);
893 data->bytes_xfered += data->blocks * (data->blksz);
895 data->bytes_xfered = 0;
898 omap_hsmmc_request_done(host, data->mrq);
901 omap_hsmmc_start_command(host, data->stop, NULL);
905 * Notify the core about command completion
908 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
912 if (cmd->flags & MMC_RSP_PRESENT) {
913 if (cmd->flags & MMC_RSP_136) {
914 /* response type 2 */
915 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
916 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
917 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
918 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
920 /* response types 1, 1b, 3, 4, 5, 6 */
921 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
924 if ((host->data == NULL && !host->response_busy) || cmd->error)
925 omap_hsmmc_request_done(host, cmd->mrq);
929 * DMA clean up for command errors
931 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
935 host->data->error = errno;
937 spin_lock(&host->irq_lock);
938 dma_ch = host->dma_ch;
940 spin_unlock(&host->irq_lock);
942 if (host->use_dma && dma_ch != -1) {
943 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
944 omap_hsmmc_get_dma_dir(host, host->data));
945 omap_free_dma(dma_ch);
951 * Readable error output
953 #ifdef CONFIG_MMC_DEBUG
954 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
956 /* --- means reserved bit without definition at documentation */
957 static const char *omap_hsmmc_status_bits[] = {
958 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
959 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
960 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
961 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
967 len = sprintf(buf, "MMC IRQ 0x%x :", status);
970 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
971 if (status & (1 << i)) {
972 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
976 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
978 #endif /* CONFIG_MMC_DEBUG */
981 * MMC controller internal state machines reset
983 * Used to reset command or data internal state machines, using respectively
984 * SRC or SRD bit of SYSCTL register
985 * Can be called from interrupt context
987 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
991 unsigned long limit = (loops_per_jiffy *
992 msecs_to_jiffies(MMC_TIMEOUT_MS));
994 OMAP_HSMMC_WRITE(host->base, SYSCTL,
995 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
998 * OMAP4 ES2 and greater has an updated reset logic.
999 * Monitor a 0->1 transition first
1001 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1002 while ((!(OMAP_HSMMC_READ(host, SYSCTL) & bit))
1008 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1012 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1013 dev_err(mmc_dev(host->mmc),
1014 "Timeout waiting on controller reset in %s\n",
1018 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1020 struct mmc_data *data;
1021 int end_cmd = 0, end_trans = 0;
1023 if (!host->req_in_progress) {
1025 OMAP_HSMMC_WRITE(host->base, STAT, status);
1026 /* Flush posted write */
1027 status = OMAP_HSMMC_READ(host->base, STAT);
1028 } while (status & INT_EN_MASK);
1033 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1036 #ifdef CONFIG_MMC_DEBUG
1037 omap_hsmmc_report_irq(host, status);
1039 if ((status & CMD_TIMEOUT) ||
1040 (status & CMD_CRC)) {
1042 if (status & CMD_TIMEOUT) {
1043 omap_hsmmc_reset_controller_fsm(host,
1045 host->cmd->error = -ETIMEDOUT;
1047 host->cmd->error = -EILSEQ;
1051 if (host->data || host->response_busy) {
1053 omap_hsmmc_dma_cleanup(host,
1055 host->response_busy = 0;
1056 omap_hsmmc_reset_controller_fsm(host, SRD);
1059 if ((status & DATA_TIMEOUT) ||
1060 (status & DATA_CRC)) {
1061 if (host->data || host->response_busy) {
1062 int err = (status & DATA_TIMEOUT) ?
1063 -ETIMEDOUT : -EILSEQ;
1066 omap_hsmmc_dma_cleanup(host, err);
1068 host->mrq->cmd->error = err;
1069 host->response_busy = 0;
1070 omap_hsmmc_reset_controller_fsm(host, SRD);
1074 if (status & CARD_ERR) {
1075 dev_dbg(mmc_dev(host->mmc),
1076 "Ignoring card err CMD%d\n", host->cmd->opcode);
1084 OMAP_HSMMC_WRITE(host->base, STAT, status);
1086 if (end_cmd || ((status & CC) && host->cmd))
1087 omap_hsmmc_cmd_done(host, host->cmd);
1088 if ((end_trans || (status & TC)) && host->mrq)
1089 omap_hsmmc_xfer_done(host, data);
1093 * MMC controller IRQ handler
1095 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1097 struct omap_hsmmc_host *host = dev_id;
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1102 omap_hsmmc_do_irq(host, status);
1103 /* Flush posted write */
1104 status = OMAP_HSMMC_READ(host->base, STAT);
1105 } while (status & INT_EN_MASK);
1110 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1114 OMAP_HSMMC_WRITE(host->base, HCTL,
1115 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1116 for (i = 0; i < loops_per_jiffy; i++) {
1117 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1124 * Switch MMC interface voltage ... only relevant for MMC1.
1126 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1127 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1128 * Some chips, like eMMC ones, use internal transceivers.
1130 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1135 /* Disable the clocks */
1136 clk_disable(host->fclk);
1137 clk_disable(host->iclk);
1138 if (host->got_dbclk)
1139 clk_disable(host->dbclk);
1141 /* Turn the power off */
1142 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1144 /* Turn the power ON with given VDD 1.8 or 3.0v */
1146 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1148 clk_enable(host->iclk);
1149 clk_enable(host->fclk);
1150 if (host->got_dbclk)
1151 clk_enable(host->dbclk);
1156 OMAP_HSMMC_WRITE(host->base, HCTL,
1157 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1158 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1161 * If a MMC dual voltage card is detected, the set_ios fn calls
1162 * this fn with VDD bit set for 1.8V. Upon card removal from the
1163 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1165 * Cope with a bit of slop in the range ... per data sheets:
1166 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1167 * but recommended values are 1.71V to 1.89V
1168 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1169 * but recommended values are 2.7V to 3.3V
1171 * Board setup code shouldn't permit anything very out-of-range.
1172 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1173 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1175 if ((1 << vdd) <= MMC_VDD_23_24)
1180 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1181 set_sd_bus_power(host);
1185 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1189 /* Protect the card while the cover is open */
1190 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1192 if (!mmc_slot(host).get_cover_state)
1195 host->reqs_blocked = 0;
1196 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1197 if (host->protect_card) {
1198 printk(KERN_INFO "%s: cover is closed, "
1199 "card is now accessible\n",
1200 mmc_hostname(host->mmc));
1201 host->protect_card = 0;
1204 if (!host->protect_card) {
1205 printk(KERN_INFO "%s: cover is open, "
1206 "card is now inaccessible\n",
1207 mmc_hostname(host->mmc));
1208 host->protect_card = 1;
1214 * Work Item to notify the core about card insertion/removal
1216 static void omap_hsmmc_detect(struct work_struct *work)
1218 struct omap_hsmmc_host *host =
1219 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1220 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1223 if (host->suspended)
1226 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1228 if (slot->card_detect)
1229 carddetect = slot->card_detect(host->dev, host->slot_id);
1231 omap_hsmmc_protect_card(host);
1232 carddetect = -ENOSYS;
1236 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1238 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1242 * ISR for handling card insertion and removal
1244 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1246 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1248 if (host->suspended)
1250 schedule_work(&host->mmc_carddetect_work);
1255 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1256 struct mmc_data *data)
1260 if (data->flags & MMC_DATA_WRITE)
1261 sync_dev = host->dma_line_tx;
1263 sync_dev = host->dma_line_rx;
1267 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1268 struct mmc_data *data,
1269 struct scatterlist *sgl)
1271 int blksz, nblk, dma_ch;
1273 dma_ch = host->dma_ch;
1274 if (data->flags & MMC_DATA_WRITE) {
1275 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1276 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1277 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1278 sg_dma_address(sgl), 0, 0);
1280 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1281 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1282 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1283 sg_dma_address(sgl), 0, 0);
1286 blksz = host->data->blksz;
1287 nblk = sg_dma_len(sgl) / blksz;
1289 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1290 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1291 omap_hsmmc_get_dma_sync_dev(host, data),
1292 !(data->flags & MMC_DATA_WRITE));
1294 omap_start_dma(dma_ch);
1298 * DMA call back function
1300 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1302 struct omap_hsmmc_host *host = cb_data;
1303 struct mmc_data *data = host->mrq->data;
1304 int dma_ch, req_in_progress;
1306 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1307 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1312 spin_lock(&host->irq_lock);
1313 if (host->dma_ch < 0) {
1314 spin_unlock(&host->irq_lock);
1319 if (host->dma_sg_idx < host->dma_len) {
1320 /* Fire up the next transfer. */
1321 omap_hsmmc_config_dma_params(host, data,
1322 data->sg + host->dma_sg_idx);
1323 spin_unlock(&host->irq_lock);
1327 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
1328 omap_hsmmc_get_dma_dir(host, data));
1330 req_in_progress = host->req_in_progress;
1331 dma_ch = host->dma_ch;
1333 spin_unlock(&host->irq_lock);
1335 omap_free_dma(dma_ch);
1337 /* If DMA has finished after TC, complete the request */
1338 if (!req_in_progress) {
1339 struct mmc_request *mrq = host->mrq;
1342 mmc_request_done(host->mmc, mrq);
1347 * Routine to configure and start DMA for the MMC card
1349 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1350 struct mmc_request *req)
1352 int dma_ch = 0, ret = 0, i;
1353 struct mmc_data *data = req->data;
1355 /* Sanity check: all the SG entries must be aligned by block size. */
1356 for (i = 0; i < data->sg_len; i++) {
1357 struct scatterlist *sgl;
1360 if (sgl->length % data->blksz)
1363 if ((data->blksz % 4) != 0)
1364 /* REVISIT: The MMC buffer increments only when MSB is written.
1365 * Return error for blksz which is non multiple of four.
1369 BUG_ON(host->dma_ch != -1);
1371 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1372 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1374 dev_err(mmc_dev(host->mmc),
1375 "%s: omap_request_dma() failed with %d\n",
1376 mmc_hostname(host->mmc), ret);
1380 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1381 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
1382 host->dma_ch = dma_ch;
1383 host->dma_sg_idx = 0;
1385 omap_hsmmc_config_dma_params(host, data, data->sg);
1390 static void set_data_timeout(struct omap_hsmmc_host *host,
1391 unsigned int timeout_ns,
1392 unsigned int timeout_clks)
1394 unsigned int timeout, cycle_ns;
1395 uint32_t reg, clkd, dto = 0;
1397 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1398 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1402 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1403 timeout = timeout_ns / cycle_ns;
1404 timeout += timeout_clks;
1406 while ((timeout & 0x80000000) == 0) {
1423 reg |= dto << DTO_SHIFT;
1424 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1428 * Configure block length for MMC/SD cards and initiate the transfer.
1431 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1434 host->data = req->data;
1436 if (req->data == NULL) {
1437 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1439 * Set an arbitrary 100ms data timeout for commands with
1442 if (req->cmd->flags & MMC_RSP_BUSY)
1443 set_data_timeout(host, 100000000U, 0);
1447 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1448 | (req->data->blocks << 16));
1449 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1451 if (host->use_dma) {
1452 ret = omap_hsmmc_start_dma_transfer(host, req);
1454 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1462 * Request function. for read/write operation
1464 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1466 struct omap_hsmmc_host *host = mmc_priv(mmc);
1469 BUG_ON(host->req_in_progress);
1470 BUG_ON(host->dma_ch != -1);
1471 if (host->protect_card) {
1472 if (host->reqs_blocked < 3) {
1474 * Ensure the controller is left in a consistent
1475 * state by resetting the command and data state
1478 omap_hsmmc_reset_controller_fsm(host, SRD);
1479 omap_hsmmc_reset_controller_fsm(host, SRC);
1480 host->reqs_blocked += 1;
1482 req->cmd->error = -EBADF;
1484 req->data->error = -EBADF;
1485 req->cmd->retries = 0;
1486 mmc_request_done(mmc, req);
1488 } else if (host->reqs_blocked)
1489 host->reqs_blocked = 0;
1490 WARN_ON(host->mrq != NULL);
1492 err = omap_hsmmc_prepare_data(host, req);
1494 req->cmd->error = err;
1496 req->data->error = err;
1498 mmc_request_done(mmc, req);
1502 omap_hsmmc_start_command(host, req->cmd, req->data);
1505 /* Routine to configure clock values. Exposed API to core */
1506 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1508 struct omap_hsmmc_host *host = mmc_priv(mmc);
1510 unsigned long regval;
1511 unsigned long timeout;
1513 int do_send_init_stream = 0;
1515 mmc_host_enable(host->mmc);
1517 if (ios->power_mode != host->power_mode) {
1518 switch (ios->power_mode) {
1520 mmc_slot(host).set_power(host->dev, host->slot_id,
1525 mmc_slot(host).set_power(host->dev, host->slot_id,
1527 host->vdd = ios->vdd;
1530 do_send_init_stream = 1;
1533 host->power_mode = ios->power_mode;
1536 /* FIXME: set registers based only on changes to ios */
1538 con = OMAP_HSMMC_READ(host->base, CON);
1539 switch (mmc->ios.bus_width) {
1540 case MMC_BUS_WIDTH_8:
1541 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1543 case MMC_BUS_WIDTH_4:
1544 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1545 OMAP_HSMMC_WRITE(host->base, HCTL,
1546 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1548 case MMC_BUS_WIDTH_1:
1549 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1550 OMAP_HSMMC_WRITE(host->base, HCTL,
1551 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1555 if (host->id == OMAP_MMC1_DEVID) {
1556 /* Only MMC1 can interface at 3V without some flavor
1557 * of external transceiver; but they all handle 1.8V.
1559 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1560 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1562 * The mmc_select_voltage fn of the core does
1563 * not seem to set the power_mode to
1564 * MMC_POWER_UP upon recalculating the voltage.
1567 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1568 dev_dbg(mmc_dev(host->mmc),
1569 "Switch operation failed\n");
1574 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1578 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1584 omap_hsmmc_stop_clock(host);
1585 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1586 regval = regval & ~(CLKD_MASK);
1587 regval = regval | (dsor << 6) | (DTO << 16);
1588 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1589 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1590 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1592 /* Wait till the ICS bit is set */
1593 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1594 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1595 && time_before(jiffies, timeout))
1598 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1599 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1601 if (do_send_init_stream)
1602 send_init_stream(host);
1604 con = OMAP_HSMMC_READ(host->base, CON);
1605 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1606 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1608 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1610 if (host->power_mode == MMC_POWER_OFF)
1611 mmc_host_disable(host->mmc);
1613 mmc_host_lazy_disable(host->mmc);
1616 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1618 struct omap_hsmmc_host *host = mmc_priv(mmc);
1620 if (!mmc_slot(host).card_detect)
1622 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1625 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1627 struct omap_hsmmc_host *host = mmc_priv(mmc);
1629 if (!mmc_slot(host).get_ro)
1631 return mmc_slot(host).get_ro(host->dev, 0);
1634 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1638 if (mmc_slot(host).init_card)
1639 mmc_slot(host).init_card(card);
1642 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1644 u32 hctl, capa, value;
1646 /* Only MMC1 supports 3.0V */
1647 if (host->id == OMAP_MMC1_DEVID) {
1655 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1656 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1658 value = OMAP_HSMMC_READ(host->base, CAPA);
1659 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1661 /* Set the controller to AUTO IDLE mode */
1662 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1663 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1665 /* Set SD bus power bit */
1666 set_sd_bus_power(host);
1670 * Dynamic power saving handling, FSM:
1671 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1673 * |______________________|______________________|
1675 * ENABLED: mmc host is fully functional
1676 * DISABLED: fclk is off
1677 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1678 * REGSLEEP: fclk is off, voltage regulator is asleep
1679 * OFF: fclk is off, voltage regulator is off
1681 * Transition handlers return the timeout for the next state transition
1682 * or negative error.
1685 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
1687 /* Handler for [ENABLED -> DISABLED] transition */
1688 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
1690 omap_hsmmc_context_save(host);
1691 clk_disable(host->fclk);
1692 host->dpm_state = DISABLED;
1694 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1696 if (host->power_mode == MMC_POWER_OFF)
1699 return OMAP_MMC_SLEEP_TIMEOUT;
1702 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1703 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
1707 if (!mmc_try_claim_host(host->mmc))
1710 clk_enable(host->fclk);
1711 omap_hsmmc_context_restore(host);
1712 if (mmc_card_can_sleep(host->mmc)) {
1713 err = mmc_card_sleep(host->mmc);
1715 clk_disable(host->fclk);
1716 mmc_release_host(host->mmc);
1719 new_state = CARDSLEEP;
1721 new_state = REGSLEEP;
1723 if (mmc_slot(host).set_sleep)
1724 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1725 new_state == CARDSLEEP);
1726 /* FIXME: turn off bus power and perhaps interrupts too */
1727 clk_disable(host->fclk);
1728 host->dpm_state = new_state;
1730 mmc_release_host(host->mmc);
1732 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1733 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1735 if (mmc_slot(host).no_off)
1738 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1739 mmc_slot(host).card_detect ||
1740 (mmc_slot(host).get_cover_state &&
1741 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1742 return OMAP_MMC_OFF_TIMEOUT;
1747 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1748 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
1750 if (!mmc_try_claim_host(host->mmc))
1753 if (mmc_slot(host).no_off)
1756 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1757 mmc_slot(host).card_detect ||
1758 (mmc_slot(host).get_cover_state &&
1759 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1760 mmc_release_host(host->mmc);
1764 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1766 host->power_mode = MMC_POWER_OFF;
1768 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1769 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1771 host->dpm_state = OFF;
1773 mmc_release_host(host->mmc);
1778 /* Handler for [DISABLED -> ENABLED] transition */
1779 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
1783 err = clk_enable(host->fclk);
1787 omap_hsmmc_context_restore(host);
1788 host->dpm_state = ENABLED;
1790 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1795 /* Handler for [SLEEP -> ENABLED] transition */
1796 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
1798 if (!mmc_try_claim_host(host->mmc))
1801 clk_enable(host->fclk);
1802 omap_hsmmc_context_restore(host);
1803 if (mmc_slot(host).set_sleep)
1804 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1805 host->vdd, host->dpm_state == CARDSLEEP);
1806 if (mmc_card_can_sleep(host->mmc))
1807 mmc_card_awake(host->mmc);
1809 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1810 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
1812 host->dpm_state = ENABLED;
1814 mmc_release_host(host->mmc);
1819 /* Handler for [OFF -> ENABLED] transition */
1820 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
1822 clk_enable(host->fclk);
1824 omap_hsmmc_context_restore(host);
1825 omap_hsmmc_conf_bus_power(host);
1826 mmc_power_restore_host(host->mmc);
1828 host->dpm_state = ENABLED;
1830 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1836 * Bring MMC host to ENABLED from any other PM state.
1838 static int omap_hsmmc_enable(struct mmc_host *mmc)
1840 struct omap_hsmmc_host *host = mmc_priv(mmc);
1842 switch (host->dpm_state) {
1844 return omap_hsmmc_disabled_to_enabled(host);
1847 return omap_hsmmc_sleep_to_enabled(host);
1849 return omap_hsmmc_off_to_enabled(host);
1851 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1857 * Bring MMC host in PM state (one level deeper).
1859 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
1861 struct omap_hsmmc_host *host = mmc_priv(mmc);
1863 switch (host->dpm_state) {
1867 delay = omap_hsmmc_enabled_to_disabled(host);
1868 if (lazy || delay < 0)
1873 return omap_hsmmc_disabled_to_sleep(host);
1876 return omap_hsmmc_sleep_to_off(host);
1878 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1883 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1885 struct omap_hsmmc_host *host = mmc_priv(mmc);
1888 err = clk_enable(host->fclk);
1891 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
1892 omap_hsmmc_context_restore(host);
1896 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1898 struct omap_hsmmc_host *host = mmc_priv(mmc);
1900 omap_hsmmc_context_save(host);
1901 clk_disable(host->fclk);
1902 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1906 static const struct mmc_host_ops omap_hsmmc_ops = {
1907 .enable = omap_hsmmc_enable_fclk,
1908 .disable = omap_hsmmc_disable_fclk,
1909 .request = omap_hsmmc_request,
1910 .set_ios = omap_hsmmc_set_ios,
1911 .get_cd = omap_hsmmc_get_cd,
1912 .get_ro = omap_hsmmc_get_ro,
1913 .init_card = omap_hsmmc_init_card,
1914 /* NYET -- enable_sdio_irq */
1917 static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1918 .enable = omap_hsmmc_enable,
1919 .disable = omap_hsmmc_disable,
1920 .request = omap_hsmmc_request,
1921 .set_ios = omap_hsmmc_set_ios,
1922 .get_cd = omap_hsmmc_get_cd,
1923 .get_ro = omap_hsmmc_get_ro,
1924 .init_card = omap_hsmmc_init_card,
1925 /* NYET -- enable_sdio_irq */
1928 #ifdef CONFIG_DEBUG_FS
1930 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1932 struct mmc_host *mmc = s->private;
1933 struct omap_hsmmc_host *host = mmc_priv(mmc);
1934 int context_loss = 0;
1936 if (host->pdata->get_context_loss_count)
1937 context_loss = host->pdata->get_context_loss_count(host->dev);
1939 seq_printf(s, "mmc%d:\n"
1942 " nesting_cnt:\t%d\n"
1943 " ctx_loss:\t%d:%d\n"
1945 mmc->index, mmc->enabled ? 1 : 0,
1946 host->dpm_state, mmc->nesting_cnt,
1947 host->context_loss, context_loss);
1949 if (host->suspended || host->dpm_state == OFF) {
1950 seq_printf(s, "host suspended, can't read registers\n");
1954 if (clk_enable(host->fclk) != 0) {
1955 seq_printf(s, "can't read the regs\n");
1959 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1960 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1961 seq_printf(s, "CON:\t\t0x%08x\n",
1962 OMAP_HSMMC_READ(host->base, CON));
1963 seq_printf(s, "HCTL:\t\t0x%08x\n",
1964 OMAP_HSMMC_READ(host->base, HCTL));
1965 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1966 OMAP_HSMMC_READ(host->base, SYSCTL));
1967 seq_printf(s, "IE:\t\t0x%08x\n",
1968 OMAP_HSMMC_READ(host->base, IE));
1969 seq_printf(s, "ISE:\t\t0x%08x\n",
1970 OMAP_HSMMC_READ(host->base, ISE));
1971 seq_printf(s, "CAPA:\t\t0x%08x\n",
1972 OMAP_HSMMC_READ(host->base, CAPA));
1974 clk_disable(host->fclk);
1979 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1981 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1984 static const struct file_operations mmc_regs_fops = {
1985 .open = omap_hsmmc_regs_open,
1987 .llseek = seq_lseek,
1988 .release = single_release,
1991 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1993 if (mmc->debugfs_root)
1994 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1995 mmc, &mmc_regs_fops);
2000 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
2006 static int __init omap_hsmmc_probe(struct platform_device *pdev)
2008 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
2009 struct mmc_host *mmc;
2010 struct omap_hsmmc_host *host = NULL;
2011 struct resource *res;
2014 if (pdata == NULL) {
2015 dev_err(&pdev->dev, "Platform Data is missing\n");
2019 if (pdata->nr_slots == 0) {
2020 dev_err(&pdev->dev, "No Slots\n");
2024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2025 irq = platform_get_irq(pdev, 0);
2026 if (res == NULL || irq < 0)
2029 res->start += pdata->reg_offset;
2030 res->end += pdata->reg_offset;
2031 res = request_mem_region(res->start, res->end - res->start + 1,
2036 ret = omap_hsmmc_gpio_init(pdata);
2040 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2046 host = mmc_priv(mmc);
2048 host->pdata = pdata;
2049 host->dev = &pdev->dev;
2051 host->dev->dma_mask = &pdata->dma_mask;
2054 host->id = pdev->id;
2056 host->mapbase = res->start;
2057 host->base = ioremap(host->mapbase, SZ_4K);
2058 host->power_mode = MMC_POWER_OFF;
2060 platform_set_drvdata(pdev, host);
2061 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
2063 if (mmc_slot(host).power_saving)
2064 mmc->ops = &omap_hsmmc_ps_ops;
2066 mmc->ops = &omap_hsmmc_ops;
2069 * If regulator_disable can only put vcc_aux to sleep then there is
2072 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2073 mmc_slot(host).no_off = 1;
2075 mmc->f_min = 400000;
2076 mmc->f_max = 52000000;
2078 spin_lock_init(&host->irq_lock);
2080 host->iclk = clk_get(&pdev->dev, "ick");
2081 if (IS_ERR(host->iclk)) {
2082 ret = PTR_ERR(host->iclk);
2086 host->fclk = clk_get(&pdev->dev, "fck");
2087 if (IS_ERR(host->fclk)) {
2088 ret = PTR_ERR(host->fclk);
2090 clk_put(host->iclk);
2094 omap_hsmmc_context_save(host);
2096 mmc->caps |= MMC_CAP_DISABLE;
2097 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2098 /* we start off in DISABLED state */
2099 host->dpm_state = DISABLED;
2101 if (mmc_host_enable(host->mmc) != 0) {
2102 clk_put(host->iclk);
2103 clk_put(host->fclk);
2107 if (clk_enable(host->iclk) != 0) {
2108 mmc_host_disable(host->mmc);
2109 clk_put(host->iclk);
2110 clk_put(host->fclk);
2114 if (cpu_is_omap2430()) {
2115 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2117 * MMC can still work without debounce clock.
2119 if (IS_ERR(host->dbclk))
2120 dev_warn(mmc_dev(host->mmc),
2121 "Failed to get debounce clock\n");
2123 host->got_dbclk = 1;
2125 if (host->got_dbclk)
2126 if (clk_enable(host->dbclk) != 0)
2127 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2131 /* Since we do only SG emulation, we can have as many segs
2133 mmc->max_phys_segs = 1024;
2134 mmc->max_hw_segs = 1024;
2136 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2137 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2138 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2139 mmc->max_seg_size = mmc->max_req_size;
2141 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2142 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2144 mmc->caps |= mmc_slot(host).caps;
2145 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2146 mmc->caps |= MMC_CAP_4_BIT_DATA;
2148 if (mmc_slot(host).nonremovable)
2149 mmc->caps |= MMC_CAP_NONREMOVABLE;
2151 omap_hsmmc_conf_bus_power(host);
2153 /* Select DMA lines */
2155 case OMAP_MMC1_DEVID:
2156 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2157 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2159 case OMAP_MMC2_DEVID:
2160 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2161 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2163 case OMAP_MMC3_DEVID:
2164 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2165 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2167 case OMAP_MMC4_DEVID:
2168 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2169 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2171 case OMAP_MMC5_DEVID:
2172 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2173 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2176 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2180 /* Request IRQ for MMC operations */
2181 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2182 mmc_hostname(mmc), host);
2184 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2188 if (pdata->init != NULL) {
2189 if (pdata->init(&pdev->dev) != 0) {
2190 dev_dbg(mmc_dev(host->mmc),
2191 "Unable to configure MMC IRQs\n");
2192 goto err_irq_cd_init;
2196 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2197 ret = omap_hsmmc_reg_get(host);
2203 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2205 /* Request IRQ for card detect */
2206 if ((mmc_slot(host).card_detect_irq)) {
2207 ret = request_irq(mmc_slot(host).card_detect_irq,
2208 omap_hsmmc_cd_handler,
2209 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2211 mmc_hostname(mmc), host);
2213 dev_dbg(mmc_dev(host->mmc),
2214 "Unable to grab MMC CD IRQ\n");
2219 omap_hsmmc_disable_irq(host);
2221 mmc_host_lazy_disable(host->mmc);
2223 omap_hsmmc_protect_card(host);
2227 if (mmc_slot(host).name != NULL) {
2228 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2232 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2233 ret = device_create_file(&mmc->class_dev,
2234 &dev_attr_cover_switch);
2239 omap_hsmmc_debugfs(mmc);
2244 mmc_remove_host(mmc);
2245 free_irq(mmc_slot(host).card_detect_irq, host);
2248 omap_hsmmc_reg_put(host);
2250 if (host->pdata->cleanup)
2251 host->pdata->cleanup(&pdev->dev);
2253 free_irq(host->irq, host);
2255 mmc_host_disable(host->mmc);
2256 clk_disable(host->iclk);
2257 clk_put(host->fclk);
2258 clk_put(host->iclk);
2259 if (host->got_dbclk) {
2260 clk_disable(host->dbclk);
2261 clk_put(host->dbclk);
2264 iounmap(host->base);
2265 platform_set_drvdata(pdev, NULL);
2268 omap_hsmmc_gpio_free(pdata);
2270 release_mem_region(res->start, res->end - res->start + 1);
2274 static int omap_hsmmc_remove(struct platform_device *pdev)
2276 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2277 struct resource *res;
2280 mmc_host_enable(host->mmc);
2281 mmc_remove_host(host->mmc);
2283 omap_hsmmc_reg_put(host);
2284 if (host->pdata->cleanup)
2285 host->pdata->cleanup(&pdev->dev);
2286 free_irq(host->irq, host);
2287 if (mmc_slot(host).card_detect_irq)
2288 free_irq(mmc_slot(host).card_detect_irq, host);
2289 flush_scheduled_work();
2291 mmc_host_disable(host->mmc);
2292 clk_disable(host->iclk);
2293 clk_put(host->fclk);
2294 clk_put(host->iclk);
2295 if (host->got_dbclk) {
2296 clk_disable(host->dbclk);
2297 clk_put(host->dbclk);
2300 mmc_free_host(host->mmc);
2301 iounmap(host->base);
2302 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2307 release_mem_region(res->start, res->end - res->start + 1);
2308 platform_set_drvdata(pdev, NULL);
2314 static int omap_hsmmc_suspend(struct device *dev)
2317 struct platform_device *pdev = to_platform_device(dev);
2318 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2320 if (host && host->suspended)
2324 host->suspended = 1;
2325 if (host->pdata->suspend) {
2326 ret = host->pdata->suspend(&pdev->dev,
2329 dev_dbg(mmc_dev(host->mmc),
2330 "Unable to handle MMC board"
2331 " level suspend\n");
2332 host->suspended = 0;
2336 cancel_work_sync(&host->mmc_carddetect_work);
2337 ret = mmc_suspend_host(host->mmc);
2338 mmc_host_enable(host->mmc);
2340 omap_hsmmc_disable_irq(host);
2341 OMAP_HSMMC_WRITE(host->base, HCTL,
2342 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2343 mmc_host_disable(host->mmc);
2344 clk_disable(host->iclk);
2345 if (host->got_dbclk)
2346 clk_disable(host->dbclk);
2348 host->suspended = 0;
2349 if (host->pdata->resume) {
2350 ret = host->pdata->resume(&pdev->dev,
2353 dev_dbg(mmc_dev(host->mmc),
2354 "Unmask interrupt failed\n");
2356 mmc_host_disable(host->mmc);
2363 /* Routine to resume the MMC device */
2364 static int omap_hsmmc_resume(struct device *dev)
2367 struct platform_device *pdev = to_platform_device(dev);
2368 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2370 if (host && !host->suspended)
2374 ret = clk_enable(host->iclk);
2378 if (mmc_host_enable(host->mmc) != 0) {
2379 clk_disable(host->iclk);
2383 if (host->got_dbclk)
2384 clk_enable(host->dbclk);
2386 omap_hsmmc_conf_bus_power(host);
2388 if (host->pdata->resume) {
2389 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2391 dev_dbg(mmc_dev(host->mmc),
2392 "Unmask interrupt failed\n");
2395 omap_hsmmc_protect_card(host);
2397 /* Notify the core to resume the host */
2398 ret = mmc_resume_host(host->mmc);
2400 host->suspended = 0;
2402 mmc_host_lazy_disable(host->mmc);
2408 dev_dbg(mmc_dev(host->mmc),
2409 "Failed to enable MMC clocks during resume\n");
2414 #define omap_hsmmc_suspend NULL
2415 #define omap_hsmmc_resume NULL
2418 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2419 .suspend = omap_hsmmc_suspend,
2420 .resume = omap_hsmmc_resume,
2423 static struct platform_driver omap_hsmmc_driver = {
2424 .remove = omap_hsmmc_remove,
2426 .name = DRIVER_NAME,
2427 .owner = THIS_MODULE,
2428 .pm = &omap_hsmmc_dev_pm_ops,
2432 static int __init omap_hsmmc_init(void)
2434 /* Register the MMC driver */
2435 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2438 static void __exit omap_hsmmc_cleanup(void)
2440 /* Unregister MMC driver */
2441 platform_driver_unregister(&omap_hsmmc_driver);
2444 module_init(omap_hsmmc_init);
2445 module_exit(omap_hsmmc_cleanup);
2447 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2448 MODULE_LICENSE("GPL");
2449 MODULE_ALIAS("platform:" DRIVER_NAME);
2450 MODULE_AUTHOR("Texas Instruments Inc");