2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
39 #include <linux/mmc/slot-gpio.h>
41 #include <linux/irq.h>
42 #include <linux/gpio.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/pinctrl/consumer.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/pm_wakeirq.h>
47 #include <linux/platform_data/hsmmc-omap.h>
49 /* OMAP HSMMC Host Controller Registers */
50 #define OMAP_HSMMC_SYSSTATUS 0x0014
51 #define OMAP_HSMMC_CON 0x002C
52 #define OMAP_HSMMC_SDMASA 0x0100
53 #define OMAP_HSMMC_BLK 0x0104
54 #define OMAP_HSMMC_ARG 0x0108
55 #define OMAP_HSMMC_CMD 0x010C
56 #define OMAP_HSMMC_RSP10 0x0110
57 #define OMAP_HSMMC_RSP32 0x0114
58 #define OMAP_HSMMC_RSP54 0x0118
59 #define OMAP_HSMMC_RSP76 0x011C
60 #define OMAP_HSMMC_DATA 0x0120
61 #define OMAP_HSMMC_PSTATE 0x0124
62 #define OMAP_HSMMC_HCTL 0x0128
63 #define OMAP_HSMMC_SYSCTL 0x012C
64 #define OMAP_HSMMC_STAT 0x0130
65 #define OMAP_HSMMC_IE 0x0134
66 #define OMAP_HSMMC_ISE 0x0138
67 #define OMAP_HSMMC_AC12 0x013C
68 #define OMAP_HSMMC_CAPA 0x0140
70 #define VS18 (1 << 26)
71 #define VS30 (1 << 25)
73 #define SDVS18 (0x5 << 9)
74 #define SDVS30 (0x6 << 9)
75 #define SDVS33 (0x7 << 9)
76 #define SDVS_MASK 0x00000E00
77 #define SDVSCLR 0xFFFFF1FF
78 #define SDVSDET 0x00000400
85 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
86 #define CLKD_MASK 0x0000FFC0
88 #define DTO_MASK 0x000F0000
90 #define INIT_STREAM (1 << 1)
91 #define ACEN_ACMD23 (2 << 2)
92 #define DP_SELECT (1 << 21)
97 #define FOUR_BIT (1 << 1)
100 #define DDR (1 << 19)
101 #define CLKEXTFREE (1 << 16)
102 #define CTPL (1 << 11)
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
113 #define DLEV_DAT(x) (1 << (20 + (x)))
115 /* Interrupt masks for IE and ISE register */
116 #define CC_EN (1 << 0)
117 #define TC_EN (1 << 1)
118 #define BWR_EN (1 << 4)
119 #define BRR_EN (1 << 5)
120 #define CIRQ_EN (1 << 8)
121 #define ERR_EN (1 << 15)
122 #define CTO_EN (1 << 16)
123 #define CCRC_EN (1 << 17)
124 #define CEB_EN (1 << 18)
125 #define CIE_EN (1 << 19)
126 #define DTO_EN (1 << 20)
127 #define DCRC_EN (1 << 21)
128 #define DEB_EN (1 << 22)
129 #define ACE_EN (1 << 24)
130 #define CERR_EN (1 << 28)
131 #define BADA_EN (1 << 29)
133 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
134 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
135 BRR_EN | BWR_EN | TC_EN | CC_EN)
138 #define ACIE (1 << 4)
139 #define ACEB (1 << 3)
140 #define ACCE (1 << 2)
141 #define ACTO (1 << 1)
142 #define ACNE (1 << 0)
144 #define MMC_AUTOSUSPEND_DELAY 100
145 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
146 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
147 #define OMAP_MMC_MIN_CLOCK 400000
148 #define OMAP_MMC_MAX_CLOCK 52000000
149 #define DRIVER_NAME "omap_hsmmc"
151 #define VDD_1V8 1800000 /* 180000 uV */
152 #define VDD_3V0 3000000 /* 300000 uV */
153 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
156 * One controller can have multiple slots, like on some omap boards using
157 * omap.c controller driver. Luckily this is not currently done on any known
158 * omap_hsmmc.c device.
160 #define mmc_pdata(host) host->pdata
163 * MMC Host controller read/write API's
165 #define OMAP_HSMMC_READ(base, reg) \
166 __raw_readl((base) + OMAP_HSMMC_##reg)
168 #define OMAP_HSMMC_WRITE(base, reg, val) \
169 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
171 struct omap_hsmmc_next {
172 unsigned int dma_len;
176 struct omap_hsmmc_host {
178 struct mmc_host *mmc;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
184 struct regulator *pbias;
187 resource_size_t mapbase;
188 spinlock_t irq_lock; /* Prevent races with irq handler */
189 unsigned int dma_len;
190 unsigned int dma_sg_idx;
191 unsigned char bus_mode;
192 unsigned char power_mode;
201 struct dma_chan *tx_chan;
202 struct dma_chan *rx_chan;
208 unsigned long clk_rate;
210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
212 struct omap_hsmmc_next next_data;
213 struct omap_hsmmc_platform_data *pdata;
215 /* return MMC cover switch state, can be NULL if not supported.
217 * possible return values:
221 int (*get_cover_state)(struct device *dev);
223 int (*card_detect)(struct device *dev);
226 struct omap_mmc_of_data {
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233 static int omap_hsmmc_card_detect(struct device *dev)
235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237 return mmc_gpio_get_cd(host->mmc);
240 static int omap_hsmmc_get_cover_state(struct device *dev)
242 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
244 return mmc_gpio_get_cd(host->mmc);
247 static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
250 struct omap_hsmmc_host *host = mmc_priv(mmc);
251 struct mmc_ios *ios = &mmc->ios;
253 if (mmc->supply.vmmc) {
254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
259 /* Enable interface voltage rail, if needed */
260 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
261 ret = regulator_enable(mmc->supply.vqmmc);
263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
266 host->vqmmc_enabled = 1;
272 if (mmc->supply.vmmc)
273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
278 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
282 struct omap_hsmmc_host *host = mmc_priv(mmc);
284 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
285 ret = regulator_disable(mmc->supply.vqmmc);
287 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
290 host->vqmmc_enabled = 0;
293 if (mmc->supply.vmmc) {
294 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
302 if (mmc->supply.vqmmc) {
303 status = regulator_enable(mmc->supply.vqmmc);
305 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
311 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
320 if (vdd <= VDD_165_195)
321 ret = regulator_set_voltage(host->pbias, VDD_1V8,
324 ret = regulator_set_voltage(host->pbias, VDD_3V0,
327 dev_err(host->dev, "pbias set voltage fail\n");
331 if (!regulator_is_enabled(host->pbias)) {
332 ret = regulator_enable(host->pbias);
334 dev_err(host->dev, "pbias reg enable fail\n");
339 if (regulator_is_enabled(host->pbias)) {
340 ret = regulator_disable(host->pbias);
342 dev_err(host->dev, "pbias reg disable fail\n");
351 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
353 struct omap_hsmmc_host *host =
354 platform_get_drvdata(to_platform_device(dev));
355 struct mmc_host *mmc = host->mmc;
358 if (mmc_pdata(host)->set_power)
359 return mmc_pdata(host)->set_power(dev, power_on, vdd);
362 * If we don't see a Vcc regulator, assume it's a fixed
363 * voltage always-on regulator.
365 if (!mmc->supply.vmmc)
368 if (mmc_pdata(host)->before_set_reg)
369 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
371 ret = omap_hsmmc_set_pbias(host, false, 0);
376 * Assume Vcc regulator is used only to power the card ... OMAP
377 * VDDS is used to power the pins, optionally with a transceiver to
378 * support cards using voltages other than VDDS (1.8V nominal). When a
379 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
381 * In some cases this regulator won't support enable/disable;
382 * e.g. it's a fixed rail for a WLAN chip.
384 * In other cases vcc_aux switches interface power. Example, for
385 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
386 * chips/cards need an interface voltage rail too.
389 ret = omap_hsmmc_enable_supply(mmc);
393 ret = omap_hsmmc_set_pbias(host, true, vdd);
395 goto err_set_voltage;
397 ret = omap_hsmmc_disable_supply(mmc);
402 if (mmc_pdata(host)->after_set_reg)
403 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
408 omap_hsmmc_disable_supply(mmc);
413 static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
420 if (regulator_is_enabled(reg)) {
421 ret = regulator_enable(reg);
425 ret = regulator_disable(reg);
433 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
435 struct mmc_host *mmc = host->mmc;
439 * disable regulators enabled during boot and get the usecount
440 * right so that regulators can be enabled/disabled by checking
441 * the return value of regulator_is_enabled
443 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
445 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
449 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
452 "fail to disable boot enabled vmmc_aux reg\n");
456 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
459 "failed to disable boot enabled pbias reg\n");
466 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
470 struct mmc_host *mmc = host->mmc;
472 if (mmc_pdata(host)->set_power)
475 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
476 if (IS_ERR(mmc->supply.vmmc)) {
477 ret = PTR_ERR(mmc->supply.vmmc);
480 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
481 PTR_ERR(mmc->supply.vmmc));
482 mmc->supply.vmmc = NULL;
484 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
486 mmc_pdata(host)->ocr_mask = ocr_value;
489 /* Allow an aux regulator */
490 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
491 if (IS_ERR(mmc->supply.vqmmc)) {
492 ret = PTR_ERR(mmc->supply.vqmmc);
495 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
496 PTR_ERR(mmc->supply.vqmmc));
497 mmc->supply.vqmmc = NULL;
500 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
501 if (IS_ERR(host->pbias)) {
502 ret = PTR_ERR(host->pbias);
505 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
506 PTR_ERR(host->pbias));
510 /* For eMMC do not power off when not in sleep state */
511 if (mmc_pdata(host)->no_regulator_off_init)
514 ret = omap_hsmmc_disable_boot_regulators(host);
521 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
523 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
524 struct omap_hsmmc_host *host,
525 struct omap_hsmmc_platform_data *pdata)
529 if (gpio_is_valid(pdata->gpio_cod)) {
530 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
534 host->get_cover_state = omap_hsmmc_get_cover_state;
535 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
536 } else if (gpio_is_valid(pdata->gpio_cd)) {
537 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
541 host->card_detect = omap_hsmmc_card_detect;
544 if (gpio_is_valid(pdata->gpio_wp)) {
545 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
554 * Start clock to the card
556 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
558 OMAP_HSMMC_WRITE(host->base, SYSCTL,
559 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
563 * Stop clock to the card
565 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
567 OMAP_HSMMC_WRITE(host->base, SYSCTL,
568 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
569 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
570 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
573 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
574 struct mmc_command *cmd)
576 u32 irq_mask = INT_EN_MASK;
580 irq_mask &= ~(BRR_EN | BWR_EN);
582 /* Disable timeout for erases */
583 if (cmd->opcode == MMC_ERASE)
586 spin_lock_irqsave(&host->irq_lock, flags);
587 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
588 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
590 /* latch pending CIRQ, but don't signal MMC core */
591 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
593 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
594 spin_unlock_irqrestore(&host->irq_lock, flags);
597 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
602 spin_lock_irqsave(&host->irq_lock, flags);
603 /* no transfer running but need to keep cirq if enabled */
604 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
606 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
607 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
608 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
609 spin_unlock_irqrestore(&host->irq_lock, flags);
612 /* Calculate divisor for the given clock frequency */
613 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
618 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
626 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
628 struct mmc_ios *ios = &host->mmc->ios;
629 unsigned long regval;
630 unsigned long timeout;
631 unsigned long clkdiv;
633 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
635 omap_hsmmc_stop_clock(host);
637 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
638 regval = regval & ~(CLKD_MASK | DTO_MASK);
639 clkdiv = calc_divisor(host, ios);
640 regval = regval | (clkdiv << 6) | (DTO << 16);
641 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
642 OMAP_HSMMC_WRITE(host->base, SYSCTL,
643 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
645 /* Wait till the ICS bit is set */
646 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
647 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
648 && time_before(jiffies, timeout))
652 * Enable High-Speed Support
654 * - Controller should support High-Speed-Enable Bit
655 * - Controller should not be using DDR Mode
656 * - Controller should advertise that it supports High Speed
657 * in capabilities register
658 * - MMC/SD clock coming out of controller > 25MHz
660 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
661 (ios->timing != MMC_TIMING_MMC_DDR52) &&
662 (ios->timing != MMC_TIMING_UHS_DDR50) &&
663 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
664 regval = OMAP_HSMMC_READ(host->base, HCTL);
665 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
670 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
673 omap_hsmmc_start_clock(host);
676 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
678 struct mmc_ios *ios = &host->mmc->ios;
681 con = OMAP_HSMMC_READ(host->base, CON);
682 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
683 ios->timing == MMC_TIMING_UHS_DDR50)
684 con |= DDR; /* configure in DDR mode */
687 switch (ios->bus_width) {
688 case MMC_BUS_WIDTH_8:
689 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
691 case MMC_BUS_WIDTH_4:
692 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
693 OMAP_HSMMC_WRITE(host->base, HCTL,
694 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
696 case MMC_BUS_WIDTH_1:
697 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
698 OMAP_HSMMC_WRITE(host->base, HCTL,
699 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
704 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
706 struct mmc_ios *ios = &host->mmc->ios;
709 con = OMAP_HSMMC_READ(host->base, CON);
710 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
711 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
713 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
719 * Restore the MMC host context, if it was lost as result of a
720 * power state change.
722 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
724 struct mmc_ios *ios = &host->mmc->ios;
726 unsigned long timeout;
728 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
729 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
730 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
731 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
734 host->context_loss++;
736 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
737 if (host->power_mode != MMC_POWER_OFF &&
738 (1 << ios->vdd) <= MMC_VDD_23_24)
748 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
751 OMAP_HSMMC_WRITE(host->base, HCTL,
752 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
754 OMAP_HSMMC_WRITE(host->base, CAPA,
755 OMAP_HSMMC_READ(host->base, CAPA) | capa);
757 OMAP_HSMMC_WRITE(host->base, HCTL,
758 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
760 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
761 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
762 && time_before(jiffies, timeout))
765 OMAP_HSMMC_WRITE(host->base, ISE, 0);
766 OMAP_HSMMC_WRITE(host->base, IE, 0);
767 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
769 /* Do not initialize card-specific things if the power is off */
770 if (host->power_mode == MMC_POWER_OFF)
773 omap_hsmmc_set_bus_width(host);
775 omap_hsmmc_set_clock(host);
777 omap_hsmmc_set_bus_mode(host);
780 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
786 * Save the MMC host context (store the number of power state changes so far).
788 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
790 host->con = OMAP_HSMMC_READ(host->base, CON);
791 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
792 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
793 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
798 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
803 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
810 * Send init stream sequence to card
811 * before sending IDLE command
813 static void send_init_stream(struct omap_hsmmc_host *host)
816 unsigned long timeout;
818 if (host->protect_card)
821 disable_irq(host->irq);
823 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
824 OMAP_HSMMC_WRITE(host->base, CON,
825 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
826 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
828 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
829 while ((reg != CC_EN) && time_before(jiffies, timeout))
830 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
832 OMAP_HSMMC_WRITE(host->base, CON,
833 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
835 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
836 OMAP_HSMMC_READ(host->base, STAT);
838 enable_irq(host->irq);
842 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
846 if (host->get_cover_state)
847 r = host->get_cover_state(host->dev);
852 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
855 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
856 struct omap_hsmmc_host *host = mmc_priv(mmc);
858 return sprintf(buf, "%s\n",
859 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
862 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
865 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
868 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
869 struct omap_hsmmc_host *host = mmc_priv(mmc);
871 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
874 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
877 * Configure the response type and send the cmd.
880 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
881 struct mmc_data *data)
883 int cmdreg = 0, resptype = 0, cmdtype = 0;
885 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
886 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
889 omap_hsmmc_enable_irq(host, cmd);
891 host->response_busy = 0;
892 if (cmd->flags & MMC_RSP_PRESENT) {
893 if (cmd->flags & MMC_RSP_136)
895 else if (cmd->flags & MMC_RSP_BUSY) {
897 host->response_busy = 1;
903 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
904 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
905 * a val of 0x3, rest 0x0.
907 if (cmd == host->mrq->stop)
910 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
912 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
914 cmdreg |= ACEN_ACMD23;
915 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
918 cmdreg |= DP_SELECT | MSBS | BCE;
919 if (data->flags & MMC_DATA_READ)
928 host->req_in_progress = 1;
930 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
931 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
935 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
937 if (data->flags & MMC_DATA_WRITE)
938 return DMA_TO_DEVICE;
940 return DMA_FROM_DEVICE;
943 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
944 struct mmc_data *data)
946 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
949 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
954 spin_lock_irqsave(&host->irq_lock, flags);
955 host->req_in_progress = 0;
956 dma_ch = host->dma_ch;
957 spin_unlock_irqrestore(&host->irq_lock, flags);
959 omap_hsmmc_disable_irq(host);
960 /* Do not complete the request if DMA is still in progress */
961 if (mrq->data && host->use_dma && dma_ch != -1)
964 mmc_request_done(host->mmc, mrq);
965 pm_runtime_mark_last_busy(host->dev);
966 pm_runtime_put_autosuspend(host->dev);
970 * Notify the transfer complete to MMC core
973 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
976 struct mmc_request *mrq = host->mrq;
978 /* TC before CC from CMD6 - don't know why, but it happens */
979 if (host->cmd && host->cmd->opcode == 6 &&
980 host->response_busy) {
981 host->response_busy = 0;
985 omap_hsmmc_request_done(host, mrq);
992 data->bytes_xfered += data->blocks * (data->blksz);
994 data->bytes_xfered = 0;
996 if (data->stop && (data->error || !host->mrq->sbc))
997 omap_hsmmc_start_command(host, data->stop, NULL);
999 omap_hsmmc_request_done(host, data->mrq);
1003 * Notify the core about command completion
1006 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1008 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
1009 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
1011 omap_hsmmc_start_dma_transfer(host);
1012 omap_hsmmc_start_command(host, host->mrq->cmd,
1019 if (cmd->flags & MMC_RSP_PRESENT) {
1020 if (cmd->flags & MMC_RSP_136) {
1021 /* response type 2 */
1022 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1023 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1024 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1025 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1027 /* response types 1, 1b, 3, 4, 5, 6 */
1028 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1031 if ((host->data == NULL && !host->response_busy) || cmd->error)
1032 omap_hsmmc_request_done(host, host->mrq);
1036 * DMA clean up for command errors
1038 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1041 unsigned long flags;
1043 host->data->error = errno;
1045 spin_lock_irqsave(&host->irq_lock, flags);
1046 dma_ch = host->dma_ch;
1048 spin_unlock_irqrestore(&host->irq_lock, flags);
1050 if (host->use_dma && dma_ch != -1) {
1051 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1053 dmaengine_terminate_all(chan);
1054 dma_unmap_sg(chan->device->dev,
1055 host->data->sg, host->data->sg_len,
1056 omap_hsmmc_get_dma_dir(host, host->data));
1058 host->data->host_cookie = 0;
1064 * Readable error output
1066 #ifdef CONFIG_MMC_DEBUG
1067 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1069 /* --- means reserved bit without definition at documentation */
1070 static const char *omap_hsmmc_status_bits[] = {
1071 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1072 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1073 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1074 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1080 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1083 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1084 if (status & (1 << i)) {
1085 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1089 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1092 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1096 #endif /* CONFIG_MMC_DEBUG */
1099 * MMC controller internal state machines reset
1101 * Used to reset command or data internal state machines, using respectively
1102 * SRC or SRD bit of SYSCTL register
1103 * Can be called from interrupt context
1105 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1108 unsigned long i = 0;
1109 unsigned long limit = MMC_TIMEOUT_US;
1111 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1112 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1115 * OMAP4 ES2 and greater has an updated reset logic.
1116 * Monitor a 0->1 transition first
1118 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1119 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1125 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1129 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1130 dev_err(mmc_dev(host->mmc),
1131 "Timeout waiting on controller reset in %s\n",
1135 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1136 int err, int end_cmd)
1139 omap_hsmmc_reset_controller_fsm(host, SRC);
1141 host->cmd->error = err;
1145 omap_hsmmc_reset_controller_fsm(host, SRD);
1146 omap_hsmmc_dma_cleanup(host, err);
1147 } else if (host->mrq && host->mrq->cmd)
1148 host->mrq->cmd->error = err;
1151 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1153 struct mmc_data *data;
1154 int end_cmd = 0, end_trans = 0;
1158 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1160 if (status & ERR_EN) {
1161 omap_hsmmc_dbg_report_irq(host, status);
1163 if (status & (CTO_EN | CCRC_EN))
1165 if (host->data || host->response_busy) {
1166 end_trans = !end_cmd;
1167 host->response_busy = 0;
1169 if (status & (CTO_EN | DTO_EN))
1170 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1171 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1173 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1175 if (status & ACE_EN) {
1177 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1178 if (!(ac12 & ACNE) && host->mrq->sbc) {
1182 else if (ac12 & (ACCE | ACEB | ACIE))
1184 host->mrq->sbc->error = error;
1185 hsmmc_command_incomplete(host, error, end_cmd);
1187 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1191 OMAP_HSMMC_WRITE(host->base, STAT, status);
1192 if (end_cmd || ((status & CC_EN) && host->cmd))
1193 omap_hsmmc_cmd_done(host, host->cmd);
1194 if ((end_trans || (status & TC_EN)) && host->mrq)
1195 omap_hsmmc_xfer_done(host, data);
1199 * MMC controller IRQ handler
1201 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1203 struct omap_hsmmc_host *host = dev_id;
1206 status = OMAP_HSMMC_READ(host->base, STAT);
1207 while (status & (INT_EN_MASK | CIRQ_EN)) {
1208 if (host->req_in_progress)
1209 omap_hsmmc_do_irq(host, status);
1211 if (status & CIRQ_EN)
1212 mmc_signal_sdio_irq(host->mmc);
1214 /* Flush posted write */
1215 status = OMAP_HSMMC_READ(host->base, STAT);
1221 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1225 OMAP_HSMMC_WRITE(host->base, HCTL,
1226 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1227 for (i = 0; i < loops_per_jiffy; i++) {
1228 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1235 * Switch MMC interface voltage ... only relevant for MMC1.
1237 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1238 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1239 * Some chips, like eMMC ones, use internal transceivers.
1241 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1246 /* Disable the clocks */
1247 pm_runtime_put_sync(host->dev);
1249 clk_disable_unprepare(host->dbclk);
1251 /* Turn the power off */
1252 ret = omap_hsmmc_set_power(host->dev, 0, 0);
1254 /* Turn the power ON with given VDD 1.8 or 3.0v */
1256 ret = omap_hsmmc_set_power(host->dev, 1, vdd);
1257 pm_runtime_get_sync(host->dev);
1259 clk_prepare_enable(host->dbclk);
1264 OMAP_HSMMC_WRITE(host->base, HCTL,
1265 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1266 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1269 * If a MMC dual voltage card is detected, the set_ios fn calls
1270 * this fn with VDD bit set for 1.8V. Upon card removal from the
1271 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1273 * Cope with a bit of slop in the range ... per data sheets:
1274 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1275 * but recommended values are 1.71V to 1.89V
1276 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1277 * but recommended values are 2.7V to 3.3V
1279 * Board setup code shouldn't permit anything very out-of-range.
1280 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1281 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1283 if ((1 << vdd) <= MMC_VDD_23_24)
1288 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1289 set_sd_bus_power(host);
1293 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1297 /* Protect the card while the cover is open */
1298 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1300 if (!host->get_cover_state)
1303 host->reqs_blocked = 0;
1304 if (host->get_cover_state(host->dev)) {
1305 if (host->protect_card) {
1306 dev_info(host->dev, "%s: cover is closed, "
1307 "card is now accessible\n",
1308 mmc_hostname(host->mmc));
1309 host->protect_card = 0;
1312 if (!host->protect_card) {
1313 dev_info(host->dev, "%s: cover is open, "
1314 "card is now inaccessible\n",
1315 mmc_hostname(host->mmc));
1316 host->protect_card = 1;
1322 * irq handler when (cell-phone) cover is mounted/removed
1324 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1326 struct omap_hsmmc_host *host = dev_id;
1328 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1330 omap_hsmmc_protect_card(host);
1331 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1335 static void omap_hsmmc_dma_callback(void *param)
1337 struct omap_hsmmc_host *host = param;
1338 struct dma_chan *chan;
1339 struct mmc_data *data;
1340 int req_in_progress;
1342 spin_lock_irq(&host->irq_lock);
1343 if (host->dma_ch < 0) {
1344 spin_unlock_irq(&host->irq_lock);
1348 data = host->mrq->data;
1349 chan = omap_hsmmc_get_dma_chan(host, data);
1350 if (!data->host_cookie)
1351 dma_unmap_sg(chan->device->dev,
1352 data->sg, data->sg_len,
1353 omap_hsmmc_get_dma_dir(host, data));
1355 req_in_progress = host->req_in_progress;
1357 spin_unlock_irq(&host->irq_lock);
1359 /* If DMA has finished after TC, complete the request */
1360 if (!req_in_progress) {
1361 struct mmc_request *mrq = host->mrq;
1364 mmc_request_done(host->mmc, mrq);
1365 pm_runtime_mark_last_busy(host->dev);
1366 pm_runtime_put_autosuspend(host->dev);
1370 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1371 struct mmc_data *data,
1372 struct omap_hsmmc_next *next,
1373 struct dma_chan *chan)
1377 if (!next && data->host_cookie &&
1378 data->host_cookie != host->next_data.cookie) {
1379 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1380 " host->next_data.cookie %d\n",
1381 __func__, data->host_cookie, host->next_data.cookie);
1382 data->host_cookie = 0;
1385 /* Check if next job is already prepared */
1386 if (next || data->host_cookie != host->next_data.cookie) {
1387 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1388 omap_hsmmc_get_dma_dir(host, data));
1391 dma_len = host->next_data.dma_len;
1392 host->next_data.dma_len = 0;
1400 next->dma_len = dma_len;
1401 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1403 host->dma_len = dma_len;
1409 * Routine to configure and start DMA for the MMC card
1411 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1412 struct mmc_request *req)
1414 struct dma_slave_config cfg;
1415 struct dma_async_tx_descriptor *tx;
1417 struct mmc_data *data = req->data;
1418 struct dma_chan *chan;
1420 /* Sanity check: all the SG entries must be aligned by block size. */
1421 for (i = 0; i < data->sg_len; i++) {
1422 struct scatterlist *sgl;
1425 if (sgl->length % data->blksz)
1428 if ((data->blksz % 4) != 0)
1429 /* REVISIT: The MMC buffer increments only when MSB is written.
1430 * Return error for blksz which is non multiple of four.
1434 BUG_ON(host->dma_ch != -1);
1436 chan = omap_hsmmc_get_dma_chan(host, data);
1438 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1439 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1440 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1441 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1442 cfg.src_maxburst = data->blksz / 4;
1443 cfg.dst_maxburst = data->blksz / 4;
1445 ret = dmaengine_slave_config(chan, &cfg);
1449 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1453 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1454 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1455 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1457 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1458 /* FIXME: cleanup */
1462 tx->callback = omap_hsmmc_dma_callback;
1463 tx->callback_param = host;
1466 dmaengine_submit(tx);
1473 static void set_data_timeout(struct omap_hsmmc_host *host,
1474 unsigned int timeout_ns,
1475 unsigned int timeout_clks)
1477 unsigned int timeout, cycle_ns;
1478 uint32_t reg, clkd, dto = 0;
1480 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1481 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1485 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1486 timeout = timeout_ns / cycle_ns;
1487 timeout += timeout_clks;
1489 while ((timeout & 0x80000000) == 0) {
1506 reg |= dto << DTO_SHIFT;
1507 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1510 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1512 struct mmc_request *req = host->mrq;
1513 struct dma_chan *chan;
1517 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1518 | (req->data->blocks << 16));
1519 set_data_timeout(host, req->data->timeout_ns,
1520 req->data->timeout_clks);
1521 chan = omap_hsmmc_get_dma_chan(host, req->data);
1522 dma_async_issue_pending(chan);
1526 * Configure block length for MMC/SD cards and initiate the transfer.
1529 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1532 host->data = req->data;
1534 if (req->data == NULL) {
1535 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1537 * Set an arbitrary 100ms data timeout for commands with
1540 if (req->cmd->flags & MMC_RSP_BUSY)
1541 set_data_timeout(host, 100000000U, 0);
1545 if (host->use_dma) {
1546 ret = omap_hsmmc_setup_dma_transfer(host, req);
1548 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1555 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1558 struct omap_hsmmc_host *host = mmc_priv(mmc);
1559 struct mmc_data *data = mrq->data;
1561 if (host->use_dma && data->host_cookie) {
1562 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1564 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1565 omap_hsmmc_get_dma_dir(host, data));
1566 data->host_cookie = 0;
1570 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1573 struct omap_hsmmc_host *host = mmc_priv(mmc);
1575 if (mrq->data->host_cookie) {
1576 mrq->data->host_cookie = 0;
1580 if (host->use_dma) {
1581 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1583 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1584 &host->next_data, c))
1585 mrq->data->host_cookie = 0;
1590 * Request function. for read/write operation
1592 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
1597 BUG_ON(host->req_in_progress);
1598 BUG_ON(host->dma_ch != -1);
1599 pm_runtime_get_sync(host->dev);
1600 if (host->protect_card) {
1601 if (host->reqs_blocked < 3) {
1603 * Ensure the controller is left in a consistent
1604 * state by resetting the command and data state
1607 omap_hsmmc_reset_controller_fsm(host, SRD);
1608 omap_hsmmc_reset_controller_fsm(host, SRC);
1609 host->reqs_blocked += 1;
1611 req->cmd->error = -EBADF;
1613 req->data->error = -EBADF;
1614 req->cmd->retries = 0;
1615 mmc_request_done(mmc, req);
1616 pm_runtime_mark_last_busy(host->dev);
1617 pm_runtime_put_autosuspend(host->dev);
1619 } else if (host->reqs_blocked)
1620 host->reqs_blocked = 0;
1621 WARN_ON(host->mrq != NULL);
1623 host->clk_rate = clk_get_rate(host->fclk);
1624 err = omap_hsmmc_prepare_data(host, req);
1626 req->cmd->error = err;
1628 req->data->error = err;
1630 mmc_request_done(mmc, req);
1631 pm_runtime_mark_last_busy(host->dev);
1632 pm_runtime_put_autosuspend(host->dev);
1635 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1636 omap_hsmmc_start_command(host, req->sbc, NULL);
1640 omap_hsmmc_start_dma_transfer(host);
1641 omap_hsmmc_start_command(host, req->cmd, req->data);
1644 /* Routine to configure clock values. Exposed API to core */
1645 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1647 struct omap_hsmmc_host *host = mmc_priv(mmc);
1648 int do_send_init_stream = 0;
1650 pm_runtime_get_sync(host->dev);
1652 if (ios->power_mode != host->power_mode) {
1653 switch (ios->power_mode) {
1655 omap_hsmmc_set_power(host->dev, 0, 0);
1658 omap_hsmmc_set_power(host->dev, 1, ios->vdd);
1661 do_send_init_stream = 1;
1664 host->power_mode = ios->power_mode;
1667 /* FIXME: set registers based only on changes to ios */
1669 omap_hsmmc_set_bus_width(host);
1671 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1672 /* Only MMC1 can interface at 3V without some flavor
1673 * of external transceiver; but they all handle 1.8V.
1675 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1676 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1678 * The mmc_select_voltage fn of the core does
1679 * not seem to set the power_mode to
1680 * MMC_POWER_UP upon recalculating the voltage.
1683 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1684 dev_dbg(mmc_dev(host->mmc),
1685 "Switch operation failed\n");
1689 omap_hsmmc_set_clock(host);
1691 if (do_send_init_stream)
1692 send_init_stream(host);
1694 omap_hsmmc_set_bus_mode(host);
1696 pm_runtime_put_autosuspend(host->dev);
1699 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1701 struct omap_hsmmc_host *host = mmc_priv(mmc);
1703 if (!host->card_detect)
1705 return host->card_detect(host->dev);
1708 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1710 struct omap_hsmmc_host *host = mmc_priv(mmc);
1712 if (mmc_pdata(host)->init_card)
1713 mmc_pdata(host)->init_card(card);
1716 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1718 struct omap_hsmmc_host *host = mmc_priv(mmc);
1720 unsigned long flags;
1722 spin_lock_irqsave(&host->irq_lock, flags);
1724 con = OMAP_HSMMC_READ(host->base, CON);
1725 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1727 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1728 irq_mask |= CIRQ_EN;
1729 con |= CTPL | CLKEXTFREE;
1731 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1732 irq_mask &= ~CIRQ_EN;
1733 con &= ~(CTPL | CLKEXTFREE);
1735 OMAP_HSMMC_WRITE(host->base, CON, con);
1736 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1739 * if enable, piggy back detection on current request
1740 * but always disable immediately
1742 if (!host->req_in_progress || !enable)
1743 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1745 /* flush posted write */
1746 OMAP_HSMMC_READ(host->base, IE);
1748 spin_unlock_irqrestore(&host->irq_lock, flags);
1751 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1756 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1757 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1758 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1759 * with functional clock disabled.
1761 if (!host->dev->of_node || !host->wake_irq)
1764 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1766 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1771 * Some omaps don't have wake-up path from deeper idle states
1772 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1774 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1775 struct pinctrl *p = devm_pinctrl_get(host->dev);
1780 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1781 dev_info(host->dev, "missing default pinctrl state\n");
1782 devm_pinctrl_put(p);
1787 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1788 dev_info(host->dev, "missing idle pinctrl state\n");
1789 devm_pinctrl_put(p);
1793 devm_pinctrl_put(p);
1796 OMAP_HSMMC_WRITE(host->base, HCTL,
1797 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1801 dev_pm_clear_wake_irq(host->dev);
1803 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1808 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1810 u32 hctl, capa, value;
1812 /* Only MMC1 supports 3.0V */
1813 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1821 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1822 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1824 value = OMAP_HSMMC_READ(host->base, CAPA);
1825 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1827 /* Set SD bus power bit */
1828 set_sd_bus_power(host);
1831 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1832 unsigned int direction, int blk_size)
1834 /* This controller can't do multiblock reads due to hw bugs */
1835 if (direction == MMC_DATA_READ)
1841 static struct mmc_host_ops omap_hsmmc_ops = {
1842 .post_req = omap_hsmmc_post_req,
1843 .pre_req = omap_hsmmc_pre_req,
1844 .request = omap_hsmmc_request,
1845 .set_ios = omap_hsmmc_set_ios,
1846 .get_cd = omap_hsmmc_get_cd,
1847 .get_ro = mmc_gpio_get_ro,
1848 .init_card = omap_hsmmc_init_card,
1849 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1852 #ifdef CONFIG_DEBUG_FS
1854 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1856 struct mmc_host *mmc = s->private;
1857 struct omap_hsmmc_host *host = mmc_priv(mmc);
1859 seq_printf(s, "mmc%d:\n", mmc->index);
1860 seq_printf(s, "sdio irq mode\t%s\n",
1861 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1863 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1864 seq_printf(s, "sdio irq \t%s\n",
1865 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1868 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1870 pm_runtime_get_sync(host->dev);
1871 seq_puts(s, "\nregs:\n");
1872 seq_printf(s, "CON:\t\t0x%08x\n",
1873 OMAP_HSMMC_READ(host->base, CON));
1874 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1875 OMAP_HSMMC_READ(host->base, PSTATE));
1876 seq_printf(s, "HCTL:\t\t0x%08x\n",
1877 OMAP_HSMMC_READ(host->base, HCTL));
1878 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1879 OMAP_HSMMC_READ(host->base, SYSCTL));
1880 seq_printf(s, "IE:\t\t0x%08x\n",
1881 OMAP_HSMMC_READ(host->base, IE));
1882 seq_printf(s, "ISE:\t\t0x%08x\n",
1883 OMAP_HSMMC_READ(host->base, ISE));
1884 seq_printf(s, "CAPA:\t\t0x%08x\n",
1885 OMAP_HSMMC_READ(host->base, CAPA));
1887 pm_runtime_mark_last_busy(host->dev);
1888 pm_runtime_put_autosuspend(host->dev);
1893 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1895 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1898 static const struct file_operations mmc_regs_fops = {
1899 .open = omap_hsmmc_regs_open,
1901 .llseek = seq_lseek,
1902 .release = single_release,
1905 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1907 if (mmc->debugfs_root)
1908 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1909 mmc, &mmc_regs_fops);
1914 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1921 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1922 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1923 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1926 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1927 .reg_offset = 0x100,
1929 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1930 .reg_offset = 0x100,
1931 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1934 static const struct of_device_id omap_mmc_of_match[] = {
1936 .compatible = "ti,omap2-hsmmc",
1939 .compatible = "ti,omap3-pre-es3-hsmmc",
1940 .data = &omap3_pre_es3_mmc_of_data,
1943 .compatible = "ti,omap3-hsmmc",
1946 .compatible = "ti,omap4-hsmmc",
1947 .data = &omap4_mmc_of_data,
1950 .compatible = "ti,am33xx-hsmmc",
1951 .data = &am33xx_mmc_of_data,
1955 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1957 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1959 struct omap_hsmmc_platform_data *pdata;
1960 struct device_node *np = dev->of_node;
1962 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1964 return ERR_PTR(-ENOMEM); /* out of memory */
1966 if (of_find_property(np, "ti,dual-volt", NULL))
1967 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1969 pdata->gpio_cd = -EINVAL;
1970 pdata->gpio_cod = -EINVAL;
1971 pdata->gpio_wp = -EINVAL;
1973 if (of_find_property(np, "ti,non-removable", NULL)) {
1974 pdata->nonremovable = true;
1975 pdata->no_regulator_off_init = true;
1978 if (of_find_property(np, "ti,needs-special-reset", NULL))
1979 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1981 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1982 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1987 static inline struct omap_hsmmc_platform_data
1988 *of_get_hsmmc_pdata(struct device *dev)
1990 return ERR_PTR(-EINVAL);
1994 static int omap_hsmmc_probe(struct platform_device *pdev)
1996 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1997 struct mmc_host *mmc;
1998 struct omap_hsmmc_host *host = NULL;
1999 struct resource *res;
2001 const struct of_device_id *match;
2002 dma_cap_mask_t mask;
2003 unsigned tx_req, rx_req;
2004 const struct omap_mmc_of_data *data;
2007 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2009 pdata = of_get_hsmmc_pdata(&pdev->dev);
2012 return PTR_ERR(pdata);
2016 pdata->reg_offset = data->reg_offset;
2017 pdata->controller_flags |= data->controller_flags;
2021 if (pdata == NULL) {
2022 dev_err(&pdev->dev, "Platform Data is missing\n");
2026 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2027 irq = platform_get_irq(pdev, 0);
2028 if (res == NULL || irq < 0)
2031 base = devm_ioremap_resource(&pdev->dev, res);
2033 return PTR_ERR(base);
2035 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2041 ret = mmc_of_parse(mmc);
2045 host = mmc_priv(mmc);
2047 host->pdata = pdata;
2048 host->dev = &pdev->dev;
2052 host->mapbase = res->start + pdata->reg_offset;
2053 host->base = base + pdata->reg_offset;
2054 host->power_mode = MMC_POWER_OFF;
2055 host->next_data.cookie = 1;
2056 host->vqmmc_enabled = 0;
2058 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2062 platform_set_drvdata(pdev, host);
2064 if (pdev->dev.of_node)
2065 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2067 mmc->ops = &omap_hsmmc_ops;
2069 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2071 if (pdata->max_freq > 0)
2072 mmc->f_max = pdata->max_freq;
2073 else if (mmc->f_max == 0)
2074 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2076 spin_lock_init(&host->irq_lock);
2078 host->fclk = devm_clk_get(&pdev->dev, "fck");
2079 if (IS_ERR(host->fclk)) {
2080 ret = PTR_ERR(host->fclk);
2085 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2086 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2087 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2090 device_init_wakeup(&pdev->dev, true);
2091 pm_runtime_enable(host->dev);
2092 pm_runtime_get_sync(host->dev);
2093 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2094 pm_runtime_use_autosuspend(host->dev);
2096 omap_hsmmc_context_save(host);
2098 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2100 * MMC can still work without debounce clock.
2102 if (IS_ERR(host->dbclk)) {
2104 } else if (clk_prepare_enable(host->dbclk) != 0) {
2105 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2109 /* Since we do only SG emulation, we can have as many segs
2111 mmc->max_segs = 1024;
2113 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2114 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2115 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2116 mmc->max_seg_size = mmc->max_req_size;
2118 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2119 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2121 mmc->caps |= mmc_pdata(host)->caps;
2122 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2123 mmc->caps |= MMC_CAP_4_BIT_DATA;
2125 if (mmc_pdata(host)->nonremovable)
2126 mmc->caps |= MMC_CAP_NONREMOVABLE;
2128 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2130 omap_hsmmc_conf_bus_power(host);
2132 if (!pdev->dev.of_node) {
2133 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2135 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2139 tx_req = res->start;
2141 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2143 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2147 rx_req = res->start;
2151 dma_cap_set(DMA_SLAVE, mask);
2154 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2155 &rx_req, &pdev->dev, "rx");
2157 if (!host->rx_chan) {
2158 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2164 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2165 &tx_req, &pdev->dev, "tx");
2167 if (!host->tx_chan) {
2168 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2173 /* Request IRQ for MMC operations */
2174 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2175 mmc_hostname(mmc), host);
2177 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2181 ret = omap_hsmmc_reg_get(host);
2185 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2187 omap_hsmmc_disable_irq(host);
2190 * For now, only support SDIO interrupt if we have a separate
2191 * wake-up interrupt configured from device tree. This is because
2192 * the wake-up interrupt is needed for idle state and some
2193 * platforms need special quirks. And we don't want to add new
2194 * legacy mux platform init code callbacks any longer as we
2195 * are moving to DT based booting anyways.
2197 ret = omap_hsmmc_configure_wake_irq(host);
2199 mmc->caps |= MMC_CAP_SDIO_IRQ;
2201 omap_hsmmc_protect_card(host);
2205 if (mmc_pdata(host)->name != NULL) {
2206 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2210 if (host->get_cover_state) {
2211 ret = device_create_file(&mmc->class_dev,
2212 &dev_attr_cover_switch);
2217 omap_hsmmc_debugfs(mmc);
2218 pm_runtime_mark_last_busy(host->dev);
2219 pm_runtime_put_autosuspend(host->dev);
2224 mmc_remove_host(mmc);
2226 device_init_wakeup(&pdev->dev, false);
2228 dma_release_channel(host->tx_chan);
2230 dma_release_channel(host->rx_chan);
2231 pm_runtime_put_sync(host->dev);
2232 pm_runtime_disable(host->dev);
2234 clk_disable_unprepare(host->dbclk);
2242 static int omap_hsmmc_remove(struct platform_device *pdev)
2244 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2246 pm_runtime_get_sync(host->dev);
2247 mmc_remove_host(host->mmc);
2250 dma_release_channel(host->tx_chan);
2252 dma_release_channel(host->rx_chan);
2254 pm_runtime_put_sync(host->dev);
2255 pm_runtime_disable(host->dev);
2256 device_init_wakeup(&pdev->dev, false);
2258 clk_disable_unprepare(host->dbclk);
2260 mmc_free_host(host->mmc);
2265 #ifdef CONFIG_PM_SLEEP
2266 static int omap_hsmmc_suspend(struct device *dev)
2268 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2273 pm_runtime_get_sync(host->dev);
2275 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2276 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2277 OMAP_HSMMC_WRITE(host->base, IE, 0);
2278 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2279 OMAP_HSMMC_WRITE(host->base, HCTL,
2280 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2284 clk_disable_unprepare(host->dbclk);
2286 pm_runtime_put_sync(host->dev);
2290 /* Routine to resume the MMC device */
2291 static int omap_hsmmc_resume(struct device *dev)
2293 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2298 pm_runtime_get_sync(host->dev);
2301 clk_prepare_enable(host->dbclk);
2303 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2304 omap_hsmmc_conf_bus_power(host);
2306 omap_hsmmc_protect_card(host);
2307 pm_runtime_mark_last_busy(host->dev);
2308 pm_runtime_put_autosuspend(host->dev);
2313 static int omap_hsmmc_runtime_suspend(struct device *dev)
2315 struct omap_hsmmc_host *host;
2316 unsigned long flags;
2319 host = platform_get_drvdata(to_platform_device(dev));
2320 omap_hsmmc_context_save(host);
2321 dev_dbg(dev, "disabled\n");
2323 spin_lock_irqsave(&host->irq_lock, flags);
2324 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2325 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2326 /* disable sdio irq handling to prevent race */
2327 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2328 OMAP_HSMMC_WRITE(host->base, IE, 0);
2330 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2332 * dat1 line low, pending sdio irq
2333 * race condition: possible irq handler running on
2336 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2337 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2338 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2339 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2340 pm_runtime_mark_last_busy(dev);
2345 pinctrl_pm_select_idle_state(dev);
2347 pinctrl_pm_select_idle_state(dev);
2351 spin_unlock_irqrestore(&host->irq_lock, flags);
2355 static int omap_hsmmc_runtime_resume(struct device *dev)
2357 struct omap_hsmmc_host *host;
2358 unsigned long flags;
2360 host = platform_get_drvdata(to_platform_device(dev));
2361 omap_hsmmc_context_restore(host);
2362 dev_dbg(dev, "enabled\n");
2364 spin_lock_irqsave(&host->irq_lock, flags);
2365 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2366 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2368 pinctrl_pm_select_default_state(host->dev);
2370 /* irq lost, if pinmux incorrect */
2371 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2372 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2373 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2375 pinctrl_pm_select_default_state(host->dev);
2377 spin_unlock_irqrestore(&host->irq_lock, flags);
2381 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2382 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2383 .runtime_suspend = omap_hsmmc_runtime_suspend,
2384 .runtime_resume = omap_hsmmc_runtime_resume,
2387 static struct platform_driver omap_hsmmc_driver = {
2388 .probe = omap_hsmmc_probe,
2389 .remove = omap_hsmmc_remove,
2391 .name = DRIVER_NAME,
2392 .pm = &omap_hsmmc_dev_pm_ops,
2393 .of_match_table = of_match_ptr(omap_mmc_of_match),
2397 module_platform_driver(omap_hsmmc_driver);
2398 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2399 MODULE_LICENSE("GPL");
2400 MODULE_ALIAS("platform:" DRIVER_NAME);
2401 MODULE_AUTHOR("Texas Instruments Inc");