2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/pm_runtime.h>
34 #include <asm/div64.h>
36 #include <asm/sizes.h>
40 #define DRIVER_NAME "mmci-pl18x"
42 static unsigned int fmax = 515633;
45 * struct variant_data - MMCI variant-specific quirks
46 * @clkreg: default value for MCICLOCK register
47 * @clkreg_enable: enable value for MMCICLOCK register
48 * @datalength_bits: number of bits in the MMCIDATALENGTH register
49 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
50 * is asserted (likewise for RX)
51 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
52 * is asserted (likewise for RX)
53 * @sdio: variant supports SDIO
54 * @st_clkdiv: true if using a ST-specific clock divider algorithm
55 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
56 * @pwrreg_powerup: power up value for MMCIPOWER register
57 * @signal_direction: input/out direction of bus signals can be indicated
61 unsigned int clkreg_enable;
62 unsigned int datalength_bits;
63 unsigned int fifosize;
64 unsigned int fifohalfsize;
67 bool blksz_datactrl16;
69 bool signal_direction;
72 static struct variant_data variant_arm = {
74 .fifohalfsize = 8 * 4,
75 .datalength_bits = 16,
76 .pwrreg_powerup = MCI_PWR_UP,
79 static struct variant_data variant_arm_extended_fifo = {
81 .fifohalfsize = 64 * 4,
82 .datalength_bits = 16,
83 .pwrreg_powerup = MCI_PWR_UP,
86 static struct variant_data variant_u300 = {
88 .fifohalfsize = 8 * 4,
89 .clkreg_enable = MCI_ST_U300_HWFCEN,
90 .datalength_bits = 16,
92 .pwrreg_powerup = MCI_PWR_ON,
93 .signal_direction = true,
96 static struct variant_data variant_ux500 = {
98 .fifohalfsize = 8 * 4,
99 .clkreg = MCI_CLK_ENABLE,
100 .clkreg_enable = MCI_ST_UX500_HWFCEN,
101 .datalength_bits = 24,
104 .pwrreg_powerup = MCI_PWR_ON,
105 .signal_direction = true,
108 static struct variant_data variant_ux500v2 = {
110 .fifohalfsize = 8 * 4,
111 .clkreg = MCI_CLK_ENABLE,
112 .clkreg_enable = MCI_ST_UX500_HWFCEN,
113 .datalength_bits = 24,
116 .blksz_datactrl16 = true,
117 .pwrreg_powerup = MCI_PWR_ON,
118 .signal_direction = true,
122 * This must be called with host->lock held
124 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
126 struct variant_data *variant = host->variant;
127 u32 clk = variant->clkreg;
130 if (desired >= host->mclk) {
131 clk = MCI_CLK_BYPASS;
132 if (variant->st_clkdiv)
133 clk |= MCI_ST_UX500_NEG_EDGE;
134 host->cclk = host->mclk;
135 } else if (variant->st_clkdiv) {
137 * DB8500 TRM says f = mclk / (clkdiv + 2)
138 * => clkdiv = (mclk / f) - 2
139 * Round the divider up so we don't exceed the max
142 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
145 host->cclk = host->mclk / (clk + 2);
148 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
149 * => clkdiv = mclk / (2 * f) - 1
151 clk = host->mclk / (2 * desired) - 1;
154 host->cclk = host->mclk / (2 * (clk + 1));
157 clk |= variant->clkreg_enable;
158 clk |= MCI_CLK_ENABLE;
159 /* This hasn't proven to be worthwhile */
160 /* clk |= MCI_CLK_PWRSAVE; */
163 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
165 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
166 clk |= MCI_ST_8BIT_BUS;
168 writel(clk, host->base + MMCICLOCK);
172 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
174 writel(0, host->base + MMCICOMMAND);
181 pm_runtime_put(mmc_dev(host->mmc));
182 mmc_request_done(host->mmc, mrq);
185 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
187 void __iomem *base = host->base;
189 if (host->singleirq) {
190 unsigned int mask0 = readl(base + MMCIMASK0);
192 mask0 &= ~MCI_IRQ1MASK;
195 writel(mask0, base + MMCIMASK0);
198 writel(mask, base + MMCIMASK1);
201 static void mmci_stop_data(struct mmci_host *host)
203 writel(0, host->base + MMCIDATACTRL);
204 mmci_set_mask1(host, 0);
208 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
210 unsigned int flags = SG_MITER_ATOMIC;
212 if (data->flags & MMC_DATA_READ)
213 flags |= SG_MITER_TO_SG;
215 flags |= SG_MITER_FROM_SG;
217 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
221 * All the DMA operation mode stuff goes inside this ifdef.
222 * This assumes that you have a generic DMA device interface,
223 * no custom DMA interfaces are supported.
225 #ifdef CONFIG_DMA_ENGINE
226 static void __devinit mmci_dma_setup(struct mmci_host *host)
228 struct mmci_platform_data *plat = host->plat;
229 const char *rxname, *txname;
232 if (!plat || !plat->dma_filter) {
233 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
237 /* initialize pre request cookie */
238 host->next_data.cookie = 1;
240 /* Try to acquire a generic DMA engine slave channel */
242 dma_cap_set(DMA_SLAVE, mask);
245 * If only an RX channel is specified, the driver will
246 * attempt to use it bidirectionally, however if it is
247 * is specified but cannot be located, DMA will be disabled.
249 if (plat->dma_rx_param) {
250 host->dma_rx_channel = dma_request_channel(mask,
253 /* E.g if no DMA hardware is present */
254 if (!host->dma_rx_channel)
255 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
258 if (plat->dma_tx_param) {
259 host->dma_tx_channel = dma_request_channel(mask,
262 if (!host->dma_tx_channel)
263 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
265 host->dma_tx_channel = host->dma_rx_channel;
268 if (host->dma_rx_channel)
269 rxname = dma_chan_name(host->dma_rx_channel);
273 if (host->dma_tx_channel)
274 txname = dma_chan_name(host->dma_tx_channel);
278 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
282 * Limit the maximum segment size in any SG entry according to
283 * the parameters of the DMA engine device.
285 if (host->dma_tx_channel) {
286 struct device *dev = host->dma_tx_channel->device->dev;
287 unsigned int max_seg_size = dma_get_max_seg_size(dev);
289 if (max_seg_size < host->mmc->max_seg_size)
290 host->mmc->max_seg_size = max_seg_size;
292 if (host->dma_rx_channel) {
293 struct device *dev = host->dma_rx_channel->device->dev;
294 unsigned int max_seg_size = dma_get_max_seg_size(dev);
296 if (max_seg_size < host->mmc->max_seg_size)
297 host->mmc->max_seg_size = max_seg_size;
302 * This is used in __devinit or __devexit so inline it
303 * so it can be discarded.
305 static inline void mmci_dma_release(struct mmci_host *host)
307 struct mmci_platform_data *plat = host->plat;
309 if (host->dma_rx_channel)
310 dma_release_channel(host->dma_rx_channel);
311 if (host->dma_tx_channel && plat->dma_tx_param)
312 dma_release_channel(host->dma_tx_channel);
313 host->dma_rx_channel = host->dma_tx_channel = NULL;
316 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
318 struct dma_chan *chan = host->dma_current;
319 enum dma_data_direction dir;
323 /* Wait up to 1ms for the DMA to complete */
325 status = readl(host->base + MMCISTATUS);
326 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
332 * Check to see whether we still have some data left in the FIFO -
333 * this catches DMA controllers which are unable to monitor the
334 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
335 * contiguous buffers. On TX, we'll get a FIFO underrun error.
337 if (status & MCI_RXDATAAVLBLMASK) {
338 dmaengine_terminate_all(chan);
343 if (data->flags & MMC_DATA_WRITE) {
346 dir = DMA_FROM_DEVICE;
349 if (!data->host_cookie)
350 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
353 * Use of DMA with scatter-gather is impossible.
354 * Give up with DMA and switch back to PIO mode.
356 if (status & MCI_RXDATAAVLBLMASK) {
357 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
358 mmci_dma_release(host);
362 static void mmci_dma_data_error(struct mmci_host *host)
364 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
365 dmaengine_terminate_all(host->dma_current);
368 static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
369 struct mmci_host_next *next)
371 struct variant_data *variant = host->variant;
372 struct dma_slave_config conf = {
373 .src_addr = host->phybase + MMCIFIFO,
374 .dst_addr = host->phybase + MMCIFIFO,
375 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
376 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
377 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
378 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
380 struct dma_chan *chan;
381 struct dma_device *device;
382 struct dma_async_tx_descriptor *desc;
383 enum dma_data_direction buffer_dirn;
386 /* Check if next job is already prepared */
387 if (data->host_cookie && !next &&
388 host->dma_current && host->dma_desc_current)
392 host->dma_current = NULL;
393 host->dma_desc_current = NULL;
396 if (data->flags & MMC_DATA_READ) {
397 conf.direction = DMA_DEV_TO_MEM;
398 buffer_dirn = DMA_FROM_DEVICE;
399 chan = host->dma_rx_channel;
401 conf.direction = DMA_MEM_TO_DEV;
402 buffer_dirn = DMA_TO_DEVICE;
403 chan = host->dma_tx_channel;
406 /* If there's no DMA channel, fall back to PIO */
410 /* If less than or equal to the fifo size, don't bother with DMA */
411 if (data->blksz * data->blocks <= variant->fifosize)
414 device = chan->device;
415 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
419 dmaengine_slave_config(chan, &conf);
420 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
421 conf.direction, DMA_CTRL_ACK);
426 next->dma_chan = chan;
427 next->dma_desc = desc;
429 host->dma_current = chan;
430 host->dma_desc_current = desc;
437 dmaengine_terminate_all(chan);
438 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
442 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
445 struct mmc_data *data = host->data;
447 ret = mmci_dma_prep_data(host, host->data, NULL);
451 /* Okay, go for it. */
452 dev_vdbg(mmc_dev(host->mmc),
453 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
454 data->sg_len, data->blksz, data->blocks, data->flags);
455 dmaengine_submit(host->dma_desc_current);
456 dma_async_issue_pending(host->dma_current);
458 datactrl |= MCI_DPSM_DMAENABLE;
460 /* Trigger the DMA transfer */
461 writel(datactrl, host->base + MMCIDATACTRL);
464 * Let the MMCI say when the data is ended and it's time
465 * to fire next DMA request. When that happens, MMCI will
466 * call mmci_data_end()
468 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
469 host->base + MMCIMASK0);
473 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
475 struct mmci_host_next *next = &host->next_data;
477 if (data->host_cookie && data->host_cookie != next->cookie) {
478 pr_warning("[%s] invalid cookie: data->host_cookie %d"
479 " host->next_data.cookie %d\n",
480 __func__, data->host_cookie, host->next_data.cookie);
481 data->host_cookie = 0;
484 if (!data->host_cookie)
487 host->dma_desc_current = next->dma_desc;
488 host->dma_current = next->dma_chan;
490 next->dma_desc = NULL;
491 next->dma_chan = NULL;
494 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
497 struct mmci_host *host = mmc_priv(mmc);
498 struct mmc_data *data = mrq->data;
499 struct mmci_host_next *nd = &host->next_data;
504 if (data->host_cookie) {
505 data->host_cookie = 0;
509 /* if config for dma */
510 if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
511 ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
512 if (mmci_dma_prep_data(host, data, nd))
513 data->host_cookie = 0;
515 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
519 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
522 struct mmci_host *host = mmc_priv(mmc);
523 struct mmc_data *data = mrq->data;
524 struct dma_chan *chan;
525 enum dma_data_direction dir;
530 if (data->flags & MMC_DATA_READ) {
531 dir = DMA_FROM_DEVICE;
532 chan = host->dma_rx_channel;
535 chan = host->dma_tx_channel;
539 /* if config for dma */
542 dmaengine_terminate_all(chan);
543 if (data->host_cookie)
544 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
546 mrq->data->host_cookie = 0;
551 /* Blank functions if the DMA engine is not available */
552 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
555 static inline void mmci_dma_setup(struct mmci_host *host)
559 static inline void mmci_dma_release(struct mmci_host *host)
563 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
567 static inline void mmci_dma_data_error(struct mmci_host *host)
571 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
576 #define mmci_pre_request NULL
577 #define mmci_post_request NULL
581 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
583 struct variant_data *variant = host->variant;
584 unsigned int datactrl, timeout, irqmask;
585 unsigned long long clks;
589 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
590 data->blksz, data->blocks, data->flags);
593 host->size = data->blksz * data->blocks;
594 data->bytes_xfered = 0;
596 clks = (unsigned long long)data->timeout_ns * host->cclk;
597 do_div(clks, 1000000000UL);
599 timeout = data->timeout_clks + (unsigned int)clks;
602 writel(timeout, base + MMCIDATATIMER);
603 writel(host->size, base + MMCIDATALENGTH);
605 blksz_bits = ffs(data->blksz) - 1;
606 BUG_ON(1 << blksz_bits != data->blksz);
608 if (variant->blksz_datactrl16)
609 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
611 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
613 if (data->flags & MMC_DATA_READ)
614 datactrl |= MCI_DPSM_DIRECTION;
617 * Attempt to use DMA operation mode, if this
618 * should fail, fall back to PIO mode
620 if (!mmci_dma_start_data(host, datactrl))
623 /* IRQ mode, map the SG list for CPU reading/writing */
624 mmci_init_sg(host, data);
626 if (data->flags & MMC_DATA_READ) {
627 irqmask = MCI_RXFIFOHALFFULLMASK;
630 * If we have less than the fifo 'half-full' threshold to
631 * transfer, trigger a PIO interrupt as soon as any data
634 if (host->size < variant->fifohalfsize)
635 irqmask |= MCI_RXDATAAVLBLMASK;
638 * We don't actually need to include "FIFO empty" here
639 * since its implicit in "FIFO half empty".
641 irqmask = MCI_TXFIFOHALFEMPTYMASK;
644 /* The ST Micro variants has a special bit to enable SDIO */
645 if (variant->sdio && host->mmc->card)
646 if (mmc_card_sdio(host->mmc->card))
647 datactrl |= MCI_ST_DPSM_SDIOEN;
649 writel(datactrl, base + MMCIDATACTRL);
650 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
651 mmci_set_mask1(host, irqmask);
655 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
657 void __iomem *base = host->base;
659 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
660 cmd->opcode, cmd->arg, cmd->flags);
662 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
663 writel(0, base + MMCICOMMAND);
667 c |= cmd->opcode | MCI_CPSM_ENABLE;
668 if (cmd->flags & MMC_RSP_PRESENT) {
669 if (cmd->flags & MMC_RSP_136)
670 c |= MCI_CPSM_LONGRSP;
671 c |= MCI_CPSM_RESPONSE;
674 c |= MCI_CPSM_INTERRUPT;
678 writel(cmd->arg, base + MMCIARGUMENT);
679 writel(c, base + MMCICOMMAND);
683 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
686 /* First check for errors */
687 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
688 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
691 /* Terminate the DMA transfer */
692 if (dma_inprogress(host))
693 mmci_dma_data_error(host);
696 * Calculate how far we are into the transfer. Note that
697 * the data counter gives the number of bytes transferred
698 * on the MMC bus, not on the host side. On reads, this
699 * can be as much as a FIFO-worth of data ahead. This
700 * matters for FIFO overruns only.
702 remain = readl(host->base + MMCIDATACNT);
703 success = data->blksz * data->blocks - remain;
705 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
707 if (status & MCI_DATACRCFAIL) {
708 /* Last block was not successful */
710 data->error = -EILSEQ;
711 } else if (status & MCI_DATATIMEOUT) {
712 data->error = -ETIMEDOUT;
713 } else if (status & MCI_STARTBITERR) {
714 data->error = -ECOMM;
715 } else if (status & MCI_TXUNDERRUN) {
717 } else if (status & MCI_RXOVERRUN) {
718 if (success > host->variant->fifosize)
719 success -= host->variant->fifosize;
724 data->bytes_xfered = round_down(success, data->blksz);
727 if (status & MCI_DATABLOCKEND)
728 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
730 if (status & MCI_DATAEND || data->error) {
731 if (dma_inprogress(host))
732 mmci_dma_unmap(host, data);
733 mmci_stop_data(host);
736 /* The error clause is handled above, success! */
737 data->bytes_xfered = data->blksz * data->blocks;
740 mmci_request_end(host, data->mrq);
742 mmci_start_command(host, data->stop, 0);
748 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
751 void __iomem *base = host->base;
755 if (status & MCI_CMDTIMEOUT) {
756 cmd->error = -ETIMEDOUT;
757 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
758 cmd->error = -EILSEQ;
760 cmd->resp[0] = readl(base + MMCIRESPONSE0);
761 cmd->resp[1] = readl(base + MMCIRESPONSE1);
762 cmd->resp[2] = readl(base + MMCIRESPONSE2);
763 cmd->resp[3] = readl(base + MMCIRESPONSE3);
766 if (!cmd->data || cmd->error) {
768 /* Terminate the DMA transfer */
769 if (dma_inprogress(host))
770 mmci_dma_data_error(host);
771 mmci_stop_data(host);
773 mmci_request_end(host, cmd->mrq);
774 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
775 mmci_start_data(host, cmd->data);
779 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
781 void __iomem *base = host->base;
784 int host_remain = host->size;
787 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
795 readsl(base + MMCIFIFO, ptr, count >> 2);
799 host_remain -= count;
804 status = readl(base + MMCISTATUS);
805 } while (status & MCI_RXDATAAVLBL);
810 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
812 struct variant_data *variant = host->variant;
813 void __iomem *base = host->base;
817 unsigned int count, maxcnt;
819 maxcnt = status & MCI_TXFIFOEMPTY ?
820 variant->fifosize : variant->fifohalfsize;
821 count = min(remain, maxcnt);
824 * The ST Micro variant for SDIO transfer sizes
825 * less then 8 bytes should have clock H/W flow
829 mmc_card_sdio(host->mmc->card)) {
831 writel(readl(host->base + MMCICLOCK) &
832 ~variant->clkreg_enable,
833 host->base + MMCICLOCK);
835 writel(readl(host->base + MMCICLOCK) |
836 variant->clkreg_enable,
837 host->base + MMCICLOCK);
841 * SDIO especially may want to send something that is
842 * not divisible by 4 (as opposed to card sectors
843 * etc), and the FIFO only accept full 32-bit writes.
844 * So compensate by adding +3 on the count, a single
845 * byte become a 32bit write, 7 bytes will be two
848 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
856 status = readl(base + MMCISTATUS);
857 } while (status & MCI_TXFIFOHALFEMPTY);
863 * PIO data transfer IRQ handler.
865 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
867 struct mmci_host *host = dev_id;
868 struct sg_mapping_iter *sg_miter = &host->sg_miter;
869 struct variant_data *variant = host->variant;
870 void __iomem *base = host->base;
874 status = readl(base + MMCISTATUS);
876 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
878 local_irq_save(flags);
881 unsigned int remain, len;
885 * For write, we only need to test the half-empty flag
886 * here - if the FIFO is completely empty, then by
887 * definition it is more than half empty.
889 * For read, check for data available.
891 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
894 if (!sg_miter_next(sg_miter))
897 buffer = sg_miter->addr;
898 remain = sg_miter->length;
901 if (status & MCI_RXACTIVE)
902 len = mmci_pio_read(host, buffer, remain);
903 if (status & MCI_TXACTIVE)
904 len = mmci_pio_write(host, buffer, remain, status);
906 sg_miter->consumed = len;
914 status = readl(base + MMCISTATUS);
917 sg_miter_stop(sg_miter);
919 local_irq_restore(flags);
922 * If we have less than the fifo 'half-full' threshold to transfer,
923 * trigger a PIO interrupt as soon as any data is available.
925 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
926 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
929 * If we run out of data, disable the data IRQs; this
930 * prevents a race where the FIFO becomes empty before
931 * the chip itself has disabled the data path, and
932 * stops us racing with our data end IRQ.
934 if (host->size == 0) {
935 mmci_set_mask1(host, 0);
936 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
943 * Handle completion of command and data transfers.
945 static irqreturn_t mmci_irq(int irq, void *dev_id)
947 struct mmci_host *host = dev_id;
951 spin_lock(&host->lock);
954 struct mmc_command *cmd;
955 struct mmc_data *data;
957 status = readl(host->base + MMCISTATUS);
959 if (host->singleirq) {
960 if (status & readl(host->base + MMCIMASK1))
961 mmci_pio_irq(irq, dev_id);
963 status &= ~MCI_IRQ1MASK;
966 status &= readl(host->base + MMCIMASK0);
967 writel(status, host->base + MMCICLEAR);
969 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
972 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
973 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
974 MCI_DATABLOCKEND) && data)
975 mmci_data_irq(host, data, status);
978 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
979 mmci_cmd_irq(host, cmd, status);
984 spin_unlock(&host->lock);
986 return IRQ_RETVAL(ret);
989 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
991 struct mmci_host *host = mmc_priv(mmc);
994 WARN_ON(host->mrq != NULL);
996 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
997 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
999 mrq->cmd->error = -EINVAL;
1000 mmc_request_done(mmc, mrq);
1004 pm_runtime_get_sync(mmc_dev(mmc));
1006 spin_lock_irqsave(&host->lock, flags);
1011 mmci_get_next_data(host, mrq->data);
1013 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1014 mmci_start_data(host, mrq->data);
1016 mmci_start_command(host, mrq->cmd, 0);
1018 spin_unlock_irqrestore(&host->lock, flags);
1021 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1023 struct mmci_host *host = mmc_priv(mmc);
1024 struct variant_data *variant = host->variant;
1026 unsigned long flags;
1029 switch (ios->power_mode) {
1032 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
1036 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
1038 dev_err(mmc_dev(mmc), "unable to set OCR\n");
1040 * The .set_ios() function in the mmc_host_ops
1041 * struct return void, and failing to set the
1042 * power should be rare so we print an error
1048 if (host->plat->vdd_handler)
1049 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
1053 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1054 * and instead uses MCI_PWR_ON so apply whatever value is
1055 * configured in the variant data.
1057 pwr |= variant->pwrreg_powerup;
1065 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1067 * The ST Micro variant has some additional bits
1068 * indicating signal direction for the signals in
1069 * the SD/MMC bus and feedback-clock usage.
1071 pwr |= host->plat->sigdir;
1073 if (ios->bus_width == MMC_BUS_WIDTH_4)
1074 pwr &= ~MCI_ST_DATA74DIREN;
1075 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1076 pwr &= (~MCI_ST_DATA74DIREN &
1077 ~MCI_ST_DATA31DIREN &
1078 ~MCI_ST_DATA2DIREN);
1081 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1082 if (host->hw_designer != AMBA_VENDOR_ST)
1086 * The ST Micro variant use the ROD bit for something
1087 * else and only has OD (Open Drain).
1093 spin_lock_irqsave(&host->lock, flags);
1095 mmci_set_clkreg(host, ios->clock);
1097 if (host->pwr != pwr) {
1099 writel(pwr, host->base + MMCIPOWER);
1102 spin_unlock_irqrestore(&host->lock, flags);
1105 static int mmci_get_ro(struct mmc_host *mmc)
1107 struct mmci_host *host = mmc_priv(mmc);
1109 if (host->gpio_wp == -ENOSYS)
1112 return gpio_get_value_cansleep(host->gpio_wp);
1115 static int mmci_get_cd(struct mmc_host *mmc)
1117 struct mmci_host *host = mmc_priv(mmc);
1118 struct mmci_platform_data *plat = host->plat;
1119 unsigned int status;
1121 if (host->gpio_cd == -ENOSYS) {
1123 return 1; /* Assume always present */
1125 status = plat->status(mmc_dev(host->mmc));
1127 status = !!gpio_get_value_cansleep(host->gpio_cd)
1131 * Use positive logic throughout - status is zero for no card,
1132 * non-zero for card inserted.
1137 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
1139 struct mmci_host *host = dev_id;
1141 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1146 static const struct mmc_host_ops mmci_ops = {
1147 .request = mmci_request,
1148 .pre_req = mmci_pre_request,
1149 .post_req = mmci_post_request,
1150 .set_ios = mmci_set_ios,
1151 .get_ro = mmci_get_ro,
1152 .get_cd = mmci_get_cd,
1155 static int __devinit mmci_probe(struct amba_device *dev,
1156 const struct amba_id *id)
1158 struct mmci_platform_data *plat = dev->dev.platform_data;
1159 struct variant_data *variant = id->data;
1160 struct mmci_host *host;
1161 struct mmc_host *mmc;
1164 /* must have platform data */
1170 ret = amba_request_regions(dev, DRIVER_NAME);
1174 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1180 host = mmc_priv(mmc);
1183 host->gpio_wp = -ENOSYS;
1184 host->gpio_cd = -ENOSYS;
1185 host->gpio_cd_irq = -1;
1187 host->hw_designer = amba_manf(dev);
1188 host->hw_revision = amba_rev(dev);
1189 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1190 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1192 host->clk = clk_get(&dev->dev, NULL);
1193 if (IS_ERR(host->clk)) {
1194 ret = PTR_ERR(host->clk);
1199 ret = clk_prepare(host->clk);
1203 ret = clk_enable(host->clk);
1208 host->variant = variant;
1209 host->mclk = clk_get_rate(host->clk);
1211 * According to the spec, mclk is max 100 MHz,
1212 * so we try to adjust the clock down to this,
1215 if (host->mclk > 100000000) {
1216 ret = clk_set_rate(host->clk, 100000000);
1219 host->mclk = clk_get_rate(host->clk);
1220 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1223 host->phybase = dev->res.start;
1224 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1230 mmc->ops = &mmci_ops;
1232 * The ARM and ST versions of the block have slightly different
1233 * clock divider equations which means that the minimum divider
1236 if (variant->st_clkdiv)
1237 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1239 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1241 * If the platform data supplies a maximum operating
1242 * frequency, this takes precedence. Else, we fall back
1243 * to using the module parameter, which has a (low)
1244 * default value in case it is not specified. Either
1245 * value must not exceed the clock rate into the block,
1249 mmc->f_max = min(host->mclk, plat->f_max);
1251 mmc->f_max = min(host->mclk, fmax);
1252 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1254 #ifdef CONFIG_REGULATOR
1255 /* If we're using the regulator framework, try to fetch a regulator */
1256 host->vcc = regulator_get(&dev->dev, "vmmc");
1257 if (IS_ERR(host->vcc))
1260 int mask = mmc_regulator_get_ocrmask(host->vcc);
1263 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1266 host->mmc->ocr_avail = (u32) mask;
1269 "Provided ocr_mask/setpower will not be used "
1270 "(using regulator instead)\n");
1274 /* Fall back to platform data if no regulator is found */
1275 if (host->vcc == NULL)
1276 mmc->ocr_avail = plat->ocr_mask;
1277 mmc->caps = plat->capabilities;
1278 mmc->caps2 = plat->capabilities2;
1283 mmc->max_segs = NR_SG;
1286 * Since only a certain number of bits are valid in the data length
1287 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1290 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1293 * Set the maximum segment size. Since we aren't doing DMA
1294 * (yet) we are only limited by the data length register.
1296 mmc->max_seg_size = mmc->max_req_size;
1299 * Block size can be up to 2048 bytes, but must be a power of two.
1301 mmc->max_blk_size = 2048;
1304 * No limit on the number of blocks transferred.
1306 mmc->max_blk_count = mmc->max_req_size;
1308 spin_lock_init(&host->lock);
1310 writel(0, host->base + MMCIMASK0);
1311 writel(0, host->base + MMCIMASK1);
1312 writel(0xfff, host->base + MMCICLEAR);
1314 if (gpio_is_valid(plat->gpio_cd)) {
1315 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1317 ret = gpio_direction_input(plat->gpio_cd);
1319 host->gpio_cd = plat->gpio_cd;
1320 else if (ret != -ENOSYS)
1324 * A gpio pin that will detect cards when inserted and removed
1325 * will most likely want to trigger on the edges if it is
1326 * 0 when ejected and 1 when inserted (or mutatis mutandis
1327 * for the inverted case) so we request triggers on both
1330 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1332 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1333 DRIVER_NAME " (cd)", host);
1335 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1337 if (gpio_is_valid(plat->gpio_wp)) {
1338 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1340 ret = gpio_direction_input(plat->gpio_wp);
1342 host->gpio_wp = plat->gpio_wp;
1343 else if (ret != -ENOSYS)
1347 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1348 && host->gpio_cd_irq < 0)
1349 mmc->caps |= MMC_CAP_NEEDS_POLL;
1351 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1355 if (dev->irq[1] == NO_IRQ)
1356 host->singleirq = true;
1358 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1359 DRIVER_NAME " (pio)", host);
1364 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1366 amba_set_drvdata(dev, mmc);
1368 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1369 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1370 amba_rev(dev), (unsigned long long)dev->res.start,
1371 dev->irq[0], dev->irq[1]);
1373 mmci_dma_setup(host);
1375 pm_runtime_put(&dev->dev);
1382 free_irq(dev->irq[0], host);
1384 if (host->gpio_wp != -ENOSYS)
1385 gpio_free(host->gpio_wp);
1387 if (host->gpio_cd_irq >= 0)
1388 free_irq(host->gpio_cd_irq, host);
1389 if (host->gpio_cd != -ENOSYS)
1390 gpio_free(host->gpio_cd);
1392 iounmap(host->base);
1394 clk_disable(host->clk);
1396 clk_unprepare(host->clk);
1402 amba_release_regions(dev);
1407 static int __devexit mmci_remove(struct amba_device *dev)
1409 struct mmc_host *mmc = amba_get_drvdata(dev);
1411 amba_set_drvdata(dev, NULL);
1414 struct mmci_host *host = mmc_priv(mmc);
1417 * Undo pm_runtime_put() in probe. We use the _sync
1418 * version here so that we can access the primecell.
1420 pm_runtime_get_sync(&dev->dev);
1422 mmc_remove_host(mmc);
1424 writel(0, host->base + MMCIMASK0);
1425 writel(0, host->base + MMCIMASK1);
1427 writel(0, host->base + MMCICOMMAND);
1428 writel(0, host->base + MMCIDATACTRL);
1430 mmci_dma_release(host);
1431 free_irq(dev->irq[0], host);
1432 if (!host->singleirq)
1433 free_irq(dev->irq[1], host);
1435 if (host->gpio_wp != -ENOSYS)
1436 gpio_free(host->gpio_wp);
1437 if (host->gpio_cd_irq >= 0)
1438 free_irq(host->gpio_cd_irq, host);
1439 if (host->gpio_cd != -ENOSYS)
1440 gpio_free(host->gpio_cd);
1442 iounmap(host->base);
1443 clk_disable(host->clk);
1444 clk_unprepare(host->clk);
1448 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1449 regulator_put(host->vcc);
1453 amba_release_regions(dev);
1460 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1462 struct mmc_host *mmc = amba_get_drvdata(dev);
1466 struct mmci_host *host = mmc_priv(mmc);
1468 ret = mmc_suspend_host(mmc);
1470 writel(0, host->base + MMCIMASK0);
1476 static int mmci_resume(struct amba_device *dev)
1478 struct mmc_host *mmc = amba_get_drvdata(dev);
1482 struct mmci_host *host = mmc_priv(mmc);
1484 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1486 ret = mmc_resume_host(mmc);
1492 #define mmci_suspend NULL
1493 #define mmci_resume NULL
1496 static struct amba_id mmci_ids[] = {
1500 .data = &variant_arm,
1505 .data = &variant_arm_extended_fifo,
1510 .data = &variant_arm,
1512 /* ST Micro variants */
1516 .data = &variant_u300,
1521 .data = &variant_u300,
1526 .data = &variant_ux500,
1531 .data = &variant_ux500v2,
1536 MODULE_DEVICE_TABLE(amba, mmci_ids);
1538 static struct amba_driver mmci_driver = {
1540 .name = DRIVER_NAME,
1542 .probe = mmci_probe,
1543 .remove = __devexit_p(mmci_remove),
1544 .suspend = mmci_suspend,
1545 .resume = mmci_resume,
1546 .id_table = mmci_ids,
1549 static int __init mmci_init(void)
1551 return amba_driver_register(&mmci_driver);
1554 static void __exit mmci_exit(void)
1556 amba_driver_unregister(&mmci_driver);
1559 module_init(mmci_init);
1560 module_exit(mmci_exit);
1561 module_param(fmax, uint, 0444);
1563 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1564 MODULE_LICENSE("GPL");