2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
41 #include <asm/div64.h>
43 #include <asm/sizes.h>
47 #define DRIVER_NAME "mmci-pl18x"
49 static unsigned int fmax = 515633;
52 * struct variant_data - MMCI variant-specific quirks
53 * @clkreg: default value for MCICLOCK register
54 * @clkreg_enable: enable value for MMCICLOCK register
55 * @clkreg_8bit_bus_enable: enable value for 8 bit bus
56 * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
57 * @datalength_bits: number of bits in the MMCIDATALENGTH register
58 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
59 * is asserted (likewise for RX)
60 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
61 * is asserted (likewise for RX)
62 * @sdio: variant supports SDIO
63 * @st_clkdiv: true if using a ST-specific clock divider algorithm
64 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
65 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
66 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
68 * @pwrreg_powerup: power up value for MMCIPOWER register
69 * @signal_direction: input/out direction of bus signals can be indicated
70 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
71 * @busy_detect: true if busy detection on dat0 is supported
72 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
76 unsigned int clkreg_enable;
77 unsigned int clkreg_8bit_bus_enable;
78 unsigned int clkreg_neg_edge_enable;
79 unsigned int datalength_bits;
80 unsigned int fifosize;
81 unsigned int fifohalfsize;
82 unsigned int datactrl_mask_ddrmode;
85 bool blksz_datactrl16;
88 bool signal_direction;
94 static struct variant_data variant_arm = {
96 .fifohalfsize = 8 * 4,
97 .datalength_bits = 16,
98 .pwrreg_powerup = MCI_PWR_UP,
101 static struct variant_data variant_arm_extended_fifo = {
103 .fifohalfsize = 64 * 4,
104 .datalength_bits = 16,
105 .pwrreg_powerup = MCI_PWR_UP,
108 static struct variant_data variant_arm_extended_fifo_hwfc = {
110 .fifohalfsize = 64 * 4,
111 .clkreg_enable = MCI_ARM_HWFCEN,
112 .datalength_bits = 16,
113 .pwrreg_powerup = MCI_PWR_UP,
116 static struct variant_data variant_u300 = {
118 .fifohalfsize = 8 * 4,
119 .clkreg_enable = MCI_ST_U300_HWFCEN,
120 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
121 .datalength_bits = 16,
123 .pwrreg_powerup = MCI_PWR_ON,
124 .signal_direction = true,
125 .pwrreg_clkgate = true,
126 .pwrreg_nopower = true,
129 static struct variant_data variant_nomadik = {
131 .fifohalfsize = 8 * 4,
132 .clkreg = MCI_CLK_ENABLE,
133 .datalength_bits = 24,
136 .pwrreg_powerup = MCI_PWR_ON,
137 .signal_direction = true,
138 .pwrreg_clkgate = true,
139 .pwrreg_nopower = true,
142 static struct variant_data variant_ux500 = {
144 .fifohalfsize = 8 * 4,
145 .clkreg = MCI_CLK_ENABLE,
146 .clkreg_enable = MCI_ST_UX500_HWFCEN,
147 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
148 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
149 .datalength_bits = 24,
152 .pwrreg_powerup = MCI_PWR_ON,
153 .signal_direction = true,
154 .pwrreg_clkgate = true,
156 .pwrreg_nopower = true,
159 static struct variant_data variant_ux500v2 = {
161 .fifohalfsize = 8 * 4,
162 .clkreg = MCI_CLK_ENABLE,
163 .clkreg_enable = MCI_ST_UX500_HWFCEN,
164 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
165 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
166 .datactrl_mask_ddrmode = MCI_ST_DPSM_DDRMODE,
167 .datalength_bits = 24,
170 .blksz_datactrl16 = true,
171 .pwrreg_powerup = MCI_PWR_ON,
172 .signal_direction = true,
173 .pwrreg_clkgate = true,
175 .pwrreg_nopower = true,
178 static int mmci_card_busy(struct mmc_host *mmc)
180 struct mmci_host *host = mmc_priv(mmc);
184 pm_runtime_get_sync(mmc_dev(mmc));
186 spin_lock_irqsave(&host->lock, flags);
187 if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
189 spin_unlock_irqrestore(&host->lock, flags);
191 pm_runtime_mark_last_busy(mmc_dev(mmc));
192 pm_runtime_put_autosuspend(mmc_dev(mmc));
198 * Validate mmc prerequisites
200 static int mmci_validate_data(struct mmci_host *host,
201 struct mmc_data *data)
206 if (!is_power_of_2(data->blksz)) {
207 dev_err(mmc_dev(host->mmc),
208 "unsupported block size (%d bytes)\n", data->blksz);
215 static void mmci_reg_delay(struct mmci_host *host)
218 * According to the spec, at least three feedback clock cycles
219 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
220 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
221 * Worst delay time during card init is at 100 kHz => 30 us.
222 * Worst delay time when up and running is at 25 MHz => 120 ns.
224 if (host->cclk < 25000000)
231 * This must be called with host->lock held
233 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
235 if (host->clk_reg != clk) {
237 writel(clk, host->base + MMCICLOCK);
242 * This must be called with host->lock held
244 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
246 if (host->pwr_reg != pwr) {
248 writel(pwr, host->base + MMCIPOWER);
253 * This must be called with host->lock held
255 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
257 /* Keep ST Micro busy mode if enabled */
258 datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;
260 if (host->datactrl_reg != datactrl) {
261 host->datactrl_reg = datactrl;
262 writel(datactrl, host->base + MMCIDATACTRL);
267 * This must be called with host->lock held
269 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
271 struct variant_data *variant = host->variant;
272 u32 clk = variant->clkreg;
274 /* Make sure cclk reflects the current calculated clock */
278 if (desired >= host->mclk) {
279 clk = MCI_CLK_BYPASS;
280 if (variant->st_clkdiv)
281 clk |= MCI_ST_UX500_NEG_EDGE;
282 host->cclk = host->mclk;
283 } else if (variant->st_clkdiv) {
285 * DB8500 TRM says f = mclk / (clkdiv + 2)
286 * => clkdiv = (mclk / f) - 2
287 * Round the divider up so we don't exceed the max
290 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
293 host->cclk = host->mclk / (clk + 2);
296 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
297 * => clkdiv = mclk / (2 * f) - 1
299 clk = host->mclk / (2 * desired) - 1;
302 host->cclk = host->mclk / (2 * (clk + 1));
305 clk |= variant->clkreg_enable;
306 clk |= MCI_CLK_ENABLE;
307 /* This hasn't proven to be worthwhile */
308 /* clk |= MCI_CLK_PWRSAVE; */
311 /* Set actual clock for debug */
312 host->mmc->actual_clock = host->cclk;
314 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
316 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
317 clk |= variant->clkreg_8bit_bus_enable;
319 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
320 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
321 clk |= variant->clkreg_neg_edge_enable;
323 mmci_write_clkreg(host, clk);
327 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
329 writel(0, host->base + MMCICOMMAND);
336 mmc_request_done(host->mmc, mrq);
338 pm_runtime_mark_last_busy(mmc_dev(host->mmc));
339 pm_runtime_put_autosuspend(mmc_dev(host->mmc));
342 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
344 void __iomem *base = host->base;
346 if (host->singleirq) {
347 unsigned int mask0 = readl(base + MMCIMASK0);
349 mask0 &= ~MCI_IRQ1MASK;
352 writel(mask0, base + MMCIMASK0);
355 writel(mask, base + MMCIMASK1);
358 static void mmci_stop_data(struct mmci_host *host)
360 mmci_write_datactrlreg(host, 0);
361 mmci_set_mask1(host, 0);
365 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
367 unsigned int flags = SG_MITER_ATOMIC;
369 if (data->flags & MMC_DATA_READ)
370 flags |= SG_MITER_TO_SG;
372 flags |= SG_MITER_FROM_SG;
374 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
378 * All the DMA operation mode stuff goes inside this ifdef.
379 * This assumes that you have a generic DMA device interface,
380 * no custom DMA interfaces are supported.
382 #ifdef CONFIG_DMA_ENGINE
383 static void mmci_dma_setup(struct mmci_host *host)
385 const char *rxname, *txname;
388 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
389 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
391 /* initialize pre request cookie */
392 host->next_data.cookie = 1;
394 /* Try to acquire a generic DMA engine slave channel */
396 dma_cap_set(DMA_SLAVE, mask);
399 * If only an RX channel is specified, the driver will
400 * attempt to use it bidirectionally, however if it is
401 * is specified but cannot be located, DMA will be disabled.
403 if (host->dma_rx_channel && !host->dma_tx_channel)
404 host->dma_tx_channel = host->dma_rx_channel;
406 if (host->dma_rx_channel)
407 rxname = dma_chan_name(host->dma_rx_channel);
411 if (host->dma_tx_channel)
412 txname = dma_chan_name(host->dma_tx_channel);
416 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
420 * Limit the maximum segment size in any SG entry according to
421 * the parameters of the DMA engine device.
423 if (host->dma_tx_channel) {
424 struct device *dev = host->dma_tx_channel->device->dev;
425 unsigned int max_seg_size = dma_get_max_seg_size(dev);
427 if (max_seg_size < host->mmc->max_seg_size)
428 host->mmc->max_seg_size = max_seg_size;
430 if (host->dma_rx_channel) {
431 struct device *dev = host->dma_rx_channel->device->dev;
432 unsigned int max_seg_size = dma_get_max_seg_size(dev);
434 if (max_seg_size < host->mmc->max_seg_size)
435 host->mmc->max_seg_size = max_seg_size;
440 * This is used in or so inline it
441 * so it can be discarded.
443 static inline void mmci_dma_release(struct mmci_host *host)
445 if (host->dma_rx_channel)
446 dma_release_channel(host->dma_rx_channel);
447 if (host->dma_tx_channel)
448 dma_release_channel(host->dma_tx_channel);
449 host->dma_rx_channel = host->dma_tx_channel = NULL;
452 static void mmci_dma_data_error(struct mmci_host *host)
454 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
455 dmaengine_terminate_all(host->dma_current);
456 host->dma_current = NULL;
457 host->dma_desc_current = NULL;
458 host->data->host_cookie = 0;
461 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
463 struct dma_chan *chan;
464 enum dma_data_direction dir;
466 if (data->flags & MMC_DATA_READ) {
467 dir = DMA_FROM_DEVICE;
468 chan = host->dma_rx_channel;
471 chan = host->dma_tx_channel;
474 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
477 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
482 /* Wait up to 1ms for the DMA to complete */
484 status = readl(host->base + MMCISTATUS);
485 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
491 * Check to see whether we still have some data left in the FIFO -
492 * this catches DMA controllers which are unable to monitor the
493 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
494 * contiguous buffers. On TX, we'll get a FIFO underrun error.
496 if (status & MCI_RXDATAAVLBLMASK) {
497 mmci_dma_data_error(host);
502 if (!data->host_cookie)
503 mmci_dma_unmap(host, data);
506 * Use of DMA with scatter-gather is impossible.
507 * Give up with DMA and switch back to PIO mode.
509 if (status & MCI_RXDATAAVLBLMASK) {
510 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
511 mmci_dma_release(host);
514 host->dma_current = NULL;
515 host->dma_desc_current = NULL;
518 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
519 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
520 struct dma_chan **dma_chan,
521 struct dma_async_tx_descriptor **dma_desc)
523 struct variant_data *variant = host->variant;
524 struct dma_slave_config conf = {
525 .src_addr = host->phybase + MMCIFIFO,
526 .dst_addr = host->phybase + MMCIFIFO,
527 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
528 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
529 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
530 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
533 struct dma_chan *chan;
534 struct dma_device *device;
535 struct dma_async_tx_descriptor *desc;
536 enum dma_data_direction buffer_dirn;
539 if (data->flags & MMC_DATA_READ) {
540 conf.direction = DMA_DEV_TO_MEM;
541 buffer_dirn = DMA_FROM_DEVICE;
542 chan = host->dma_rx_channel;
544 conf.direction = DMA_MEM_TO_DEV;
545 buffer_dirn = DMA_TO_DEVICE;
546 chan = host->dma_tx_channel;
549 /* If there's no DMA channel, fall back to PIO */
553 /* If less than or equal to the fifo size, don't bother with DMA */
554 if (data->blksz * data->blocks <= variant->fifosize)
557 device = chan->device;
558 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
562 dmaengine_slave_config(chan, &conf);
563 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
564 conf.direction, DMA_CTRL_ACK);
574 dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
578 static inline int mmci_dma_prep_data(struct mmci_host *host,
579 struct mmc_data *data)
581 /* Check if next job is already prepared. */
582 if (host->dma_current && host->dma_desc_current)
585 /* No job were prepared thus do it now. */
586 return __mmci_dma_prep_data(host, data, &host->dma_current,
587 &host->dma_desc_current);
590 static inline int mmci_dma_prep_next(struct mmci_host *host,
591 struct mmc_data *data)
593 struct mmci_host_next *nd = &host->next_data;
594 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
597 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
600 struct mmc_data *data = host->data;
602 ret = mmci_dma_prep_data(host, host->data);
606 /* Okay, go for it. */
607 dev_vdbg(mmc_dev(host->mmc),
608 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
609 data->sg_len, data->blksz, data->blocks, data->flags);
610 dmaengine_submit(host->dma_desc_current);
611 dma_async_issue_pending(host->dma_current);
613 datactrl |= MCI_DPSM_DMAENABLE;
615 /* Trigger the DMA transfer */
616 mmci_write_datactrlreg(host, datactrl);
619 * Let the MMCI say when the data is ended and it's time
620 * to fire next DMA request. When that happens, MMCI will
621 * call mmci_data_end()
623 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
624 host->base + MMCIMASK0);
628 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
630 struct mmci_host_next *next = &host->next_data;
632 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
633 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
635 host->dma_desc_current = next->dma_desc;
636 host->dma_current = next->dma_chan;
637 next->dma_desc = NULL;
638 next->dma_chan = NULL;
641 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
644 struct mmci_host *host = mmc_priv(mmc);
645 struct mmc_data *data = mrq->data;
646 struct mmci_host_next *nd = &host->next_data;
651 BUG_ON(data->host_cookie);
653 if (mmci_validate_data(host, data))
656 if (!mmci_dma_prep_next(host, data))
657 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
660 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
663 struct mmci_host *host = mmc_priv(mmc);
664 struct mmc_data *data = mrq->data;
666 if (!data || !data->host_cookie)
669 mmci_dma_unmap(host, data);
672 struct mmci_host_next *next = &host->next_data;
673 struct dma_chan *chan;
674 if (data->flags & MMC_DATA_READ)
675 chan = host->dma_rx_channel;
677 chan = host->dma_tx_channel;
678 dmaengine_terminate_all(chan);
680 next->dma_desc = NULL;
681 next->dma_chan = NULL;
686 /* Blank functions if the DMA engine is not available */
687 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
690 static inline void mmci_dma_setup(struct mmci_host *host)
694 static inline void mmci_dma_release(struct mmci_host *host)
698 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
702 static inline void mmci_dma_finalize(struct mmci_host *host,
703 struct mmc_data *data)
707 static inline void mmci_dma_data_error(struct mmci_host *host)
711 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
716 #define mmci_pre_request NULL
717 #define mmci_post_request NULL
721 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
723 struct variant_data *variant = host->variant;
724 unsigned int datactrl, timeout, irqmask;
725 unsigned long long clks;
729 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
730 data->blksz, data->blocks, data->flags);
733 host->size = data->blksz * data->blocks;
734 data->bytes_xfered = 0;
736 clks = (unsigned long long)data->timeout_ns * host->cclk;
737 do_div(clks, NSEC_PER_SEC);
739 timeout = data->timeout_clks + (unsigned int)clks;
742 writel(timeout, base + MMCIDATATIMER);
743 writel(host->size, base + MMCIDATALENGTH);
745 blksz_bits = ffs(data->blksz) - 1;
746 BUG_ON(1 << blksz_bits != data->blksz);
748 if (variant->blksz_datactrl16)
749 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
750 else if (variant->blksz_datactrl4)
751 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
753 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
755 if (data->flags & MMC_DATA_READ)
756 datactrl |= MCI_DPSM_DIRECTION;
758 /* The ST Micro variants has a special bit to enable SDIO */
759 if (variant->sdio && host->mmc->card)
760 if (mmc_card_sdio(host->mmc->card)) {
762 * The ST Micro variants has a special bit
767 datactrl |= MCI_ST_DPSM_SDIOEN;
770 * The ST Micro variant for SDIO small write transfers
771 * needs to have clock H/W flow control disabled,
772 * otherwise the transfer will not start. The threshold
773 * depends on the rate of MCLK.
775 if (data->flags & MMC_DATA_WRITE &&
777 (host->size <= 8 && host->mclk > 50000000)))
778 clk = host->clk_reg & ~variant->clkreg_enable;
780 clk = host->clk_reg | variant->clkreg_enable;
782 mmci_write_clkreg(host, clk);
785 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
786 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
787 datactrl |= variant->datactrl_mask_ddrmode;
790 * Attempt to use DMA operation mode, if this
791 * should fail, fall back to PIO mode
793 if (!mmci_dma_start_data(host, datactrl))
796 /* IRQ mode, map the SG list for CPU reading/writing */
797 mmci_init_sg(host, data);
799 if (data->flags & MMC_DATA_READ) {
800 irqmask = MCI_RXFIFOHALFFULLMASK;
803 * If we have less than the fifo 'half-full' threshold to
804 * transfer, trigger a PIO interrupt as soon as any data
807 if (host->size < variant->fifohalfsize)
808 irqmask |= MCI_RXDATAAVLBLMASK;
811 * We don't actually need to include "FIFO empty" here
812 * since its implicit in "FIFO half empty".
814 irqmask = MCI_TXFIFOHALFEMPTYMASK;
817 mmci_write_datactrlreg(host, datactrl);
818 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
819 mmci_set_mask1(host, irqmask);
823 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
825 void __iomem *base = host->base;
827 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
828 cmd->opcode, cmd->arg, cmd->flags);
830 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
831 writel(0, base + MMCICOMMAND);
832 mmci_reg_delay(host);
835 c |= cmd->opcode | MCI_CPSM_ENABLE;
836 if (cmd->flags & MMC_RSP_PRESENT) {
837 if (cmd->flags & MMC_RSP_136)
838 c |= MCI_CPSM_LONGRSP;
839 c |= MCI_CPSM_RESPONSE;
842 c |= MCI_CPSM_INTERRUPT;
846 writel(cmd->arg, base + MMCIARGUMENT);
847 writel(c, base + MMCICOMMAND);
851 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
854 /* First check for errors */
855 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
856 MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
859 /* Terminate the DMA transfer */
860 if (dma_inprogress(host)) {
861 mmci_dma_data_error(host);
862 mmci_dma_unmap(host, data);
866 * Calculate how far we are into the transfer. Note that
867 * the data counter gives the number of bytes transferred
868 * on the MMC bus, not on the host side. On reads, this
869 * can be as much as a FIFO-worth of data ahead. This
870 * matters for FIFO overruns only.
872 remain = readl(host->base + MMCIDATACNT);
873 success = data->blksz * data->blocks - remain;
875 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
877 if (status & MCI_DATACRCFAIL) {
878 /* Last block was not successful */
880 data->error = -EILSEQ;
881 } else if (status & MCI_DATATIMEOUT) {
882 data->error = -ETIMEDOUT;
883 } else if (status & MCI_STARTBITERR) {
884 data->error = -ECOMM;
885 } else if (status & MCI_TXUNDERRUN) {
887 } else if (status & MCI_RXOVERRUN) {
888 if (success > host->variant->fifosize)
889 success -= host->variant->fifosize;
894 data->bytes_xfered = round_down(success, data->blksz);
897 if (status & MCI_DATABLOCKEND)
898 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
900 if (status & MCI_DATAEND || data->error) {
901 if (dma_inprogress(host))
902 mmci_dma_finalize(host, data);
903 mmci_stop_data(host);
906 /* The error clause is handled above, success! */
907 data->bytes_xfered = data->blksz * data->blocks;
909 if (!data->stop || host->mrq->sbc) {
910 mmci_request_end(host, data->mrq);
912 mmci_start_command(host, data->stop, 0);
918 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
921 void __iomem *base = host->base;
922 bool sbc = (cmd == host->mrq->sbc);
923 bool busy_resp = host->variant->busy_detect &&
924 (cmd->flags & MMC_RSP_BUSY);
926 /* Check if we need to wait for busy completion. */
927 if (host->busy_status && (status & MCI_ST_CARDBUSY))
930 /* Enable busy completion if needed and supported. */
931 if (!host->busy_status && busy_resp &&
932 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
933 (readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
934 writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
936 host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
940 /* At busy completion, mask the IRQ and complete the request. */
941 if (host->busy_status) {
942 writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
944 host->busy_status = 0;
949 if (status & MCI_CMDTIMEOUT) {
950 cmd->error = -ETIMEDOUT;
951 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
952 cmd->error = -EILSEQ;
954 cmd->resp[0] = readl(base + MMCIRESPONSE0);
955 cmd->resp[1] = readl(base + MMCIRESPONSE1);
956 cmd->resp[2] = readl(base + MMCIRESPONSE2);
957 cmd->resp[3] = readl(base + MMCIRESPONSE3);
960 if ((!sbc && !cmd->data) || cmd->error) {
962 /* Terminate the DMA transfer */
963 if (dma_inprogress(host)) {
964 mmci_dma_data_error(host);
965 mmci_dma_unmap(host, host->data);
967 mmci_stop_data(host);
969 mmci_request_end(host, host->mrq);
971 mmci_start_command(host, host->mrq->cmd, 0);
972 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
973 mmci_start_data(host, cmd->data);
977 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
979 void __iomem *base = host->base;
982 int host_remain = host->size;
985 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
994 * SDIO especially may want to send something that is
995 * not divisible by 4 (as opposed to card sectors
996 * etc). Therefore make sure to always read the last bytes
997 * while only doing full 32-bit reads towards the FIFO.
999 if (unlikely(count & 0x3)) {
1001 unsigned char buf[4];
1002 ioread32_rep(base + MMCIFIFO, buf, 1);
1003 memcpy(ptr, buf, count);
1005 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1009 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1014 host_remain -= count;
1019 status = readl(base + MMCISTATUS);
1020 } while (status & MCI_RXDATAAVLBL);
1022 return ptr - buffer;
1025 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1027 struct variant_data *variant = host->variant;
1028 void __iomem *base = host->base;
1032 unsigned int count, maxcnt;
1034 maxcnt = status & MCI_TXFIFOEMPTY ?
1035 variant->fifosize : variant->fifohalfsize;
1036 count = min(remain, maxcnt);
1039 * SDIO especially may want to send something that is
1040 * not divisible by 4 (as opposed to card sectors
1041 * etc), and the FIFO only accept full 32-bit writes.
1042 * So compensate by adding +3 on the count, a single
1043 * byte become a 32bit write, 7 bytes will be two
1046 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1054 status = readl(base + MMCISTATUS);
1055 } while (status & MCI_TXFIFOHALFEMPTY);
1057 return ptr - buffer;
1061 * PIO data transfer IRQ handler.
1063 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1065 struct mmci_host *host = dev_id;
1066 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1067 struct variant_data *variant = host->variant;
1068 void __iomem *base = host->base;
1069 unsigned long flags;
1072 status = readl(base + MMCISTATUS);
1074 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1076 local_irq_save(flags);
1079 unsigned int remain, len;
1083 * For write, we only need to test the half-empty flag
1084 * here - if the FIFO is completely empty, then by
1085 * definition it is more than half empty.
1087 * For read, check for data available.
1089 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1092 if (!sg_miter_next(sg_miter))
1095 buffer = sg_miter->addr;
1096 remain = sg_miter->length;
1099 if (status & MCI_RXACTIVE)
1100 len = mmci_pio_read(host, buffer, remain);
1101 if (status & MCI_TXACTIVE)
1102 len = mmci_pio_write(host, buffer, remain, status);
1104 sg_miter->consumed = len;
1112 status = readl(base + MMCISTATUS);
1115 sg_miter_stop(sg_miter);
1117 local_irq_restore(flags);
1120 * If we have less than the fifo 'half-full' threshold to transfer,
1121 * trigger a PIO interrupt as soon as any data is available.
1123 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1124 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1127 * If we run out of data, disable the data IRQs; this
1128 * prevents a race where the FIFO becomes empty before
1129 * the chip itself has disabled the data path, and
1130 * stops us racing with our data end IRQ.
1132 if (host->size == 0) {
1133 mmci_set_mask1(host, 0);
1134 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1141 * Handle completion of command and data transfers.
1143 static irqreturn_t mmci_irq(int irq, void *dev_id)
1145 struct mmci_host *host = dev_id;
1149 spin_lock(&host->lock);
1152 struct mmc_command *cmd;
1153 struct mmc_data *data;
1155 status = readl(host->base + MMCISTATUS);
1157 if (host->singleirq) {
1158 if (status & readl(host->base + MMCIMASK1))
1159 mmci_pio_irq(irq, dev_id);
1161 status &= ~MCI_IRQ1MASK;
1165 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
1166 * enabled) since the HW seems to be triggering the IRQ on both
1167 * edges while monitoring DAT0 for busy completion.
1169 status &= readl(host->base + MMCIMASK0);
1170 writel(status, host->base + MMCICLEAR);
1172 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1175 if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
1176 MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1177 mmci_cmd_irq(host, cmd, status);
1180 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
1181 MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
1182 MCI_DATABLOCKEND) && data)
1183 mmci_data_irq(host, data, status);
1185 /* Don't poll for busy completion in irq context. */
1186 if (host->busy_status)
1187 status &= ~MCI_ST_CARDBUSY;
1192 spin_unlock(&host->lock);
1194 return IRQ_RETVAL(ret);
1197 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1199 struct mmci_host *host = mmc_priv(mmc);
1200 unsigned long flags;
1202 WARN_ON(host->mrq != NULL);
1204 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1205 if (mrq->cmd->error) {
1206 mmc_request_done(mmc, mrq);
1210 pm_runtime_get_sync(mmc_dev(mmc));
1212 spin_lock_irqsave(&host->lock, flags);
1217 mmci_get_next_data(host, mrq->data);
1219 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1220 mmci_start_data(host, mrq->data);
1223 mmci_start_command(host, mrq->sbc, 0);
1225 mmci_start_command(host, mrq->cmd, 0);
1227 spin_unlock_irqrestore(&host->lock, flags);
1230 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1232 struct mmci_host *host = mmc_priv(mmc);
1233 struct variant_data *variant = host->variant;
1235 unsigned long flags;
1238 pm_runtime_get_sync(mmc_dev(mmc));
1240 if (host->plat->ios_handler &&
1241 host->plat->ios_handler(mmc_dev(mmc), ios))
1242 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1244 switch (ios->power_mode) {
1246 if (!IS_ERR(mmc->supply.vmmc))
1247 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1249 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1250 regulator_disable(mmc->supply.vqmmc);
1251 host->vqmmc_enabled = false;
1256 if (!IS_ERR(mmc->supply.vmmc))
1257 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1260 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1261 * and instead uses MCI_PWR_ON so apply whatever value is
1262 * configured in the variant data.
1264 pwr |= variant->pwrreg_powerup;
1268 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1269 ret = regulator_enable(mmc->supply.vqmmc);
1271 dev_err(mmc_dev(mmc),
1272 "failed to enable vqmmc regulator\n");
1274 host->vqmmc_enabled = true;
1281 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1283 * The ST Micro variant has some additional bits
1284 * indicating signal direction for the signals in
1285 * the SD/MMC bus and feedback-clock usage.
1287 pwr |= host->pwr_reg_add;
1289 if (ios->bus_width == MMC_BUS_WIDTH_4)
1290 pwr &= ~MCI_ST_DATA74DIREN;
1291 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1292 pwr &= (~MCI_ST_DATA74DIREN &
1293 ~MCI_ST_DATA31DIREN &
1294 ~MCI_ST_DATA2DIREN);
1297 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1298 if (host->hw_designer != AMBA_VENDOR_ST)
1302 * The ST Micro variant use the ROD bit for something
1303 * else and only has OD (Open Drain).
1310 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1311 * gating the clock, the MCI_PWR_ON bit is cleared.
1313 if (!ios->clock && variant->pwrreg_clkgate)
1316 spin_lock_irqsave(&host->lock, flags);
1318 mmci_set_clkreg(host, ios->clock);
1319 mmci_write_pwrreg(host, pwr);
1320 mmci_reg_delay(host);
1322 spin_unlock_irqrestore(&host->lock, flags);
1324 pm_runtime_mark_last_busy(mmc_dev(mmc));
1325 pm_runtime_put_autosuspend(mmc_dev(mmc));
1328 static int mmci_get_cd(struct mmc_host *mmc)
1330 struct mmci_host *host = mmc_priv(mmc);
1331 struct mmci_platform_data *plat = host->plat;
1332 unsigned int status = mmc_gpio_get_cd(mmc);
1334 if (status == -ENOSYS) {
1336 return 1; /* Assume always present */
1338 status = plat->status(mmc_dev(host->mmc));
1343 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1347 if (!IS_ERR(mmc->supply.vqmmc)) {
1349 pm_runtime_get_sync(mmc_dev(mmc));
1351 switch (ios->signal_voltage) {
1352 case MMC_SIGNAL_VOLTAGE_330:
1353 ret = regulator_set_voltage(mmc->supply.vqmmc,
1356 case MMC_SIGNAL_VOLTAGE_180:
1357 ret = regulator_set_voltage(mmc->supply.vqmmc,
1360 case MMC_SIGNAL_VOLTAGE_120:
1361 ret = regulator_set_voltage(mmc->supply.vqmmc,
1367 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1369 pm_runtime_mark_last_busy(mmc_dev(mmc));
1370 pm_runtime_put_autosuspend(mmc_dev(mmc));
1376 static struct mmc_host_ops mmci_ops = {
1377 .request = mmci_request,
1378 .pre_req = mmci_pre_request,
1379 .post_req = mmci_post_request,
1380 .set_ios = mmci_set_ios,
1381 .get_ro = mmc_gpio_get_ro,
1382 .get_cd = mmci_get_cd,
1383 .start_signal_voltage_switch = mmci_sig_volt_switch,
1386 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1388 struct mmci_host *host = mmc_priv(mmc);
1389 int ret = mmc_of_parse(mmc);
1394 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1395 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1396 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1397 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1398 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1399 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1400 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1401 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1402 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1403 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1404 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1405 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1407 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1408 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1409 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1410 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1415 static int mmci_probe(struct amba_device *dev,
1416 const struct amba_id *id)
1418 struct mmci_platform_data *plat = dev->dev.platform_data;
1419 struct device_node *np = dev->dev.of_node;
1420 struct variant_data *variant = id->data;
1421 struct mmci_host *host;
1422 struct mmc_host *mmc;
1425 /* Must have platform data or Device Tree. */
1427 dev_err(&dev->dev, "No plat data or DT found\n");
1432 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1437 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1441 ret = mmci_of_parse(np, mmc);
1445 host = mmc_priv(mmc);
1448 host->hw_designer = amba_manf(dev);
1449 host->hw_revision = amba_rev(dev);
1450 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1451 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1453 host->clk = devm_clk_get(&dev->dev, NULL);
1454 if (IS_ERR(host->clk)) {
1455 ret = PTR_ERR(host->clk);
1459 ret = clk_prepare_enable(host->clk);
1464 host->variant = variant;
1465 host->mclk = clk_get_rate(host->clk);
1467 * According to the spec, mclk is max 100 MHz,
1468 * so we try to adjust the clock down to this,
1471 if (host->mclk > 100000000) {
1472 ret = clk_set_rate(host->clk, 100000000);
1475 host->mclk = clk_get_rate(host->clk);
1476 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1480 host->phybase = dev->res.start;
1481 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1482 if (IS_ERR(host->base)) {
1483 ret = PTR_ERR(host->base);
1488 * The ARM and ST versions of the block have slightly different
1489 * clock divider equations which means that the minimum divider
1492 if (variant->st_clkdiv)
1493 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1495 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1497 * If no maximum operating frequency is supplied, fall back to use
1498 * the module parameter, which has a (low) default value in case it
1499 * is not specified. Either value must not exceed the clock rate into
1500 * the block, of course.
1503 mmc->f_max = min(host->mclk, mmc->f_max);
1505 mmc->f_max = min(host->mclk, fmax);
1506 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1508 /* Get regulators and the supported OCR mask */
1509 mmc_regulator_get_supply(mmc);
1510 if (!mmc->ocr_avail)
1511 mmc->ocr_avail = plat->ocr_mask;
1512 else if (plat->ocr_mask)
1513 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1515 /* DT takes precedence over platform data. */
1517 if (!plat->cd_invert)
1518 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1519 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1522 /* We support these capabilities. */
1523 mmc->caps |= MMC_CAP_CMD23;
1525 if (variant->busy_detect) {
1526 mmci_ops.card_busy = mmci_card_busy;
1527 mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
1528 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1529 mmc->max_busy_timeout = 0;
1532 mmc->ops = &mmci_ops;
1534 /* We support these PM capabilities. */
1535 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1540 mmc->max_segs = NR_SG;
1543 * Since only a certain number of bits are valid in the data length
1544 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1547 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1550 * Set the maximum segment size. Since we aren't doing DMA
1551 * (yet) we are only limited by the data length register.
1553 mmc->max_seg_size = mmc->max_req_size;
1556 * Block size can be up to 2048 bytes, but must be a power of two.
1558 mmc->max_blk_size = 1 << 11;
1561 * Limit the number of blocks transferred so that we don't overflow
1562 * the maximum request size.
1564 mmc->max_blk_count = mmc->max_req_size >> 11;
1566 spin_lock_init(&host->lock);
1568 writel(0, host->base + MMCIMASK0);
1569 writel(0, host->base + MMCIMASK1);
1570 writel(0xfff, host->base + MMCICLEAR);
1572 /* If DT, cd/wp gpios must be supplied through it. */
1573 if (!np && gpio_is_valid(plat->gpio_cd)) {
1574 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1578 if (!np && gpio_is_valid(plat->gpio_wp)) {
1579 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1584 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1585 DRIVER_NAME " (cmd)", host);
1590 host->singleirq = true;
1592 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1593 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1598 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1600 amba_set_drvdata(dev, mmc);
1602 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1603 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1604 amba_rev(dev), (unsigned long long)dev->res.start,
1605 dev->irq[0], dev->irq[1]);
1607 mmci_dma_setup(host);
1609 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1610 pm_runtime_use_autosuspend(&dev->dev);
1611 pm_runtime_put(&dev->dev);
1618 clk_disable_unprepare(host->clk);
1624 static int mmci_remove(struct amba_device *dev)
1626 struct mmc_host *mmc = amba_get_drvdata(dev);
1629 struct mmci_host *host = mmc_priv(mmc);
1632 * Undo pm_runtime_put() in probe. We use the _sync
1633 * version here so that we can access the primecell.
1635 pm_runtime_get_sync(&dev->dev);
1637 mmc_remove_host(mmc);
1639 writel(0, host->base + MMCIMASK0);
1640 writel(0, host->base + MMCIMASK1);
1642 writel(0, host->base + MMCICOMMAND);
1643 writel(0, host->base + MMCIDATACTRL);
1645 mmci_dma_release(host);
1646 clk_disable_unprepare(host->clk);
1654 static void mmci_save(struct mmci_host *host)
1656 unsigned long flags;
1658 spin_lock_irqsave(&host->lock, flags);
1660 writel(0, host->base + MMCIMASK0);
1661 if (host->variant->pwrreg_nopower) {
1662 writel(0, host->base + MMCIDATACTRL);
1663 writel(0, host->base + MMCIPOWER);
1664 writel(0, host->base + MMCICLOCK);
1666 mmci_reg_delay(host);
1668 spin_unlock_irqrestore(&host->lock, flags);
1671 static void mmci_restore(struct mmci_host *host)
1673 unsigned long flags;
1675 spin_lock_irqsave(&host->lock, flags);
1677 if (host->variant->pwrreg_nopower) {
1678 writel(host->clk_reg, host->base + MMCICLOCK);
1679 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1680 writel(host->pwr_reg, host->base + MMCIPOWER);
1682 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1683 mmci_reg_delay(host);
1685 spin_unlock_irqrestore(&host->lock, flags);
1688 static int mmci_runtime_suspend(struct device *dev)
1690 struct amba_device *adev = to_amba_device(dev);
1691 struct mmc_host *mmc = amba_get_drvdata(adev);
1694 struct mmci_host *host = mmc_priv(mmc);
1695 pinctrl_pm_select_sleep_state(dev);
1697 clk_disable_unprepare(host->clk);
1703 static int mmci_runtime_resume(struct device *dev)
1705 struct amba_device *adev = to_amba_device(dev);
1706 struct mmc_host *mmc = amba_get_drvdata(adev);
1709 struct mmci_host *host = mmc_priv(mmc);
1710 clk_prepare_enable(host->clk);
1712 pinctrl_pm_select_default_state(dev);
1719 static const struct dev_pm_ops mmci_dev_pm_ops = {
1720 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1721 pm_runtime_force_resume)
1722 SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1725 static struct amba_id mmci_ids[] = {
1729 .data = &variant_arm,
1734 .data = &variant_arm_extended_fifo,
1739 .data = &variant_arm_extended_fifo_hwfc,
1744 .data = &variant_arm,
1746 /* ST Micro variants */
1750 .data = &variant_u300,
1755 .data = &variant_nomadik,
1760 .data = &variant_u300,
1765 .data = &variant_ux500,
1770 .data = &variant_ux500v2,
1775 MODULE_DEVICE_TABLE(amba, mmci_ids);
1777 static struct amba_driver mmci_driver = {
1779 .name = DRIVER_NAME,
1780 .pm = &mmci_dev_pm_ops,
1782 .probe = mmci_probe,
1783 .remove = mmci_remove,
1784 .id_table = mmci_ids,
1787 module_amba_driver(mmci_driver);
1789 module_param(fmax, uint, 0444);
1791 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1792 MODULE_LICENSE("GPL");