drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Rockchip Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2014, Rockchip Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/mmc.h>
  17 #include <linux/mmc/rk_mmc.h>
  18 #include <linux/of.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/slab.h>
  21 #include <linux/rockchip/cpu.h>
  22
  23 #include "rk_sdmmc.h"
  24 #include "dw_mmc-pltfm.h"
  25 #include "../../clk/rockchip/clk-ops.h"
  26
  27 #include "rk_sdmmc_dbg.h"
  28
  29 /*CRU SDMMC TUNING*/
  30 /*
  31 *   sdmmc,sdio0,sdio1,emmc id=0~3
  32 *   cclk_in_drv, cclk_in_sample  i=0,1
  33 */
  34 #define CRU_SDMMC_CON(id, tuning_type)  (0x200 + ((id) * 8) + ((tuning_type) * 4))
  35
  36 #define MAX_DELAY_LINE  (0xff)
  37 #define FREQ_REF_150MHZ (150000000)
  38 #define PRECISE_ADJUST  (0)
  39
  40 #define SDMMC_TUNING_SEL(tuning_type)           ( tuning_type? 10:11 )
  41 #define SDMMC_TUNING_DELAYNUM(tuning_type)      ( tuning_type? 2:3 )
  42 #define SDMMC_TUNING_DEGREE(tuning_type)        ( tuning_type? 0:1 )
  43 #define SDMMC_TUNING_INIT_STATE                 (0)
  44
  45 enum{
  46        SDMMC_SHIFT_DEGREE_0 = 0,
  47        SDMMC_SHIFT_DEGREE_90,
  48        SDMMC_SHIFT_DEGREE_180,
  49        SDMMC_SHIFT_DEGREE_270,
  50        SDMMC_SHIFT_DEGREE_INVALID,
  51 };
  52
  53 const char *phase_desc[SDMMC_SHIFT_DEGREE_INVALID + 1] = {
  54         "SDMMC_SHIFT_DEGREE_0",
  55         "SDMMC_SHIFT_DEGREE_90",
  56         "SDMMC_SHIFT_DEGREE_180",
  57         "SDMMC_SHIFT_DEGREE_270",
  58         "SDMMC_SHIFT_DEGREE_INVALID",
  59 };
  60
  61 enum{
  62         USE_CLK_AFTER_PHASE = 0,
  63         USE_CLK_AFTER_PHASE_AND_DELAY_LINE = 1,
  64 };
  65
  66 /* Variations in Rockchip specific dw-mshc controller */
  67 enum dw_mci_rockchip_type {
  68         DW_MCI_TYPE_RK3188,
  69         DW_MCI_TYPE_RK3288,
  70 };
  71
  72 /* Rockchip implementation specific driver private data */
  73 struct dw_mci_rockchip_priv_data {
  74         enum dw_mci_rockchip_type               ctrl_type;
  75         u8                              ciu_div;
  76         u32                             sdr_timing;
  77         u32                             ddr_timing;
  78         u32                             cur_speed;
  79 };
  80
  81 static struct dw_mci_rockchip_compatible {
  82         char                            *compatible;
  83         enum dw_mci_rockchip_type               ctrl_type;
  84 } rockchip_compat[] = {
  85         {
  86                 .compatible     = "rockchip,rk31xx-sdmmc",
  87                 .ctrl_type      = DW_MCI_TYPE_RK3188,
  88         },{
  89                 .compatible     = "rockchip,rk32xx-sdmmc",
  90                 .ctrl_type      = DW_MCI_TYPE_RK3288,
  91         },
  92 };
  93
  94 static int dw_mci_rockchip_priv_init(struct dw_mci *host)
  95 {
  96         struct dw_mci_rockchip_priv_data *priv;
  97         int idx;
  98
  99         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 100         if (!priv) {
 101                 dev_err(host->dev, "mem alloc failed for private data\n");
 102                 return -ENOMEM;
 103         }
 104
 105         for (idx = 0; idx < ARRAY_SIZE(rockchip_compat); idx++) {
 106                 if (of_device_is_compatible(host->dev->of_node,
 107                                         rockchip_compat[idx].compatible))
 108                         priv->ctrl_type = rockchip_compat[idx].ctrl_type;
 109         }
 110
 111         host->priv = priv;
 112         return 0;
 113 }
 114
 115 static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
 116 {
 117         struct dw_mci_rockchip_priv_data *priv = host->priv;
 118
 119         if (priv->ctrl_type == DW_MCI_TYPE_RK3288)
 120                 host->bus_hz /= (priv->ciu_div + 1);
 121
 122         return 0;
 123 }
 124
 125 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
 126 {
 127 //      if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
 128 //              *cmdr |= SDMMC_CMD_USE_HOLD_REG;
 129 }
 130
 131 static void dw_mci_rockchip_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 132 {
 133
 134 }
 135
 136 static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
 137 {
 138         return 0;
 139 }
 140 static inline u8 dw_mci_rockchip_get_delaynum(struct dw_mci *host, u8 con_id, u8 tuning_type)
 141 {
 142         u32 regs;
 143         u8 delaynum;
 144
 145         regs =  cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
 146         delaynum = ((regs>>SDMMC_TUNING_DELAYNUM(tuning_type)) & 0xff);
 147
 148         return delaynum;
 149 }
 150
 151 static inline void dw_mci_rockchip_set_delaynum(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 delaynum)
 152 {
 153         u32 regs;
 154         regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
 155         regs &= ~( 0xff << SDMMC_TUNING_DELAYNUM(tuning_type));
 156         regs |= (delaynum  << SDMMC_TUNING_DELAYNUM(tuning_type));
 157         regs |= (0xff  << (SDMMC_TUNING_DELAYNUM(tuning_type)+16));
 158
 159         MMC_DBG_INFO_FUNC(host->mmc,"tuning_result[delayline]: con_id = %d, tuning_type = %d, CRU_CON = 0x%x. [%s]",
 160                 con_id, tuning_type, regs, mmc_hostname(host->mmc));
 161
 162         cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
 163 }
 164
 165 static inline void dw_mci_rockchip_set_degree(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 phase)
 166 {
 167         u32 regs;
 168
 169         regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
 170         regs &= ~( 0x3 << SDMMC_TUNING_DEGREE(tuning_type));
 171         regs |= (phase  << SDMMC_TUNING_DEGREE(tuning_type));
 172         regs |= (0x3  << (SDMMC_TUNING_DEGREE(tuning_type)+16));
 173
 174         MMC_DBG_INFO_FUNC(host->mmc,"tuning_result[phase]: con_id = %d, tuning_type= %d, CRU_CON = 0x%x. [%s]",
 175                 con_id, tuning_type, regs, mmc_hostname(host->mmc));
 176
 177         cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
 178 }
 179
 180 static inline void dw_mci_rockchip_turning_sel(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 mode)
 181 {
 182         u32 regs;
 183         regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type)) ;
 184         regs &= ~( 0x1 << SDMMC_TUNING_SEL(tuning_type));
 185         regs |= (mode  << SDMMC_TUNING_SEL(tuning_type));
 186         regs |= (0x1  << (SDMMC_TUNING_SEL(tuning_type)+16));
 187
 188         MMC_DBG_INFO_FUNC(host->mmc,"tuning_sel: con_id = %d, tuning_type = %d, CRU_CON = 0x%x. [%s]",
 189                 con_id, tuning_type, regs, mmc_hostname(host->mmc));
 190
 191         cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
 192 }
 193
 194
 195 static inline u8 dw_mci_rockchip_get_phase(struct dw_mci *host, u8 con_id, u8 tuning_type)
 196 {
 197         return 0;
 198 }
 199
 200 static inline u8 dw_mci_rockchip_move_next_clksmpl(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 val)
 201 {
 202         u32 regs;
 203
 204         regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type)) ;
 205
 206         if(tuning_type) {
 207             val = ((regs>>SDMMC_TUNING_DELAYNUM(tuning_type)) & 0xff);
 208         }
 209
 210         return val;
 211 }
 212
 213
 214
 215
 216
 217 static int inline __dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
 218                                         u8 *blk_test, unsigned int blksz)
 219 {
 220         struct dw_mci *host = slot->host;
 221         struct mmc_host *mmc = slot->mmc;
 222         struct mmc_request mrq = {NULL};
 223         struct mmc_command cmd = {0};
 224         struct mmc_command stop = {0};
 225         struct mmc_data data = {0};
 226         struct scatterlist sg;
 227
 228         cmd.opcode = opcode;
 229         cmd.arg = 0;
 230         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 231         stop.opcode = MMC_STOP_TRANSMISSION;
 232         stop.arg = 0;
 233         stop.flags = MMC_RSP_R1B | MMC_CMD_AC;
 234         data.blksz = blksz;
 235         data.blocks = 1;
 236         data.flags = MMC_DATA_READ;
 237         data.sg = &sg;
 238         data.sg_len = 1;
 239
 240         sg_init_one(&sg, blk_test, blksz);
 241         mrq.cmd = &cmd;
 242         mrq.stop = &stop;
 243         mrq.data = &data;
 244         host->mrq = &mrq;
 245         mci_writel(host, TMOUT, ~0);
 246
 247         mmc_wait_for_req(mmc, &mrq);
 248         if(!cmd.error && !data.error){
 249                 return 0;
 250         }else{
 251                 dev_dbg(host->dev,
 252                         "Tuning error: cmd.error:%d, data.error:%d\n",cmd.error, data.error);
 253                 return -EIO;
 254         }
 255
 256 }
 257
 258
 259 static int dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
 260                                         struct dw_mci_tuning_data *tuning_data)
 261 {
 262
 263         struct dw_mci *host = slot->host;
 264         u8 step;
 265         u8 candidates_delayline[MAX_DELAY_LINE] = {0};
 266         u8 candidates_degree[SDMMC_SHIFT_DEGREE_INVALID] = {4,4,4,4};
 267         u8 index = 0;
 268         u8 start_degree = 0;
 269         u32 start_delayline = 0;
 270         const u8 *blk_pattern = tuning_data->blk_pattern;
 271         u8 *blk_test;
 272         int ret = -1;
 273         int ref = 0;
 274         unsigned int blksz = tuning_data->blksz;
 275
 276         MMC_DBG_INFO_FUNC(host->mmc,"execute tuning:  [%s]", mmc_hostname(host->mmc));
 277
 278         blk_test = kmalloc(blksz, GFP_KERNEL);
 279         if (!blk_test)
 280         {
 281                 MMC_DBG_ERR_FUNC(host->mmc,"execute tuning:  blk_test kmalloc failed[%s]",
 282                         mmc_hostname(host->mmc));
 283                 return -ENOMEM;
 284         }
 285
 286         /* Select use delay line*/
 287         dw_mci_rockchip_turning_sel(host, tuning_data->con_id, tuning_data->tuning_type,
 288                                     USE_CLK_AFTER_PHASE_AND_DELAY_LINE);
 289
 290         /* For RK32XX signoff 150M clk, 1 cycle = 6.66ns , and 1/4 phase = 1.66ns.
 291            Netlist level sample LT:  10.531ns / 42.126ps   WC: 19.695ns / 76.936ps.
 292            So we take average --- 60ps, (1.66ns/ 2) = 0.83(middle-value),TAKE 0.9
 293            0.9 / 60ps = 15 delayline
 294          */
 295         if(cpu_is_rk3288()){
 296                  ref = ((FREQ_REF_150MHZ + host->bus_hz - 1) / host->bus_hz);
 297                  step = (15 * ref);
 298
 299                  if(step > MAX_DELAY_LINE){
 300                         step = MAX_DELAY_LINE;
 301                         MMC_DBG_WARN_FUNC(host->mmc,
 302                                         "execute tuning: TOO LARGE STEP![%s]", mmc_hostname(host->mmc));
 303                  }
 304                  MMC_DBG_INFO_FUNC(host->mmc,
 305                                 "execute tuning: SOC is RK3288, ref = %d, step = %d[%s]",
 306                                 ref, step, mmc_hostname(host->mmc));
 307
 308         }else{
 309                  step = (15 * ((FREQ_REF_150MHZ / host->bus_hz) * 100)) / 100;
 310
 311                  if(step > MAX_DELAY_LINE){
 312                         step = MAX_DELAY_LINE;
 313                         MMC_DBG_WARN_FUNC(host->mmc,
 314                                         "execute tuning: TOO LARGE STEP![%s]", mmc_hostname(host->mmc));
 315                  }
 316                  MMC_DBG_INFO_FUNC(host->mmc,
 317                                 "execute tuning: SOC is UNKNOWN, step = %d[%s]",
 318                                 step, mmc_hostname(host->mmc));
 319         }
 320
 321         /* Loop degree from 0 ~ 270 */
 322         for(start_degree = SDMMC_SHIFT_DEGREE_0; start_degree < SDMMC_SHIFT_DEGREE_270; start_degree++){
 323
 324                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, start_degree);
 325                 if(0 == __dw_mci_rockchip_execute_tuning(slot, opcode, blk_test, blksz)){
 326                         if(!memcmp(blk_pattern, blk_test, blksz)){
 327                                 /* Successfully tuning in this condition*/
 328                                 candidates_degree[index] = start_degree;
 329                                 index++;
 330                          }
 331                }
 332
 333         }
 334
 335         MMC_DBG_INFO_FUNC(host->mmc,"\n execute tuning: candidates_degree = %s \t%s \t%s \t%s[%s]",
 336                 phase_desc[candidates_degree[0]], phase_desc[candidates_degree[1]],
 337                 phase_desc[candidates_degree[2]], phase_desc[candidates_degree[3]],
 338                 mmc_hostname(host->mmc));
 339
 340
 341         if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_0)
 342                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_90)
 343                 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_180)){
 344
 345                 MMC_DBG_INFO_FUNC(host->mmc,
 346                                 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_90 [%s]",
 347                                 mmc_hostname(host->mmc));
 348
 349                 dw_mci_rockchip_set_degree(host, tuning_data->con_id,
 350                         tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
 351                 ret = 0;
 352                 goto done;
 353         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
 354                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_180)
 355                 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_270)){
 356                 MMC_DBG_INFO_FUNC(host->mmc,
 357                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_180 [%s]",
 358                         mmc_hostname(host->mmc));
 359                 dw_mci_rockchip_set_degree(host, tuning_data->con_id,
 360                         tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
 361                 ret = 0;
 362                 goto done;
 363         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_0)
 364                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_90)
 365                 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_INVALID)){
 366
 367                 MMC_DBG_INFO_FUNC(host->mmc,
 368                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_0 ~  SDMMC_SHIFT_DEGREE_90[%s]",
 369                         mmc_hostname(host->mmc));
 370
 371                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
 372                 #if PRECISE_ADJUST
 373                 goto delayline;
 374                 #else
 375                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 376                 ret = 0;
 377                 goto done;
 378                 #endif
 379         }else if((candidates_degree[0]==SDMMC_SHIFT_DEGREE_0)
 380                 && (candidates_degree[1]==SDMMC_SHIFT_DEGREE_180)){
 381
 382                 MMC_DBG_INFO_FUNC(host->mmc,
 383                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_0 AND SDMMC_SHIFT_DEGREE_180[%s]",
 384                         mmc_hostname(host->mmc));
 385
 386                 /* FixMe: NO sense any signal indicator make this case happen*/
 387                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
 388                 goto delayline;
 389         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
 390                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_180)
 391                 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_INVALID)){
 392
 393                 MMC_DBG_INFO_FUNC(host->mmc,
 394                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_90 ~  SDMMC_SHIFT_DEGREE_180[%s]",
 395                         mmc_hostname(host->mmc));
 396
 397                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
 398                 #if PRECISE_ADJUST
 399                 goto delayline;
 400                 #else
 401                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 402                 ret = 0;
 403                 goto done;
 404                 #endif
 405         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_180)
 406                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_270)){
 407
 408                 MMC_DBG_INFO_FUNC(host->mmc,
 409                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_180 ~  SDMMC_SHIFT_DEGREE_270[%s]",
 410                         mmc_hostname(host->mmc));
 411
 412                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
 413                 #if PRECISE_ADJUST
 414                 goto delayline;
 415                 #else
 416                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 417                 ret = 0;
 418                 goto done;
 419                 #endif
 420         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_180)
 421                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_INVALID)){
 422
 423                 MMC_DBG_INFO_FUNC(host->mmc,
 424                         "execute tuning: candidates_degree = [SDMMC_SHIFT_DEGREE_90 + n ~  SDMMC_SHIFT_DEGREE_180][%s]",
 425                         mmc_hostname(host->mmc));
 426
 427                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
 428                 #if PRECISE_ADJUST
 429                 goto delayline;
 430                 #else
 431                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 432                 ret = 0;
 433                 goto done;
 434                 #endif
 435         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
 436                 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_INVALID)){
 437
 438                 MMC_DBG_INFO_FUNC(host->mmc,
 439                         "execute tuning: candidates_degree = [SDMMC_SHIFT_DEGREE_0 + n ~  SDMMC_SHIFT_DEGREE_90][%s]",
 440                         mmc_hostname(host->mmc));
 441
 442                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
 443                 #if PRECISE_ADJUST
 444                 goto delayline;
 445                 #else
 446                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 447                 ret = 0;
 448                 goto done;
 449                 #endif
 450         }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_270)){
 451
 452                 MMC_DBG_INFO_FUNC(host->mmc,
 453                         "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_270 [%s]",
 454                         mmc_hostname(host->mmc));
 455
 456                 /*FixME: so urgly signal indicator, HW engineer help!*/
 457
 458                 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
 459                 #if PRECISE_ADJUST
 460                 goto delayline;
 461                 #else
 462                 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
 463                 ret = 0;
 464                 goto done;
 465                 #endif
 466         }else{
 467                 MMC_DBG_ERR_FUNC(host->mmc,
 468                                 "execute tuning: candidates_degree beyong limited case! [%s]",
 469                                 mmc_hostname(host->mmc));
 470                 if(host->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
 471                         BUG();
 472                 return -EAGAIN;
 473         }
 474
 475 delayline:
 476                 index = 0;
 477                 for(start_delayline = 0; start_delayline <= MAX_DELAY_LINE; start_delayline += step){
 478
 479                         dw_mci_rockchip_set_delaynum(host, tuning_data->con_id,
 480                                 tuning_data->tuning_type, start_delayline);
 481                         if(0 == __dw_mci_rockchip_execute_tuning(slot, opcode, blk_test, blksz)){
 482                                 if(!memcmp(blk_pattern, blk_test, blksz)){
 483                                         /* Successfully tuning in this condition*/
 484                                         candidates_delayline[index] = start_delayline;
 485                                         index++;
 486                                 }
 487                         }
 488                 }
 489                 if((index < 2) && (index != 0)) {
 490                         MMC_DBG_INFO_FUNC(host->mmc,
 491                                 "execute tuning: candidates_delayline failed for only one element [%s]",
 492                                 mmc_hostname(host->mmc));
 493
 494                         /* Make step smaller, and re-calculate */
 495                         step = step >> 1;
 496                         index = 0;
 497                         goto delayline;
 498                 }else if(index >= 2){
 499                         /* Find it! */
 500                         MMC_DBG_INFO_FUNC(host->mmc,
 501                                 "execute tuning: candidates_delayline calculate successfully  [%s]",
 502                                 mmc_hostname(host->mmc));
 503
 504                         dw_mci_rockchip_set_delaynum(host, tuning_data->con_id,
 505                                 tuning_data->tuning_type, candidates_delayline[index/2]);
 506                         ret = 0;
 507                         goto done;
 508                 }
 509
 510 done:
 511         kfree(blk_test);
 512         blk_test = NULL;
 513         return ret;
 514
 515 }
 516
 517 /* Common capabilities of RK32XX SoC */
 518 static unsigned long rockchip_dwmmc_caps[4] = {
 519         MMC_CAP_CMD23,
 520         MMC_CAP_CMD23,
 521         MMC_CAP_CMD23,
 522         MMC_CAP_CMD23,
 523 };
 524
 525 unsigned int  rockchip_dwmmc_hold_reg[4] = {1,0,0,0};
 526
 527 static const struct dw_mci_drv_data rockchip_drv_data = {
 528         .caps                   = rockchip_dwmmc_caps,
 529         .hold_reg_flag  = rockchip_dwmmc_hold_reg,
 530         .init                   = dw_mci_rockchip_priv_init,
 531         .setup_clock            = dw_mci_rockchip_setup_clock,
 532         .prepare_command        = dw_mci_rockchip_prepare_command,
 533         .set_ios                = dw_mci_rockchip_set_ios,
 534         .parse_dt               = dw_mci_rockchip_parse_dt,
 535         .execute_tuning         = dw_mci_rockchip_execute_tuning,
 536 };
 537
 538 static const struct of_device_id dw_mci_rockchip_match[] = {
 539         { .compatible = "rockchip,rk_mmc",
 540                         .data = &rockchip_drv_data, },
 541         { /* Sentinel */},
 542 };
 543 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 544
 545 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 546 {
 547         const struct dw_mci_drv_data *drv_data;
 548         const struct of_device_id *match;
 549
 550         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 551         drv_data = match->data;
 552         return dw_mci_pltfm_register(pdev, drv_data);
 553 }
 554
 555 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 556         .probe          = dw_mci_rockchip_probe,
 557         .remove         = __exit_p(dw_mci_pltfm_remove),
 558         .driver         = {
 559                 .name           = "dwmmc_rockchip",
 560                 .of_match_table = dw_mci_rockchip_match,
 561                 .pm             = &dw_mci_pltfm_pmops,
 562         },
 563 };
 564
 565 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 566
 567 MODULE_DESCRIPTION("Rockchip Specific DW-SDMMC Driver Extension");
 568 MODULE_AUTHOR("Bangwang Xie < xbw@rock-chips.com>");
 569 MODULE_LICENSE("GPL v2");
 570 MODULE_ALIAS("platform:dwmmc-rockchip");