drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Rockchip Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2014, Rockchip Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15
  16 #include <linux/slab.h>
  17
  18 #include <linux/mmc/host.h>
  19 #include <linux/mmc/rk_mmc.h>
  20 #include <linux/of.h>
  21 #include <linux/of_gpio.h>
  22
  23 #include "rk_sdmmc.h"
  24 #include "dw_mmc-pltfm.h"
  25
  26 #include "rk_sdmmc_of.h"
  27 //u32 mmc_debug_level = MMC_DBG_ALL;
  28
  29
  30 #define NUM_PINS(x)                     (x + 2)
  31
  32 /* SDMMC_CLKSEL is not used in Rockchip
  33 #define SDMMC_CLKSEL                    0x09C
  34 #define SDMMC_CLKSEL_CCLK_SAMPLE(x)     (((x) & 7) << 0)
  35 #define SDMMC_CLKSEL_CCLK_DRIVE(x)      (((x) & 7) << 16)
  36 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)    (((x) & 7) << 24)
  37 #define SDMMC_CLKSEL_GET_DRV_WD3(x)     (((x) >> 16) & 0x7)
  38 #define SDMMC_CLKSEL_TIMING(x, y, z)    (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
  39                                         SDMMC_CLKSEL_CCLK_DRIVE(y) |    \
  40                                         SDMMC_CLKSEL_CCLK_DIVIDER(z))
  41 */
  42 #define SDMMC_CMD_USE_HOLD_REG          BIT(29)
  43
  44 //#define EXYNOS4210_FIXED_CIU_CLK_DIV  2
  45 //#define EXYNOS4412_FIXED_CIU_CLK_DIV  4
  46
  47 /* Variations in Rockchip specific dw-mshc controller */
  48 enum dw_mci_rockchip_type {
  49         DW_MCI_TYPE_RK3288,
  50 };
  51
  52 /* Rockchip implementation specific driver private data */
  53 struct dw_mci_rockchip_priv_data {
  54         enum dw_mci_rockchip_type               ctrl_type;
  55         u8                              ciu_div;
  56         u32                             sdr_timing;
  57         u32                             ddr_timing;
  58 };
  59
  60 static struct dw_mci_rockchip_compatible {
  61         char                            *compatible;
  62         enum dw_mci_rockchip_type               ctrl_type;
  63 } rockchip_compat[] = {
  64         {
  65                 .compatible     = "rockchip,rk3288-sdmmc",
  66                 .ctrl_type      = DW_MCI_TYPE_RK3288,
  67         },
  68 };
  69
  70 static int dw_mci_rockchip_priv_init(struct dw_mci *host)
  71 {
  72         struct dw_mci_rockchip_priv_data *priv;
  73         int idx;
  74
  75         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  76         if (!priv) {
  77                 dev_err(host->dev, "mem alloc failed for private data\n");
  78                 return -ENOMEM;
  79         }
  80
  81         for (idx = 0; idx < ARRAY_SIZE(rockchip_compat); idx++) {
  82                 if (of_device_is_compatible(host->dev->of_node,
  83                                         rockchip_compat[idx].compatible))
  84                         priv->ctrl_type = rockchip_compat[idx].ctrl_type;
  85         }
  86
  87         host->priv = priv;
  88         return 0;
  89 }
  90
  91 static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
  92 {
  93         struct dw_mci_rockchip_priv_data *priv = host->priv;
  94
  95         if (priv->ctrl_type == DW_MCI_TYPE_RK3288)
  96                 host->bus_hz /= (priv->ciu_div + 1);
  97         /*else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
  98                 host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV;
  99         else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
 100                 host->bus_hz /= EXYNOS4210_FIXED_CIU_CLK_DIV;
 101     */
 102         return 0;
 103 }
 104
 105 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
 106 {
 107         /*
 108          * Exynos4412 and Exynos5250 extends the use of CMD register with the
 109          * use of bit 29 (which is reserved on standard MSHC controllers) for
 110          * optionally bypassing the HOLD register for command and data. The
 111          * HOLD register should be bypassed in case there is no phase shift
 112          * applied on CMD/DATA that is sent to the card.
 113          */
 114 //      if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
 115 //              *cmdr |= SDMMC_CMD_USE_HOLD_REG;
 116 }
 117
 118 static void dw_mci_rockchip_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 119 {
 120         //struct dw_mci_rockchip_priv_data *priv = host->priv;
 121 /*
 122         if (ios->timing == MMC_TIMING_UHS_DDR50)
 123                 mci_writel(host, CLKSEL, priv->ddr_timing);
 124         else
 125                 mci_writel(host, CLKSEL, priv->sdr_timing);
 126 */
 127 }
 128
 129 static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
 130 {
 131 /*
 132         struct dw_mci_rockchip_priv_data *priv = host->priv;
 133         struct device_node *np = host->dev->of_node;
 134         u32 timing[2];
 135         u32 div = 0;
 136         int ret;
 137         //rk set the timing in CRU
 138         of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 139         priv->ciu_div = div;
 140
 141         ret = of_property_read_u32_array(np,
 142                         "samsung,dw-mshc-sdr-timing", timing, 2);
 143         if (ret)
 144                 return ret;
 145
 146         priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 147
 148         ret = of_property_read_u32_array(np,
 149                         "samsung,dw-mshc-ddr-timing", timing, 2);
 150         if (ret)
 151                 return ret;
 152
 153         priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
 154         */
 155         return 0;
 156 }
 157
 158 /* Common capabilities of RK32XX SoC */
 159 static unsigned long rockchip_dwmmc_caps[4] = {
 160         MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR |
 161                 MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
 162         MMC_CAP_CMD23,
 163         MMC_CAP_CMD23,
 164         MMC_CAP_CMD23,
 165 };
 166
 167 static const struct dw_mci_drv_data rockchip_drv_data = {
 168         .caps                   = rockchip_dwmmc_caps,
 169         .init                   = dw_mci_rockchip_priv_init,
 170         .setup_clock            = dw_mci_rockchip_setup_clock,
 171         .prepare_command        = dw_mci_rockchip_prepare_command,
 172         .set_ios                = dw_mci_rockchip_set_ios,
 173         .parse_dt               = dw_mci_rockchip_parse_dt,
 174 };
 175
 176 static const struct of_device_id dw_mci_rockchip_match[] = {
 177         { .compatible = "rockchip,rk_mmc",
 178                         .data = &rockchip_drv_data, },
 179         { /* Sentinel */},
 180 };
 181 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 182
 183 extern void rockchip_mmc_of_probe(struct device_node *np,struct rk_sdmmc_of *mmc_property);
 184
 185 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 186 {
 187         const struct dw_mci_drv_data *drv_data;
 188         const struct of_device_id *match;
 189     struct device_node *np = pdev->dev.of_node;
 190         struct rk_sdmmc_of *rk_mmc_property = NULL;
 191
 192
 193     rk_mmc_property = (struct rk_sdmmc_of *)kmalloc(sizeof(struct rk_sdmmc_of),GFP_KERNEL);
 194     if(NULL == rk_mmc_property)
 195     {
 196
 197         kfree(rk_mmc_property);
 198         rk_mmc_property = NULL;
 199         //mmc_error("");
 200         printk("rk_mmc_property malloc space failed!\n");
 201         return 0;
 202     }
 203
 204
 205         rockchip_mmc_of_probe(np,rk_mmc_property);
 206
 207
 208
 209         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 210         drv_data = match->data;
 211         return dw_mci_pltfm_register(pdev, drv_data);
 212 }
 213
 214 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 215         .probe          = dw_mci_rockchip_probe,
 216         .remove         = __exit_p(dw_mci_pltfm_remove),
 217         .driver         = {
 218                 .name           = "dwmmc_rockchip",
 219                 .of_match_table = dw_mci_rockchip_match,
 220                 .pm             = &dw_mci_pltfm_pmops,
 221         },
 222 };
 223
 224 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 225
 226 MODULE_DESCRIPTION("Rockchip Specific DW-SDMMC Driver Extension");
 227 MODULE_AUTHOR("Bangwang Xie < xbw@rock-chips.com>");
 228 MODULE_LICENSE("GPL v2");
 229 MODULE_ALIAS("platform:dwmmc-rockchip");