drivers/mmc/host/dw_mmc-rockchip.c

   1 /*
   2  * Rockchip Specific Extensions for Synopsys DW Multimedia Card Interface driver
   3  *
   4  * Copyright (C) 2014, Rockchip Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/mmc/mmc.h>
  17 #include <linux/mmc/rk_mmc.h>
  18 #include <linux/of.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/slab.h>
  21 #include <linux/rockchip/cpu.h>
  22 #include <linux/rockchip/cru.h>
  23 #include <linux/delay.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/regmap.h>
  26 #include "rk_sdmmc.h"
  27 #include "dw_mmc-pltfm.h"
  28 #include "../../clk/rockchip/clk-ops.h"
  29
  30 #include "rk_sdmmc_dbg.h"
  31
  32 /* Rockchip implementation specific driver private data */
  33 struct dw_mci_rockchip_priv_data {
  34         enum dw_mci_rockchip_type               ctrl_type;
  35         u8                              ciu_div;
  36         u32                             sdr_timing;
  37         u32                             ddr_timing;
  38         u32                             cur_speed;
  39 };
  40
  41 static struct dw_mci_rockchip_compatible {
  42         char                            *compatible;
  43         enum dw_mci_rockchip_type               ctrl_type;
  44 } rockchip_compat[] = {
  45         {
  46                 .compatible     = "rockchip,rk31xx-sdmmc",
  47                 .ctrl_type      = DW_MCI_TYPE_RK3188,
  48         },
  49         {
  50                 .compatible     = "rockchip,rk32xx-sdmmc",
  51                 .ctrl_type      = DW_MCI_TYPE_RK3288,
  52         },
  53         {
  54                 .compatible     = "rockchip,rk3036-sdmmc",
  55                 .ctrl_type      = DW_MCI_TYPE_RK3036,
  56         },
  57         {
  58                 .compatible     = "rockchip,rk312x-sdmmc",
  59                 .ctrl_type      = DW_MCI_TYPE_RK312X,
  60         },
  61         {
  62                 .compatible     = "rockchip,rk3368-sdmmc",
  63                 .ctrl_type      = DW_MCI_TYPE_RK3368,
  64         },
  65 };
  66
  67 #define syscon_find(np, property) \
  68 syscon_regmap_lookup_by_phandle(np, property)
  69
  70 static int dw_mci_rockchip_priv_init(struct dw_mci *host)
  71 {
  72         struct dw_mci_rockchip_priv_data *priv;
  73         int idx;
  74
  75         priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
  76         if (!priv) {
  77                 dev_err(host->dev, "mem alloc failed for private data\n");
  78                 return -ENOMEM;
  79         }
  80
  81         for (idx = 0; idx < ARRAY_SIZE(rockchip_compat); idx++) {
  82                 if (of_device_is_compatible(host->dev->of_node,
  83                                             rockchip_compat[idx].compatible)) {
  84                         priv->ctrl_type = rockchip_compat[idx].ctrl_type;
  85                         host->cid = priv->ctrl_type;
  86                         if (priv->ctrl_type == DW_MCI_TYPE_RK3368) {
  87                                 host->grf = syscon_regmap_lookup_by_phandle(
  88                                                 host->dev->of_node, "rockchip,grf");
  89                                 if (IS_ERR(host->grf)) {
  90                                         pr_err("No rockchip,grf phandle specified");
  91                                         return PTR_ERR(host->grf);
  92                                 }
  93                                 host->cru = syscon_regmap_lookup_by_phandle(
  94                                         host->dev->of_node, "rockchip,cru");
  95                                 if (IS_ERR(host->cru)) {
  96                                         pr_err("No rockchip,cru phandle specified");
  97                                         return PTR_ERR(host->cru);
  98                                 }
  99                         }
 100                 }
 101         }
 102
 103         host->priv = priv;
 104         return 0;
 105 }
 106
 107 static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
 108 {
 109         struct dw_mci_rockchip_priv_data *priv = host->priv;
 110
 111         if ((priv->ctrl_type == DW_MCI_TYPE_RK3288) ||
 112             (priv->ctrl_type == DW_MCI_TYPE_RK3036) ||
 113             (priv->ctrl_type == DW_MCI_TYPE_RK312X) ||
 114             (priv->ctrl_type == DW_MCI_TYPE_RK3368))
 115                 host->bus_hz /= (priv->ciu_div + 1);
 116
 117         return 0;
 118 }
 119
 120 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
 121 {
 122 }
 123
 124 static void dw_mci_rockchip_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 125 {
 126 }
 127
 128 static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
 129 {
 130         return 0;
 131 }
 132
 133 #define ROCKCHIP_MMC_DELAY_SEL BIT(10)
 134 #define ROCKCHIP_MMC_DEGREE_MASK 0x3
 135 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
 136 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
 137 #define PSECS_PER_SEC 1000000000000LL
 138
 139 /*
 140  * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
 141  * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
 142  */
 143 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
 144
 145 #define NUM_PHASES                      32
 146 #define TUNING_ITERATION_TO_PHASE(i)    (DIV_ROUND_UP((i) * 360, NUM_PHASES))
 147
 148 static int rockchip_mmc_set_phase(int degrees, struct dw_mci *host)
 149 {
 150         unsigned long rate = clk_get_rate(host->clk_mmc)/2; /* 150M */
 151         u8 nineties, remainder;
 152         u8 delay_num;
 153         u32 raw_value;
 154         u64 delay;
 155
 156         degrees++;
 157         degrees -= ((degrees) * 10 % (360/NUM_PHASES*10)) / 10;
 158         nineties = degrees / 90;
 159         remainder = (degrees % 90) / (360/NUM_PHASES);
 160
 161         delay = PSECS_PER_SEC;
 162         do_div(delay, rate);
 163         do_div(delay, NUM_PHASES);
 164         do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
 165
 166         delay *= remainder;
 167         delay_num = (u8) min(delay, 255ULL);
 168
 169         raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
 170         raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
 171         raw_value |= nineties;
 172
 173         cru_writel(0x00010001, host->tune_regsbase);
 174         cru_writel(((0x07ff << 16)|(raw_value)), host->tune_regsbase + 4);
 175         cru_writel(0x00010000, host->tune_regsbase);
 176
 177         return 0;
 178 }
 179
 180 static int dw_mci_tuning_test(struct dw_mci_slot *slot, u32 opcode,
 181                               struct dw_mci_tuning_data *tuning_data,
 182                               u8 *blk_test)
 183 {
 184         struct dw_mci *host = slot->host;
 185         struct mmc_host *mmc = slot->mmc;
 186         const u8 *blk_pattern = tuning_data->blk_pattern;
 187         unsigned int blksz = tuning_data->blksz;
 188         struct mmc_request mrq = { NULL };
 189         struct mmc_command cmd = {0};
 190         struct mmc_command stop = {0};
 191         struct mmc_data data = {0};
 192         struct scatterlist sg;
 193
 194         memset(blk_test, 0, blksz);
 195
 196         cmd.opcode = opcode;
 197         cmd.arg = 0;
 198         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 199
 200         stop.opcode = MMC_STOP_TRANSMISSION;
 201         stop.arg = 0;
 202         stop.flags = MMC_RSP_R1B | MMC_CMD_AC;
 203
 204         data.blksz = blksz;
 205         data.blocks = 1;
 206         data.flags = MMC_DATA_READ;
 207         data.sg = &sg;
 208         data.sg_len = 1;
 209
 210         sg_init_one(&sg, blk_test, blksz);
 211         mrq.cmd = &cmd;
 212         mrq.stop = &stop;
 213         mrq.data = &data;
 214         host->mrq = &mrq;
 215         mci_writel(host, TMOUT, ~0);
 216
 217         mmc_wait_for_req(mmc, &mrq);
 218         if (!cmd.error && !data.error) {
 219                 if (!memcmp(blk_pattern, blk_test, blksz))
 220                         return 0;
 221
 222                 return -EIO;
 223         } else {
 224                 dev_err(host->dev,
 225                         "Tuning error: cmd.error:%d, data.error:%d\n",
 226                         cmd.error, data.error);
 227                 if (cmd.error)
 228                         return cmd.error;
 229                 else
 230                         return data.error;
 231         }
 232 }
 233
 234 static int
 235 dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
 236                                struct dw_mci_tuning_data *tuning_data)
 237 {
 238         struct dw_mci *host = slot->host;
 239         struct device *dev = host->dev;
 240         struct device_node *np = dev->of_node;
 241         unsigned int blksz = tuning_data->blksz;
 242         u8 *blk_test;
 243         int ret = 0;
 244         int i;
 245         bool v, prev_v = 0, first_v;
 246         struct range_t {
 247                 int start;
 248                 int end; /* inclusive */
 249         };
 250         struct range_t *ranges;
 251         unsigned int range_count = 0;
 252         int longest_range_len = -1;
 253         int longest_range = -1;
 254         int middle_phase;
 255
 256         if (!of_property_read_u32(np, "tune_regsbase", &host->tune_regsbase)) {
 257                 pr_info("[%s] tuning regsbase addr 0x%03x.\n",
 258                         mmc_hostname(host->mmc), host->tune_regsbase);
 259         } else {
 260                 pr_err("[%s] tuning regsbase addr is missing!\n",
 261                        mmc_hostname(host->mmc));
 262                 return -1;
 263         }
 264
 265         blk_test = kmalloc(blksz, GFP_KERNEL);
 266         if (!blk_test)
 267                 return -ENOMEM;
 268
 269
 270         ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
 271         if (!ranges) {
 272                 ret = -ENOMEM;
 273                 goto free_blk_test;
 274         }
 275
 276         /* Try each phase and extract good ranges */
 277         for (i = 0; i < NUM_PHASES - 8; i++) {
 278                 rockchip_mmc_set_phase(TUNING_ITERATION_TO_PHASE(i), host);
 279                 v = !dw_mci_tuning_test(slot, opcode, tuning_data, blk_test);
 280
 281                 if ((!prev_v) && v) {
 282                         range_count++;
 283                         ranges[range_count-1].start = i;
 284                 }
 285                 if (v)
 286                         ranges[range_count-1].end = i;
 287
 288                 if (i == 0)
 289                         first_v = v;
 290
 291                 prev_v = v;
 292         }
 293
 294         if (range_count == 0) {
 295                 dev_err(host->dev, "All phases bad!");
 296                 ret = -EIO;
 297                 goto free;
 298         }
 299
 300         /* wrap around case, merge the end points
 301         if ((range_count > 1) && first_v && v) {
 302                 ranges[0].start = ranges[range_count-1].start;
 303                 range_count--;
 304         }
 305         */
 306
 307         if ((ranges[0].start == 0) && (ranges[0].end == NUM_PHASES - 1)) {
 308                 rockchip_mmc_set_phase(0, host);
 309                 dev_err(host->dev,
 310                         "All phases work, using default phase %d.", 0);
 311                 goto free;
 312         }
 313
 314         /* Find the longest range */
 315         for (i = 0; i < range_count; i++) {
 316                 int len = (ranges[i].end - ranges[i].start + 1);
 317
 318                 if (len < 0)
 319                         len += NUM_PHASES;
 320
 321                 if (longest_range_len < len) {
 322                         longest_range_len = len;
 323                         longest_range = i;
 324                 }
 325
 326                 dev_err(host->dev, "Good phase range %d-%d (%d len)\n",
 327                         TUNING_ITERATION_TO_PHASE(ranges[i].start),
 328                         TUNING_ITERATION_TO_PHASE(ranges[i].end),
 329                         len
 330                 );
 331         }
 332
 333         dev_err(host->dev, "Best phase range %d-%d (%d len)\n",
 334                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
 335                 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
 336                 longest_range_len
 337         );
 338
 339         middle_phase = ranges[longest_range].start + longest_range_len / 2;
 340         middle_phase %= NUM_PHASES;
 341         dev_err(host->dev, "Successfully tuned phase to %d\n",
 342                 TUNING_ITERATION_TO_PHASE(middle_phase));
 343
 344         rockchip_mmc_set_phase(TUNING_ITERATION_TO_PHASE(middle_phase), host);
 345
 346 free:
 347         kfree(ranges);
 348 free_blk_test:
 349         kfree(blk_test);
 350         return ret;
 351 }
 352
 353 /* Common capabilities of RK32XX SoC */
 354 static unsigned long rockchip_dwmmc_caps[4] = {
 355         MMC_CAP_CMD23,
 356         MMC_CAP_CMD23,
 357         MMC_CAP_CMD23,
 358         MMC_CAP_CMD23,
 359 };
 360
 361 unsigned int  rockchip_dwmmc_hold_reg[4] = {1, 0, 0, 0};
 362
 363 static const struct dw_mci_drv_data rockchip_drv_data = {
 364         .caps                   = rockchip_dwmmc_caps,
 365         .hold_reg_flag  = rockchip_dwmmc_hold_reg,
 366         .init                   = dw_mci_rockchip_priv_init,
 367         .setup_clock            = dw_mci_rockchip_setup_clock,
 368         .prepare_command        = dw_mci_rockchip_prepare_command,
 369         .set_ios                = dw_mci_rockchip_set_ios,
 370         .parse_dt               = dw_mci_rockchip_parse_dt,
 371         .execute_tuning         = dw_mci_rockchip_execute_tuning,
 372 };
 373
 374 static const struct of_device_id dw_mci_rockchip_match[] = {
 375         { .compatible = "rockchip,rk_mmc",
 376                         .data = &rockchip_drv_data, },
 377         { /* Sentinel */},
 378 };
 379 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 380
 381 static int dw_mci_rockchip_probe(struct platform_device *pdev)
 382 {
 383         const struct dw_mci_drv_data *drv_data;
 384         const struct of_device_id *match;
 385
 386         match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 387         drv_data = match->data;
 388         return dw_mci_pltfm_register(pdev, drv_data);
 389 }
 390
 391 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 392         .probe          = dw_mci_rockchip_probe,
 393         .remove         = __exit_p(dw_mci_pltfm_remove),
 394         .driver         = {
 395                 .name           = "dwmmc_rockchip",
 396                 .of_match_table = dw_mci_rockchip_match,
 397                 .pm             = &dw_mci_pltfm_pmops,
 398         },
 399 };
 400
 401 module_platform_driver(dw_mci_rockchip_pltfm_driver);
 402
 403 MODULE_DESCRIPTION("Rockchip Specific DW-SDMMC Driver Extension");
 404 MODULE_AUTHOR("Shawn Lin <lintao@rock-chips.com>");
 405 MODULE_AUTHOR("Bangwang Xie <xbw@rock-chips.com>");
 406 MODULE_LICENSE("GPL v2");
 407 MODULE_ALIAS("platform:dwmmc-rockchip");