2 * Rockchip Specific Extensions for Synopsys DW Multimedia Card Interface driver
4 * Copyright (C) 2014, Rockchip Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/mmc.h>
17 #include <linux/mmc/rk_mmc.h>
19 #include <linux/of_gpio.h>
20 #include <linux/slab.h>
21 #include <linux/rockchip/cpu.h>
24 #include "dw_mmc-pltfm.h"
25 #include "../../clk/rockchip/clk-ops.h"
27 #include "rk_sdmmc_of.h"
31 * sdmmc,sdio0,sdio1,emmc id=0~3
32 * cclk_in_drv, cclk_in_sample i=0,1
34 #define CRU_SDMMC_CON(id, tuning_type) (0x200 + ((id) * 8) + ((tuning_type) * 4))
36 #define MAX_DELAY_LINE (0xff)
37 #define FREQ_REF_150MHZ (150000000)
38 #define PRECISE_ADJUST (0)
40 #define SDMMC_TUNING_SEL(tuning_type) ( tuning_type? 10:11 )
41 #define SDMMC_TUNING_DELAYNUM(tuning_type) ( tuning_type? 2:3 )
42 #define SDMMC_TUNING_DEGREE(tuning_type) ( tuning_type? 0:1 )
43 #define SDMMC_TUNING_INIT_STATE (0)
46 SDMMC_SHIFT_DEGREE_0 = 0,
47 SDMMC_SHIFT_DEGREE_90,
48 SDMMC_SHIFT_DEGREE_180,
49 SDMMC_SHIFT_DEGREE_270,
50 SDMMC_SHIFT_DEGREE_INVALID,
53 const char *phase_desc[SDMMC_SHIFT_DEGREE_INVALID + 1] = {
54 "SDMMC_SHIFT_DEGREE_0",
55 "SDMMC_SHIFT_DEGREE_90",
56 "SDMMC_SHIFT_DEGREE_180",
57 "SDMMC_SHIFT_DEGREE_270",
58 "SDMMC_SHIFT_DEGREE_INVALID",
62 USE_CLK_AFTER_PHASE = 0,
63 USE_CLK_AFTER_PHASE_AND_DELAY_LINE = 1,
66 /* Variations in Rockchip specific dw-mshc controller */
67 enum dw_mci_rockchip_type {
72 /* Rockchip implementation specific driver private data */
73 struct dw_mci_rockchip_priv_data {
74 enum dw_mci_rockchip_type ctrl_type;
81 static struct dw_mci_rockchip_compatible {
83 enum dw_mci_rockchip_type ctrl_type;
84 } rockchip_compat[] = {
86 .compatible = "rockchip,rk31xx-sdmmc",
87 .ctrl_type = DW_MCI_TYPE_RK3188,
89 .compatible = "rockchip,rk32xx-sdmmc",
90 .ctrl_type = DW_MCI_TYPE_RK3288,
94 static int dw_mci_rockchip_priv_init(struct dw_mci *host)
96 struct dw_mci_rockchip_priv_data *priv;
99 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
101 dev_err(host->dev, "mem alloc failed for private data\n");
105 for (idx = 0; idx < ARRAY_SIZE(rockchip_compat); idx++) {
106 if (of_device_is_compatible(host->dev->of_node,
107 rockchip_compat[idx].compatible))
108 priv->ctrl_type = rockchip_compat[idx].ctrl_type;
115 static int dw_mci_rockchip_setup_clock(struct dw_mci *host)
117 struct dw_mci_rockchip_priv_data *priv = host->priv;
119 if (priv->ctrl_type == DW_MCI_TYPE_RK3288)
120 host->bus_hz /= (priv->ciu_div + 1);
125 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
127 // if (SDMMC_CLKSEL_GET_DRV_WD3(mci_readl(host, CLKSEL)))
128 // *cmdr |= SDMMC_CMD_USE_HOLD_REG;
131 static void dw_mci_rockchip_set_ios(struct dw_mci *host, struct mmc_ios *ios)
136 static int dw_mci_rockchip_parse_dt(struct dw_mci *host)
140 static inline u8 dw_mci_rockchip_get_delaynum(struct dw_mci *host, u8 con_id, u8 tuning_type)
145 regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
146 delaynum = ((regs>>SDMMC_TUNING_DELAYNUM(tuning_type)) & 0xff);
151 static inline void dw_mci_rockchip_set_delaynum(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 delaynum)
154 regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
155 regs &= ~( 0xff << SDMMC_TUNING_DELAYNUM(tuning_type));
156 regs |= (delaynum << SDMMC_TUNING_DELAYNUM(tuning_type));
157 regs |= (0xff << (SDMMC_TUNING_DELAYNUM(tuning_type)+16));
159 MMC_DBG_INFO_FUNC(host->mmc,"tuning_result[delayline]: con_id = %d, tuning_type = %d, CRU_CON = 0x%x. [%s]",
160 con_id, tuning_type, regs, mmc_hostname(host->mmc));
162 cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
165 static inline void dw_mci_rockchip_set_degree(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 phase)
169 regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type));
170 regs &= ~( 0x3 << SDMMC_TUNING_DEGREE(tuning_type));
171 regs |= (phase << SDMMC_TUNING_DEGREE(tuning_type));
172 regs |= (0x3 << (SDMMC_TUNING_DEGREE(tuning_type)+16));
174 MMC_DBG_INFO_FUNC(host->mmc,"tuning_result[phase]: con_id = %d, tuning_type= %d, CRU_CON = 0x%x. [%s]",
175 con_id, tuning_type, regs, mmc_hostname(host->mmc));
177 cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
180 static inline void dw_mci_rockchip_turning_sel(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 mode)
183 regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type)) ;
184 regs &= ~( 0x1 << SDMMC_TUNING_SEL(tuning_type));
185 regs |= (mode << SDMMC_TUNING_SEL(tuning_type));
186 regs |= (0x1 << (SDMMC_TUNING_SEL(tuning_type)+16));
188 MMC_DBG_INFO_FUNC(host->mmc,"tuning_sel: con_id = %d, tuning_type = %d, CRU_CON = 0x%x. [%s]",
189 con_id, tuning_type, regs, mmc_hostname(host->mmc));
191 cru_writel(regs, CRU_SDMMC_CON(con_id, tuning_type));
195 static inline u8 dw_mci_rockchip_get_phase(struct dw_mci *host, u8 con_id, u8 tuning_type)
200 static inline u8 dw_mci_rockchip_move_next_clksmpl(struct dw_mci *host, u8 con_id, u8 tuning_type, u8 val)
204 regs = cru_readl(CRU_SDMMC_CON(con_id, tuning_type)) ;
207 val = ((regs>>SDMMC_TUNING_DELAYNUM(tuning_type)) & 0xff);
217 static int inline __dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
218 u8 *blk_test, unsigned int blksz)
220 struct dw_mci *host = slot->host;
221 struct mmc_host *mmc = slot->mmc;
222 struct mmc_request mrq = {NULL};
223 struct mmc_command cmd = {0};
224 struct mmc_command stop = {0};
225 struct mmc_data data = {0};
226 struct scatterlist sg;
230 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
231 stop.opcode = MMC_STOP_TRANSMISSION;
233 stop.flags = MMC_RSP_R1B | MMC_CMD_AC;
236 data.flags = MMC_DATA_READ;
240 sg_init_one(&sg, blk_test, blksz);
245 mci_writel(host, TMOUT, ~0);
247 mmc_wait_for_req(mmc, &mrq);
248 if(!cmd.error && !data.error){
252 "Tuning error: cmd.error:%d, data.error:%d\n",cmd.error, data.error);
259 static int dw_mci_rockchip_execute_tuning(struct dw_mci_slot *slot, u32 opcode,
260 struct dw_mci_tuning_data *tuning_data)
263 struct dw_mci *host = slot->host;
265 u8 candidates_delayline[MAX_DELAY_LINE] = {0};
266 u8 candidates_degree[SDMMC_SHIFT_DEGREE_INVALID] = {4,4,4,4};
269 u32 start_delayline = 0;
270 const u8 *blk_pattern = tuning_data->blk_pattern;
274 unsigned int blksz = tuning_data->blksz;
276 MMC_DBG_INFO_FUNC(host->mmc,"execute tuning: [%s]", mmc_hostname(host->mmc));
278 blk_test = kmalloc(blksz, GFP_KERNEL);
281 MMC_DBG_ERR_FUNC(host->mmc,"execute tuning: blk_test kmalloc failed[%s]",
282 mmc_hostname(host->mmc));
286 /* Select use delay line*/
287 dw_mci_rockchip_turning_sel(host, tuning_data->con_id, tuning_data->tuning_type,
288 USE_CLK_AFTER_PHASE_AND_DELAY_LINE);
290 /* For RK32XX signoff 150M clk, 1 cycle = 6.66ns , and 1/4 phase = 1.66ns.
291 Netlist level sample LT: 10.531ns / 42.126ps WC: 19.695ns / 76.936ps.
292 So we take average --- 60ps, (1.66ns/ 2) = 0.83(middle-value),TAKE 0.9
293 0.9 / 60ps = 15 delayline
296 ref = ((FREQ_REF_150MHZ + host->bus_hz - 1) / host->bus_hz);
299 if(step > MAX_DELAY_LINE){
300 step = MAX_DELAY_LINE;
301 MMC_DBG_WARN_FUNC(host->mmc,
302 "execute tuning: TOO LARGE STEP![%s]", mmc_hostname(host->mmc));
304 MMC_DBG_INFO_FUNC(host->mmc,
305 "execute tuning: SOC is RK3288, ref = %d, step = %d[%s]",
306 ref, step, mmc_hostname(host->mmc));
309 step = (15 * ((FREQ_REF_150MHZ / host->bus_hz) * 100)) / 100;
311 if(step > MAX_DELAY_LINE){
312 step = MAX_DELAY_LINE;
313 MMC_DBG_WARN_FUNC(host->mmc,
314 "execute tuning: TOO LARGE STEP![%s]", mmc_hostname(host->mmc));
316 MMC_DBG_INFO_FUNC(host->mmc,
317 "execute tuning: SOC is UNKNOWN, step = %d[%s]",
318 step, mmc_hostname(host->mmc));
321 /* Loop degree from 0 ~ 270 */
322 for(start_degree = SDMMC_SHIFT_DEGREE_0; start_degree < SDMMC_SHIFT_DEGREE_270; start_degree++){
324 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, start_degree);
325 if(0 == __dw_mci_rockchip_execute_tuning(slot, opcode, blk_test, blksz)){
326 if(!memcmp(blk_pattern, blk_test, blksz)){
327 /* Successfully tuning in this condition*/
328 candidates_degree[index] = start_degree;
335 MMC_DBG_INFO_FUNC(host->mmc,"\n execute tuning: candidates_degree = %s \t%s \t%s \t%s[%s]",
336 phase_desc[candidates_degree[0]], phase_desc[candidates_degree[1]],
337 phase_desc[candidates_degree[2]], phase_desc[candidates_degree[3]],
338 mmc_hostname(host->mmc));
341 if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_0)
342 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_90)
343 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_180)){
345 MMC_DBG_INFO_FUNC(host->mmc,
346 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_90 [%s]",
347 mmc_hostname(host->mmc));
349 dw_mci_rockchip_set_degree(host, tuning_data->con_id,
350 tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
353 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
354 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_180)
355 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_270)){
356 MMC_DBG_INFO_FUNC(host->mmc,
357 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_180 [%s]",
358 mmc_hostname(host->mmc));
359 dw_mci_rockchip_set_degree(host, tuning_data->con_id,
360 tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
363 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_0)
364 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_90)
365 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_INVALID)){
367 MMC_DBG_INFO_FUNC(host->mmc,
368 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_0 ~ SDMMC_SHIFT_DEGREE_90[%s]",
369 mmc_hostname(host->mmc));
371 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
375 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
379 }else if((candidates_degree[0]==SDMMC_SHIFT_DEGREE_0)
380 && (candidates_degree[1]==SDMMC_SHIFT_DEGREE_180)){
382 MMC_DBG_INFO_FUNC(host->mmc,
383 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_0 AND SDMMC_SHIFT_DEGREE_180[%s]",
384 mmc_hostname(host->mmc));
386 /* FixMe: NO sense any signal indicator make this case happen*/
387 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
389 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
390 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_180)
391 && (candidates_degree[2] == SDMMC_SHIFT_DEGREE_INVALID)){
393 MMC_DBG_INFO_FUNC(host->mmc,
394 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_90 ~ SDMMC_SHIFT_DEGREE_180[%s]",
395 mmc_hostname(host->mmc));
397 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
401 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
405 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_180)
406 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_270)){
408 MMC_DBG_INFO_FUNC(host->mmc,
409 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_180 ~ SDMMC_SHIFT_DEGREE_270[%s]",
410 mmc_hostname(host->mmc));
412 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
416 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
420 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_180)
421 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_INVALID)){
423 MMC_DBG_INFO_FUNC(host->mmc,
424 "execute tuning: candidates_degree = [SDMMC_SHIFT_DEGREE_90 + n ~ SDMMC_SHIFT_DEGREE_180][%s]",
425 mmc_hostname(host->mmc));
427 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_90);
431 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
435 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_90)
436 && (candidates_degree[1] == SDMMC_SHIFT_DEGREE_INVALID)){
438 MMC_DBG_INFO_FUNC(host->mmc,
439 "execute tuning: candidates_degree = [SDMMC_SHIFT_DEGREE_0 + n ~ SDMMC_SHIFT_DEGREE_90][%s]",
440 mmc_hostname(host->mmc));
442 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_0);
446 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
450 }else if((candidates_degree[0] == SDMMC_SHIFT_DEGREE_270)){
452 MMC_DBG_INFO_FUNC(host->mmc,
453 "execute tuning: candidates_degree = SDMMC_SHIFT_DEGREE_270 [%s]",
454 mmc_hostname(host->mmc));
456 /*FixME: so urgly signal indicator, HW engineer help!*/
458 dw_mci_rockchip_set_degree(host, tuning_data->con_id, tuning_data->tuning_type, SDMMC_SHIFT_DEGREE_180);
462 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id, tuning_data->tuning_type, step);
467 MMC_DBG_ERR_FUNC(host->mmc,
468 "execute tuning: candidates_degree beyong limited case! [%s]",
469 mmc_hostname(host->mmc));
475 for(start_delayline = 0; start_delayline <= MAX_DELAY_LINE; start_delayline += step){
477 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id,
478 tuning_data->tuning_type, start_delayline);
479 if(0 == __dw_mci_rockchip_execute_tuning(slot, opcode, blk_test, blksz)){
480 if(!memcmp(blk_pattern, blk_test, blksz)){
481 /* Successfully tuning in this condition*/
482 candidates_delayline[index] = start_delayline;
487 if((index < 2) && (index != 0)) {
488 MMC_DBG_INFO_FUNC(host->mmc,
489 "execute tuning: candidates_delayline failed for only one element [%s]",
490 mmc_hostname(host->mmc));
492 /* Make step smaller, and re-calculate */
496 }else if(index >= 2){
498 MMC_DBG_INFO_FUNC(host->mmc,
499 "execute tuning: candidates_delayline calculate successfully [%s]",
500 mmc_hostname(host->mmc));
502 dw_mci_rockchip_set_delaynum(host, tuning_data->con_id,
503 tuning_data->tuning_type, candidates_delayline[index/2]);
515 /* Common capabilities of RK32XX SoC */
516 static unsigned long rockchip_dwmmc_caps[4] = {
523 unsigned int rockchip_dwmmc_hold_reg[4] = {1,0,0,0};
525 static const struct dw_mci_drv_data rockchip_drv_data = {
526 .caps = rockchip_dwmmc_caps,
527 .hold_reg_flag = rockchip_dwmmc_hold_reg,
528 .init = dw_mci_rockchip_priv_init,
529 .setup_clock = dw_mci_rockchip_setup_clock,
530 .prepare_command = dw_mci_rockchip_prepare_command,
531 .set_ios = dw_mci_rockchip_set_ios,
532 .parse_dt = dw_mci_rockchip_parse_dt,
533 .execute_tuning = dw_mci_rockchip_execute_tuning,
536 static const struct of_device_id dw_mci_rockchip_match[] = {
537 { .compatible = "rockchip,rk_mmc",
538 .data = &rockchip_drv_data, },
541 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
544 extern void rockchip_mmc_of_probe(struct device_node *np,struct rk_sdmmc_of *mmc_property);
547 static int dw_mci_rockchip_probe(struct platform_device *pdev)
549 const struct dw_mci_drv_data *drv_data;
550 const struct of_device_id *match;
553 struct device_node *np = pdev->dev.of_node;
554 struct rk_sdmmc_of *rk_mmc_property = NULL;
556 rk_mmc_property = (struct rk_sdmmc_of *)kmalloc(sizeof(struct rk_sdmmc_of),GFP_KERNEL);
557 if(NULL == rk_mmc_property)
559 kfree(rk_mmc_property);
560 rk_mmc_property = NULL;
561 printk("rk_mmc_property malloc space failed!\n");
565 rockchip_mmc_of_probe(np,rk_mmc_property);
566 #endif /*DW_MMC_OF_PROBE*/
569 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
570 drv_data = match->data;
571 return dw_mci_pltfm_register(pdev, drv_data);
574 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
575 .probe = dw_mci_rockchip_probe,
576 .remove = __exit_p(dw_mci_pltfm_remove),
578 .name = "dwmmc_rockchip",
579 .of_match_table = dw_mci_rockchip_match,
580 .pm = &dw_mci_pltfm_pmops,
584 module_platform_driver(dw_mci_rockchip_pltfm_driver);
586 MODULE_DESCRIPTION("Rockchip Specific DW-SDMMC Driver Extension");
587 MODULE_AUTHOR("Bangwang Xie < xbw@rock-chips.com>");
588 MODULE_LICENSE("GPL v2");
589 MODULE_ALIAS("platform:dwmmc-rockchip");