3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef _MEI_HW_TYPES_H_
18 #define _MEI_HW_TYPES_H_
20 #include <linux/uuid.h>
25 #define MEI_INTEROP_TIMEOUT 7 /* Timeout on ready message */
26 #define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */
28 #define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */
29 #define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout */
31 #define MEI_IAMTHIF_STALL_TIMER 12 /* HPS */
32 #define MEI_IAMTHIF_READ_TIMER 10 /* HPS */
38 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
39 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
40 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
41 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
43 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
44 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
46 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
47 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
48 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
49 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
50 #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
52 #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
53 #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
54 #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
55 #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
56 #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
58 #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
59 #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
60 #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
61 #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
63 #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
64 #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
65 #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
66 #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
68 #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
69 #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
71 #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
72 #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */
74 #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
75 #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
76 #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
78 #define MEI_DEV_ID_LPT 0x8C3A /* Lynx Point */
79 #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */
85 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */
87 /* H_CSR - Host Control Status register */
89 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
91 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
95 /* register bits of H_CSR (Host Control Status register) */
96 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
97 #define H_CBD 0xFF000000
98 /* Host Circular Buffer Write Pointer */
99 #define H_CBWP 0x00FF0000
100 /* Host Circular Buffer Read Pointer */
101 #define H_CBRP 0x0000FF00
103 #define H_RST 0x00000010
105 #define H_RDY 0x00000008
106 /* Host Interrupt Generate */
107 #define H_IG 0x00000004
108 /* Host Interrupt Status */
109 #define H_IS 0x00000002
110 /* Host Interrupt Enable */
111 #define H_IE 0x00000001
114 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */
115 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
117 #define ME_CBD_HRA 0xFF000000
118 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
119 #define ME_CBWP_HRA 0x00FF0000
120 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
121 #define ME_CBRP_HRA 0x0000FF00
122 /* ME Reset HRA - host read only access to ME_RST */
123 #define ME_RST_HRA 0x00000010
124 /* ME Ready HRA - host read only access to ME_RDY */
125 #define ME_RDY_HRA 0x00000008
126 /* ME Interrupt Generate HRA - host read only access to ME_IG */
127 #define ME_IG_HRA 0x00000004
128 /* ME Interrupt Status HRA - host read only access to ME_IS */
129 #define ME_IS_HRA 0x00000002
130 /* ME Interrupt Enable HRA - host read only access to ME_IE */
131 #define ME_IE_HRA 0x00000001
136 #define HBM_MINOR_VERSION 0
137 #define HBM_MAJOR_VERSION 1
138 #define HBM_TIMEOUT 1 /* 1 second */
140 /* Host bus message command opcode */
141 #define MEI_HBM_CMD_OP_MSK 0x7f
142 /* Host bus message command RESPONSE */
143 #define MEI_HBM_CMD_RES_MSK 0x80
146 * MEI Bus Message Command IDs
148 #define HOST_START_REQ_CMD 0x01
149 #define HOST_START_RES_CMD 0x81
151 #define HOST_STOP_REQ_CMD 0x02
152 #define HOST_STOP_RES_CMD 0x82
154 #define ME_STOP_REQ_CMD 0x03
156 #define HOST_ENUM_REQ_CMD 0x04
157 #define HOST_ENUM_RES_CMD 0x84
159 #define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
160 #define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
162 #define CLIENT_CONNECT_REQ_CMD 0x06
163 #define CLIENT_CONNECT_RES_CMD 0x86
165 #define CLIENT_DISCONNECT_REQ_CMD 0x07
166 #define CLIENT_DISCONNECT_RES_CMD 0x87
168 #define MEI_FLOW_CONTROL_CMD 0x08
172 * used by hbm_host_stop_request.reason
174 enum mei_stop_reason_types {
175 DRIVER_STOP_REQUEST = 0x00,
176 DEVICE_D1_ENTRY = 0x01,
177 DEVICE_D2_ENTRY = 0x02,
178 DEVICE_D3_ENTRY = 0x03,
179 SYSTEM_S1_ENTRY = 0x04,
180 SYSTEM_S2_ENTRY = 0x05,
181 SYSTEM_S3_ENTRY = 0x06,
182 SYSTEM_S4_ENTRY = 0x07,
183 SYSTEM_S5_ENTRY = 0x08
187 * Client Connect Status
188 * used by hbm_client_connect_response.status
190 enum client_connect_status_types {
192 CCS_NOT_FOUND = 0x01,
193 CCS_ALREADY_STARTED = 0x02,
194 CCS_OUT_OF_RESOURCES = 0x03,
195 CCS_MESSAGE_SMALL = 0x04
199 * Client Disconnect Status
201 enum client_disconnect_status_types {
206 * MEI BUS Interface Section
217 struct mei_bus_message {
227 struct hbm_host_version_request {
230 struct hbm_version host_version;
233 struct hbm_host_version_response {
235 u8 host_version_supported;
236 struct hbm_version me_max_version;
239 struct hbm_host_stop_request {
245 struct hbm_host_stop_response {
250 struct hbm_me_stop_request {
256 struct hbm_host_enum_request {
261 struct hbm_host_enum_response {
264 u8 valid_addresses[32];
267 struct mei_client_properties {
268 uuid_le protocol_name;
270 u8 max_number_of_connections;
276 struct hbm_props_request {
283 struct hbm_props_response {
288 struct mei_client_properties client_properties;
292 * struct hbm_client_connect_request - connect/disconnect request
294 * @hbm_cmd - bus message command header
295 * @me_addr - address of the client in ME
296 * @host_addr - address of the client in the driver
299 struct hbm_client_connect_request {
307 * struct hbm_client_connect_response - connect/disconnect response
309 * @hbm_cmd - bus message command header
310 * @me_addr - address of the client in ME
311 * @host_addr - address of the client in the driver
312 * @status - status of the request
314 struct hbm_client_connect_response {
322 #define MEI_FC_MESSAGE_RESERVED_LENGTH 5
324 struct hbm_flow_control {
328 u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
331 struct mei_me_client {
332 struct mei_client_properties props;
334 u8 mei_flow_ctrl_creds;