drivers/mfd/wm831x-irq.c

   1 /*
   2  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
   3  *
   4  * Copyright 2009 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <linux/mfd/wm831x/core.h>
  23 #include <linux/mfd/wm831x/pdata.h>
  24 #include <linux/mfd/wm831x/gpio.h>
  25 #include <linux/mfd/wm831x/irq.h>
  26
  27 #include <linux/delay.h>
  28 <<<<<<< HEAD
  29 =======
  30 #include <linux/wakelock.h>
  31 /*
  32  * Since generic IRQs don't currently support interrupt controllers on
  33  * interrupt driven buses we don't use genirq but instead provide an
  34  * interface that looks very much like the standard ones.  This leads
  35  * to some bodges, including storing interrupt handler information in
  36  * the static irq_data table we use to look up the data for individual
  37  * interrupts, but hopefully won't last too long.
  38  */
  39 #define WM831X_IRQ_TYPE IRQF_TRIGGER_LOW
  40 >>>>>>> parent of 15f7fab... temp revert rk change
  41
  42 struct wm831x_irq_data {
  43         int primary;
  44         int reg;
  45         int mask;
  46 };
  47
  48 struct wm831x_handle_irq
  49 {
  50         int irq;
  51         struct list_head        queue;
  52 };
  53
  54 static struct wm831x_irq_data wm831x_irqs[] = {
  55         [WM831X_IRQ_TEMP_THW] = {
  56                 .primary = WM831X_TEMP_INT,
  57                 .reg = 1,
  58                 .mask = WM831X_TEMP_THW_EINT,
  59         },
  60         [WM831X_IRQ_GPIO_1] = {
  61                 .primary = WM831X_GP_INT,
  62                 .reg = 5,
  63                 .mask = WM831X_GP1_EINT,
  64         },
  65         [WM831X_IRQ_GPIO_2] = {
  66                 .primary = WM831X_GP_INT,
  67                 .reg = 5,
  68                 .mask = WM831X_GP2_EINT,
  69         },
  70         [WM831X_IRQ_GPIO_3] = {
  71                 .primary = WM831X_GP_INT,
  72                 .reg = 5,
  73                 .mask = WM831X_GP3_EINT,
  74         },
  75         [WM831X_IRQ_GPIO_4] = {
  76                 .primary = WM831X_GP_INT,
  77                 .reg = 5,
  78                 .mask = WM831X_GP4_EINT,
  79         },
  80         [WM831X_IRQ_GPIO_5] = {
  81                 .primary = WM831X_GP_INT,
  82                 .reg = 5,
  83                 .mask = WM831X_GP5_EINT,
  84         },
  85         [WM831X_IRQ_GPIO_6] = {
  86                 .primary = WM831X_GP_INT,
  87                 .reg = 5,
  88                 .mask = WM831X_GP6_EINT,
  89         },
  90         [WM831X_IRQ_GPIO_7] = {
  91                 .primary = WM831X_GP_INT,
  92                 .reg = 5,
  93                 .mask = WM831X_GP7_EINT,
  94         },
  95         [WM831X_IRQ_GPIO_8] = {
  96                 .primary = WM831X_GP_INT,
  97                 .reg = 5,
  98                 .mask = WM831X_GP8_EINT,
  99         },
 100         [WM831X_IRQ_GPIO_9] = {
 101                 .primary = WM831X_GP_INT,
 102                 .reg = 5,
 103                 .mask = WM831X_GP9_EINT,
 104         },
 105         [WM831X_IRQ_GPIO_10] = {
 106                 .primary = WM831X_GP_INT,
 107                 .reg = 5,
 108                 .mask = WM831X_GP10_EINT,
 109         },
 110         [WM831X_IRQ_GPIO_11] = {
 111                 .primary = WM831X_GP_INT,
 112                 .reg = 5,
 113                 .mask = WM831X_GP11_EINT,
 114         },
 115         [WM831X_IRQ_GPIO_12] = {
 116                 .primary = WM831X_GP_INT,
 117                 .reg = 5,
 118                 .mask = WM831X_GP12_EINT,
 119         },
 120         [WM831X_IRQ_GPIO_13] = {
 121                 .primary = WM831X_GP_INT,
 122                 .reg = 5,
 123                 .mask = WM831X_GP13_EINT,
 124         },
 125         [WM831X_IRQ_GPIO_14] = {
 126                 .primary = WM831X_GP_INT,
 127                 .reg = 5,
 128                 .mask = WM831X_GP14_EINT,
 129         },
 130         [WM831X_IRQ_GPIO_15] = {
 131                 .primary = WM831X_GP_INT,
 132                 .reg = 5,
 133                 .mask = WM831X_GP15_EINT,
 134         },
 135         [WM831X_IRQ_GPIO_16] = {
 136                 .primary = WM831X_GP_INT,
 137                 .reg = 5,
 138                 .mask = WM831X_GP16_EINT,
 139         },
 140         [WM831X_IRQ_ON] = {
 141                 .primary = WM831X_ON_PIN_INT,
 142                 .reg = 1,
 143                 .mask = WM831X_ON_PIN_EINT,
 144         },
 145         [WM831X_IRQ_PPM_SYSLO] = {
 146                 .primary = WM831X_PPM_INT,
 147                 .reg = 1,
 148                 .mask = WM831X_PPM_SYSLO_EINT,
 149         },
 150         [WM831X_IRQ_PPM_PWR_SRC] = {
 151                 .primary = WM831X_PPM_INT,
 152                 .reg = 1,
 153                 .mask = WM831X_PPM_PWR_SRC_EINT,
 154         },
 155         [WM831X_IRQ_PPM_USB_CURR] = {
 156                 .primary = WM831X_PPM_INT,
 157                 .reg = 1,
 158                 .mask = WM831X_PPM_USB_CURR_EINT,
 159         },
 160         [WM831X_IRQ_WDOG_TO] = {
 161                 .primary = WM831X_WDOG_INT,
 162                 .reg = 1,
 163                 .mask = WM831X_WDOG_TO_EINT,
 164         },
 165         [WM831X_IRQ_RTC_PER] = {
 166                 .primary = WM831X_RTC_INT,
 167                 .reg = 1,
 168                 .mask = WM831X_RTC_PER_EINT,
 169         },
 170         [WM831X_IRQ_RTC_ALM] = {
 171                 .primary = WM831X_RTC_INT,
 172                 .reg = 1,
 173                 .mask = WM831X_RTC_ALM_EINT,
 174         },
 175         [WM831X_IRQ_CHG_BATT_HOT] = {
 176                 .primary = WM831X_CHG_INT,
 177                 .reg = 2,
 178                 .mask = WM831X_CHG_BATT_HOT_EINT,
 179         },
 180         [WM831X_IRQ_CHG_BATT_COLD] = {
 181                 .primary = WM831X_CHG_INT,
 182                 .reg = 2,
 183                 .mask = WM831X_CHG_BATT_COLD_EINT,
 184         },
 185         [WM831X_IRQ_CHG_BATT_FAIL] = {
 186                 .primary = WM831X_CHG_INT,
 187                 .reg = 2,
 188                 .mask = WM831X_CHG_BATT_FAIL_EINT,
 189         },
 190         [WM831X_IRQ_CHG_OV] = {
 191                 .primary = WM831X_CHG_INT,
 192                 .reg = 2,
 193                 .mask = WM831X_CHG_OV_EINT,
 194         },
 195         [WM831X_IRQ_CHG_END] = {
 196                 .primary = WM831X_CHG_INT,
 197                 .reg = 2,
 198                 .mask = WM831X_CHG_END_EINT,
 199         },
 200         [WM831X_IRQ_CHG_TO] = {
 201                 .primary = WM831X_CHG_INT,
 202                 .reg = 2,
 203                 .mask = WM831X_CHG_TO_EINT,
 204         },
 205         [WM831X_IRQ_CHG_MODE] = {
 206                 .primary = WM831X_CHG_INT,
 207                 .reg = 2,
 208                 .mask = WM831X_CHG_MODE_EINT,
 209         },
 210         [WM831X_IRQ_CHG_START] = {
 211                 .primary = WM831X_CHG_INT,
 212                 .reg = 2,
 213                 .mask = WM831X_CHG_START_EINT,
 214         },
 215         [WM831X_IRQ_TCHDATA] = {
 216                 .primary = WM831X_TCHDATA_INT,
 217                 .reg = 1,
 218                 .mask = WM831X_TCHDATA_EINT,
 219         },
 220         [WM831X_IRQ_TCHPD] = {
 221                 .primary = WM831X_TCHPD_INT,
 222                 .reg = 1,
 223                 .mask = WM831X_TCHPD_EINT,
 224         },
 225         [WM831X_IRQ_AUXADC_DATA] = {
 226                 .primary = WM831X_AUXADC_INT,
 227                 .reg = 1,
 228                 .mask = WM831X_AUXADC_DATA_EINT,
 229         },
 230         [WM831X_IRQ_AUXADC_DCOMP1] = {
 231                 .primary = WM831X_AUXADC_INT,
 232                 .reg = 1,
 233                 .mask = WM831X_AUXADC_DCOMP1_EINT,
 234         },
 235         [WM831X_IRQ_AUXADC_DCOMP2] = {
 236                 .primary = WM831X_AUXADC_INT,
 237                 .reg = 1,
 238                 .mask = WM831X_AUXADC_DCOMP2_EINT,
 239         },
 240         [WM831X_IRQ_AUXADC_DCOMP3] = {
 241                 .primary = WM831X_AUXADC_INT,
 242                 .reg = 1,
 243                 .mask = WM831X_AUXADC_DCOMP3_EINT,
 244         },
 245         [WM831X_IRQ_AUXADC_DCOMP4] = {
 246                 .primary = WM831X_AUXADC_INT,
 247                 .reg = 1,
 248                 .mask = WM831X_AUXADC_DCOMP4_EINT,
 249         },
 250         [WM831X_IRQ_CS1] = {
 251                 .primary = WM831X_CS_INT,
 252                 .reg = 2,
 253                 .mask = WM831X_CS1_EINT,
 254         },
 255         [WM831X_IRQ_CS2] = {
 256                 .primary = WM831X_CS_INT,
 257                 .reg = 2,
 258                 .mask = WM831X_CS2_EINT,
 259         },
 260         [WM831X_IRQ_HC_DC1] = {
 261                 .primary = WM831X_HC_INT,
 262                 .reg = 4,
 263                 .mask = WM831X_HC_DC1_EINT,
 264         },
 265         [WM831X_IRQ_HC_DC2] = {
 266                 .primary = WM831X_HC_INT,
 267                 .reg = 4,
 268                 .mask = WM831X_HC_DC2_EINT,
 269         },
 270         [WM831X_IRQ_UV_LDO1] = {
 271                 .primary = WM831X_UV_INT,
 272                 .reg = 3,
 273                 .mask = WM831X_UV_LDO1_EINT,
 274         },
 275         [WM831X_IRQ_UV_LDO2] = {
 276                 .primary = WM831X_UV_INT,
 277                 .reg = 3,
 278                 .mask = WM831X_UV_LDO2_EINT,
 279         },
 280         [WM831X_IRQ_UV_LDO3] = {
 281                 .primary = WM831X_UV_INT,
 282                 .reg = 3,
 283                 .mask = WM831X_UV_LDO3_EINT,
 284         },
 285         [WM831X_IRQ_UV_LDO4] = {
 286                 .primary = WM831X_UV_INT,
 287                 .reg = 3,
 288                 .mask = WM831X_UV_LDO4_EINT,
 289         },
 290         [WM831X_IRQ_UV_LDO5] = {
 291                 .primary = WM831X_UV_INT,
 292                 .reg = 3,
 293                 .mask = WM831X_UV_LDO5_EINT,
 294         },
 295         [WM831X_IRQ_UV_LDO6] = {
 296                 .primary = WM831X_UV_INT,
 297                 .reg = 3,
 298                 .mask = WM831X_UV_LDO6_EINT,
 299         },
 300         [WM831X_IRQ_UV_LDO7] = {
 301                 .primary = WM831X_UV_INT,
 302                 .reg = 3,
 303                 .mask = WM831X_UV_LDO7_EINT,
 304         },
 305         [WM831X_IRQ_UV_LDO8] = {
 306                 .primary = WM831X_UV_INT,
 307                 .reg = 3,
 308                 .mask = WM831X_UV_LDO8_EINT,
 309         },
 310         [WM831X_IRQ_UV_LDO9] = {
 311                 .primary = WM831X_UV_INT,
 312                 .reg = 3,
 313                 .mask = WM831X_UV_LDO9_EINT,
 314         },
 315         [WM831X_IRQ_UV_LDO10] = {
 316                 .primary = WM831X_UV_INT,
 317                 .reg = 3,
 318                 .mask = WM831X_UV_LDO10_EINT,
 319         },
 320         [WM831X_IRQ_UV_DC1] = {
 321                 .primary = WM831X_UV_INT,
 322                 .reg = 4,
 323                 .mask = WM831X_UV_DC1_EINT,
 324         },
 325         [WM831X_IRQ_UV_DC2] = {
 326                 .primary = WM831X_UV_INT,
 327                 .reg = 4,
 328                 .mask = WM831X_UV_DC2_EINT,
 329         },
 330         [WM831X_IRQ_UV_DC3] = {
 331                 .primary = WM831X_UV_INT,
 332                 .reg = 4,
 333                 .mask = WM831X_UV_DC3_EINT,
 334         },
 335         [WM831X_IRQ_UV_DC4] = {
 336                 .primary = WM831X_UV_INT,
 337                 .reg = 4,
 338                 .mask = WM831X_UV_DC4_EINT,
 339         },
 340 };
 341
 342 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
 343 {
 344         return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
 345 }
 346
 347 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
 348 {
 349         return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
 350 }
 351
 352 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
 353                                                         int irq)
 354 {
 355         return &wm831x_irqs[irq - wm831x->irq_base];
 356 }
 357
 358 static void wm831x_irq_lock(struct irq_data *data)
 359 {
 360         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 361
 362         mutex_lock(&wm831x->irq_lock);
 363 }
 364
 365 static void wm831x_irq_sync_unlock(struct irq_data *data)
 366 {
 367         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 368         int i;
 369
 370         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 371                 /* If there's been a change in the mask write it back
 372                  * to the hardware. */
 373                 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
 374                         dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
 375                                 WM831X_INTERRUPT_STATUS_1_MASK + i,
 376                                 wm831x->irq_masks_cur[i]);
 377
 378                         wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
 379                         wm831x_reg_write(wm831x,
 380                                          WM831X_INTERRUPT_STATUS_1_MASK + i,
 381                                          wm831x->irq_masks_cur[i]);
 382                 }
 383         }
 384
 385         mutex_unlock(&wm831x->irq_lock);
 386 }
 387
 388 static void wm831x_irq_enable(struct irq_data *data)
 389 {
 390         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 391         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 392                                                              data->irq);
 393
 394         wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 395         //printk("%s:irq=%d\n",__FUNCTION__,irq);
 396 }
 397
 398 static void wm831x_irq_disable(struct irq_data *data)
 399 {
 400         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 401         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 402                                                              data->irq);
 403
 404         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 405         //printk("%s:irq=%d\n",__FUNCTION__,irq);
 406 }
 407
 408 static void wm831x_irq_disable(unsigned int irq)
 409 {
 410         struct wm831x *wm831x = get_irq_chip_data(irq);
 411         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
 412
 413         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 414         //printk("%s:irq=%d\n",__FUNCTION__,irq);
 415 }
 416
 417 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
 418 {
 419         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 420         int val, irq;
 421
 422 <<<<<<< HEAD
 423         irq = data->irq - wm831x->irq_base;
 424
 425         if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
 426 =======
 427         irq = irq - wm831x->irq_base;
 428         if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_12) {
 429 >>>>>>> parent of 15f7fab... temp revert rk change
 430                 /* Ignore internal-only IRQs */
 431                 if (irq >= 0 && irq < WM831X_NUM_IRQS)
 432                         return 0;
 433                 else
 434                         return -EINVAL;
 435         }
 436         //printk("wm831x_irq_set_type:type=%x,irq=%d\n",type,irq);
 437         switch (type) {
 438         case IRQ_TYPE_EDGE_BOTH:
 439                 val = WM831X_GPN_INT_MODE;
 440                 break;
 441         case IRQ_TYPE_EDGE_RISING:
 442                 val = WM831X_GPN_POL;
 443                 break;
 444         case IRQ_TYPE_EDGE_FALLING:
 445                 val = 0;
 446                 break;
 447         default:
 448                 return -EINVAL;
 449         }
 450
 451         return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + irq - 1,
 452                                WM831X_GPN_INT_MODE | WM831X_GPN_POL, val);
 453 }
 454
 455 static int wm831x_irq_set_wake(unsigned irq, unsigned state)
 456 {
 457         struct wm831x *wm831x = get_irq_chip_data(irq);
 458
 459         //only wm831x irq
 460         if ((irq > wm831x->irq_base + WM831X_IRQ_TEMP_THW) &&( irq < wm831x->irq_base + WM831X_NUM_IRQS))
 461         {
 462                 if(state)
 463                 wm831x_irq_unmask(irq);
 464                 else
 465                 wm831x_irq_mask(irq);
 466                 return 0;
 467         }
 468         else
 469         {
 470                 printk("%s:irq number err!irq=%d\n",__FUNCTION__,irq);
 471                 return -EINVAL;
 472         }
 473
 474
 475 }
 476
 477 static struct irq_chip wm831x_irq_chip = {
 478 <<<<<<< HEAD
 479         .name                   = "wm831x",
 480         .irq_bus_lock           = wm831x_irq_lock,
 481         .irq_bus_sync_unlock    = wm831x_irq_sync_unlock,
 482         .irq_disable            = wm831x_irq_disable,
 483         .irq_enable             = wm831x_irq_enable,
 484         .irq_set_type           = wm831x_irq_set_type,
 485 =======
 486         .name = "wm831x",
 487         .bus_lock = wm831x_irq_lock,
 488         .bus_sync_unlock = wm831x_irq_sync_unlock,
 489         .disable = wm831x_irq_disable,
 490         .mask = wm831x_irq_mask,
 491         .unmask = wm831x_irq_unmask,
 492         .set_type = wm831x_irq_set_type,
 493         .set_wake       = wm831x_irq_set_wake,
 494 >>>>>>> parent of 15f7fab... temp revert rk change
 495 };
 496
 497 #if WM831X_IRQ_LIST
 498 static void wm831x_handle_worker(struct work_struct *work)
 499 {
 500         struct wm831x *wm831x = container_of(work, struct wm831x, handle_work);
 501         int irq;
 502
 503         while (1) {
 504                 unsigned long flags;
 505                 struct wm831x_handle_irq *hd = NULL;
 506
 507                 spin_lock_irqsave(&wm831x->work_lock, flags);
 508                 if (!list_empty(&wm831x->handle_queue)) {
 509                         hd = list_first_entry(&wm831x->handle_queue, struct wm831x_handle_irq, queue);
 510                         list_del(&hd->queue);
 511                 }
 512                 spin_unlock_irqrestore(&wm831x->work_lock, flags);
 513
 514                 if (!hd)        // trans_queue empty
 515                         break;
 516
 517                 irq = hd->irq;  //get wm831x intterupt status
 518                 //printk("%s:irq=%d\n",__FUNCTION__,irq);
 519
 520                 /*start to handle wm831x intterupt*/
 521                 handle_nested_irq(wm831x->irq_base + irq);
 522
 523                 kfree(hd);
 524
 525         }
 526 }
 527 #endif
 528 /* Main interrupt handling occurs in a workqueue since we need
 529  * interrupts enabled to interact with the chip. */
 530 static void wm831x_irq_worker(struct work_struct *work)
 531 {
 532         struct wm831x *wm831x = container_of(work, struct wm831x, irq_work);
 533         unsigned int i;
 534         int primary;
 535         int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
 536         int read[WM831X_NUM_IRQ_REGS] = { 0 };
 537         int *status;
 538         unsigned long flags;
 539         struct wm831x_handle_irq *hd;
 540         int ret;
 541
 542 #if (WM831X_IRQ_TYPE != IRQF_TRIGGER_LOW)
 543         /*mask wm831x irq at first*/
 544         ret = wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 545                               WM831X_IRQ_IM_MASK, WM831X_IRQ_IM_EANBLE);
 546         if (ret < 0) {
 547                 dev_err(wm831x->dev, "Failed to mask irq: %d\n", ret);
 548                 goto out;
 549         }
 550 #endif
 551
 552         primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
 553         if (primary < 0) {
 554                 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
 555                         primary);
 556                 goto out;
 557         }
 558
 559         mutex_lock(&wm831x->irq_lock);
 560
 561         /* The touch interrupts are visible in the primary register as
 562          * an optimisation; open code this to avoid complicating the
 563          * main handling loop and so we can also skip iterating the
 564          * descriptors.
 565          */
 566         if (primary & WM831X_TCHPD_INT)
 567                 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHPD);
 568         if (primary & WM831X_TCHDATA_INT)
 569                 handle_nested_irq(wm831x->irq_base + WM831X_IRQ_TCHDATA);
 570         if (primary & (WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT))
 571                 goto out;
 572
 573         for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
 574                 int offset = wm831x_irqs[i].reg - 1;
 575
 576                 if (!(primary & wm831x_irqs[i].primary))
 577                         continue;
 578
 579                 status = &status_regs[offset];
 580
 581                 /* Hopefully there should only be one register to read
 582                  * each time otherwise we ought to do a block read. */
 583                 if (!read[offset]) {
 584                         *status = wm831x_reg_read(wm831x,
 585                                      irq_data_to_status_reg(&wm831x_irqs[i]));
 586                         if (*status < 0) {
 587                                 dev_err(wm831x->dev,
 588                                         "Failed to read IRQ status: %d\n",
 589                                         *status);
 590                                 goto out_lock;
 591                         }
 592
 593                         read[offset] = 1;
 594                 }
 595
 596                 /* Report it if it isn't masked, or forget the status. */
 597                 if ((*status & ~wm831x->irq_masks_cur[offset])
 598                     & wm831x_irqs[i].mask)
 599                 {
 600                         #if WM831X_IRQ_LIST
 601                         /*add intterupt handle on list*/
 602                         hd = kzalloc(sizeof(struct wm831x_handle_irq), GFP_KERNEL);
 603                         if (!hd)
 604                         {
 605                                 printk("err:%s:ENOMEM\n",__FUNCTION__);
 606                                 return ;
 607                         }
 608
 609                         if(i == WM831X_IRQ_ON)
 610                         wake_lock(&wm831x->handle_wake);                //keep wake while handle WM831X_IRQ_ON
 611                         hd->irq = i;
 612                         spin_lock_irqsave(&wm831x->work_lock, flags);
 613                         list_add_tail(&hd->queue, &wm831x->handle_queue);
 614                         spin_unlock_irqrestore(&wm831x->work_lock, flags);
 615                         queue_work(wm831x->handle_wq, &wm831x->handle_work);
 616
 617                         #else
 618                         if(i == WM831X_IRQ_ON)
 619                         wake_lock(&wm831x->handle_wake);                //keep wake while handle WM831X_IRQ_ON
 620                         handle_nested_irq(wm831x->irq_base + i);
 621
 622                         #endif
 623                 }
 624
 625                 else
 626                         *status &= ~wm831x_irqs[i].mask;
 627         }
 628
 629 out_lock:
 630         mutex_unlock(&wm831x->irq_lock);
 631
 632 out:
 633         /* Touchscreen interrupts are handled specially in the driver */
 634         status_regs[0] &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);
 635
 636         for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
 637                 if (status_regs[i])
 638                         wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
 639                                          status_regs[i]);
 640         }
 641
 642 #if (WM831X_IRQ_TYPE != IRQF_TRIGGER_LOW)
 643         ret = wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 644                               WM831X_IRQ_IM_MASK, 0);
 645         if (ret < 0) {
 646                 dev_err(wm831x->dev, "Failed to open irq: %d\n", ret);
 647         }
 648 #endif
 649 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 650         enable_irq(wm831x->irq);
 651 #endif
 652         wake_unlock(&wm831x->irq_wake);
 653
 654 }
 655 /* The processing of the primary interrupt occurs in a thread so that
 656  * we can interact with the device over I2C or SPI. */
 657 static irqreturn_t wm831x_irq_thread(int irq, void *data)
 658 {
 659         struct wm831x *wm831x = data;
 660         int msdelay = 0;
 661         /* Shut the interrupt to the CPU up and schedule the actual
 662          * handler; we can't check that the IRQ is asserted. */
 663 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 664         disable_irq_nosync(irq);
 665 #endif
 666         wake_lock(&wm831x->irq_wake);
 667         if(wm831x->flag_suspend)
 668         {
 669                 spin_lock(&wm831x->flag_lock);
 670                 wm831x->flag_suspend = 0;
 671                 spin_unlock(&wm831x->flag_lock);
 672                 msdelay = 50;   //wait for spi/i2c resume
 673                 printk("%s:msdelay=%d\n",__FUNCTION__,msdelay);
 674         }
 675         else
 676                 msdelay = 0;
 677
 678         queue_delayed_work(wm831x->irq_wq, &wm831x->irq_work, msecs_to_jiffies(msdelay));
 679         //printk("%s\n",__FUNCTION__);
 680         return IRQ_HANDLED;
 681 }
 682
 683 int wm831x_irq_init(struct wm831x *wm831x, int irq)
 684 {
 685         struct wm831x_pdata *pdata = wm831x->dev->platform_data;
 686         int i, cur_irq, ret;
 687         printk( "wm831x_irq_init:irq=%d,%d\n",irq,pdata->irq_base);
 688         mutex_init(&wm831x->irq_lock);
 689
 690         /* Mask the individual interrupt sources */
 691         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 692                 wm831x->irq_masks_cur[i] = 0xffff;
 693                 wm831x->irq_masks_cache[i] = 0xffff;
 694                 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
 695                                  0xffff);
 696         }
 697
 698         if (!pdata || !pdata->irq_base) {
 699                 dev_err(wm831x->dev,
 700                         "No interrupt base specified, no interrupts\n");
 701                 return 0;
 702         }
 703
 704 <<<<<<< HEAD
 705         if (pdata->irq_cmos)
 706                 i = 0;
 707         else
 708                 i = WM831X_IRQ_OD;
 709
 710         wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 711                         WM831X_IRQ_OD, i);
 712
 713         /* Try to flag /IRQ as a wake source; there are a number of
 714          * unconditional wake sources in the PMIC so this isn't
 715          * conditional but we don't actually care *too* much if it
 716          * fails.
 717          */
 718         ret = enable_irq_wake(irq);
 719         if (ret != 0) {
 720                 dev_warn(wm831x->dev, "Can't enable IRQ as wake source: %d\n",
 721                          ret);
 722         }
 723
 724 =======
 725         wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq");
 726         if (!wm831x->irq_wq) {
 727                 dev_err(wm831x->dev, "Failed to allocate IRQ worker\n");
 728                 return -ESRCH;
 729         }
 730
 731
 732 >>>>>>> parent of 15f7fab... temp revert rk change
 733         wm831x->irq = irq;
 734         wm831x->flag_suspend = 0;
 735         wm831x->irq_base = pdata->irq_base;
 736         INIT_DELAYED_WORK(&wm831x->irq_work, wm831x_irq_worker);
 737         wake_lock_init(&wm831x->irq_wake, WAKE_LOCK_SUSPEND, "wm831x_irq_wake");
 738         wake_lock_init(&wm831x->handle_wake, WAKE_LOCK_SUSPEND, "wm831x_handle_wake");
 739 #if WM831X_IRQ_LIST
 740         wm831x->handle_wq = create_rt_workqueue("wm831x_handle_wq");
 741         if (!wm831x->handle_wq) {
 742                 printk("cannot create workqueue\n");
 743                 return -EBUSY;
 744         }
 745         INIT_WORK(&wm831x->handle_work, wm831x_handle_worker);
 746         INIT_LIST_HEAD(&wm831x->handle_queue);
 747
 748 #endif
 749
 750         /* Register them with genirq */
 751         for (cur_irq = wm831x->irq_base;
 752              cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
 753              cur_irq++) {
 754                 irq_set_chip_data(cur_irq, wm831x);
 755                 irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
 756                                          handle_edge_irq);
 757                 irq_set_nested_thread(cur_irq, 1);
 758
 759                 /* ARM needs us to explicitly flag the IRQ as valid
 760                  * and will set them noprobe when we do so. */
 761 #ifdef CONFIG_ARM
 762                 set_irq_flags(cur_irq, IRQF_VALID);
 763 #else
 764                 irq_set_noprobe(cur_irq);
 765 #endif
 766         }
 767 <<<<<<< HEAD
 768
 769         if (irq) {
 770                 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
 771                                            IRQF_TRIGGER_LOW | IRQF_ONESHOT,
 772                                            "wm831x", wm831x);
 773                 if (ret != 0) {
 774                         dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 775                                 irq, ret);
 776                         return ret;
 777                 }
 778         } else {
 779                 dev_warn(wm831x->dev,
 780                          "No interrupt specified - functionality limited\n");
 781         }
 782
 783
 784
 785 =======
 786 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 787         ret = request_threaded_irq(wm831x->irq, wm831x_irq_thread, NULL,
 788                                  IRQF_TRIGGER_LOW| IRQF_ONESHOT,//IRQF_TRIGGER_FALLING, //
 789                                    "wm831x", wm831x);
 790 #else
 791         ret = request_threaded_irq(wm831x->irq, wm831x_irq_thread, NULL,
 792                                  IRQF_TRIGGER_FALLING, //IRQF_TRIGGER_LOW| IRQF_ONESHOT,//
 793                                    "wm831x", wm831x);
 794 #endif
 795         if (ret != 0) {
 796                 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 797                         wm831x->irq, ret);
 798                 return ret;
 799         }
 800
 801         enable_irq_wake(wm831x->irq); // so wm831x irq can wake up system
 802 >>>>>>> parent of 15f7fab... temp revert rk change
 803         /* Enable top level interrupts, we mask at secondary level */
 804         wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
 805
 806         return 0;
 807 }
 808
 809 void wm831x_irq_exit(struct wm831x *wm831x)
 810 {
 811         if (wm831x->irq)
 812                 free_irq(wm831x->irq, wm831x);
 813 }