drivers/mfd/wm831x-irq.c

   1 /*
   2  * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
   3  *
   4  * Copyright 2009 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/i2c.h>
  18 #include <linux/irq.h>
  19 #include <linux/mfd/core.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/slab.h>
  22 #include <linux/mfd/wm831x/core.h>
  23 #include <linux/mfd/wm831x/pdata.h>
  24 #include <linux/mfd/wm831x/gpio.h>
  25 #include <linux/mfd/wm831x/irq.h>
  26
  27 #include <linux/delay.h>
  28 #include <linux/wakelock.h>
  29 /*
  30  * Since generic IRQs don't currently support interrupt controllers on
  31  * interrupt driven buses we don't use genirq but instead provide an
  32  * interface that looks very much like the standard ones.  This leads
  33  * to some bodges, including storing interrupt handler information in
  34  * the static irq_data table we use to look up the data for individual
  35  * interrupts, but hopefully won't last too long.
  36  */
  37 #define WM831X_IRQ_TYPE IRQF_TRIGGER_LOW
  38
  39 struct wm831x_irq_data {
  40         int primary;
  41         int reg;
  42         int mask;
  43 };
  44
  45 struct wm831x_handle_irq
  46 {
  47         int irq;
  48         struct list_head        queue;
  49 };
  50
  51 static struct wm831x_irq_data wm831x_irqs[] = {
  52         [WM831X_IRQ_TEMP_THW] = {
  53                 .primary = WM831X_TEMP_INT,
  54                 .reg = 1,
  55                 .mask = WM831X_TEMP_THW_EINT,
  56         },
  57         [WM831X_IRQ_GPIO_1] = {
  58                 .primary = WM831X_GP_INT,
  59                 .reg = 5,
  60                 .mask = WM831X_GP1_EINT,
  61         },
  62         [WM831X_IRQ_GPIO_2] = {
  63                 .primary = WM831X_GP_INT,
  64                 .reg = 5,
  65                 .mask = WM831X_GP2_EINT,
  66         },
  67         [WM831X_IRQ_GPIO_3] = {
  68                 .primary = WM831X_GP_INT,
  69                 .reg = 5,
  70                 .mask = WM831X_GP3_EINT,
  71         },
  72         [WM831X_IRQ_GPIO_4] = {
  73                 .primary = WM831X_GP_INT,
  74                 .reg = 5,
  75                 .mask = WM831X_GP4_EINT,
  76         },
  77         [WM831X_IRQ_GPIO_5] = {
  78                 .primary = WM831X_GP_INT,
  79                 .reg = 5,
  80                 .mask = WM831X_GP5_EINT,
  81         },
  82         [WM831X_IRQ_GPIO_6] = {
  83                 .primary = WM831X_GP_INT,
  84                 .reg = 5,
  85                 .mask = WM831X_GP6_EINT,
  86         },
  87         [WM831X_IRQ_GPIO_7] = {
  88                 .primary = WM831X_GP_INT,
  89                 .reg = 5,
  90                 .mask = WM831X_GP7_EINT,
  91         },
  92         [WM831X_IRQ_GPIO_8] = {
  93                 .primary = WM831X_GP_INT,
  94                 .reg = 5,
  95                 .mask = WM831X_GP8_EINT,
  96         },
  97         [WM831X_IRQ_GPIO_9] = {
  98                 .primary = WM831X_GP_INT,
  99                 .reg = 5,
 100                 .mask = WM831X_GP9_EINT,
 101         },
 102         [WM831X_IRQ_GPIO_10] = {
 103                 .primary = WM831X_GP_INT,
 104                 .reg = 5,
 105                 .mask = WM831X_GP10_EINT,
 106         },
 107         [WM831X_IRQ_GPIO_11] = {
 108                 .primary = WM831X_GP_INT,
 109                 .reg = 5,
 110                 .mask = WM831X_GP11_EINT,
 111         },
 112         [WM831X_IRQ_GPIO_12] = {
 113                 .primary = WM831X_GP_INT,
 114                 .reg = 5,
 115                 .mask = WM831X_GP12_EINT,
 116         },
 117         [WM831X_IRQ_GPIO_13] = {
 118                 .primary = WM831X_GP_INT,
 119                 .reg = 5,
 120                 .mask = WM831X_GP13_EINT,
 121         },
 122         [WM831X_IRQ_GPIO_14] = {
 123                 .primary = WM831X_GP_INT,
 124                 .reg = 5,
 125                 .mask = WM831X_GP14_EINT,
 126         },
 127         [WM831X_IRQ_GPIO_15] = {
 128                 .primary = WM831X_GP_INT,
 129                 .reg = 5,
 130                 .mask = WM831X_GP15_EINT,
 131         },
 132         [WM831X_IRQ_GPIO_16] = {
 133                 .primary = WM831X_GP_INT,
 134                 .reg = 5,
 135                 .mask = WM831X_GP16_EINT,
 136         },
 137         [WM831X_IRQ_ON] = {
 138                 .primary = WM831X_ON_PIN_INT,
 139                 .reg = 1,
 140                 .mask = WM831X_ON_PIN_EINT,
 141         },
 142         [WM831X_IRQ_PPM_SYSLO] = {
 143                 .primary = WM831X_PPM_INT,
 144                 .reg = 1,
 145                 .mask = WM831X_PPM_SYSLO_EINT,
 146         },
 147         [WM831X_IRQ_PPM_PWR_SRC] = {
 148                 .primary = WM831X_PPM_INT,
 149                 .reg = 1,
 150                 .mask = WM831X_PPM_PWR_SRC_EINT,
 151         },
 152         [WM831X_IRQ_PPM_USB_CURR] = {
 153                 .primary = WM831X_PPM_INT,
 154                 .reg = 1,
 155                 .mask = WM831X_PPM_USB_CURR_EINT,
 156         },
 157         [WM831X_IRQ_WDOG_TO] = {
 158                 .primary = WM831X_WDOG_INT,
 159                 .reg = 1,
 160                 .mask = WM831X_WDOG_TO_EINT,
 161         },
 162         [WM831X_IRQ_RTC_PER] = {
 163                 .primary = WM831X_RTC_INT,
 164                 .reg = 1,
 165                 .mask = WM831X_RTC_PER_EINT,
 166         },
 167         [WM831X_IRQ_RTC_ALM] = {
 168                 .primary = WM831X_RTC_INT,
 169                 .reg = 1,
 170                 .mask = WM831X_RTC_ALM_EINT,
 171         },
 172         [WM831X_IRQ_CHG_BATT_HOT] = {
 173                 .primary = WM831X_CHG_INT,
 174                 .reg = 2,
 175                 .mask = WM831X_CHG_BATT_HOT_EINT,
 176         },
 177         [WM831X_IRQ_CHG_BATT_COLD] = {
 178                 .primary = WM831X_CHG_INT,
 179                 .reg = 2,
 180                 .mask = WM831X_CHG_BATT_COLD_EINT,
 181         },
 182         [WM831X_IRQ_CHG_BATT_FAIL] = {
 183                 .primary = WM831X_CHG_INT,
 184                 .reg = 2,
 185                 .mask = WM831X_CHG_BATT_FAIL_EINT,
 186         },
 187         [WM831X_IRQ_CHG_OV] = {
 188                 .primary = WM831X_CHG_INT,
 189                 .reg = 2,
 190                 .mask = WM831X_CHG_OV_EINT,
 191         },
 192         [WM831X_IRQ_CHG_END] = {
 193                 .primary = WM831X_CHG_INT,
 194                 .reg = 2,
 195                 .mask = WM831X_CHG_END_EINT,
 196         },
 197         [WM831X_IRQ_CHG_TO] = {
 198                 .primary = WM831X_CHG_INT,
 199                 .reg = 2,
 200                 .mask = WM831X_CHG_TO_EINT,
 201         },
 202         [WM831X_IRQ_CHG_MODE] = {
 203                 .primary = WM831X_CHG_INT,
 204                 .reg = 2,
 205                 .mask = WM831X_CHG_MODE_EINT,
 206         },
 207         [WM831X_IRQ_CHG_START] = {
 208                 .primary = WM831X_CHG_INT,
 209                 .reg = 2,
 210                 .mask = WM831X_CHG_START_EINT,
 211         },
 212         [WM831X_IRQ_TCHDATA] = {
 213                 .primary = WM831X_TCHDATA_INT,
 214                 .reg = 1,
 215                 .mask = WM831X_TCHDATA_EINT,
 216         },
 217         [WM831X_IRQ_TCHPD] = {
 218                 .primary = WM831X_TCHPD_INT,
 219                 .reg = 1,
 220                 .mask = WM831X_TCHPD_EINT,
 221         },
 222         [WM831X_IRQ_AUXADC_DATA] = {
 223                 .primary = WM831X_AUXADC_INT,
 224                 .reg = 1,
 225                 .mask = WM831X_AUXADC_DATA_EINT,
 226         },
 227         [WM831X_IRQ_AUXADC_DCOMP1] = {
 228                 .primary = WM831X_AUXADC_INT,
 229                 .reg = 1,
 230                 .mask = WM831X_AUXADC_DCOMP1_EINT,
 231         },
 232         [WM831X_IRQ_AUXADC_DCOMP2] = {
 233                 .primary = WM831X_AUXADC_INT,
 234                 .reg = 1,
 235                 .mask = WM831X_AUXADC_DCOMP2_EINT,
 236         },
 237         [WM831X_IRQ_AUXADC_DCOMP3] = {
 238                 .primary = WM831X_AUXADC_INT,
 239                 .reg = 1,
 240                 .mask = WM831X_AUXADC_DCOMP3_EINT,
 241         },
 242         [WM831X_IRQ_AUXADC_DCOMP4] = {
 243                 .primary = WM831X_AUXADC_INT,
 244                 .reg = 1,
 245                 .mask = WM831X_AUXADC_DCOMP4_EINT,
 246         },
 247         [WM831X_IRQ_CS1] = {
 248                 .primary = WM831X_CS_INT,
 249                 .reg = 2,
 250                 .mask = WM831X_CS1_EINT,
 251         },
 252         [WM831X_IRQ_CS2] = {
 253                 .primary = WM831X_CS_INT,
 254                 .reg = 2,
 255                 .mask = WM831X_CS2_EINT,
 256         },
 257         [WM831X_IRQ_HC_DC1] = {
 258                 .primary = WM831X_HC_INT,
 259                 .reg = 4,
 260                 .mask = WM831X_HC_DC1_EINT,
 261         },
 262         [WM831X_IRQ_HC_DC2] = {
 263                 .primary = WM831X_HC_INT,
 264                 .reg = 4,
 265                 .mask = WM831X_HC_DC2_EINT,
 266         },
 267         [WM831X_IRQ_UV_LDO1] = {
 268                 .primary = WM831X_UV_INT,
 269                 .reg = 3,
 270                 .mask = WM831X_UV_LDO1_EINT,
 271         },
 272         [WM831X_IRQ_UV_LDO2] = {
 273                 .primary = WM831X_UV_INT,
 274                 .reg = 3,
 275                 .mask = WM831X_UV_LDO2_EINT,
 276         },
 277         [WM831X_IRQ_UV_LDO3] = {
 278                 .primary = WM831X_UV_INT,
 279                 .reg = 3,
 280                 .mask = WM831X_UV_LDO3_EINT,
 281         },
 282         [WM831X_IRQ_UV_LDO4] = {
 283                 .primary = WM831X_UV_INT,
 284                 .reg = 3,
 285                 .mask = WM831X_UV_LDO4_EINT,
 286         },
 287         [WM831X_IRQ_UV_LDO5] = {
 288                 .primary = WM831X_UV_INT,
 289                 .reg = 3,
 290                 .mask = WM831X_UV_LDO5_EINT,
 291         },
 292         [WM831X_IRQ_UV_LDO6] = {
 293                 .primary = WM831X_UV_INT,
 294                 .reg = 3,
 295                 .mask = WM831X_UV_LDO6_EINT,
 296         },
 297         [WM831X_IRQ_UV_LDO7] = {
 298                 .primary = WM831X_UV_INT,
 299                 .reg = 3,
 300                 .mask = WM831X_UV_LDO7_EINT,
 301         },
 302         [WM831X_IRQ_UV_LDO8] = {
 303                 .primary = WM831X_UV_INT,
 304                 .reg = 3,
 305                 .mask = WM831X_UV_LDO8_EINT,
 306         },
 307         [WM831X_IRQ_UV_LDO9] = {
 308                 .primary = WM831X_UV_INT,
 309                 .reg = 3,
 310                 .mask = WM831X_UV_LDO9_EINT,
 311         },
 312         [WM831X_IRQ_UV_LDO10] = {
 313                 .primary = WM831X_UV_INT,
 314                 .reg = 3,
 315                 .mask = WM831X_UV_LDO10_EINT,
 316         },
 317         [WM831X_IRQ_UV_DC1] = {
 318                 .primary = WM831X_UV_INT,
 319                 .reg = 4,
 320                 .mask = WM831X_UV_DC1_EINT,
 321         },
 322         [WM831X_IRQ_UV_DC2] = {
 323                 .primary = WM831X_UV_INT,
 324                 .reg = 4,
 325                 .mask = WM831X_UV_DC2_EINT,
 326         },
 327         [WM831X_IRQ_UV_DC3] = {
 328                 .primary = WM831X_UV_INT,
 329                 .reg = 4,
 330                 .mask = WM831X_UV_DC3_EINT,
 331         },
 332         [WM831X_IRQ_UV_DC4] = {
 333                 .primary = WM831X_UV_INT,
 334                 .reg = 4,
 335                 .mask = WM831X_UV_DC4_EINT,
 336         },
 337 };
 338
 339 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
 340 {
 341         return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
 342 }
 343
 344 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
 345 {
 346         return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
 347 }
 348
 349 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
 350                                                         int irq)
 351 {
 352         return &wm831x_irqs[irq - wm831x->irq_base];
 353 }
 354
 355 static void wm831x_irq_lock(struct irq_data *data)
 356 {
 357         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 358
 359         mutex_lock(&wm831x->irq_lock);
 360 }
 361
 362 static void wm831x_irq_sync_unlock(struct irq_data *data)
 363 {
 364         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 365         int i;
 366
 367         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 368                 /* If there's been a change in the mask write it back
 369                  * to the hardware. */
 370                 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
 371                         dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
 372                                 WM831X_INTERRUPT_STATUS_1_MASK + i,
 373                                 wm831x->irq_masks_cur[i]);
 374
 375                         wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
 376                         wm831x_reg_write(wm831x,
 377                                          WM831X_INTERRUPT_STATUS_1_MASK + i,
 378                                          wm831x->irq_masks_cur[i]);
 379                 }
 380         }
 381
 382         mutex_unlock(&wm831x->irq_lock);
 383 }
 384
 385 static void wm831x_irq_enable(struct irq_data *data)
 386 {
 387         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 388         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 389                                                              data->irq);
 390
 391         wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
 392         //printk("%s:irq=%d\n",__FUNCTION__,irq);
 393 }
 394
 395 static void wm831x_irq_disable(struct irq_data *data)
 396 {
 397         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 398         struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
 399                                                              data->irq);
 400
 401         wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
 402         //printk("%s:irq=%d\n",__FUNCTION__,irq);
 403 }
 404
 405 static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
 406 {
 407         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 408         int val, irq = 0;
 409
 410         irq = data->irq - wm831x->irq_base;
 411         if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_12) {
 412                 /* Ignore internal-only IRQs */
 413                 if (irq >= 0 && irq < WM831X_NUM_IRQS)
 414                         return 0;
 415                 else
 416                         return -EINVAL;
 417         }
 418         //printk("wm831x_irq_set_type:type=%x,irq=%d\n",type,irq);
 419         switch (type) {
 420         case IRQ_TYPE_EDGE_BOTH:
 421                 val = WM831X_GPN_INT_MODE;
 422                 break;
 423         case IRQ_TYPE_EDGE_RISING:
 424                 val = WM831X_GPN_POL;
 425                 break;
 426         case IRQ_TYPE_EDGE_FALLING:
 427                 val = 0;
 428                 break;
 429         default:
 430                 return -EINVAL;
 431         }
 432
 433         return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + irq - 1,
 434                                WM831X_GPN_INT_MODE | WM831X_GPN_POL, val);
 435 }
 436
 437 static int wm831x_irq_set_wake(struct irq_data *data, unsigned state)
 438 {
 439         struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
 440         int irq = data->irq;
 441         //only wm831x irq
 442         if ((irq > wm831x->irq_base + WM831X_IRQ_TEMP_THW) &&( irq < wm831x->irq_base + WM831X_NUM_IRQS))
 443         {
 444                 if(state)
 445                 wm831x_irq_enable(data);
 446                 else
 447                 wm831x_irq_disable(data);
 448                 return 0;
 449         }
 450         else
 451         {
 452                 printk("%s:irq number err!irq=%d\n",__FUNCTION__,irq);
 453                 return -EINVAL;
 454         }
 455
 456
 457 }
 458
 459 static struct irq_chip wm831x_irq_chip = {
 460         .name                   = "wm831x",
 461         .irq_bus_lock           = wm831x_irq_lock,
 462         .irq_bus_sync_unlock    = wm831x_irq_sync_unlock,
 463         .irq_disable            = wm831x_irq_disable,
 464         .irq_enable             = wm831x_irq_enable,
 465         .irq_set_type           = wm831x_irq_set_type,
 466         .irq_set_wake   = wm831x_irq_set_wake,
 467 };
 468
 469 #if WM831X_IRQ_LIST
 470 static void wm831x_handle_worker(struct work_struct *work)
 471 {
 472         struct wm831x *wm831x = container_of(work, struct wm831x, handle_work);
 473         int irq;
 474
 475         while (1) {
 476                 unsigned long flags;
 477                 struct wm831x_handle_irq *hd = NULL;
 478
 479                 spin_lock_irqsave(&wm831x->work_lock, flags);
 480                 if (!list_empty(&wm831x->handle_queue)) {
 481                         hd = list_first_entry(&wm831x->handle_queue, struct wm831x_handle_irq, queue);
 482                         list_del(&hd->queue);
 483                 }
 484                 spin_unlock_irqrestore(&wm831x->work_lock, flags);
 485
 486                 if (!hd)        // trans_queue empty
 487                         break;
 488
 489                 irq = hd->irq;  //get wm831x intterupt status
 490                 //printk("%s:irq=%d\n",__FUNCTION__,irq);
 491
 492                 /*start to handle wm831x intterupt*/
 493                 handle_nested_irq(wm831x->irq_base + irq);
 494
 495                 kfree(hd);
 496
 497         }
 498 }
 499 #endif
 500 /* Main interrupt handling occurs in a workqueue since we need
 501  * interrupts enabled to interact with the chip. */
 502 static void wm831x_irq_worker(struct work_struct *work)
 503 {
 504         struct wm831x *wm831x = container_of(to_delayed_work(work), struct wm831x, irq_work);
 505         unsigned int i;
 506         int primary;
 507         int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
 508         int read[WM831X_NUM_IRQ_REGS] = { 0 };
 509         int *status;
 510         unsigned long flags;
 511         struct wm831x_handle_irq *hd;
 512
 513 #if (WM831X_IRQ_TYPE != IRQF_TRIGGER_LOW)
 514         /*mask wm831x irq at first*/
 515         int ret;
 516         ret = wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 517                               WM831X_IRQ_IM_MASK, WM831X_IRQ_IM_EANBLE);
 518         if (ret < 0) {
 519                 dev_err(wm831x->dev, "Failed to mask irq: %d\n", ret);
 520                 goto out;
 521         }
 522 #endif
 523
 524         primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
 525         if (primary < 0) {
 526                 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
 527                         primary);
 528                 goto out;
 529         }
 530
 531         mutex_lock(&wm831x->irq_lock);
 532
 533         for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
 534                 int offset = wm831x_irqs[i].reg - 1;
 535
 536                 if (!(primary & wm831x_irqs[i].primary))
 537                         continue;
 538
 539                 status = &status_regs[offset];
 540
 541                 /* Hopefully there should only be one register to read
 542                  * each time otherwise we ought to do a block read. */
 543                 if (!read[offset]) {
 544                         *status = wm831x_reg_read(wm831x,
 545                                      irq_data_to_status_reg(&wm831x_irqs[i]));
 546                         if (*status < 0) {
 547                                 dev_err(wm831x->dev,
 548                                         "Failed to read IRQ status: %d\n",
 549                                         *status);
 550                                 goto out_lock;
 551                         }
 552
 553                         read[offset] = 1;
 554                 }
 555
 556                 /* Report it if it isn't masked, or forget the status. */
 557                 if ((*status & ~wm831x->irq_masks_cur[offset])
 558                     & wm831x_irqs[i].mask)
 559                 {
 560                         #if WM831X_IRQ_LIST
 561                         /*add intterupt handle on list*/
 562                         hd = kzalloc(sizeof(struct wm831x_handle_irq), GFP_KERNEL);
 563                         if (!hd)
 564                         {
 565                                 printk("err:%s:ENOMEM\n",__FUNCTION__);
 566                                 return ;
 567                         }
 568
 569                         if(i == WM831X_IRQ_ON)
 570                         wake_lock(&wm831x->handle_wake);                //keep wake while handle WM831X_IRQ_ON
 571                         hd->irq = i;
 572                         spin_lock_irqsave(&wm831x->work_lock, flags);
 573                         list_add_tail(&hd->queue, &wm831x->handle_queue);
 574                         spin_unlock_irqrestore(&wm831x->work_lock, flags);
 575                         queue_work(wm831x->handle_wq, &wm831x->handle_work);
 576
 577                         #else
 578                         if(i == WM831X_IRQ_ON)
 579                         wake_lock(&wm831x->handle_wake);                //keep wake while handle WM831X_IRQ_ON
 580                         handle_nested_irq(wm831x->irq_base + i);
 581
 582                         #endif
 583                 }
 584
 585                 else
 586                         *status &= ~wm831x_irqs[i].mask;
 587         }
 588
 589 out_lock:
 590         mutex_unlock(&wm831x->irq_lock);
 591
 592 out:
 593         for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
 594                 if (status_regs[i])
 595                         wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
 596                                          status_regs[i]);
 597         }
 598
 599 #if (WM831X_IRQ_TYPE != IRQF_TRIGGER_LOW)
 600         ret = wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
 601                               WM831X_IRQ_IM_MASK, 0);
 602         if (ret < 0) {
 603                 dev_err(wm831x->dev, "Failed to open irq: %d\n", ret);
 604         }
 605 #endif
 606 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 607         enable_irq(wm831x->irq);
 608 #endif
 609         wake_unlock(&wm831x->irq_wake);
 610
 611 }
 612 /* The processing of the primary interrupt occurs in a thread so that
 613  * we can interact with the device over I2C or SPI. */
 614 static irqreturn_t wm831x_irq_thread(int irq, void *data)
 615 {
 616         struct wm831x *wm831x = data;
 617         int msdelay = 0;
 618         /* Shut the interrupt to the CPU up and schedule the actual
 619          * handler; we can't check that the IRQ is asserted. */
 620 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 621         disable_irq_nosync(irq);
 622 #endif
 623         wake_lock(&wm831x->irq_wake);
 624         if(wm831x->flag_suspend)
 625         {
 626                 spin_lock(&wm831x->flag_lock);
 627                 wm831x->flag_suspend = 0;
 628                 spin_unlock(&wm831x->flag_lock);
 629                 msdelay = 50;   //wait for spi/i2c resume
 630                 printk("%s:msdelay=%d\n",__FUNCTION__,msdelay);
 631         }
 632         else
 633                 msdelay = 0;
 634
 635         queue_delayed_work(wm831x->irq_wq, &wm831x->irq_work, msecs_to_jiffies(msdelay));
 636         //printk("%s\n",__FUNCTION__);
 637         return IRQ_HANDLED;
 638 }
 639
 640 int wm831x_irq_init(struct wm831x *wm831x, int irq)
 641 {
 642         struct wm831x_pdata *pdata = wm831x->dev->platform_data;
 643         int i, cur_irq, ret;
 644         printk( "wm831x_irq_init:irq=%d,%d\n",irq,pdata->irq_base);
 645         mutex_init(&wm831x->irq_lock);
 646
 647         /* Mask the individual interrupt sources */
 648         for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
 649                 wm831x->irq_masks_cur[i] = 0xffff;
 650                 wm831x->irq_masks_cache[i] = 0xffff;
 651                 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
 652                                  0xffff);
 653         }
 654
 655         if (!irq) {
 656                 dev_warn(wm831x->dev,
 657                          "No interrupt specified - functionality limited\n");
 658                 return 0;
 659         }
 660
 661         if (!pdata || !pdata->irq_base) {
 662                 dev_err(wm831x->dev,
 663                         "No interrupt base specified, no interrupts\n");
 664                 return 0;
 665         }
 666
 667         wm831x->irq_wq = create_singlethread_workqueue("wm831x-irq");
 668         if (!wm831x->irq_wq) {
 669                 dev_err(wm831x->dev, "Failed to allocate IRQ worker\n");
 670                 return -ESRCH;
 671         }
 672
 673
 674         wm831x->irq = irq;
 675         wm831x->flag_suspend = 0;
 676         wm831x->irq_base = pdata->irq_base;
 677         INIT_DELAYED_WORK(&wm831x->irq_work, wm831x_irq_worker);
 678         wake_lock_init(&wm831x->irq_wake, WAKE_LOCK_SUSPEND, "wm831x_irq_wake");
 679         wake_lock_init(&wm831x->handle_wake, WAKE_LOCK_SUSPEND, "wm831x_handle_wake");
 680 #if WM831X_IRQ_LIST
 681         wm831x->handle_wq = create_workqueue("wm831x_handle_wq");
 682         if (!wm831x->handle_wq) {
 683                 printk("cannot create workqueue\n");
 684                 return -EBUSY;
 685         }
 686         INIT_WORK(&wm831x->handle_work, wm831x_handle_worker);
 687         INIT_LIST_HEAD(&wm831x->handle_queue);
 688
 689 #endif
 690
 691         /* Register them with genirq */
 692         for (cur_irq = wm831x->irq_base;
 693              cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
 694              cur_irq++) {
 695                 irq_set_chip_data(cur_irq, wm831x);
 696                 irq_set_chip_and_handler(cur_irq, &wm831x_irq_chip,
 697                                          handle_edge_irq);
 698                 irq_set_nested_thread(cur_irq, 1);
 699
 700                 /* ARM needs us to explicitly flag the IRQ as valid
 701                  * and will set them noprobe when we do so. */
 702 #ifdef CONFIG_ARM
 703                 set_irq_flags(cur_irq, IRQF_VALID);
 704 #else
 705                 irq_set_noprobe(cur_irq);
 706 #endif
 707         }
 708 #if (WM831X_IRQ_TYPE == IRQF_TRIGGER_LOW)
 709         ret = request_threaded_irq(wm831x->irq, wm831x_irq_thread, NULL,
 710                                  IRQF_TRIGGER_LOW| IRQF_ONESHOT,//IRQF_TRIGGER_FALLING, //
 711                                    "wm831x", wm831x);
 712 #else
 713         ret = request_threaded_irq(wm831x->irq, wm831x_irq_thread, NULL,
 714                                  IRQF_TRIGGER_FALLING, //IRQF_TRIGGER_LOW| IRQF_ONESHOT,//
 715                                    "wm831x", wm831x);
 716 #endif
 717         if (ret != 0) {
 718                 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
 719                         wm831x->irq, ret);
 720                 return ret;
 721         }
 722
 723         enable_irq_wake(wm831x->irq); // so wm831x irq can wake up system
 724         /* Enable top level interrupts, we mask at secondary level */
 725         wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
 726
 727         return 0;
 728 }
 729
 730 void wm831x_irq_exit(struct wm831x *wm831x)
 731 {
 732         if (wm831x->irq)
 733                 free_irq(wm831x->irq, wm831x);
 734 }