2 * Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
4 * Copyright (C) 2010 Texas Instruments Inc
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/errno.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/err.h>
26 #include <linux/init.h>
27 #include <linux/wait.h>
28 #include <linux/clk.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/spinlock.h>
32 #include <linux/platform_device.h>
33 #include <linux/delay.h>
35 #include <linux/mfd/core.h>
36 #include <linux/mfd/ti_ssp.h>
38 /* Register Offsets */
40 #define REG_IOSEL_1 0x04
41 #define REG_IOSEL_2 0x08
42 #define REG_PREDIV 0x0c
43 #define REG_INTR_ST 0x10
44 #define REG_INTR_EN 0x14
45 #define REG_TEST_CTRL 0x18
47 /* Per port registers */
48 #define PORT_CFG_2 0x00
49 #define PORT_ADDR 0x04
50 #define PORT_DATA 0x08
51 #define PORT_CFG_1 0x0c
52 #define PORT_STATE 0x10
54 #define SSP_PORT_CONFIG_MASK (SSP_EARLY_DIN | SSP_DELAY_DOUT)
55 #define SSP_PORT_CLKRATE_MASK 0x0f
57 #define SSP_SEQRAM_WR_EN BIT(4)
58 #define SSP_SEQRAM_RD_EN BIT(5)
59 #define SSP_START BIT(15)
60 #define SSP_BUSY BIT(10)
61 #define SSP_PORT_ASL BIT(7)
62 #define SSP_PORT_CFO1 BIT(6)
64 #define SSP_PORT_SEQRAM_SIZE 32
66 static const int ssp_port_base[] = {0x040, 0x080};
67 static const int ssp_port_seqram[] = {0x100, 0x180};
76 wait_queue_head_t wqh;
79 * Some of the iosel2 register bits always read-back as 0, we need to
80 * remember these values so that we don't clobber previously set
86 static inline struct ti_ssp *dev_to_ssp(struct device *dev)
88 return dev_get_drvdata(dev->parent);
91 static inline int dev_to_port(struct device *dev)
93 return to_platform_device(dev)->id;
96 /* Register Access Helpers, rmw() functions need to run locked */
97 static inline u32 ssp_read(struct ti_ssp *ssp, int reg)
99 return __raw_readl(ssp->regs + reg);
102 static inline void ssp_write(struct ti_ssp *ssp, int reg, u32 val)
104 __raw_writel(val, ssp->regs + reg);
107 static inline void ssp_rmw(struct ti_ssp *ssp, int reg, u32 mask, u32 bits)
109 ssp_write(ssp, reg, (ssp_read(ssp, reg) & ~mask) | bits);
112 static inline u32 ssp_port_read(struct ti_ssp *ssp, int port, int reg)
114 return ssp_read(ssp, ssp_port_base[port] + reg);
117 static inline void ssp_port_write(struct ti_ssp *ssp, int port, int reg,
120 ssp_write(ssp, ssp_port_base[port] + reg, val);
123 static inline void ssp_port_rmw(struct ti_ssp *ssp, int port, int reg,
126 ssp_rmw(ssp, ssp_port_base[port] + reg, mask, bits);
129 static inline void ssp_port_clr_bits(struct ti_ssp *ssp, int port, int reg,
132 ssp_port_rmw(ssp, port, reg, bits, 0);
135 static inline void ssp_port_set_bits(struct ti_ssp *ssp, int port, int reg,
138 ssp_port_rmw(ssp, port, reg, 0, bits);
141 /* Called to setup port clock mode, caller must hold ssp->lock */
142 static int __set_mode(struct ti_ssp *ssp, int port, int mode)
144 mode &= SSP_PORT_CONFIG_MASK;
145 ssp_port_rmw(ssp, port, PORT_CFG_1, SSP_PORT_CONFIG_MASK, mode);
150 int ti_ssp_set_mode(struct device *dev, int mode)
152 struct ti_ssp *ssp = dev_to_ssp(dev);
153 int port = dev_to_port(dev);
156 spin_lock(&ssp->lock);
157 ret = __set_mode(ssp, port, mode);
158 spin_unlock(&ssp->lock);
162 EXPORT_SYMBOL(ti_ssp_set_mode);
164 /* Called to setup iosel2, caller must hold ssp->lock */
165 static void __set_iosel2(struct ti_ssp *ssp, u32 mask, u32 val)
167 ssp->iosel2 = (ssp->iosel2 & ~mask) | val;
168 ssp_write(ssp, REG_IOSEL_2, ssp->iosel2);
171 /* Called to setup port iosel, caller must hold ssp->lock */
172 static void __set_iosel(struct ti_ssp *ssp, int port, u32 iosel)
174 unsigned val, shift = port ? 16 : 0;
176 /* IOSEL1 gets the least significant 16 bits */
177 val = ssp_read(ssp, REG_IOSEL_1);
178 val &= 0xffff << (port ? 0 : 16);
179 val |= (iosel & 0xffff) << (port ? 16 : 0);
180 ssp_write(ssp, REG_IOSEL_1, val);
182 /* IOSEL2 gets the most significant 16 bits */
183 val = (iosel >> 16) & 0x7;
184 __set_iosel2(ssp, 0x7 << shift, val << shift);
187 int ti_ssp_set_iosel(struct device *dev, u32 iosel)
189 struct ti_ssp *ssp = dev_to_ssp(dev);
190 int port = dev_to_port(dev);
192 spin_lock(&ssp->lock);
193 __set_iosel(ssp, port, iosel);
194 spin_unlock(&ssp->lock);
198 EXPORT_SYMBOL(ti_ssp_set_iosel);
200 int ti_ssp_load(struct device *dev, int offs, u32* prog, int len)
202 struct ti_ssp *ssp = dev_to_ssp(dev);
203 int port = dev_to_port(dev);
206 if (len > SSP_PORT_SEQRAM_SIZE)
209 spin_lock(&ssp->lock);
211 /* Enable SeqRAM access */
212 ssp_port_set_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
215 for (i = 0; i < len; i++) {
216 __raw_writel(prog[i], ssp->regs + offs + 4*i +
217 ssp_port_seqram[port]);
220 /* Disable SeqRAM access */
221 ssp_port_clr_bits(ssp, port, PORT_CFG_2, SSP_SEQRAM_WR_EN);
223 spin_unlock(&ssp->lock);
227 EXPORT_SYMBOL(ti_ssp_load);
229 int ti_ssp_raw_read(struct device *dev)
231 struct ti_ssp *ssp = dev_to_ssp(dev);
232 int port = dev_to_port(dev);
233 int shift = port ? 27 : 11;
235 return (ssp_read(ssp, REG_IOSEL_2) >> shift) & 0xf;
237 EXPORT_SYMBOL(ti_ssp_raw_read);
239 int ti_ssp_raw_write(struct device *dev, u32 val)
241 struct ti_ssp *ssp = dev_to_ssp(dev);
242 int port = dev_to_port(dev), shift;
244 spin_lock(&ssp->lock);
246 shift = port ? 22 : 6;
248 __set_iosel2(ssp, 0xf << shift, val << shift);
250 spin_unlock(&ssp->lock);
254 EXPORT_SYMBOL(ti_ssp_raw_write);
256 static inline int __xfer_done(struct ti_ssp *ssp, int port)
258 return !(ssp_port_read(ssp, port, PORT_CFG_1) & SSP_BUSY);
261 int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output)
263 struct ti_ssp *ssp = dev_to_ssp(dev);
264 int port = dev_to_port(dev);
270 /* Grab ssp->lock to serialize rmw on ssp registers */
271 spin_lock(&ssp->lock);
273 ssp_port_write(ssp, port, PORT_ADDR, input >> 16);
274 ssp_port_write(ssp, port, PORT_DATA, input & 0xffff);
275 ssp_port_rmw(ssp, port, PORT_CFG_1, 0x3f, pc);
277 /* grab wait queue head lock to avoid race with the isr */
278 spin_lock_irq(&ssp->wqh.lock);
280 /* kick off sequence execution in hardware */
281 ssp_port_set_bits(ssp, port, PORT_CFG_1, SSP_START);
283 /* drop ssp lock; no register writes beyond this */
284 spin_unlock(&ssp->lock);
286 ret = wait_event_interruptible_locked_irq(ssp->wqh,
287 __xfer_done(ssp, port));
288 spin_unlock_irq(&ssp->wqh.lock);
294 *output = (ssp_port_read(ssp, port, PORT_ADDR) << 16) |
295 (ssp_port_read(ssp, port, PORT_DATA) & 0xffff);
298 ret = ssp_port_read(ssp, port, PORT_STATE) & 0x3f; /* stop address */
302 EXPORT_SYMBOL(ti_ssp_run);
304 static irqreturn_t ti_ssp_interrupt(int irq, void *dev_data)
306 struct ti_ssp *ssp = dev_data;
308 spin_lock(&ssp->wqh.lock);
310 ssp_write(ssp, REG_INTR_ST, 0x3);
311 wake_up_locked(&ssp->wqh);
313 spin_unlock(&ssp->wqh.lock);
318 static int ti_ssp_probe(struct platform_device *pdev)
320 static struct ti_ssp *ssp;
321 const struct ti_ssp_data *pdata = pdev->dev.platform_data;
322 int error = 0, prediv = 0xff, id;
323 unsigned long sysclk;
324 struct device *dev = &pdev->dev;
325 struct mfd_cell cells[2];
327 ssp = kzalloc(sizeof(*ssp), GFP_KERNEL);
329 dev_err(dev, "cannot allocate device info\n");
334 dev_set_drvdata(dev, ssp);
336 ssp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339 dev_err(dev, "cannot determine register area\n");
343 if (!request_mem_region(ssp->res->start, resource_size(ssp->res),
346 dev_err(dev, "cannot claim register memory\n");
350 ssp->regs = ioremap(ssp->res->start, resource_size(ssp->res));
353 dev_err(dev, "cannot map register memory\n");
357 ssp->clk = clk_get(dev, NULL);
358 if (IS_ERR(ssp->clk)) {
359 error = PTR_ERR(ssp->clk);
360 dev_err(dev, "cannot claim device clock\n");
364 ssp->irq = platform_get_irq(pdev, 0);
367 dev_err(dev, "unknown irq\n");
371 error = request_threaded_irq(ssp->irq, NULL, ti_ssp_interrupt, 0,
374 dev_err(dev, "cannot acquire irq\n");
378 spin_lock_init(&ssp->lock);
379 init_waitqueue_head(&ssp->wqh);
381 /* Power on and initialize SSP */
382 error = clk_enable(ssp->clk);
384 dev_err(dev, "cannot enable device clock\n");
388 /* Reset registers to a sensible known state */
389 ssp_write(ssp, REG_IOSEL_1, 0);
390 ssp_write(ssp, REG_IOSEL_2, 0);
391 ssp_write(ssp, REG_INTR_EN, 0x3);
392 ssp_write(ssp, REG_INTR_ST, 0x3);
393 ssp_write(ssp, REG_TEST_CTRL, 0);
394 ssp_port_write(ssp, 0, PORT_CFG_1, SSP_PORT_ASL);
395 ssp_port_write(ssp, 1, PORT_CFG_1, SSP_PORT_ASL);
396 ssp_port_write(ssp, 0, PORT_CFG_2, SSP_PORT_CFO1);
397 ssp_port_write(ssp, 1, PORT_CFG_2, SSP_PORT_CFO1);
399 sysclk = clk_get_rate(ssp->clk);
400 if (pdata && pdata->out_clock)
401 prediv = (sysclk / pdata->out_clock) - 1;
402 prediv = clamp(prediv, 0, 0xff);
403 ssp_rmw(ssp, REG_PREDIV, 0xff, prediv);
405 memset(cells, 0, sizeof(cells));
406 for (id = 0; id < 2; id++) {
407 const struct ti_ssp_dev_data *data = &pdata->dev_data[id];
410 cells[id].name = data->dev_name;
411 cells[id].platform_data = data->pdata;
412 cells[id].data_size = data->pdata_size;
415 error = mfd_add_devices(dev, 0, cells, 2, NULL, 0, NULL);
417 dev_err(dev, "cannot add mfd cells\n");
424 free_irq(ssp->irq, ssp);
430 release_mem_region(ssp->res->start, resource_size(ssp->res));
436 static int ti_ssp_remove(struct platform_device *pdev)
438 struct device *dev = &pdev->dev;
439 struct ti_ssp *ssp = dev_get_drvdata(dev);
441 mfd_remove_devices(dev);
442 clk_disable(ssp->clk);
443 free_irq(ssp->irq, ssp);
446 release_mem_region(ssp->res->start, resource_size(ssp->res));
448 dev_set_drvdata(dev, NULL);
452 static struct platform_driver ti_ssp_driver = {
453 .probe = ti_ssp_probe,
454 .remove = ti_ssp_remove,
457 .owner = THIS_MODULE,
461 module_platform_driver(ti_ssp_driver);
463 MODULE_DESCRIPTION("Sequencer Serial Port (SSP) Driver");
464 MODULE_AUTHOR("Cyril Chemparathy");
465 MODULE_LICENSE("GPL");
466 MODULE_ALIAS("platform:ti-ssp");