drivers/mfd/rk616-vif.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/slab.h>
   4 #include <linux/mfd/rk616.h>
   5
   6
   7
   8 extern int rk616_pll_set_rate(struct mfd_rk616 *rk616,int id,u32 cfg_val,u32 frac);
   9 extern int rk616_pll_pwr_down(struct mfd_rk616 *rk616,int id);
  10
  11
  12 /*rk616 video interface config*/
  13
  14  int rk616_vif_disable(struct mfd_rk616 *rk616,int id)
  15 {
  16         u32 val = 0;
  17         int ret = 0;
  18
  19         if(id == 0) //video interface 0
  20         {
  21                         val = (VIF0_EN << 16); //disable vif0
  22                         ret = rk616->write_dev(rk616,VIF0_REG0,&val);
  23
  24         }
  25         else       //vide0 interface 1
  26         {
  27                         val = (VIF0_EN << 16); //disabl VIF1
  28                         ret = rk616->write_dev(rk616,VIF1_REG0,&val);
  29
  30         }
  31
  32         msleep(21);
  33
  34         if(id == 0) //video interface 0
  35         {
  36                         val = VIF0_CLK_GATE | (VIF0_CLK_GATE << 16); //gating vif0
  37                         ret = rk616->write_dev(rk616,CRU_CLKSEL2_CON,&val);
  38
  39         }
  40         else       //vide0 interface 1
  41         {
  42                         val = VIF1_CLK_GATE | (VIF1_CLK_GATE << 16); //gating vif1
  43                         ret = rk616->write_dev(rk616,CRU_CLKSEL2_CON,&val);
  44
  45         }
  46
  47         rk616_dbg(rk616->dev,"rk616 vif%d disable\n",id);
  48
  49         return 0;
  50 }
  51
  52
  53 int rk616_vif_enable(struct mfd_rk616 *rk616,int id)
  54 {
  55         u32 val = 0;
  56         u32 offset = 0;
  57         int ret;
  58
  59
  60         if(id == 0)
  61         {
  62                 val = (VIF0_CLK_BYPASS << 16) | (VIF0_CLK_GATE << 16);
  63                 offset = 0;
  64         }
  65         else
  66         {
  67                 val = (VIF1_CLK_BYPASS << 16) |(VIF1_CLK_GATE << 16);
  68                 offset = 0x18;
  69         }
  70
  71         ret = rk616->write_dev(rk616,CRU_CLKSEL2_CON,&val);
  72
  73         val = 0;
  74         val |= (VIF0_DDR_CLK_EN <<16) | (VIF0_DDR_PHASEN_EN << 16) | (VIF0_DDR_MODE_EN << 16)|
  75                 (VIF0_EN <<16) | VIF0_EN; //disable ddr mode,enable VIF
  76         ret = rk616->write_dev(rk616,VIF0_REG0 + offset,&val);
  77
  78
  79         rk616_dbg(rk616->dev,"rk616 vif%d enable\n",id);
  80
  81         return 0;
  82
  83 }
  84 static int  rk616_vif_bypass(struct mfd_rk616 *rk616,int id)
  85 {
  86         u32 val = 0;
  87         int ret;
  88
  89         if(id == 0)
  90         {
  91                 val = (VIF0_CLK_BYPASS | VIF0_CLK_BYPASS << 16);
  92         }
  93         else
  94         {
  95                 val = (VIF1_CLK_BYPASS | VIF1_CLK_BYPASS << 16);
  96         }
  97
  98         ret = rk616->write_dev(rk616,CRU_CLKSEL2_CON,&val);
  99
 100         rk616_dbg(rk616->dev,"rk616 vif%d bypass\n",id);
 101         return 0;
 102 }
 103
 104 static bool pll_sel_mclk12m(struct mfd_rk616 *rk616,int pll_id)
 105 {
 106         if(pll_id == 0) //pll0
 107         {
 108                 if(rk616->route.pll0_clk_sel == PLL0_CLK_SEL(MCLK_12M))
 109                         return true;
 110                 else
 111                         return false;
 112         }
 113         else
 114         {
 115                 if(rk616->route.pll1_clk_sel == PLL1_CLK_SEL(MCLK_12M))
 116                         return  true;
 117                 else
 118                         return false;
 119         }
 120
 121         return false;
 122 }
 123
 124
 125
 126 int rk616_vif_cfg(struct mfd_rk616 *rk616,rk_screen *screen,int id)
 127 {
 128         int ret = 0;
 129         u32 val = 0;
 130         int offset = 0;
 131         int pll_id;
 132         bool pll_use_mclk12m = false;
 133
 134         if(id == 0) //video interface 0
 135         {
 136                 if(!rk616->route.vif0_en)
 137                 {
 138                         rk616_vif_disable(rk616,id);
 139                         return 0;
 140                 }
 141                 offset = 0;
 142                 pll_id = rk616->route.vif0_clk_sel;
 143         }
 144         else       //vide0 interface 1
 145         {
 146                 if(!rk616->route.vif1_en)
 147                 {
 148                         rk616_vif_disable(rk616,id);
 149                         return 0;
 150                 }
 151                 offset = 0x18;
 152                 pll_id = (rk616->route.vif1_clk_sel >> 6);
 153
 154         }
 155
 156         pll_use_mclk12m = pll_sel_mclk12m(rk616,pll_id);
 157
 158         if(pll_use_mclk12m)
 159         {
 160                 clk_set_rate(rk616->mclk, 12000000);
 161         }
 162
 163
 164         if(!screen)
 165         {
 166                 dev_err(rk616->dev,"%s:screen is null.........\n",__func__);
 167                 return -EINVAL;
 168         }
 169
 170
 171         rk616_vif_disable(rk616,id);
 172         if( (screen->x_res == 1920) && (screen->y_res == 1080))
 173         {
 174                 if(pll_use_mclk12m)
 175                         //rk616_pll_set_rate(rk616,pll_id,0xc11025,0x200000);
 176                         rk616_pll_set_rate(rk616,pll_id,0x028853de,0);
 177                 else
 178                         rk616_pll_set_rate(rk616,pll_id,0x02bf5276,0);
 179
 180                 val = (0xc1) | (0x01 <<16);
 181         }
 182         else if((screen->x_res == 1280) && (screen->y_res == 720))
 183         {
 184                 if(pll_use_mclk12m)
 185                         //rk616_pll_set_rate(rk616,pll_id,0x01811025,0x200000);
 186                         rk616_pll_set_rate(rk616,pll_id,0x0288418c,0);
 187                 else
 188                         rk616_pll_set_rate(rk616,pll_id,0x1422014,0);
 189
 190                 val = (0xc1) | (0x01 <<16);
 191
 192         }
 193         else if((screen->x_res == 720))
 194         {
 195                 if(pll_use_mclk12m )
 196                 {
 197                         rk616_pll_set_rate(rk616,pll_id,0x0306510e,0);
 198                 }
 199                 else
 200                         rk616_pll_set_rate(rk616,pll_id,0x1c13015,0);
 201
 202                 val = (0x1) | (0x01 <<16);
 203         }
 204
 205
 206         ret = rk616->write_dev(rk616,VIF0_REG1 + offset,&val);
 207
 208         val = (screen->hsync_len << 16) | (screen->hsync_len + screen->left_margin +
 209                 screen->right_margin + screen->x_res);
 210         ret = rk616->write_dev(rk616,VIF0_REG2 + offset,&val);
 211
 212
 213         val = ((screen->hsync_len + screen->left_margin + screen->x_res)<<16) |
 214                 (screen->hsync_len + screen->left_margin);
 215         ret = rk616->write_dev(rk616,VIF0_REG3 + offset,&val);
 216
 217         val = (screen->vsync_len << 16) | (screen->vsync_len + screen->upper_margin +
 218                 screen->lower_margin + screen->y_res);
 219         ret = rk616->write_dev(rk616,VIF0_REG4 + offset,&val);
 220
 221
 222         val = ((screen->vsync_len + screen->upper_margin + screen->y_res)<<16) |
 223                 (screen->vsync_len + screen->upper_margin);
 224         ret = rk616->write_dev(rk616,VIF0_REG5 + offset,&val);
 225
 226         rk616_vif_enable(rk616,id);
 227
 228         return ret;
 229
 230 }
 231
 232
 233 static int rk616_scaler_disable(struct mfd_rk616 *rk616)
 234 {
 235         u32 val = 0;
 236         int ret;
 237         val &= (~SCL_EN);       //disable scaler
 238         val |= (SCL_EN<<16);
 239         ret = rk616->write_dev(rk616,SCL_REG0,&val);
 240         rk616_dbg(rk616->dev,"rk616 scaler disable\n");
 241         return 0;
 242 }
 243
 244 int rk616_scaler_cfg(struct mfd_rk616 *rk616,rk_screen *screen)
 245 {
 246         u32 scl_hor_mode,scl_ver_mode;
 247         u32 scl_v_factor,scl_h_factor;
 248         u32 scl_reg0_value,scl_reg1_value,scl_reg2_value;                //scl_con,scl_h_factor,scl_v_factor,
 249         u32 scl_reg3_value,scl_reg4_value,scl_reg5_value,scl_reg6_value; //dsp_frame_hst,dsp_frame_vst,dsp_timing,dsp_act_timing
 250         u32 scl_reg7_value,scl_reg8_value;                               //dsp_hbor ,dsp_vbor
 251         u32 dst_frame_hst,dst_frame_vst;                    //Ê±Ðò»º´æ
 252         u32 dst_vact_st;
 253
 254         u32 dsp_htotal,dsp_hs_end,dsp_hact_st,dsp_hact_end; //scalerÊä³öµÄtiming²ÎÊý
 255         u32 dsp_vtotal,dsp_vs_end,dsp_vact_st,dsp_vact_end;
 256         u32 dsp_hbor_end,dsp_hbor_st,dsp_vbor_end,dsp_vbor_st;
 257         u32 src_w,src_h,src_htotal,dst_w,dst_h,src_vact_st;
 258         u16 bor_right = 0;
 259         u16 bor_left = 0;
 260         u16 bor_up = 0;
 261         u16 bor_down = 0;
 262         u8 hor_down_mode = 0;  //1:average,0:bilinear
 263         u8 ver_down_mode = 0;
 264         u8 bic_coe_sel = 2;
 265         rk_screen *src;
 266         rk_screen *dst;
 267         int pll_id;
 268
 269         struct rk616_route *route = &rk616->route;
 270
 271
 272         if(!route->scl_en)
 273         {
 274                 rk616_scaler_disable(rk616);
 275                 return 0;
 276         }
 277
 278
 279         dst = screen;
 280         if(!dst)
 281         {
 282                 dev_err(rk616->dev,"%s:screen is null!\n",__func__);
 283                 return -EINVAL;
 284         }
 285
 286         if(route->scl_bypass)
 287         {
 288                 src = dst;
 289                 dst->pll_cfg_val = 0x01422014;
 290                 dst->frac = 0;
 291         }
 292         else
 293                 src = screen->ext_screen;
 294
 295         if(route->sclk_sel == SCLK_SEL(SCLK_SEL_PLL0))
 296                 pll_id = 0;
 297         else
 298                 pll_id = 1;
 299
 300         rk616_scaler_disable(rk616);
 301         rk616_pll_set_rate(rk616,pll_id,dst->pll_cfg_val,dst->frac);
 302         dst_frame_vst = dst->scl_vst;
 303         dst_frame_hst = dst->scl_hst;
 304
 305
 306 #if 1
 307
 308         src_htotal = src->hsync_len + src->left_margin + src->x_res + src->right_margin;
 309         src_vact_st = src->vsync_len + src->upper_margin  ;
 310         dst_vact_st = dst->vsync_len + dst->upper_margin;
 311
 312         dsp_htotal    = dst->hsync_len + dst->left_margin + dst->x_res + dst->right_margin; //dst_htotal ;
 313         dsp_hs_end    = dst->hsync_len;
 314
 315         dsp_vtotal    = dst->vsync_len + dst->upper_margin + dst->y_res + dst->lower_margin;
 316         dsp_vs_end    = dst->vsync_len;
 317
 318         dsp_hbor_end  = dst->hsync_len + dst->left_margin + dst->x_res;
 319         dsp_hbor_st   = dst->hsync_len + dst->left_margin  ;
 320         dsp_vbor_end  = dst->vsync_len + dst->upper_margin + dst->y_res; //dst_vact_end ;
 321         dsp_vbor_st   = dst_vact_st  ;
 322
 323         dsp_hact_st   = dsp_hbor_st  + bor_left;
 324         dsp_hact_end  = dsp_hbor_end - bor_right;
 325         dsp_vact_st   = dsp_vbor_st  + bor_up;
 326         dsp_vact_end  = dsp_vbor_end - bor_down;
 327
 328         src_w = src->x_res;
 329         src_h = src->y_res;
 330         dst_w = dsp_hact_end - dsp_hact_st ;
 331         dst_h = dsp_vact_end - dsp_vact_st ;
 332
 333         if(src_w > dst_w)         //ÅÐ¶ÏhorµÄËõ·ÅÄ£Ê½ 0£ºno_scl 1£ºscl_up 2£ºscl_down
 334         {
 335                 scl_hor_mode = 0x2;   //scl_down
 336                 if(hor_down_mode == 0)//bilinear
 337                 {
 338                         if((src_w-1)/(dst_w-1) > 2)
 339                         {
 340                                 scl_h_factor = ((src_w-1)<<14)/(dst_w-1);
 341                         }
 342                         else
 343                                 scl_h_factor = ((src_w-2)<<14)/(dst_w-1);
 344                 }
 345                 else  //average
 346                 {
 347                         scl_h_factor = ((dst_w)<<16)/(src_w-1);
 348                 }
 349         }
 350         else if(src_w == dst_w)
 351         {
 352                 scl_hor_mode = 0x0;   //no_Scl
 353                 scl_h_factor = 0x0;
 354         }
 355         else
 356         {
 357                 scl_hor_mode = 0x1;   //scl_up
 358                 scl_h_factor = ((src_w-1)<<16)/(dst_w-1);
 359         }
 360
 361         if(src_h > dst_h)         //ÅÐ¶ÏverµÄËõ·ÅÄ£Ê½ 0£ºno_scl 1£ºscl_up 2£ºscl_down
 362         {
 363                 scl_ver_mode = 0x2;   //scl_down
 364                 if(ver_down_mode == 0)//bilinearhor_down_mode,u8 ver_down_mode
 365                 {
 366                         if((src_h-1)/(dst_h-1) > 2)
 367                         {
 368                                 scl_v_factor = ((src_h-1)<<14)/(dst_h-1);
 369                         }
 370                         else
 371                                 scl_v_factor = ((src_h-2)<<14)/(dst_h-1);
 372                 }
 373                 else
 374                 {
 375                         scl_v_factor = ((dst_h)<<16)/(src_h-1);
 376                 }
 377         }
 378         else if(src_h == dst_h)
 379         {
 380                 scl_ver_mode = 0x0;   //no_Scl
 381                 scl_v_factor = 0x0;
 382         }
 383         else
 384         {
 385                 scl_ver_mode = 0x1;   //scl_up
 386                 scl_v_factor = ((src_h-1)<<16)/(dst_h-1);
 387         }
 388
 389         //control   register0
 390         scl_reg0_value = (0x1ff<<16) | SCL_EN | (scl_hor_mode<<1) |
 391                         (scl_ver_mode<<3) | (bic_coe_sel<<5) |
 392                         (hor_down_mode<<7) | (ver_down_mode<<8) ;
 393         //factor    register1
 394         scl_reg1_value = (scl_v_factor << 16) | scl_h_factor ;
 395         //dsp_frame register2
 396         scl_reg2_value = dst_frame_vst<<16 | dst_frame_hst ;
 397         //dsp_h     register3
 398         scl_reg3_value = dsp_hs_end<<16 | dsp_htotal ;
 399         //dsp_hact  register4
 400         scl_reg4_value = dsp_hact_end <<16 | dsp_hact_st ;
 401         //dsp_v     register5
 402         scl_reg5_value = dsp_vs_end<<16 | dsp_vtotal ;
 403         //dsp_vact  register6
 404         scl_reg6_value = dsp_vact_end<<16 | dsp_vact_st ;
 405         //hbor      register7
 406         scl_reg7_value = dsp_hbor_end<<16 | dsp_hbor_st ;
 407         //vbor      register8
 408         scl_reg8_value = dsp_vbor_end<<16 | dsp_vbor_st ;
 409
 410         rk616->write_dev(rk616,SCL_REG1,&scl_reg1_value);
 411         rk616->write_dev(rk616,SCL_REG2,&scl_reg2_value);
 412         rk616->write_dev(rk616,SCL_REG3,&scl_reg3_value);
 413         rk616->write_dev(rk616,SCL_REG4,&scl_reg4_value);
 414         rk616->write_dev(rk616,SCL_REG5,&scl_reg5_value);
 415         rk616->write_dev(rk616,SCL_REG6,&scl_reg6_value);
 416         rk616->write_dev(rk616,SCL_REG7,&scl_reg7_value);
 417         rk616->write_dev(rk616,SCL_REG8,&scl_reg8_value);
 418         rk616->write_dev(rk616,SCL_REG0,&scl_reg0_value);
 419
 420         rk616_dbg(rk616->dev,"rk616 scaler enable\n");
 421 #endif
 422         return 0;
 423
 424 }
 425
 426
 427 static int rk616_dual_input_cfg(struct mfd_rk616 *rk616,rk_screen *screen,
 428                                         bool enable)
 429 {
 430         struct rk616_platform_data *pdata = rk616->pdata;
 431         struct rk616_route *route = &rk616->route;
 432
 433         route->vif0_bypass = VIF0_CLK_BYPASS;
 434         route->vif0_en     = 0;
 435         route->vif0_clk_sel = VIF0_CLKIN_SEL(VIF_CLKIN_SEL_PLL0);
 436         route->pll0_clk_sel = PLL0_CLK_SEL(LCD0_DCLK);
 437         route->pll1_clk_sel = PLL1_CLK_SEL(LCD1_DCLK);
 438         route->vif1_clk_sel = VIF1_CLKIN_SEL(VIF_CLKIN_SEL_PLL1);
 439         route->hdmi_sel     = HDMI_IN_SEL(HDMI_CLK_SEL_VIF1);
 440         if(enable)  //hdmi plug in
 441         {
 442                 route->vif1_bypass  = 0;
 443                 route->vif1_en      = 1;
 444
 445         }
 446         else  //hdmi plug out
 447         {
 448                 route->vif1_bypass = VIF1_CLK_BYPASS;
 449                 route->vif1_en     = 0;
 450         }
 451
 452         route->sclin_sel   = SCL_IN_SEL(SCL_SEL_VIF0); //from vif0
 453         route->scl_en      = 0;            //dual lcdc, scaler not needed
 454         route->dither_sel  = DITHER_IN_SEL(DITHER_SEL_VIF0); //dither from vif0
 455         route->lcd1_input  = 1;
 456
 457
 458         if(screen->type == SCREEN_RGB)
 459         {
 460                 route->lvds_en     = 1;
 461                 route->lvds_mode   = RGB; //rgb output
 462         }
 463         else if(screen->type == SCREEN_LVDS)
 464         {
 465                 route->lvds_en     = 1;
 466                 route->lvds_mode = LVDS;
 467                 route->lvds_ch_nr = pdata->lvds_ch_nr;
 468         }
 469         else if(screen->type == SCREEN_MIPI)
 470         {
 471                 route->lvds_en = 0;
 472         }
 473
 474
 475         return 0;
 476
 477 }
 478
 479 static int rk616_lcd0_input_lcd1_unused_cfg(struct mfd_rk616 *rk616,rk_screen *screen,
 480                                                         bool enable)
 481 {
 482         struct rk616_platform_data *pdata = rk616->pdata;
 483         struct rk616_route *route = &rk616->route;
 484
 485         if(enable)  //hdmi plug in
 486         {
 487                 route->vif0_bypass  = 0;
 488                 route->vif0_en      = 1;
 489                 route->vif0_clk_sel = VIF0_CLKIN_SEL(VIF_CLKIN_SEL_PLL0);
 490                 route->sclin_sel    = SCL_IN_SEL(SCL_SEL_VIF0); //from vif0
 491                 route->scl_en       = 1;
 492                 route->sclk_sel     = SCLK_SEL(SCLK_SEL_PLL1);
 493                 route->dither_sel   = DITHER_IN_SEL(DITHER_SEL_SCL); //dither from sclaer
 494                 route->hdmi_sel     = HDMI_IN_SEL(HDMI_CLK_SEL_VIF0);//from vif0
 495
 496         }
 497         else
 498         {
 499                 route->vif0_bypass = VIF0_CLK_BYPASS;
 500                 route->vif0_en     = 0;
 501                 route->sclin_sel   = SCL_IN_SEL(SCL_SEL_VIF0); //from vif0
 502                 route->scl_en      = 0;
 503                 route->dither_sel  = DITHER_IN_SEL(DITHER_SEL_VIF0); //dither from sclaer
 504                 route->hdmi_sel    = HDMI_IN_SEL(HDMI_CLK_SEL_VIF0);//from vif0
 505         }
 506         route->pll1_clk_sel = PLL1_CLK_SEL(LCD0_DCLK);
 507         route->pll0_clk_sel = PLL0_CLK_SEL(LCD0_DCLK);
 508         route->vif1_bypass = VIF1_CLK_BYPASS;
 509         route->vif1_en     = 0;
 510         route->lcd1_input  = 0;
 511
 512         if(screen->type == SCREEN_RGB)
 513         {
 514                 route->lvds_en     = 1;
 515                 route->lvds_mode   = RGB; //rgb output
 516         }
 517         else if(screen->type == SCREEN_LVDS)
 518         {
 519                 route->lvds_en     = 1;
 520                 route->lvds_mode = LVDS;
 521                 route->lvds_ch_nr = pdata->lvds_ch_nr;
 522         }
 523         else if(screen->type == SCREEN_MIPI)
 524         {
 525                 route->lvds_en = 0;
 526         }
 527
 528
 529         return 0;
 530 }
 531
 532
 533 static int rk616_lcd0_input_lcd1_output_cfg(struct mfd_rk616 *rk616,rk_screen *screen,
 534                                                         bool enable)
 535 {
 536         struct rk616_route *route = &rk616->route;
 537
 538         if(enable)
 539         {
 540                 route->vif0_bypass  = 0;
 541                 route->vif0_en      = 1;
 542                 route->vif0_clk_sel = VIF0_CLKIN_SEL(VIF_CLKIN_SEL_PLL0);
 543                 route->sclin_sel    = SCL_IN_SEL(SCL_SEL_VIF0); //from vif0
 544                 route->scl_en       = 1;
 545                 route->sclk_sel     = SCLK_SEL(SCLK_SEL_PLL1);
 546                 route->dither_sel   = DITHER_IN_SEL(DITHER_SEL_SCL); //dither from sclaer
 547                 route->hdmi_sel     = HDMI_IN_SEL(HDMI_CLK_SEL_VIF0);//from vif0
 548         }
 549         else
 550         {
 551                 route->vif0_bypass = VIF0_CLK_BYPASS;
 552                 route->vif0_en     = 0;
 553                 route->sclin_sel   = SCL_IN_SEL(SCL_SEL_VIF0); //from vif0
 554                 route->scl_en      = 0;
 555                 route->dither_sel  = DITHER_IN_SEL(DITHER_SEL_VIF0); //dither from sclaer
 556                 route->hdmi_sel    = HDMI_IN_SEL(HDMI_CLK_SEL_VIF0);//from vif0
 557         }
 558         route->pll0_clk_sel = PLL0_CLK_SEL(LCD0_DCLK);
 559         route->pll1_clk_sel = PLL1_CLK_SEL(LCD0_DCLK);
 560         route->vif1_bypass = VIF1_CLK_BYPASS;
 561         route->vif1_en = 0;
 562         route->lcd1_input = 0; //lcd1 as out put
 563         route->lvds_en  = 0;
 564
 565         //route->scl_en      = 0;
 566         //route->dither_sel  = DITHER_IN_SEL(DITHER_SEL_VIF0);
 567
 568         return 0;
 569
 570 }
 571
 572
 573 static int rk616_lcd0_unused_lcd1_input_cfg(struct mfd_rk616 *rk616,rk_screen *screen,
 574                                                         bool enable)
 575 {
 576         struct rk616_platform_data *pdata = rk616->pdata;
 577         struct rk616_route *route = &rk616->route;
 578
 579         route->pll0_clk_sel = PLL0_CLK_SEL(LCD1_DCLK);
 580         route->pll1_clk_sel = PLL1_CLK_SEL(LCD1_DCLK);
 581         route->vif0_bypass = VIF0_CLK_BYPASS;
 582         route->vif0_en     = 0;
 583         if(enable)
 584         {
 585                 route->vif1_bypass = 0;
 586                 route->vif1_en     = 1;
 587                 route->scl_bypass  = 0;
 588         }
 589         else
 590         {
 591                 route->vif1_bypass = VIF1_CLK_BYPASS;
 592                 route->vif1_en     = 0;
 593                 route->scl_bypass = 1; //1:1 scaler
 594         }
 595         route->vif1_clk_sel = VIF1_CLKIN_SEL(VIF_CLKIN_SEL_PLL1);
 596         route->sclin_sel   = SCL_IN_SEL(SCL_SEL_VIF1); //from vif1
 597         route->scl_en      = 1;
 598         route->sclk_sel    = SCLK_SEL(SCLK_SEL_PLL0);
 599
 600         route->dither_sel  = DITHER_IN_SEL(DITHER_SEL_SCL); //dither from sclaer
 601         route->hdmi_sel    = HDMI_IN_SEL(HDMI_CLK_SEL_VIF1); //from vif1
 602         route->lcd1_input  = 1;
 603         if(screen->type == SCREEN_RGB)
 604         {
 605                 route->lvds_en     = 1;
 606                 route->lvds_mode   = RGB; //rgb output
 607         }
 608         else if(screen->type == SCREEN_LVDS)
 609         {
 610                 route->lvds_en = 1;
 611                 route->lvds_mode = LVDS;
 612                 route->lvds_ch_nr = pdata->lvds_ch_nr;
 613         }
 614         else if(screen->type == SCREEN_MIPI)
 615         {
 616                 route->lvds_en = 0;
 617         }
 618
 619
 620         return 0;
 621 }
 622
 623 int  rk616_set_router(struct mfd_rk616 *rk616,rk_screen *screen,bool enable)
 624 {
 625         struct rk616_platform_data *pdata = rk616->pdata;
 626         int ret;
 627
 628         if((pdata->lcd0_func == INPUT) && (pdata->lcd1_func == INPUT))
 629         {
 630
 631                 ret = rk616_dual_input_cfg(rk616,screen,enable);
 632                 rk616_dbg(rk616->dev,"rk616 use dual input for dual display!\n");
 633         }
 634         else if((pdata->lcd0_func == INPUT) && (pdata->lcd1_func == UNUSED))
 635         {
 636                 ret = rk616_lcd0_input_lcd1_unused_cfg(rk616,screen,enable);
 637
 638                 rk616_dbg(rk616->dev,
 639                         "rk616 use lcd0 as input and lvds/rgb "
 640                         "port as output for dual display\n");
 641         }
 642         else if((pdata->lcd0_func == INPUT) && (pdata->lcd1_func == OUTPUT))
 643         {
 644                 ret = rk616_lcd0_input_lcd1_output_cfg(rk616,screen,enable);
 645
 646                 rk616_dbg(rk616->dev,
 647                         "rk616 use lcd0 as input and lcd1 as "
 648                         "output for dual display\n");
 649         }
 650         else if((pdata->lcd0_func == UNUSED) && (pdata->lcd1_func == INPUT))
 651         {
 652                 ret = rk616_lcd0_unused_lcd1_input_cfg(rk616,screen,enable);
 653                 rk616_dbg(rk616->dev,
 654                         "rk616 use lcd1 as input and lvds/rgb as "
 655                         "output for dual display\n");
 656         }
 657         else
 658         {
 659                 dev_err(rk616->dev,
 660                         "invalid configration,please check your"
 661                         "rk616_platform_data setting in your board file!\n");
 662                 return -EINVAL;
 663         }
 664
 665         return ret ;
 666
 667 }
 668
 669
 670
 671
 672 static int rk616_router_cfg(struct mfd_rk616 *rk616)
 673 {
 674         u32 val;
 675         int ret;
 676         struct rk616_route *route = &rk616->route;
 677         val = (route->pll0_clk_sel) | (route->pll1_clk_sel) |
 678                 PLL1_CLK_SEL_MASK | PLL0_CLK_SEL_MASK; //pll1 clk from lcdc1_dclk,pll0 clk from lcdc0_dclk,mux_lcdx = lcdx_clk
 679         ret = rk616->write_dev(rk616,CRU_CLKSEL0_CON,&val);
 680
 681         val = (route->sclk_sel) | SCLK_SEL_MASK;
 682         ret = rk616->write_dev(rk616,CRU_CLKSEL1_CON,&val);
 683
 684         val = (SCL_IN_SEL_MASK) | (DITHER_IN_SEL_MASK) | (HDMI_IN_SEL_MASK) |
 685                 (VIF1_CLKIN_SEL_MASK) | (VIF0_CLKIN_SEL_MASK) | (VIF1_CLK_BYPASS << 16) |
 686                 (VIF0_CLK_BYPASS << 16) |(route->sclin_sel) | (route->dither_sel) |
 687                 (route->hdmi_sel) | (route->vif1_bypass) | (route->vif0_bypass) |
 688                 (route->vif1_clk_sel)| (route->vif0_clk_sel);
 689         ret = rk616->write_dev(rk616,CRU_CLKSEL2_CON,&val);
 690
 691         return ret;
 692 }
 693
 694
 695 static int rk616_dither_cfg(struct mfd_rk616 *rk616,rk_screen *screen,bool enable)
 696 {
 697         u32 val = 0;
 698         int ret = 0;
 699         val = FRC_DCLK_INV | (FRC_DCLK_INV << 16);
 700         if((screen->face != OUT_P888) && enable)  //enable frc dither if the screen is not 24bit
 701                 val |= FRC_DITHER_EN | (FRC_DITHER_EN << 16);
 702                 //val |= (FRC_DITHER_EN << 16);
 703         else
 704                 val |= (FRC_DITHER_EN << 16);
 705         ret = rk616->write_dev(rk616,FRC_REG,&val);
 706
 707         return 0;
 708
 709 }
 710
 711 int rk616_display_router_cfg(struct mfd_rk616 *rk616,rk_screen *screen,bool enable)
 712 {
 713         int ret;
 714         rk_screen *hdmi_screen = screen->ext_screen;
 715         ret = rk616_set_router(rk616,screen,enable);
 716         if(ret < 0)
 717                 return ret;
 718         ret = rk616_router_cfg(rk616);
 719         ret = rk616_vif_cfg(rk616,hdmi_screen,0);
 720         ret = rk616_vif_cfg(rk616,hdmi_screen,1);
 721         ret = rk616_scaler_cfg(rk616,screen);
 722         ret = rk616_dither_cfg(rk616,screen,enable);
 723         return 0;
 724
 725 }
 726
 727 int rk616_set_vif(struct mfd_rk616 *rk616,rk_screen *screen,bool connect)
 728 {
 729         struct rk616_platform_data *pdata;
 730         if(!rk616)
 731         {
 732                 printk(KERN_ERR "%s:mfd rk616 is null!\n",__func__);
 733                 return -1;
 734         }
 735         else
 736         {
 737                 pdata = rk616->pdata;
 738         }
 739
 740         if(!connect)
 741         {
 742                 rk616_vif_disable(rk616,0);
 743                 rk616_vif_disable(rk616,1);
 744                 clk_set_rate(rk616->mclk, 11289600);
 745                 return 0;
 746         }
 747 #if defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)
 748         return 0;
 749 #else
 750         if((pdata->lcd0_func == INPUT) && (pdata->lcd1_func == INPUT))
 751         {
 752
 753                 rk616_dual_input_cfg(rk616,screen,connect);
 754                 rk616_dbg(rk616->dev,"rk616 use dual input for dual display!\n");
 755         }
 756         else if((pdata->lcd0_func == INPUT) && (pdata->lcd1_func == UNUSED))
 757         {
 758                 rk616_lcd0_input_lcd1_unused_cfg(rk616,screen,connect);
 759                 rk616_dbg(rk616->dev,"rk616 use lcd0 input for hdmi display!\n");
 760         }
 761         rk616_router_cfg(rk616);
 762         rk616_vif_cfg(rk616,screen,0);
 763         rk616_vif_cfg(rk616,screen,1);
 764         rk616_scaler_disable(rk616);
 765 #endif
 766
 767         return 0;
 768
 769
 770 }
 771
 772
 773
 774