drivers/mfd/rk616-core.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/module.h>
   4 #include <linux/delay.h>
   5 #include <linux/mfd/core.h>
   6 #include <linux/slab.h>
   7 #include <linux/mfd/rk616.h>
   8 #include <mach/iomux.h>
   9 #include <linux/err.h>
  10 #include <linux/uaccess.h>
  11 #if defined(CONFIG_DEBUG_FS)
  12 #include <linux/fs.h>
  13 #include <linux/debugfs.h>
  14 #include <linux/seq_file.h>
  15 #endif
  16
  17 #ifndef MHZ
  18 #define MHZ (1000*1000)
  19 #endif
  20
  21 static struct mfd_cell rk616_devs[] = {
  22         {
  23                 .name = "rk616-lvds",
  24                 .id = 0,
  25         },
  26         {
  27                 .name = "rk616-codec",
  28                 .id = 1,
  29         },
  30         {
  31                 .name = "rk616-hdmi",
  32                 .id = 2,
  33         },
  34         {
  35                 .name = "rk616-mipi",
  36                 .id = 3,
  37         },
  38 };
  39
  40 static int rk616_i2c_read_reg(struct mfd_rk616 *rk616, u16 reg,u32 *pval)
  41 {
  42         struct i2c_client * client = rk616->client;
  43         struct i2c_adapter *adap = client->adapter;
  44         struct i2c_msg msgs[2];
  45         int ret;
  46         char reg_buf[2];
  47
  48         memcpy(reg_buf, &reg, 2);
  49
  50         msgs[0].addr = client->addr;
  51         msgs[0].flags = client->flags;
  52         msgs[0].len = 2;
  53         msgs[0].buf = reg_buf;
  54         msgs[0].scl_rate = rk616->pdata->scl_rate;
  55         msgs[0].udelay = client->udelay;
  56
  57         msgs[1].addr = client->addr;
  58         msgs[1].flags = client->flags | I2C_M_RD;
  59         msgs[1].len = 4;
  60         msgs[1].buf = (char *)pval;
  61         msgs[1].scl_rate = rk616->pdata->scl_rate;
  62         msgs[1].udelay = client->udelay;
  63
  64         ret = i2c_transfer(adap, msgs, 2);
  65
  66
  67         return (ret == 2)? 4 : ret;
  68
  69 }
  70
  71 static int rk616_i2c_write_reg(struct mfd_rk616 *rk616, u16 reg,u32 *pval)
  72 {
  73         struct i2c_client *client = rk616->client;
  74         struct i2c_adapter *adap = client->adapter;
  75         struct i2c_msg msg;
  76         int ret;
  77         char *tx_buf = (char *)kmalloc(6, GFP_KERNEL);
  78         if(!tx_buf)
  79                 return -ENOMEM;
  80
  81         memcpy(tx_buf, &reg, 2);
  82         memcpy(tx_buf+2, (char *)pval, 4);
  83
  84         msg.addr = client->addr;
  85         msg.flags = client->flags;
  86         msg.len = 6;
  87         msg.buf = (char *)tx_buf;
  88         msg.scl_rate = rk616->pdata->scl_rate;
  89         msg.udelay = client->udelay;
  90
  91         ret = i2c_transfer(adap, &msg, 1);
  92         kfree(tx_buf);
  93
  94         return (ret == 1) ? 4 : ret;
  95 }
  96
  97
  98 #if defined(CONFIG_DEBUG_FS)
  99 static int rk616_reg_show(struct seq_file *s, void *v)
 100 {
 101         int i = 0;
 102         u32 val = 0;
 103         struct mfd_rk616 *rk616 = s->private;
 104         if(!rk616)
 105         {
 106                 dev_err(rk616->dev,"no mfd rk616!\n");
 107                 return 0;
 108         }
 109
 110         for(i=0;i<= CRU_CFGMISC_CON;i+=4)
 111         {
 112                 rk616->read_dev(rk616,i,&val);
 113                 if(i%16==0)
 114                         seq_printf(s,"\n0x%04x:",i);
 115                 seq_printf(s," %08x",val);
 116         }
 117         seq_printf(s,"\n");
 118
 119         return 0;
 120 }
 121
 122 static ssize_t rk616_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
 123 {
 124         struct mfd_rk616 *rk616 = file->f_path.dentry->d_inode->i_private;
 125         u32 reg;
 126         u32 val;
 127
 128         char kbuf[25];
 129         if (copy_from_user(kbuf, buf, count))
 130                 return -EFAULT;
 131         sscanf(kbuf, "%x%x", &reg,&val);
 132         dev_dbg(rk616->dev,"%s:reg:0x%04x val:0x%08x\n",__func__,reg,val);
 133         rk616->write_dev(rk616,reg,&val);
 134         return count;
 135 }
 136
 137 static int rk616_reg_open(struct inode *inode, struct file *file)
 138 {
 139         struct mfd_rk616 *rk616 = inode->i_private;
 140         return single_open(file,rk616_reg_show,rk616);
 141 }
 142
 143 static const struct file_operations rk616_reg_fops = {
 144         .owner          = THIS_MODULE,
 145         .open           = rk616_reg_open,
 146         .read           = seq_read,
 147         .write          = rk616_reg_write,
 148         .llseek         = seq_lseek,
 149         .release        = single_release,
 150 };
 151 #endif
 152
 153
 154 static u32 rk616_clk_gcd(u32 numerator, u32 denominator)
 155 {
 156         u32 a, b;
 157
 158         if (!numerator || !denominator)
 159                 return 0;
 160
 161         if (numerator > denominator) {
 162                 a = numerator;
 163                 b = denominator;
 164         } else {
 165                 a = denominator;
 166                 b = numerator;
 167         }
 168
 169         while (b != 0) {
 170                 int r = b;
 171                 b = a % b;
 172                 a = r;
 173         }
 174
 175         return a;
 176 }
 177
 178
 179 static int rk616_pll_par_calc(u32 fin_hz,u32 fout_hz,u32 *refdiv, u32 *fbdiv,
 180                                         u32 *postdiv1, u32 *postdiv2, u32 *frac)
 181 {
 182         // FIXME set postdiv1/2 always 1
 183         u32 gcd;
 184         u64 fin_64, frac_64;
 185         u32 f_frac;
 186         if(!fin_hz || !fout_hz)
 187                 return -EINVAL;
 188
 189         if(fin_hz / MHZ * MHZ == fin_hz && fout_hz /MHZ * MHZ == fout_hz)
 190         {
 191                 fin_hz /= MHZ;
 192                 fout_hz /= MHZ;
 193                 gcd = rk616_clk_gcd(fin_hz, fout_hz);
 194                 *refdiv = fin_hz / gcd;
 195                 *fbdiv = fout_hz / gcd;
 196                 *postdiv1 = 1;
 197                 *postdiv2 = 1;
 198
 199                 *frac = 0;
 200
 201         }
 202         else
 203         {
 204
 205                 gcd = rk616_clk_gcd(fin_hz / MHZ, fout_hz / MHZ);
 206                 *refdiv = fin_hz / MHZ / gcd;
 207                 *fbdiv = fout_hz / MHZ / gcd;
 208                 *postdiv1 = 1;
 209                 *postdiv2 = 1;
 210
 211                 *frac = 0;
 212
 213                 f_frac = (fout_hz % MHZ);
 214                 fin_64 = fin_hz;
 215                 do_div(fin_64, (u64)*refdiv);
 216                 frac_64 = (u64)f_frac << 24;
 217                 do_div(frac_64, fin_64);
 218                 *frac = (u32) frac_64;
 219                 printk(KERN_INFO "frac_64=%llx, frac=%u\n", frac_64, *frac);
 220         }
 221         printk(KERN_INFO "fin=%u,fout=%u,gcd=%u,refdiv=%u,fbdiv=%u,postdiv1=%u,postdiv2=%u,frac=%u\n",
 222                                 fin_hz, fout_hz, gcd, *refdiv, *fbdiv, *postdiv1, *postdiv2, *frac);
 223         return 0;
 224 }
 225
 226
 227 static  int  rk616_pll_wait_lock(struct mfd_rk616 *rk616,int id)
 228 {
 229         u32 delay = 10;
 230         u32 val = 0;
 231         int ret;
 232         int offset;
 233
 234         if(id == 0)  //PLL0
 235         {
 236                 offset = 0;
 237         }
 238         else // PLL1
 239         {
 240                 offset = 0x0c;
 241         }
 242         while (delay >= 1)
 243         {
 244                 ret = rk616->read_dev(rk616,CRU_PLL0_CON1 + offset,&val);
 245                 if (val&PLL0_LOCK)
 246                 {
 247                         dev_info(rk616->dev,"PLL%d locked\n",id);
 248                         break;
 249                 }
 250                 msleep(1);
 251                 delay--;
 252         }
 253         if (delay == 0)
 254         {
 255                 printk(KERN_ALERT "rk616 wait PLL%d lock time out!\n",id);
 256         }
 257
 258         return 0;
 259 }
 260
 261
 262
 263 int rk616_pll_pwr_down(struct mfd_rk616 *rk616,int id)
 264 {
 265         u32 val = 0;
 266         int ret;
 267         int offset;
 268         if(id == 0)  //PLL0
 269         {
 270                 offset = 0;
 271         }
 272         else // PLL1
 273         {
 274                 offset = 0x0c;
 275         }
 276
 277
 278         val = PLL0_PWR_DN | (PLL0_PWR_DN << 16);
 279         ret = rk616->write_dev(rk616,CRU_PLL0_CON1 + offset,&val);
 280
 281         return 0;
 282
 283 }
 284
 285
 286
 287 int rk616_pll_set_rate(struct mfd_rk616 *rk616,int id,u32 cfg_val,u32 frac)
 288 {
 289         u32 val = 0;
 290         int ret;
 291         int offset;
 292         u16 con0 = cfg_val & 0xffff;
 293         u16 con1 = (cfg_val >> 16)&0xffff;
 294         u32 fbdiv = con0 & 0xfff;
 295         u32 postdiv1 = (con0 >> 12)&0x7;
 296         u32 refdiv = con1 & 0x3f;
 297         u32 postdiv2 = (con1 >> 6) & 0x7;
 298         u8 mode = !frac;
 299
 300         if(id == 0)  //PLL0
 301         {
 302                 if(((rk616->pll0_rate >> 32) == cfg_val) &&
 303                         ((rk616->pll0_rate & 0xffffffff) == frac))
 304                 {
 305                         //return 0;
 306                 }
 307                 rk616->pll0_rate = ((u64)cfg_val << 32) | frac;
 308                 offset = 0;
 309         }
 310         else // PLL1
 311         {
 312                 if(((rk616->pll1_rate >> 32) == cfg_val) &&
 313                         ((rk616->pll1_rate & 0xffffffff) == frac))
 314                 {
 315                         // return 0;
 316                 }
 317                 rk616->pll1_rate = ((u64)cfg_val << 32) | frac;
 318                 offset = 0x0c;
 319         }
 320
 321
 322         val = PLL0_PWR_DN | (PLL0_PWR_DN << 16);
 323         ret = rk616->write_dev(rk616,CRU_PLL0_CON1 + offset,&val);
 324
 325
 326         ret = rk616->read_dev(rk616,CRU_PLL0_CON2 + offset,&val);
 327         val &= 0xff000000;
 328         if(frac)
 329                 val |= PLL0_FRAC(frac);
 330         else
 331                 val |= 0x800000; //default value
 332         ret = rk616->write_dev(rk616,CRU_PLL0_CON2 + offset,&val);
 333
 334         val = PLL0_POSTDIV1(postdiv1) | PLL0_FBDIV(fbdiv) | PLL0_POSTDIV1_MASK |
 335                 PLL0_FBDIV_MASK | (PLL0_BYPASS << 16);
 336         ret = rk616->write_dev(rk616,CRU_PLL0_CON0 + offset,&val);
 337
 338         val = PLL0_DIV_MODE(mode) | PLL0_POSTDIV2(postdiv2) | PLL0_REFDIV(refdiv) |
 339                 (PLL0_DIV_MODE_MASK) | PLL0_POSTDIV2_MASK | PLL0_REFDIV_MASK;
 340         ret = rk616->write_dev(rk616,CRU_PLL0_CON1 + offset,&val);
 341
 342         val = (PLL0_PWR_DN << 16);
 343         ret = rk616->write_dev(rk616,CRU_PLL0_CON1 + offset,&val);
 344
 345         rk616_pll_wait_lock(rk616,id);
 346
 347         msleep(5);
 348
 349         return 0;
 350
 351 }
 352 /***********************************
 353 default clk patch settiing:
 354 CLKIN-------->CODEC
 355 LCD_DCLK0--->PLL0--->Dither--->LVDS/MIPI
 356 LCD_DCLK1--->PLL1--->HDMI
 357 ************************************/
 358
 359 static int rk616_clk_common_init(struct mfd_rk616 *rk616)
 360 {
 361         u32 val = 0;
 362         int ret;
 363
 364         val = PLL1_CLK_SEL(LCD1_DCLK) | PLL0_CLK_SEL(LCD0_DCLK) | LCD1_CLK_DIV(0) |
 365                 LCD0_CLK_DIV(0) | PLL1_CLK_SEL_MASK | PLL0_CLK_SEL_MASK |
 366                 LCD1_CLK_DIV_MASK | LCD0_CLK_DIV_MASK; //pll1 clk from lcdc1_dclk,pll0 clk from lcdc0_dclk,mux_lcdx = lcdx_clk
 367         ret = rk616->write_dev(rk616,CRU_CLKSEL0_CON,&val);
 368
 369         val = SCLK_SEL(SCLK_SEL_PLL1) | CODEC_MCLK_SEL(CODEC_MCLK_SEL_12M) |
 370                 CODEC_MCLK_SEL_MASK | SCLK_SEL_MASK; //codec mclk from clkin
 371         ret = rk616->write_dev(rk616,CRU_CLKSEL1_CON,&val);
 372
 373         val = 0; //codec mck = clkin
 374         ret = rk616->write_dev(rk616,CRU_CODEC_DIV,&val);
 375
 376         val = (PLL0_BYPASS) | (PLL0_BYPASS << 16);  //bypass pll0
 377         ret = rk616->write_dev(rk616,CRU_PLL0_CON0,&val);
 378         val = PLL0_PWR_DN | (PLL0_PWR_DN << 16);
 379         ret = rk616->write_dev(rk616,CRU_PLL0_CON1,&val); //power down pll0
 380
 381         val = (PLL1_BYPASS) | (PLL1_BYPASS << 16);
 382         ret = rk616->write_dev(rk616,CRU_PLL1_CON0,&val);
 383
 384
 385         return 0;
 386 }
 387
 388
 389 static int rk616_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
 390 {
 391         int ret;
 392         struct mfd_rk616 *rk616 = NULL;
 393         struct clk *iis_clk;
 394
 395         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
 396         {
 397                 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
 398                 ret = -ENODEV;
 399         }
 400         rk616 = kzalloc(sizeof(struct mfd_rk616), GFP_KERNEL);
 401         if (rk616 == NULL)
 402         {
 403                 printk(KERN_ALERT "alloc for struct rk616 fail\n");
 404                 ret = -ENOMEM;
 405         }
 406
 407         rk616->dev = &client->dev;
 408         rk616->pdata = client->dev.platform_data;
 409         rk616->client = client;
 410         i2c_set_clientdata(client, rk616);
 411         dev_set_drvdata(rk616->dev,rk616);
 412
 413 #if defined(CONFIG_SND_RK29_SOC_I2S_8CH)
 414         iis_clk = clk_get_sys("rk29_i2s.0", "i2s");
 415 #elif defined(CONFIG_SND_RK29_SOC_I2S_2CH)
 416         iis_clk = clk_get_sys("rk29_i2s.1", "i2s");
 417 #else
 418         iis_clk = clk_get_sys("rk29_i2s.2", "i2s");
 419 #endif
 420         if (IS_ERR(iis_clk))
 421         {
 422                 dev_err(&client->dev,"failed to get i2s clk\n");
 423                 ret = PTR_ERR(iis_clk);
 424         }
 425         else
 426         {
 427                 rk616->mclk = iis_clk;
 428
 429                 #if defined(CONFIG_ARCH_RK29)
 430                 rk29_mux_api_set(GPIO2D0_I2S0CLK_MIIRXCLKIN_NAME, GPIO2H_I2S0_CLK);
 431                 #else
 432                 iomux_set(I2S0_CLK);
 433                 #endif
 434                 clk_enable(iis_clk);
 435                 clk_set_rate(iis_clk, 11289600);
 436                 //clk_put(iis_clk);
 437         }
 438
 439
 440         if(rk616->pdata->power_init)
 441                 rk616->pdata->power_init();
 442
 443         rk616->read_dev = rk616_i2c_read_reg;
 444         rk616->write_dev = rk616_i2c_write_reg;
 445
 446 #if defined(CONFIG_DEBUG_FS)
 447         rk616->debugfs_dir = debugfs_create_dir("rk616", NULL);
 448         if (IS_ERR(rk616->debugfs_dir))
 449         {
 450                 dev_err(rk616->dev,"failed to create debugfs dir for rk616!\n");
 451         }
 452         else
 453                 debugfs_create_file("core", S_IRUSR,rk616->debugfs_dir,rk616,&rk616_reg_fops);
 454 #endif
 455         rk616_clk_common_init(rk616);
 456         ret = mfd_add_devices(rk616->dev, -1,
 457                                       rk616_devs, ARRAY_SIZE(rk616_devs),
 458                                       NULL, rk616->irq_base);
 459
 460         dev_info(&client->dev,"rk616 core probe success!\n");
 461         return 0;
 462 }
 463
 464 static int __devexit rk616_i2c_remove(struct i2c_client *client)
 465 {
 466         return 0;
 467 }
 468
 469 static void rk616_core_shutdown(struct i2c_client *client)
 470 {
 471         struct mfd_rk616 *rk616 = i2c_get_clientdata(client);
 472         if(rk616->pdata->power_deinit)
 473                 rk616->pdata->power_deinit();
 474 }
 475
 476
 477 static const struct i2c_device_id id_table[] = {
 478         {"rk616", 0 },
 479         { }
 480 };
 481
 482 static struct i2c_driver rk616_i2c_driver  = {
 483         .driver = {
 484                 .name  = "rk616",
 485                 .owner = THIS_MODULE,
 486         },
 487         .probe          = &rk616_i2c_probe,
 488         .remove         = &rk616_i2c_remove,
 489         .shutdown       = &rk616_core_shutdown,
 490         .id_table       = id_table,
 491 };
 492
 493
 494 static int __init rk616_module_init(void)
 495 {
 496         return i2c_add_driver(&rk616_i2c_driver);
 497 }
 498
 499 static void __exit rk616_module_exit(void)
 500 {
 501         i2c_del_driver(&rk616_i2c_driver);
 502 }
 503
 504 subsys_initcall_sync(rk616_module_init);
 505 module_exit(rk616_module_exit);
 506
 507