2 * driver/mfd/ricoh619-irq.c
4 * Interrupt driver for RICOH RC5T619 power management chip.
6 * Copyright (C) 2012-2013 RICOH COMPANY,LTD
9 * Copyright (C) 2011 NVIDIA Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/i2c.h>
31 #include <linux/mfd/ricoh619.h>
32 #include <linux/irqdomain.h>
34 static DEFINE_MUTEX(int_flag_mutex);
45 static int gpedge_add[] = {
46 RICOH619_GPIO_GPEDGE1,
50 static int irq_en_add[] = {
58 RICOH619_INT_EN_GPIO2,
59 RICOH619_INT_MSK_CHGCTR,
60 RICOH619_INT_MSK_CHGSTS1,
61 RICOH619_INT_MSK_CHGSTS2,
62 RICOH619_INT_MSK_CHGERR,
63 RICOH619_INT_MSK_CHGEXTIF
66 static int irq_mon_add[] = {
67 RICOH619_INT_IR_SYS, //RICOH619_INT_MON_SYS,
68 RICOH619_INT_IR_DCDC, //RICOH619_INT_MON_DCDC,
69 RICOH619_INT_IR_RTC, //RICOH619_INT_MON_RTC,
72 RICOH619_INT_IR_ADCEND,
73 RICOH619_INT_IR_GPIOR,
74 RICOH619_INT_IR_GPIOF,
75 RICOH619_INT_IR_CHGCTR, //RICOH619_INT_MON_CHGCTR,
76 RICOH619_INT_IR_CHGSTS1, //RICOH619_INT_MON_CHGSTS1,
77 RICOH619_INT_IR_CHGSTS2, //RICOH619_INT_MON_CHGSTS2,
78 RICOH619_INT_IR_CHGERR, //RICOH619_INT_MON_CHGERR
79 RICOH619_INT_IR_CHGEXTIF //RICOH619_INT_MON_CHGEXTIF
82 static int irq_clr_add[] = {
88 RICOH619_INT_IR_ADCEND,
89 RICOH619_INT_IR_GPIOR,
90 RICOH619_INT_IR_GPIOF,
91 RICOH619_INT_IR_CHGCTR,
92 RICOH619_INT_IR_CHGSTS1,
93 RICOH619_INT_IR_CHGSTS2,
94 RICOH619_INT_IR_CHGERR,
95 RICOH619_INT_IR_CHGEXTIF
98 static int main_int_type[] = {
114 struct ricoh619_irq_data {
122 #define RICOH619_IRQ(_int_type, _master_bit, _grp_index, _int_bit, _mask_ind) \
124 .int_type = _int_type, \
125 .master_bit = _master_bit, \
126 .grp_index = _grp_index, \
127 .int_en_bit = _int_bit, \
128 .mask_reg_index = _mask_ind, \
131 static const struct ricoh619_irq_data ricoh619_irqs[RICOH619_NR_IRQS] = {
132 [RICOH619_IRQ_POWER_ON] = RICOH619_IRQ(SYS_INT, 0, 0, 0, 0),
133 [RICOH619_IRQ_EXTIN] = RICOH619_IRQ(SYS_INT, 0, 1, 1, 0),
134 [RICOH619_IRQ_PRE_VINDT] = RICOH619_IRQ(SYS_INT, 0, 2, 2, 0),
135 [RICOH619_IRQ_PREOT] = RICOH619_IRQ(SYS_INT, 0, 3, 3, 0),
136 [RICOH619_IRQ_POWER_OFF] = RICOH619_IRQ(SYS_INT, 0, 4, 4, 0),
137 [RICOH619_IRQ_NOE_OFF] = RICOH619_IRQ(SYS_INT, 0, 5, 5, 0),
138 [RICOH619_IRQ_WD] = RICOH619_IRQ(SYS_INT, 0, 6, 6, 0),
140 [RICOH619_IRQ_DC1LIM] = RICOH619_IRQ(DCDC_INT, 1, 0, 0, 1),
141 [RICOH619_IRQ_DC2LIM] = RICOH619_IRQ(DCDC_INT, 1, 1, 1, 1),
142 [RICOH619_IRQ_DC3LIM] = RICOH619_IRQ(DCDC_INT, 1, 2, 2, 1),
143 [RICOH619_IRQ_DC4LIM] = RICOH619_IRQ(DCDC_INT, 1, 3, 3, 1),
144 [RICOH619_IRQ_DC5LIM] = RICOH619_IRQ(DCDC_INT, 1, 4, 4, 1),
146 [RICOH619_IRQ_CTC] = RICOH619_IRQ(RTC_INT, 2, 0, 0, 2),
147 [RICOH619_IRQ_DALE] = RICOH619_IRQ(RTC_INT, 2, 1, 6, 2),
149 [RICOH619_IRQ_ILIMLIR] = RICOH619_IRQ(ADC_INT, 3, 0, 0, 3),
150 [RICOH619_IRQ_VBATLIR] = RICOH619_IRQ(ADC_INT, 3, 1, 1, 3),
151 [RICOH619_IRQ_VADPLIR] = RICOH619_IRQ(ADC_INT, 3, 2, 2, 3),
152 [RICOH619_IRQ_VUSBLIR] = RICOH619_IRQ(ADC_INT, 3, 3, 3, 3),
153 [RICOH619_IRQ_VSYSLIR] = RICOH619_IRQ(ADC_INT, 3, 4, 4, 3),
154 [RICOH619_IRQ_VTHMLIR] = RICOH619_IRQ(ADC_INT, 3, 5, 5, 3),
155 [RICOH619_IRQ_AIN1LIR] = RICOH619_IRQ(ADC_INT, 3, 6, 6, 3),
156 [RICOH619_IRQ_AIN0LIR] = RICOH619_IRQ(ADC_INT, 3, 7, 7, 3),
158 [RICOH619_IRQ_ILIMHIR] = RICOH619_IRQ(ADC_INT, 3, 8, 0, 4),
159 [RICOH619_IRQ_VBATHIR] = RICOH619_IRQ(ADC_INT, 3, 9, 1, 4),
160 [RICOH619_IRQ_VADPHIR] = RICOH619_IRQ(ADC_INT, 3, 10, 2, 4),
161 [RICOH619_IRQ_VUSBHIR] = RICOH619_IRQ(ADC_INT, 3, 11, 3, 4),
162 [RICOH619_IRQ_VSYSHIR] = RICOH619_IRQ(ADC_INT, 3, 12, 4, 4),
163 [RICOH619_IRQ_VTHMHIR] = RICOH619_IRQ(ADC_INT, 3, 13, 5, 4),
164 [RICOH619_IRQ_AIN1HIR] = RICOH619_IRQ(ADC_INT, 3, 14, 6, 4),
165 [RICOH619_IRQ_AIN0HIR] = RICOH619_IRQ(ADC_INT, 3, 15, 7, 4),
167 [RICOH619_IRQ_ADC_ENDIR] = RICOH619_IRQ(ADC_INT, 3, 16, 0, 5),
169 [RICOH619_IRQ_GPIO0] = RICOH619_IRQ(GPIO_INT, 4, 0, 0, 6),
170 [RICOH619_IRQ_GPIO1] = RICOH619_IRQ(GPIO_INT, 4, 1, 1, 6),
171 [RICOH619_IRQ_GPIO2] = RICOH619_IRQ(GPIO_INT, 4, 2, 2, 6),
172 [RICOH619_IRQ_GPIO3] = RICOH619_IRQ(GPIO_INT, 4, 3, 3, 6),
173 [RICOH619_IRQ_GPIO4] = RICOH619_IRQ(GPIO_INT, 4, 4, 4, 6),
175 [RICOH619_IRQ_FVADPDETSINT] = RICOH619_IRQ(CHG_INT, 6, 0, 0, 8),
176 [RICOH619_IRQ_FVUSBDETSINT] = RICOH619_IRQ(CHG_INT, 6, 1, 1, 8),
177 [RICOH619_IRQ_FVADPLVSINT] = RICOH619_IRQ(CHG_INT, 6, 2, 2, 8),
178 [RICOH619_IRQ_FVUSBLVSINT] = RICOH619_IRQ(CHG_INT, 6, 3, 3, 8),
179 [RICOH619_IRQ_FWVADPSINT] = RICOH619_IRQ(CHG_INT, 6, 4, 4, 8),
180 [RICOH619_IRQ_FWVUSBSINT] = RICOH619_IRQ(CHG_INT, 6, 5, 5, 8),
182 [RICOH619_IRQ_FONCHGINT] = RICOH619_IRQ(CHG_INT, 6, 6, 0, 9),
183 [RICOH619_IRQ_FCHGCMPINT] = RICOH619_IRQ(CHG_INT, 6, 7, 1, 9),
184 [RICOH619_IRQ_FBATOPENINT] = RICOH619_IRQ(CHG_INT, 6, 8, 2, 9),
185 [RICOH619_IRQ_FSLPMODEINT] = RICOH619_IRQ(CHG_INT, 6, 9, 3, 9),
186 [RICOH619_IRQ_FBTEMPJTA1INT] = RICOH619_IRQ(CHG_INT, 6, 10, 4, 9),
187 [RICOH619_IRQ_FBTEMPJTA2INT] = RICOH619_IRQ(CHG_INT, 6, 11, 5, 9),
188 [RICOH619_IRQ_FBTEMPJTA3INT] = RICOH619_IRQ(CHG_INT, 6, 12, 6, 9),
189 [RICOH619_IRQ_FBTEMPJTA4INT] = RICOH619_IRQ(CHG_INT, 6, 13, 7, 9),
191 [RICOH619_IRQ_FCURTERMINT] = RICOH619_IRQ(CHG_INT, 6, 14, 0, 10),
192 [RICOH619_IRQ_FVOLTERMINT] = RICOH619_IRQ(CHG_INT, 6, 15, 1, 10),
193 [RICOH619_IRQ_FICRVSINT] = RICOH619_IRQ(CHG_INT, 6, 16, 2, 10),
194 [RICOH619_IRQ_FPOOR_CHGCURINT] = RICOH619_IRQ(CHG_INT, 6, 17, 3, 10),
195 [RICOH619_IRQ_FOSCFDETINT1] = RICOH619_IRQ(CHG_INT, 6, 18, 4, 10),
196 [RICOH619_IRQ_FOSCFDETINT2] = RICOH619_IRQ(CHG_INT, 6, 19, 5, 10),
197 [RICOH619_IRQ_FOSCFDETINT3] = RICOH619_IRQ(CHG_INT, 6, 20, 6, 10),
198 [RICOH619_IRQ_FOSCMDETINT] = RICOH619_IRQ(CHG_INT, 6, 21, 7, 10),
200 [RICOH619_IRQ_FDIEOFFINT] = RICOH619_IRQ(CHG_INT, 6, 22, 0, 11),
201 [RICOH619_IRQ_FDIEERRINT] = RICOH619_IRQ(CHG_INT, 6, 23, 1, 11),
202 [RICOH619_IRQ_FBTEMPERRINT] = RICOH619_IRQ(CHG_INT, 6, 24, 2, 11),
203 [RICOH619_IRQ_FVBATOVINT] = RICOH619_IRQ(CHG_INT, 6, 25, 3, 11),
204 [RICOH619_IRQ_FTTIMOVINT] = RICOH619_IRQ(CHG_INT, 6, 26, 4, 11),
205 [RICOH619_IRQ_FRTIMOVINT] = RICOH619_IRQ(CHG_INT, 6, 27, 5, 11),
206 [RICOH619_IRQ_FVADPOVSINT] = RICOH619_IRQ(CHG_INT, 6, 28, 6, 11),
207 [RICOH619_IRQ_FVUSBOVSINT] = RICOH619_IRQ(CHG_INT, 6, 29, 7, 11),
209 [RICOH619_IRQ_FGCDET] = RICOH619_IRQ(CHG_INT, 6, 30, 0, 12),
210 [RICOH619_IRQ_FPCDET] = RICOH619_IRQ(CHG_INT, 6, 31, 1, 12),
211 [RICOH619_IRQ_FWARN_ADP] = RICOH619_IRQ(CHG_INT, 6, 32, 3, 12),
214 static const inline struct ricoh619_irq_data * irq_to_ricoh619_irq(struct ricoh619 *ricoh619, int irq)
216 struct irq_data *data = irq_get_irq_data(irq);
217 return &ricoh619_irqs[data->hwirq];
219 static void ricoh619_irq_lock(struct irq_data *irq_data)
221 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
223 mutex_lock(&ricoh619->irq_lock);
226 static void ricoh619_irq_unmask(struct irq_data *irq_data)
228 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
229 const struct ricoh619_irq_data *data= irq_to_ricoh619_irq(ricoh619,irq_data->irq);
230 mutex_lock(&int_flag_mutex);
232 ricoh619->group_irq_en[data->master_bit] |= (1 << data->grp_index);
233 if (ricoh619->group_irq_en[data->master_bit])
234 ricoh619->intc_inten_reg |= 1 << data->master_bit;
236 if (data->master_bit == 6) /* if Charger */
237 ricoh619->irq_en_reg[data->mask_reg_index]
238 &= ~(1 << data->int_en_bit);
240 ricoh619->irq_en_reg[data->mask_reg_index]
241 |= 1 << data->int_en_bit;
242 mutex_unlock(&int_flag_mutex);
245 static void ricoh619_irq_mask(struct irq_data *irq_data)
247 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
248 const struct ricoh619_irq_data *data= irq_to_ricoh619_irq(ricoh619,irq_data->irq);
249 mutex_lock(&int_flag_mutex);
251 ricoh619->group_irq_en[data->master_bit] &= ~(1 << data->grp_index);
252 if (!ricoh619->group_irq_en[data->master_bit])
253 ricoh619->intc_inten_reg &= ~(1 << data->master_bit);
255 if (data->master_bit == 6) /* if Charger */
256 ricoh619->irq_en_reg[data->mask_reg_index]
257 |= 1 << data->int_en_bit;
259 ricoh619->irq_en_reg[data->mask_reg_index]
260 &= ~(1 << data->int_en_bit);
261 mutex_unlock(&int_flag_mutex);
264 static void ricoh619_irq_sync_unlock(struct irq_data *irq_data)
266 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
269 for (i = 0; i < ARRAY_SIZE(ricoh619->gpedge_reg); i++) {
270 if (ricoh619->gpedge_reg[i] != ricoh619->gpedge_cache[i]) {
271 if (!WARN_ON(ricoh619_write(ricoh619->dev, gpedge_add[i],ricoh619->gpedge_reg[i])))
272 ricoh619->gpedge_cache[i] =ricoh619->gpedge_reg[i];
276 for (i = 0; i < ARRAY_SIZE(ricoh619->irq_en_reg); i++) {
277 if (ricoh619->irq_en_reg[i] != ricoh619->irq_en_cache[i]) {
278 if (!WARN_ON(ricoh619_write(ricoh619->dev, irq_en_add[i],ricoh619->irq_en_reg[i])))
279 ricoh619->irq_en_cache[i] =ricoh619->irq_en_reg[i];
283 if (ricoh619->intc_inten_reg != ricoh619->intc_inten_cache) {
284 if (!WARN_ON(ricoh619_write(ricoh619->dev,RICOH619_INTC_INTEN, ricoh619->intc_inten_reg)))
285 ricoh619->intc_inten_cache = ricoh619->intc_inten_reg;
288 mutex_unlock(&ricoh619->irq_lock);
291 static int ricoh619_irq_set_type(struct irq_data *irq_data, unsigned int type)
293 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
294 const struct ricoh619_irq_data *data= irq_to_ricoh619_irq(ricoh619,irq_data->irq);
299 if (data->int_type & GPIO_INT) {
300 gpedge_index = data->int_en_bit / 4;
301 gpedge_bit_pos = data->int_en_bit % 4;
303 if (type & IRQ_TYPE_EDGE_FALLING)
306 if (type & IRQ_TYPE_EDGE_RISING)
309 ricoh619->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
310 ricoh619->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
311 ricoh619_irq_unmask(irq_data);
316 #ifdef CONFIG_PM_SLEEP
317 static int ricoh619_irq_set_wake(struct irq_data *irq_data, unsigned int on)
319 struct ricoh619 *ricoh619 = irq_data_get_irq_chip_data(irq_data);
320 return irq_set_irq_wake(ricoh619->chip_irq, on); //i2c->irq
323 #define ricoh619_irq_set_wake NULL
325 u8 ricoh619_pwr_key_reg;
326 static irqreturn_t ricoh619_irq(int irq, void *data)
328 struct ricoh619 *ricoh619 = data;
329 u8 int_sts[MAX_INTERRUPT_MASKS];
333 unsigned int rtc_int_sts = 0;
336 ret = ricoh619_read(ricoh619->dev, RICOH619_INT_IR_SYS, &ricoh619_pwr_key_reg);
338 /* Clear the status */
339 for (i = 0; i < MAX_INTERRUPT_MASKS; i++)
342 ret = ricoh619_read(ricoh619->dev, RICOH619_INTC_INTMON,
344 // printk("PMU1: %s: master_int=0x%x\n", __func__, master_int);
346 dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
347 "error: %d\n", RICOH619_INTC_INTMON, ret);
351 for (i = 0; i < MAX_INTERRUPT_MASKS; ++i) {
352 /* Even if INTC_INTMON register = 1, INT signal might not output
353 because INTC_INTMON register indicates only interrupt facter level.
354 So remove the following procedure */
355 if (!(master_int & main_int_type[i]))
358 ret = ricoh619_read(ricoh619->dev,
359 irq_mon_add[i], &int_sts[i]);
360 // printk("PMU2: %s: int_sts[%d]=0x%x\n", __func__,i, int_sts[i]);
362 dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
363 "error: %d\n", irq_mon_add[i], ret);
370 if (main_int_type[i] & RTC_INT) {
371 // Changes status bit position from RTCCNT2 to RTCCNT1
373 if (int_sts[i] & 0x1)
374 rtc_int_sts |= BIT(6);
375 if (int_sts[i] & 0x4)
376 rtc_int_sts |= BIT(0);
379 if(irq_clr_add[i] == RICOH619_INT_IR_RTC)
382 ret = ricoh619_write(ricoh619->dev,
383 irq_clr_add[i], int_sts[i]);
385 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
386 "error: %d\n", irq_clr_add[i], ret);
390 ret = ricoh619_write(ricoh619->dev,
391 irq_clr_add[i], ~int_sts[i]);
393 dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
394 "error: %d\n", irq_clr_add[i], ret);
397 /* Mask Charger Interrupt */
398 if (main_int_type[i] & CHG_INT) {
400 ret = ricoh619_write(ricoh619->dev,
401 irq_en_add[i], 0xff);
403 dev_err(ricoh619->dev,
404 "Error in write reg 0x%02x error: %d\n",
409 /* Mask ADC Interrupt */
410 if (main_int_type[i] & ADC_INT) {
412 ret = ricoh619_write(ricoh619->dev,
415 dev_err(ricoh619->dev,
416 "Error in write reg 0x%02x error: %d\n",
422 if (main_int_type[i] & RTC_INT)
423 int_sts[i] = rtc_int_sts;
427 /* Merge gpio interrupts for rising and falling case*/
428 int_sts[6] |= int_sts[7];
430 /* Call interrupt handler if enabled */
431 mutex_lock(&int_flag_mutex);
432 for (i = 0; i <RICOH619_NR_IRQS; ++i) {
433 const struct ricoh619_irq_data *data = &ricoh619_irqs[i];
434 if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&(ricoh619->group_irq_en[data->master_bit] & (1 << data->grp_index))){
435 cur_irq = irq_find_mapping(ricoh619->irq_domain, i);
437 handle_nested_irq(cur_irq);
440 mutex_unlock(&int_flag_mutex);
442 // printk(KERN_INFO "PMU: %s: out\n", __func__);
446 static struct irq_chip ricoh619_irq_chip = {
448 //.irq_mask = ricoh619_irq_mask,
449 //.irq_unmask = ricoh619_irq_unmask,
450 .irq_enable = ricoh619_irq_unmask,
451 .irq_disable = ricoh619_irq_mask,
452 .irq_bus_lock = ricoh619_irq_lock,
453 .irq_bus_sync_unlock = ricoh619_irq_sync_unlock,
454 .irq_set_type = ricoh619_irq_set_type,
455 .irq_set_wake = ricoh619_irq_set_wake,
458 static int ricoh619_irq_domain_map(struct irq_domain *d, unsigned int irq,
461 struct ricoh619 *ricoh619 = d->host_data;
463 irq_set_chip_data(irq, ricoh619);
464 irq_set_chip_and_handler(irq, &ricoh619_irq_chip, handle_edge_irq);
465 irq_set_nested_thread(irq, 1);
467 set_irq_flags(irq, IRQF_VALID);
469 irq_set_noprobe(irq);
474 static struct irq_domain_ops ricoh619_irq_domain_ops = {
475 .map = ricoh619_irq_domain_map,
478 int ricoh619_irq_init(struct ricoh619 *ricoh619, int irq,
479 struct ricoh619_platform_data *pdata)
481 int i, ret,val,irq_type,flags;
483 struct irq_domain *domain;
485 // printk("%s,line=%d\n", __func__,__LINE__);
487 dev_warn(ricoh619->dev, "No interrupt support, no core IRQ\n");
491 mutex_init(&ricoh619->irq_lock);
493 /* Initialize all locals to 0 */
494 for (i = 0; i < 2; i++) {
495 ricoh619->irq_en_cache[i] = 0;
496 ricoh619->irq_en_reg[i] = 0;
500 ricoh619->irq_en_cache[2] = 0x20;
501 ricoh619->irq_en_reg[2] = 0x20;
503 /* Initialize all locals to 0 */
504 for (i = 3; i < 8; i++) {
505 ricoh619->irq_en_cache[i] = 0;
506 ricoh619->irq_en_reg[i] = 0;
509 // Charger Mask register must be set to 1 for masking Int output.
510 for (i = 8; i < MAX_INTERRUPT_MASKS; i++) {
511 ricoh619->irq_en_cache[i] = 0xff;
512 ricoh619->irq_en_reg[i] = 0xff;
515 ricoh619->intc_inten_cache = 0;
516 ricoh619->intc_inten_reg = 0;
517 for (i = 0; i < MAX_GPEDGE_REG; i++) {
518 ricoh619->gpedge_cache[i] = 0;
519 ricoh619->gpedge_reg[i] = 0;
522 /* Initailize all int register to 0 */
523 for (i = 0; i < MAX_INTERRUPT_MASKS; i++) {
524 ret = ricoh619_write(ricoh619->dev,
526 ricoh619->irq_en_reg[i]);
528 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
529 "error: %d\n", irq_en_add[i], ret);
532 for (i = 0; i < MAX_GPEDGE_REG; i++) {
533 ret = ricoh619_write(ricoh619->dev,
535 ricoh619->gpedge_reg[i]);
537 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
538 "error: %d\n", gpedge_add[i], ret);
541 ret = ricoh619_write(ricoh619->dev, RICOH619_INTC_INTEN, 0x0);
543 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
544 "error: %d\n", RICOH619_INTC_INTEN, ret);
546 /* Clear all interrupts in case they woke up active. */
547 for (i = 0; i < MAX_INTERRUPT_MASKS; i++) {
548 if(irq_clr_add[i] != RICOH619_INT_IR_RTC)
550 ret = ricoh619_write(ricoh619->dev,
553 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
554 "error: %d\n", irq_clr_add[i], ret);
558 ret = ricoh619_read(ricoh619->dev,
559 RICOH619_INT_IR_RTC, ®_data);
561 dev_err(ricoh619->dev, "Error in reading reg 0x%02x "
562 "error: %d\n", RICOH619_INT_IR_RTC, ret);
564 ret = ricoh619_write(ricoh619->dev,
565 RICOH619_INT_IR_RTC, reg_data);
567 dev_err(ricoh619->dev, "Error in writing reg 0x%02x "
568 "error: %d\n", RICOH619_INT_IR_RTC, ret);
573 if (pdata->irq_gpio && !ricoh619->chip_irq) {
574 ricoh619->chip_irq = gpio_to_irq(pdata->irq_gpio);
576 if (pdata->irq_gpio) {
577 ret = gpio_request(pdata->irq_gpio, "ricoh619_pmic_irq");
579 dev_err(ricoh619->dev,
580 "Failed to request gpio %d with ret:"
581 "%d\n", pdata->irq_gpio, ret);
584 gpio_direction_input(pdata->irq_gpio);
585 val = gpio_get_value(pdata->irq_gpio);
587 irq_type = IRQ_TYPE_LEVEL_LOW;
588 flags = IRQF_TRIGGER_LOW;
591 irq_type = IRQ_TYPE_LEVEL_HIGH;
592 flags = IRQF_TRIGGER_HIGH;
594 gpio_free(pdata->irq_gpio);
595 pr_info("%s: ricoh619_pmic_irq=%x\n", __func__, val);
599 domain = irq_domain_add_linear(NULL, RICOH619_NR_IRQS,
600 &ricoh619_irq_domain_ops, ricoh619);
602 dev_err(ricoh619->dev, "could not create irq domain\n");
605 ricoh619->irq_domain = domain;
606 ret = devm_request_threaded_irq(ricoh619->dev,ricoh619->chip_irq, NULL, ricoh619_irq, flags |IRQF_ONESHOT, "ricoh619", ricoh619);
607 // ret = devm_request_threaded_irq(ricoh619->dev,ricoh619->chip_irq, NULL, ricoh619_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT , "ricoh619", ricoh619);
609 irq_set_irq_type(ricoh619->chip_irq, irq_type);
610 enable_irq_wake(ricoh619->chip_irq);
614 int ricoh619_irq_exit(struct ricoh619 *ricoh619)