2 * max77693-irq.c - Interrupt controller support for MAX77693
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * SangYoung Son <hello.son@samsung.com>
7 * This program is not provided / owned by Maxim Integrated Products.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * This driver is based on max8997-irq.c
26 #include <linux/err.h>
27 #include <linux/irq.h>
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/irqdomain.h>
31 #include <linux/mfd/max77693.h>
32 #include <linux/mfd/max77693-private.h>
34 static const u8 max77693_mask_reg[] = {
35 [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK,
36 [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK,
37 [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK,
38 [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1,
39 [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2,
40 [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3,
43 static struct regmap *max77693_get_regmap(struct max77693_dev *max77693,
44 enum max77693_irq_source src)
47 case LED_INT ... CHG_INT:
48 return max77693->regmap;
49 case MUIC_INT1 ... MUIC_INT3:
50 return max77693->regmap_muic;
52 return ERR_PTR(-EINVAL);
56 struct max77693_irq_data {
58 enum max77693_irq_source group;
61 #define DECLARE_IRQ(idx, _group, _mask) \
62 [(idx)] = { .group = (_group), .mask = (_mask) }
63 static const struct max77693_irq_data max77693_irqs[] = {
64 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0),
65 DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1),
66 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2),
67 DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3),
68 DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4),
70 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0),
71 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1),
72 DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3),
74 DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0),
75 DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2),
76 DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3),
77 DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4),
78 DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6),
80 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0),
81 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1),
82 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2),
83 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3),
85 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0),
86 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1),
87 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2),
88 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3),
89 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4),
90 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5),
92 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0),
93 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1),
94 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2),
95 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3),
96 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4),
97 DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5),
100 static void max77693_irq_lock(struct irq_data *data)
102 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
104 mutex_lock(&max77693->irqlock);
107 static void max77693_irq_sync_unlock(struct irq_data *data)
109 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
112 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
113 u8 mask_reg = max77693_mask_reg[i];
114 struct regmap *map = max77693_get_regmap(max77693, i);
116 if (mask_reg == MAX77693_REG_INVALID ||
119 max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i];
121 max77693_write_reg(map, max77693_mask_reg[i],
122 max77693->irq_masks_cur[i]);
125 mutex_unlock(&max77693->irqlock);
128 static const inline struct max77693_irq_data *
129 irq_to_max77693_irq(struct max77693_dev *max77693, int irq)
131 return &max77693_irqs[irq];
134 static void max77693_irq_mask(struct irq_data *data)
136 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
137 const struct max77693_irq_data *irq_data =
138 irq_to_max77693_irq(max77693, data->irq);
140 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
143 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
144 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
146 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
149 static void max77693_irq_unmask(struct irq_data *data)
151 struct max77693_dev *max77693 = irq_get_chip_data(data->irq);
152 const struct max77693_irq_data *irq_data =
153 irq_to_max77693_irq(max77693, data->irq);
155 if (irq_data->group >= MAX77693_IRQ_GROUP_NR)
158 if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3)
159 max77693->irq_masks_cur[irq_data->group] |= irq_data->mask;
161 max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
164 static struct irq_chip max77693_irq_chip = {
166 .irq_bus_lock = max77693_irq_lock,
167 .irq_bus_sync_unlock = max77693_irq_sync_unlock,
168 .irq_mask = max77693_irq_mask,
169 .irq_unmask = max77693_irq_unmask,
172 #define MAX77693_IRQSRC_CHG (1 << 0)
173 #define MAX77693_IRQSRC_TOP (1 << 1)
174 #define MAX77693_IRQSRC_FLASH (1 << 2)
175 #define MAX77693_IRQSRC_MUIC (1 << 3)
176 static irqreturn_t max77693_irq_thread(int irq, void *data)
178 struct max77693_dev *max77693 = data;
179 u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {};
184 ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC,
187 dev_err(max77693->dev, "Failed to read interrupt source: %d\n",
192 if (irq_src & MAX77693_IRQSRC_CHG)
194 ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT,
197 if (irq_src & MAX77693_IRQSRC_TOP)
199 ret = max77693_read_reg(max77693->regmap,
200 MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]);
202 if (irq_src & MAX77693_IRQSRC_FLASH)
204 ret = max77693_read_reg(max77693->regmap,
205 MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]);
207 if (irq_src & MAX77693_IRQSRC_MUIC)
208 /* MUIC INT1 ~ INT3 */
209 max77693_bulk_read(max77693->regmap_muic, MAX77693_MUIC_REG_INT1,
210 MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]);
213 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
214 if (i >= MUIC_INT1 && i <= MUIC_INT3)
215 irq_reg[i] &= max77693->irq_masks_cur[i];
217 irq_reg[i] &= ~max77693->irq_masks_cur[i];
221 for (i = 0; i < MAX77693_IRQ_NR; i++) {
222 if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) {
223 cur_irq = irq_find_mapping(max77693->irq_domain, i);
225 handle_nested_irq(cur_irq);
232 int max77693_irq_resume(struct max77693_dev *max77693)
235 max77693_irq_thread(0, max77693);
240 static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq,
243 struct max77693_dev *max77693 = d->host_data;
245 irq_set_chip_data(irq, max77693);
246 irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq);
247 irq_set_nested_thread(irq, 1);
249 set_irq_flags(irq, IRQF_VALID);
251 irq_set_noprobe(irq);
256 static struct irq_domain_ops max77693_irq_domain_ops = {
257 .map = max77693_irq_domain_map,
260 int max77693_irq_init(struct max77693_dev *max77693)
262 struct irq_domain *domain;
267 mutex_init(&max77693->irqlock);
269 /* Mask individual interrupt sources */
270 for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) {
272 /* MUIC IRQ 0:MASK 1:NOT MASK */
273 /* Other IRQ 1:MASK 0:NOT MASK */
274 if (i >= MUIC_INT1 && i <= MUIC_INT3) {
275 max77693->irq_masks_cur[i] = 0x00;
276 max77693->irq_masks_cache[i] = 0x00;
278 max77693->irq_masks_cur[i] = 0xff;
279 max77693->irq_masks_cache[i] = 0xff;
281 map = max77693_get_regmap(max77693, i);
283 if (IS_ERR_OR_NULL(map))
285 if (max77693_mask_reg[i] == MAX77693_REG_INVALID)
287 if (i >= MUIC_INT1 && i <= MUIC_INT3)
288 max77693_write_reg(map, max77693_mask_reg[i], 0x00);
290 max77693_write_reg(map, max77693_mask_reg[i], 0xff);
293 domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR,
294 &max77693_irq_domain_ops, max77693);
296 dev_err(max77693->dev, "could not create irq domain\n");
300 max77693->irq_domain = domain;
302 /* Unmask max77693 interrupt */
303 ret = max77693_read_reg(max77693->regmap,
304 MAX77693_PMIC_REG_INTSRC_MASK, &intsrc_mask);
306 dev_err(max77693->dev, "fail to read PMIC register\n");
310 intsrc_mask &= ~(MAX77693_IRQSRC_CHG);
311 intsrc_mask &= ~(MAX77693_IRQSRC_FLASH);
312 intsrc_mask &= ~(MAX77693_IRQSRC_MUIC);
313 ret = max77693_write_reg(max77693->regmap,
314 MAX77693_PMIC_REG_INTSRC_MASK, intsrc_mask);
316 dev_err(max77693->dev, "fail to write PMIC register\n");
320 ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread,
321 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
322 "max77693-irq", max77693);
324 dev_err(max77693->dev, "Failed to request IRQ %d: %d\n",
331 void max77693_irq_exit(struct max77693_dev *max77693)
334 free_irq(max77693->irq, max77693);