2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Zain Wang <zain.wang@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * Some ideas are from chrome ec and fairchild GPL fusb302 driver.
12 #include <linux/delay.h>
13 #include <linux/extcon.h>
14 #include <linux/gpio.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_gpio.h>
18 #include <linux/regmap.h>
22 #define FUSB302_MAX_REG (FUSB_REG_FIFO + 50)
23 #define FUSB_MS_TO_NS(x) ((s64)x * 1000 * 1000)
25 #define FUSB_MODE_DRP 0
26 #define FUSB_MODE_UFP 1
27 #define FUSB_MODE_DFP 2
28 #define FUSB_MODE_ASS 3
30 #define TYPEC_CC_VOLT_OPEN 0
31 #define TYPEC_CC_VOLT_RA 1
32 #define TYPEC_CC_VOLT_RD 2
33 #define TYPEC_CC_VOLT_RP 3
35 #define EVENT_CC BIT(0)
36 #define EVENT_RX BIT(1)
37 #define EVENT_TX BIT(2)
38 #define EVENT_REC_RESET BIT(3)
39 #define EVENT_WORK_CONTINUE BIT(5)
40 #define EVENT_TIMER_MUX BIT(6)
41 #define EVENT_TIMER_STATE BIT(7)
42 #define FLAG_EVENT (EVENT_RX | EVENT_TIMER_MUX | \
45 #define PIN_MAP_A BIT(0)
46 #define PIN_MAP_B BIT(1)
47 #define PIN_MAP_C BIT(2)
48 #define PIN_MAP_D BIT(3)
49 #define PIN_MAP_E BIT(4)
50 #define PIN_MAP_F BIT(5)
52 static u8 fusb30x_port_used;
53 static struct fusb30x_chip *fusb30x_port_info[256];
55 static bool is_write_reg(struct device *dev, unsigned int reg)
57 if (reg >= FUSB_REG_FIFO)
60 return ((reg < (FUSB_REG_CONTROL4 + 1)) && (reg > 0x01)) ?
64 static bool is_volatile_reg(struct device *dev, unsigned int reg)
66 if (reg > FUSB_REG_CONTROL4)
70 case FUSB_REG_CONTROL0:
71 case FUSB_REG_CONTROL1:
72 case FUSB_REG_CONTROL3:
79 struct regmap_config fusb302_regmap_config = {
82 .writeable_reg = is_write_reg,
83 .volatile_reg = is_volatile_reg,
84 .max_register = FUSB302_MAX_REG,
85 .cache_type = REGCACHE_RBTREE,
88 static void dump_notify_info(struct fusb30x_chip *chip)
90 dev_dbg(chip->dev, "port %d\n", chip->port_num);
91 dev_dbg(chip->dev, "orientation %d\n", chip->notify.orientation);
92 dev_dbg(chip->dev, "power_role %d\n", chip->notify.power_role);
93 dev_dbg(chip->dev, "data_role %d\n", chip->notify.data_role);
94 dev_dbg(chip->dev, "cc %d\n", chip->notify.is_cc_connected);
95 dev_dbg(chip->dev, "pd %d\n", chip->notify.is_pd_connected);
96 dev_dbg(chip->dev, "enter_mode %d\n", chip->notify.is_enter_mode);
97 dev_dbg(chip->dev, "pin support %d\n",
98 chip->notify.pin_assignment_support);
99 dev_dbg(chip->dev, "pin def %d\n", chip->notify.pin_assignment_def);
100 dev_dbg(chip->dev, "attention %d\n", chip->notify.attention);
103 static const unsigned int fusb302_cable[] = {
115 void fusb_irq_disable(struct fusb30x_chip *chip)
117 unsigned long irqflags = 0;
119 spin_lock_irqsave(&chip->irq_lock, irqflags);
120 if (chip->enable_irq) {
121 disable_irq_nosync(chip->gpio_int_irq);
122 chip->enable_irq = 0;
124 dev_warn(chip->dev, "irq have already disabled\n");
126 spin_unlock_irqrestore(&chip->irq_lock, irqflags);
129 void fusb_irq_enable(struct fusb30x_chip *chip)
131 unsigned long irqflags = 0;
133 spin_lock_irqsave(&chip->irq_lock, irqflags);
134 if (!chip->enable_irq) {
135 enable_irq(chip->gpio_int_irq);
136 chip->enable_irq = 1;
138 spin_unlock_irqrestore(&chip->irq_lock, irqflags);
141 static void platform_fusb_notify(struct fusb30x_chip *chip)
143 bool plugged = 0, flip = 0, dfp = 0, ufp = 0, dp = 0, usb_ss = 0;
144 union extcon_property_value property;
146 if (chip->notify.is_cc_connected)
147 chip->notify.orientation = chip->cc_polarity + 1;
149 /* avoid notify repeated */
150 if (memcmp(&chip->notify, &chip->notify_cmp,
151 sizeof(struct notify_info))) {
152 dump_notify_info(chip);
153 chip->notify.attention = 0;
154 memcpy(&chip->notify_cmp, &chip->notify,
155 sizeof(struct notify_info));
157 plugged = chip->notify.is_cc_connected ||
158 chip->notify.is_pd_connected;
159 flip = chip->notify.orientation ?
160 (chip->notify.orientation - 1) : 0;
161 dp = chip->notify.is_enter_mode;
165 usb_ss = (chip->notify.pin_assignment_def &
166 (PIN_MAP_B | PIN_MAP_D | PIN_MAP_F)) ? 1 : 0;
167 } else if (chip->notify.data_role) {
170 } else if (plugged) {
175 property.intval = flip;
176 extcon_set_property(chip->extcon, EXTCON_USB,
177 EXTCON_PROP_USB_TYPEC_POLARITY, property);
178 extcon_set_property(chip->extcon, EXTCON_USB_HOST,
179 EXTCON_PROP_USB_TYPEC_POLARITY, property);
180 extcon_set_property(chip->extcon, EXTCON_DISP_DP,
181 EXTCON_PROP_USB_TYPEC_POLARITY, property);
183 property.intval = usb_ss;
184 extcon_set_property(chip->extcon, EXTCON_USB,
185 EXTCON_PROP_USB_SS, property);
186 extcon_set_property(chip->extcon, EXTCON_USB_HOST,
187 EXTCON_PROP_USB_SS, property);
188 extcon_set_property(chip->extcon, EXTCON_DISP_DP,
189 EXTCON_PROP_USB_SS, property);
190 extcon_set_state(chip->extcon, EXTCON_USB, ufp);
191 extcon_set_state(chip->extcon, EXTCON_USB_HOST, dfp);
192 extcon_set_state(chip->extcon, EXTCON_DISP_DP, dp);
193 extcon_sync(chip->extcon, EXTCON_USB);
194 extcon_sync(chip->extcon, EXTCON_USB_HOST);
195 extcon_sync(chip->extcon, EXTCON_DISP_DP);
199 static bool platform_get_device_irq_state(struct fusb30x_chip *chip)
201 return !gpiod_get_value(chip->gpio_int);
204 static void fusb_timer_start(struct hrtimer *timer, int ms)
208 ktime = ktime_set(0, FUSB_MS_TO_NS(ms));
209 hrtimer_start(timer, ktime, HRTIMER_MODE_REL);
212 static void platform_set_vbus_lvl_enable(struct fusb30x_chip *chip, int vbus_5v,
215 if (chip->gpio_vbus_5v) {
216 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_5v);
217 /* Only set state here, don't sync notifier to PMIC */
218 extcon_set_state(chip->extcon, EXTCON_USB_VBUS_EN, vbus_5v);
220 extcon_set_state(chip->extcon, EXTCON_USB_VBUS_EN, vbus_5v);
221 extcon_sync(chip->extcon, EXTCON_USB_VBUS_EN);
222 dev_info(chip->dev, "fusb302 send extcon to enable vbus 5v\n");
225 if (chip->gpio_vbus_other)
226 gpiod_set_raw_value(chip->gpio_vbus_5v, vbus_other);
229 static void set_state(struct fusb30x_chip *chip, enum connection_state state)
231 dev_dbg(chip->dev, "port %d, state %d\n", chip->port_num, state);
233 dev_info(chip->dev, "PD disabled\n");
234 chip->conn_state = state;
237 chip->work_continue = 1;
240 static int tcpm_get_message(struct fusb30x_chip *chip)
245 regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, 3);
246 chip->rec_head = (buf[1] & 0xff) | ((buf[2] << 8) & 0xff00);
248 len = PD_HEADER_CNT(chip->rec_head) << 2;
249 regmap_raw_read(chip->regmap, FUSB_REG_FIFO, buf, len + 4);
251 memcpy(chip->rec_load, buf, len);
256 static void fusb302_flush_rx_fifo(struct fusb30x_chip *chip)
258 tcpm_get_message(chip);
261 static int tcpm_get_cc(struct fusb30x_chip *chip, int *CC1, int *CC2)
267 *CC1 = TYPEC_CC_VOLT_OPEN;
268 *CC2 = TYPEC_CC_VOLT_OPEN;
270 if (chip->cc_state & 0x01)
275 if (chip->cc_state & 0x04) {
276 regmap_read(chip->regmap, FUSB_REG_SWITCHES0, &store);
278 /* measure cc1 first */
279 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
280 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
281 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
282 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
283 SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
285 usleep_range(250, 300);
287 regmap_read(chip->regmap, FUSB_REG_STATUS0, &val);
288 val &= STATUS0_BC_LVL;
292 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
293 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2 |
294 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
295 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
296 SWITCHES0_PDWN1 | SWITCHES0_PDWN2 |
298 usleep_range(250, 300);
300 regmap_read(chip->regmap, FUSB_REG_STATUS0, &val);
301 val &= STATUS0_BC_LVL;
305 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
306 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
309 if (chip->cc_state & 0x01) {
310 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
320 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
331 regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x26 << 2);
332 usleep_range(250, 300);
334 regmap_read(chip->regmap, FUSB_REG_STATUS0, &val);
336 if (val & STATUS0_COMP) {
337 *CC_MEASURE = TYPEC_CC_VOLT_OPEN;
339 regmap_write(chip->regmap, FUSB_REG_MEASURE, 0x05 << 2);
340 usleep_range(250, 300);
342 regmap_read(chip->regmap, FUSB_REG_STATUS0, &val);
344 if (val & STATUS0_COMP)
345 *CC_MEASURE = TYPEC_CC_VOLT_RA;
347 *CC_MEASURE = TYPEC_CC_VOLT_RD;
353 static int tcpm_set_cc(struct fusb30x_chip *chip, int mode)
357 val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
358 SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
364 if (chip->togdone_pullup)
365 val |= SWITCHES0_PU_EN2;
367 val |= SWITCHES0_PU_EN1;
370 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
373 val |= SWITCHES0_PDWN1 | SWITCHES0_PDWN2;
379 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0, mask, val);
383 static int tcpm_set_rx_enable(struct fusb30x_chip *chip, int enable)
388 if (chip->cc_polarity)
389 val |= SWITCHES0_MEAS_CC2;
391 val |= SWITCHES0_MEAS_CC1;
392 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
393 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
395 fusb302_flush_rx_fifo(chip);
396 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
397 SWITCHES1_AUTO_CRC, SWITCHES1_AUTO_CRC);
400 * bit of a hack here.
401 * when this function is called to disable rx (enable=0)
402 * using it as an indication of detach (gulp!)
403 * to reset our knowledge of where
404 * the toggle state machine landed.
406 chip->togdone_pullup = 0;
409 tcpm_set_cc(chip, FUSB_MODE_DRP);
410 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
411 CONTROL2_TOG_RD_ONLY,
412 CONTROL2_TOG_RD_ONLY);
414 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
415 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
417 regmap_update_bits(chip->regmap,
418 FUSB_REG_SWITCHES1, SWITCHES1_AUTO_CRC, 0);
424 static int tcpm_set_msg_header(struct fusb30x_chip *chip)
426 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
427 SWITCHES1_POWERROLE | SWITCHES1_DATAROLE,
428 (chip->notify.power_role << 7) |
429 (chip->notify.data_role << 4));
430 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
431 SWITCHES1_SPECREV, 2 << 5);
435 static int tcpm_set_polarity(struct fusb30x_chip *chip, bool polarity)
439 #ifdef FUSB_VCONN_SUPPORT
440 if (chip->vconn_enabled) {
442 val |= SWITCHES0_VCONN_CC1;
444 val |= SWITCHES0_VCONN_CC2;
449 val |= SWITCHES0_MEAS_CC2;
451 val |= SWITCHES0_MEAS_CC1;
453 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
454 SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2 |
455 SWITCHES0_MEAS_CC1 | SWITCHES0_MEAS_CC2,
460 val |= SWITCHES1_TXCC2;
462 val |= SWITCHES1_TXCC1;
463 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES1,
464 SWITCHES1_TXCC1 | SWITCHES1_TXCC2,
467 chip->cc_polarity = polarity;
472 static int tcpm_set_vconn(struct fusb30x_chip *chip, int enable)
477 tcpm_set_polarity(chip, chip->cc_polarity);
479 val &= ~(SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2);
480 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
481 SWITCHES0_VCONN_CC1 | SWITCHES0_VCONN_CC2,
484 chip->vconn_enabled = enable;
488 static void fusb302_pd_reset(struct fusb30x_chip *chip)
490 regmap_write(chip->regmap, FUSB_REG_RESET, RESET_PD_RESET);
491 regmap_reinit_cache(chip->regmap, &fusb302_regmap_config);
494 static void tcpm_init(struct fusb30x_chip *chip)
499 regmap_read(chip->regmap, FUSB_REG_DEVICEID, &tmp);
500 chip->chip_id = (u8)tmp;
501 platform_set_vbus_lvl_enable(chip, 0, 0);
502 chip->notify.is_cc_connected = 0;
505 /* restore default settings */
506 regmap_update_bits(chip->regmap, FUSB_REG_RESET, RESET_SW_RESET,
508 fusb302_pd_reset(chip);
509 /* set auto_retry and number of retries */
510 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
511 CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES,
512 CONTROL3_AUTO_RETRY | CONTROL3_N_RETRIES),
516 val &= ~(MASK_M_BC_LVL | MASK_M_COLLISION | MASK_M_ALERT |
518 regmap_write(chip->regmap, FUSB_REG_MASK, val);
521 val &= ~(MASKA_M_TOGDONE | MASKA_M_RETRYFAIL | MASKA_M_HARDSENT |
522 MASKA_M_TXSENT | MASKA_M_HARDRST);
523 regmap_write(chip->regmap, FUSB_REG_MASKA, val);
526 val = ~MASKB_M_GCRCSEND;
527 regmap_write(chip->regmap, FUSB_REG_MASKB, val);
530 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
531 CONTROL2_MODE | CONTROL2_TOGGLE,
532 (1 << 1) | CONTROL2_TOGGLE);
534 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
535 CONTROL2_TOG_RD_ONLY,
536 CONTROL2_TOG_RD_ONLY);
538 /* Interrupts Enable */
539 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL0, CONTROL0_INT_MASK,
542 tcpm_set_polarity(chip, 0);
543 tcpm_set_vconn(chip, 0);
545 regmap_write(chip->regmap, FUSB_REG_POWER, 0xf);
548 static void pd_execute_hard_reset(struct fusb30x_chip *chip)
552 if (chip->notify.power_role)
553 set_state(chip, policy_src_transition_default);
555 set_state(chip, policy_snk_transition_default);
558 static void tcpc_alert(struct fusb30x_chip *chip, int *evt)
560 int interrupt, interrupta, interruptb;
563 regmap_read(chip->regmap, FUSB_REG_INTERRUPT, &interrupt);
564 regmap_read(chip->regmap, FUSB_REG_INTERRUPTA, &interrupta);
565 regmap_read(chip->regmap, FUSB_REG_INTERRUPTB, &interruptb);
567 if (interrupt & INTERRUPT_BC_LVL) {
568 if (chip->notify.is_cc_connected)
572 if (interrupt & INTERRUPT_VBUSOK) {
573 if (chip->notify.is_cc_connected)
577 if (interrupta & INTERRUPTA_TOGDONE) {
579 regmap_read(chip->regmap, FUSB_REG_STATUS1A, &val);
580 chip->cc_state = ((u8)val >> 3) & 0x07;
582 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL2,
586 val &= ~(SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
587 SWITCHES0_PDWN1 | SWITCHES0_PDWN2);
589 if (chip->cc_state | 0x01)
590 val |= SWITCHES0_PU_EN1;
592 val |= SWITCHES0_PU_EN2;
594 regmap_update_bits(chip->regmap, FUSB_REG_SWITCHES0,
595 SWITCHES0_PU_EN1 | SWITCHES0_PU_EN2 |
596 SWITCHES0_PDWN1 | SWITCHES0_PDWN2,
600 if (interrupta & INTERRUPTA_TXSENT) {
602 fusb302_flush_rx_fifo(chip);
603 chip->tx_state = tx_success;
606 if (interruptb & INTERRUPTB_GCRCSENT)
609 if (interrupta & INTERRUPTA_HARDRST) {
610 fusb302_pd_reset(chip);
611 pd_execute_hard_reset(chip);
612 *evt |= EVENT_REC_RESET;
615 if (interrupta & INTERRUPTA_RETRYFAIL) {
617 chip->tx_state = tx_failed;
620 if (interrupta & INTERRUPTA_HARDSENT) {
621 chip->tx_state = tx_success;
622 chip->timer_state = T_DISABLED;
627 static void mux_alert(struct fusb30x_chip *chip, int *evt)
629 if (!chip->timer_mux) {
630 *evt |= EVENT_TIMER_MUX;
631 chip->timer_mux = T_DISABLED;
634 if (!chip->timer_state) {
635 *evt |= EVENT_TIMER_STATE;
636 chip->timer_state = T_DISABLED;
639 if (chip->work_continue) {
640 *evt |= EVENT_WORK_CONTINUE;
641 chip->work_continue = 0;
645 static void set_state_unattached(struct fusb30x_chip *chip)
647 dev_info(chip->dev, "connection has disconnected\n");
649 tcpm_set_rx_enable(chip, 0);
650 chip->conn_state = unattached;
651 tcpm_set_cc(chip, FUSB_MODE_DRP);
653 /* claer notify_info */
654 memset(&chip->notify, 0, sizeof(struct notify_info));
655 platform_fusb_notify(chip);
660 static int tcpm_check_vbus(struct fusb30x_chip *chip)
664 /* Read status register */
665 regmap_read(chip->regmap, FUSB_REG_STATUS0, &val);
667 return (val & STATUS0_VBUSOK) ? 1 : 0;
670 static void set_mesg(struct fusb30x_chip *chip, int cmd, int is_DMT)
673 struct PD_CAP_INFO *pd_cap_info = &chip->pd_cap_info;
675 chip->send_head = ((chip->msg_id & 0x7) << 9) |
676 ((chip->notify.power_role & 0x1) << 8) |
678 ((chip->notify.data_role & 0x1) << 5);
682 case DMT_SOURCECAPABILITIES:
683 chip->send_head |= ((chip->n_caps_used & 0x3) << 12) | (cmd & 0xf);
685 for (i = 0; i < chip->n_caps_used; i++) {
686 chip->send_load[i] = (pd_cap_info->supply_type << 30) |
687 (pd_cap_info->dual_role_power << 29) |
688 (pd_cap_info->usb_suspend_support << 28) |
689 (pd_cap_info->externally_powered << 27) |
690 (pd_cap_info->usb_communications_cap << 26) |
691 (pd_cap_info->data_role_swap << 25) |
692 (pd_cap_info->peak_current << 20) |
693 (chip->source_power_supply[i] << 10) |
694 (chip->source_max_current[i]);
698 chip->send_head |= ((1 << 12) | (cmd & 0xf));
699 /* send request with FVRDO */
700 chip->send_load[0] = (chip->pos_power << 28) |
706 switch (CAP_POWER_TYPE(chip->rec_load[chip->pos_power - 1])) {
709 chip->send_load[0] |= ((CAP_FPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
710 chip->send_load[0] |= (CAP_FPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
714 chip->send_load[0] |= ((CAP_VPDO_VOLTAGE(chip->rec_load[chip->pos_power - 1]) << 10) & 0x3ff);
715 chip->send_load[0] |= (CAP_VPDO_CURRENT(chip->rec_load[chip->pos_power - 1]) & 0x3ff);
718 /* not meet battery caps */
722 case DMT_SINKCAPABILITIES:
724 case DMT_VENDERDEFINED:
730 chip->send_head |= (cmd & 0xf);
734 static void set_vdm_mesg(struct fusb30x_chip *chip, int cmd, int type, int mode)
736 chip->send_head = (chip->msg_id & 0x7) << 9;
737 chip->send_head |= (chip->notify.power_role & 0x1) << 8;
739 chip->send_head = ((chip->msg_id & 0x7) << 9) |
740 ((chip->notify.power_role & 0x1) << 8) |
742 ((chip->notify.data_role & 0x1) << 5) |
743 (DMT_VENDERDEFINED & 0xf);
745 chip->send_load[0] = (1 << 15) |
751 case VDM_DISCOVERY_ID:
752 case VDM_DISCOVERY_SVIDS:
754 chip->send_load[0] |= (0xff00 << 16);
755 chip->send_head |= (1 << 12);
757 case VDM_DISCOVERY_MODES:
758 chip->send_load[0] |=
759 (chip->vdm_svid[chip->val_tmp >> 1] << 16);
760 chip->send_head |= (1 << 12);
763 chip->send_head |= (1 << 12);
764 chip->send_load[0] |= (mode << 8) | (0xff01 << 16);
767 chip->send_head |= (1 << 12);
768 chip->send_load[0] |= (0x0f << 8) | (0xff01 << 16);
770 case VDM_DP_STATUS_UPDATE:
771 chip->send_head |= (2 << 12);
772 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
773 chip->send_load[1] = 5;
776 chip->send_head |= (2 << 12);
777 chip->send_load[0] |= (1 << 8) | (0xff01 << 16);
778 chip->send_load[1] = (chip->notify.pin_assignment_def << 8) |
786 static enum tx_state policy_send_hardrst(struct fusb30x_chip *chip, int evt)
788 switch (chip->tx_state) {
790 regmap_update_bits(chip->regmap, FUSB_REG_CONTROL3,
791 CONTROL3_SEND_HARDRESET,
792 CONTROL3_SEND_HARDRESET);
793 chip->tx_state = tx_busy;
794 chip->timer_state = T_BMC_TIMEOUT;
795 fusb_timer_start(&chip->timer_state_machine,
799 if (evt & EVENT_TIMER_STATE)
800 chip->tx_state = tx_success;
803 return chip->tx_state;
806 static enum tx_state policy_send_data(struct fusb30x_chip *chip)
812 switch (chip->tx_state) {
814 senddata[pos++] = FUSB_TKN_SYNC1;
815 senddata[pos++] = FUSB_TKN_SYNC1;
816 senddata[pos++] = FUSB_TKN_SYNC1;
817 senddata[pos++] = FUSB_TKN_SYNC2;
819 len = PD_HEADER_CNT(chip->send_head) << 2;
820 senddata[pos++] = FUSB_TKN_PACKSYM | ((len + 2) & 0x1f);
822 senddata[pos++] = chip->send_head & 0xff;
823 senddata[pos++] = (chip->send_head >> 8) & 0xff;
825 memcpy(&senddata[pos], chip->send_load, len);
828 senddata[pos++] = FUSB_TKN_JAMCRC;
829 senddata[pos++] = FUSB_TKN_EOP;
830 senddata[pos++] = FUSB_TKN_TXOFF;
831 senddata[pos++] = FUSB_TKN_TXON;
833 regmap_raw_write(chip->regmap, FUSB_REG_FIFO, senddata, pos);
834 chip->tx_state = tx_busy;
842 return chip->tx_state;
845 static void process_vdm_msg(struct fusb30x_chip *chip)
847 u32 vdm_header = chip->rec_load[0];
851 /* can't procee unstructed vdm msg */
852 if (!GET_VDMHEAD_STRUCT_TYPE(vdm_header))
855 switch (GET_VDMHEAD_CMD_TYPE(vdm_header)) {
857 switch (GET_VDMHEAD_CMD(vdm_header)) {
859 dev_info(chip->dev, "attention, dp_status %x\n",
861 chip->notify.attention = 1;
865 dev_warn(chip->dev, "rec unknown init vdm msg\n");
870 switch (GET_VDMHEAD_CMD(vdm_header)) {
871 case VDM_DISCOVERY_ID:
872 chip->vdm_id = chip->rec_load[1];
874 case VDM_DISCOVERY_SVIDS:
875 for (i = 0; i < 6; i++) {
876 tmp = (chip->rec_load[i + 1] >> 16) &
879 chip->vdm_svid[i * 2] = tmp;
880 chip->vdm_svid_num++;
885 tmp = (chip->rec_load[i + 1] & 0x0000ffff);
887 chip->vdm_svid[i * 2 + 1] = tmp;
888 chip->vdm_svid_num++;
894 case VDM_DISCOVERY_MODES:
895 /* indicate there are some vdo modes */
896 if (PD_HEADER_CNT(chip->rec_head) > 1) {
899 * enter first mode default
901 if (!((chip->rec_load[1] >> 8) & 0x3f)) {
905 chip->notify.pin_assignment_support = 0;
906 chip->notify.pin_assignment_def = 0;
907 chip->notify.pin_assignment_support =
908 (chip->rec_load[1] >> 8) & 0x3f;
909 tmp = chip->notify.pin_assignment_support;
910 for (i = 0; i < 6; i++) {
916 chip->notify.pin_assignment_def = 0x20 >> i;
923 case VDM_DP_STATUS_UPDATE:
924 dev_dbg(chip->dev, "dp_status 0x%x\n",
931 "DP config successful, pin_assignment 0x%x\n",
932 chip->notify.pin_assignment_def);
933 chip->notify.is_enter_mode = 1;
940 dev_warn(chip->dev, "REC NACK for 0x%x\n",
941 GET_VDMHEAD_CMD(vdm_header));
943 chip->vdm_state = 0xff;
948 static int vdm_send_discoveryid(struct fusb30x_chip *chip, int evt)
952 switch (chip->vdm_send_state) {
954 set_vdm_mesg(chip, VDM_DISCOVERY_ID, VDM_TYPE_INIT, 0);
957 chip->vdm_send_state++;
959 tmp = policy_send_data(chip);
960 if (tmp == tx_success) {
961 chip->vdm_send_state++;
962 chip->timer_state = T_SENDER_RESPONSE;
963 fusb_timer_start(&chip->timer_state_machine,
965 } else if (tmp == tx_failed) {
966 dev_warn(chip->dev, "VDM_DISCOVERY_ID send failed\n");
967 /* disable auto_vdm_machine */
968 chip->vdm_state = 0xff;
971 if (chip->vdm_send_state != 2)
974 if (evt & EVENT_TIMER_STATE) {
975 dev_warn(chip->dev, "VDM_DISCOVERY_ID time out\n");
976 chip->vdm_state = 0xff;
977 chip->work_continue = 1;
982 chip->vdm_send_state = 0;
988 static int vdm_send_discoverysvid(struct fusb30x_chip *chip, int evt)
992 switch (chip->vdm_send_state) {
994 set_vdm_mesg(chip, VDM_DISCOVERY_SVIDS, VDM_TYPE_INIT, 0);
995 memset(chip->vdm_svid, 0, 12);
996 chip->vdm_svid_num = 0;
998 chip->vdm_send_state++;
1000 tmp = policy_send_data(chip);
1001 if (tmp == tx_success) {
1002 chip->vdm_send_state++;
1003 chip->timer_state = T_SENDER_RESPONSE;
1004 fusb_timer_start(&chip->timer_state_machine,
1006 } else if (tmp == tx_failed) {
1007 dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS send failed\n");
1008 /* disable auto_vdm_machine */
1009 chip->vdm_state = 0xff;
1012 if (chip->vdm_send_state != 2)
1015 if (evt & EVENT_TIMER_STATE) {
1016 dev_warn(chip->dev, "VDM_DISCOVERY_SVIDS time out\n");
1017 chip->vdm_state = 0xff;
1018 chip->work_continue = 1;
1021 if (!chip->vdm_svid_num)
1023 chip->vdm_send_state = 0;
1026 return -EINPROGRESS;
1029 static int vdm_send_discoverymodes(struct fusb30x_chip *chip, int evt)
1033 if ((chip->val_tmp >> 1) != chip->vdm_svid_num) {
1034 switch (chip->vdm_send_state) {
1036 set_vdm_mesg(chip, VDM_DISCOVERY_MODES,
1039 chip->vdm_send_state++;
1041 tmp = policy_send_data(chip);
1042 if (tmp == tx_success) {
1043 chip->vdm_send_state++;
1044 chip->timer_state = T_SENDER_RESPONSE;
1045 fusb_timer_start(&chip->timer_state_machine,
1047 } else if (tmp == tx_failed) {
1049 "VDM_DISCOVERY_MODES send failed\n");
1050 chip->vdm_state = 0xff;
1053 if (chip->vdm_send_state != 2)
1056 if (evt & EVENT_TIMER_STATE) {
1058 "VDM_DISCOVERY_MODES time out\n");
1059 chip->vdm_state = 0xff;
1060 chip->work_continue = 1;
1063 if (!(chip->val_tmp & 1))
1065 chip->val_tmp &= 0xfe;
1067 chip->vdm_send_state = 0;
1068 chip->work_continue = 1;
1076 return -EINPROGRESS;
1079 static int vdm_send_entermode(struct fusb30x_chip *chip, int evt)
1083 switch (chip->vdm_send_state) {
1085 set_vdm_mesg(chip, VDM_ENTER_MODE, VDM_TYPE_INIT, 1);
1087 chip->vdm_send_state++;
1088 chip->notify.is_enter_mode = 0;
1090 tmp = policy_send_data(chip);
1091 if (tmp == tx_success) {
1092 chip->vdm_send_state++;
1093 chip->timer_state = T_SENDER_RESPONSE;
1094 fusb_timer_start(&chip->timer_state_machine,
1096 } else if (tmp == tx_failed) {
1097 dev_warn(chip->dev, "VDM_ENTER_MODE send failed\n");
1098 /* disable auto_vdm_machine */
1099 chip->vdm_state = 0xff;
1102 if (chip->vdm_send_state != 2)
1105 if (evt & EVENT_TIMER_STATE) {
1106 dev_warn(chip->dev, "VDM_ENTER_MODE time out\n");
1107 chip->vdm_state = 0xff;
1108 chip->work_continue = 1;
1114 chip->vdm_send_state = 0;
1117 return -EINPROGRESS;
1120 static int vdm_send_getdpstatus(struct fusb30x_chip *chip, int evt)
1124 switch (chip->vdm_send_state) {
1126 set_vdm_mesg(chip, VDM_DP_STATUS_UPDATE, VDM_TYPE_INIT, 1);
1128 chip->vdm_send_state++;
1130 tmp = policy_send_data(chip);
1131 if (tmp == tx_success) {
1132 chip->vdm_send_state++;
1133 chip->timer_state = T_SENDER_RESPONSE;
1134 fusb_timer_start(&chip->timer_state_machine,
1136 } else if (tmp == tx_failed) {
1138 "VDM_DP_STATUS_UPDATE send failed\n");
1139 /* disable auto_vdm_machine */
1140 chip->vdm_state = 0xff;
1143 if (chip->vdm_send_state != 2)
1146 if (evt & EVENT_TIMER_STATE) {
1147 dev_warn(chip->dev, "VDM_DP_STATUS_UPDATE time out\n");
1148 chip->vdm_state = 0xff;
1149 chip->work_continue = 1;
1155 chip->vdm_send_state = 0;
1158 return -EINPROGRESS;
1161 static int vdm_send_dpconfig(struct fusb30x_chip *chip, int evt)
1165 switch (chip->vdm_send_state) {
1167 set_vdm_mesg(chip, VDM_DP_CONFIG, VDM_TYPE_INIT, 0);
1169 chip->vdm_send_state++;
1171 tmp = policy_send_data(chip);
1172 if (tmp == tx_success) {
1173 chip->vdm_send_state++;
1174 chip->timer_state = T_SENDER_RESPONSE;
1175 fusb_timer_start(&chip->timer_state_machine,
1177 } else if (tmp == tx_failed) {
1178 dev_warn(chip->dev, "vdm_send_dpconfig send failed\n");
1179 /* disable auto_vdm_machine */
1180 chip->vdm_state = 0xff;
1183 if (chip->vdm_send_state != 2)
1186 if (evt & EVENT_TIMER_STATE) {
1187 dev_warn(chip->dev, "vdm_send_dpconfig time out\n");
1188 chip->vdm_state = 0xff;
1189 chip->work_continue = 1;
1195 chip->vdm_send_state = 0;
1198 return -EINPROGRESS;
1201 static void auto_vdm_machine(struct fusb30x_chip *chip, int evt)
1203 switch (chip->vdm_state) {
1205 if (vdm_send_discoveryid(chip, evt))
1210 if (vdm_send_discoverysvid(chip, evt))
1215 if (vdm_send_discoverymodes(chip, evt))
1220 if (vdm_send_entermode(chip, evt))
1225 if (vdm_send_dpconfig(chip, evt))
1227 chip->vdm_state = 6;
1230 if (vdm_send_getdpstatus(chip, evt))
1235 platform_fusb_notify(chip);
1240 static void fusb_state_disabled(struct fusb30x_chip *chip, int evt)
1242 platform_fusb_notify(chip);
1245 static void fusb_state_unattached(struct fusb30x_chip *chip, int evt)
1247 chip->notify.is_cc_connected = 0;
1248 if ((evt & EVENT_CC) && chip->cc_state) {
1249 if (chip->cc_state & 0x04)
1250 set_state(chip, attach_wait_sink);
1252 set_state(chip, attach_wait_source);
1254 tcpm_get_cc(chip, &chip->cc1, &chip->cc2);
1255 chip->debounce_cnt = 0;
1256 chip->timer_mux = 2;
1257 fusb_timer_start(&chip->timer_mux_machine, chip->timer_mux);
1261 static void fusb_state_attach_wait_sink(struct fusb30x_chip *chip, int evt)
1265 if (evt & EVENT_TIMER_MUX) {
1266 tcpm_get_cc(chip, &cc1, &cc2);
1268 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1269 chip->debounce_cnt++;
1273 chip->debounce_cnt = 0;
1276 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1277 if ((chip->cc1 != chip->cc2) &&
1278 ((!chip->cc1) || (!chip->cc2))) {
1279 set_state(chip, attached_sink);
1281 set_state_unattached(chip);
1286 chip->timer_mux = 2;
1287 fusb_timer_start(&chip->timer_mux_machine,
1292 static void fusb_state_attach_wait_source(struct fusb30x_chip *chip, int evt)
1296 if (evt & EVENT_TIMER_MUX) {
1297 tcpm_get_cc(chip, &cc1, &cc2);
1299 if ((chip->cc1 == cc1) && (chip->cc2 == cc2)) {
1300 chip->debounce_cnt++;
1304 chip->debounce_cnt = 0;
1307 if (chip->debounce_cnt > N_DEBOUNCE_CNT) {
1308 if (((!chip->cc1) || (!chip->cc2)) &&
1309 ((chip->cc1 == TYPEC_CC_VOLT_RD) ||
1310 (chip->cc2 == TYPEC_CC_VOLT_RD))) {
1311 set_state(chip, attached_source);
1313 set_state_unattached(chip);
1319 chip->timer_mux = 2;
1320 fusb_timer_start(&chip->timer_mux_machine,
1325 static void fusb_state_attached_source(struct fusb30x_chip *chip, int evt)
1327 tcpm_set_polarity(chip, !(chip->cc_state & 0x01));
1328 platform_set_vbus_lvl_enable(chip, 1, 0);
1329 tcpm_set_vconn(chip, 1);
1331 chip->notify.is_cc_connected = 1;
1332 if (chip->cc_state & 0x01)
1333 chip->cc_polarity = 0;
1335 chip->cc_polarity = 1;
1337 chip->notify.power_role = 1;
1338 chip->notify.data_role = 1;
1339 chip->hardrst_count = 0;
1340 set_state(chip, policy_src_startup);
1341 dev_info(chip->dev, "CC connected in %d as DFP\n", chip->cc_polarity);
1344 static void fusb_state_attached_sink(struct fusb30x_chip *chip, int evt)
1346 chip->notify.is_cc_connected = 1;
1347 if (chip->cc_state & 0x01)
1348 chip->cc_polarity = 0;
1350 chip->cc_polarity = 1;
1352 chip->notify.power_role = 0;
1353 chip->notify.data_role = 0;
1354 chip->hardrst_count = 0;
1355 set_state(chip, policy_snk_startup);
1356 dev_info(chip->dev, "CC connected in %d as UFP\n", chip->cc_polarity);
1359 static void fusb_state_src_startup(struct fusb30x_chip *chip, int evt)
1361 chip->caps_counter = 0;
1362 chip->notify.is_pd_connected = 0;
1364 chip->vdm_state = 0;
1365 chip->vdm_substate = 0;
1366 chip->vdm_send_state = 0;
1369 memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1371 tcpm_set_msg_header(chip);
1372 tcpm_set_polarity(chip, chip->cc_polarity);
1373 tcpm_set_rx_enable(chip, 1);
1375 set_state(chip, policy_src_send_caps);
1378 static void fusb_state_src_discovery(struct fusb30x_chip *chip, int evt)
1380 switch (chip->sub_state) {
1382 chip->caps_counter++;
1384 if (chip->caps_counter < N_CAPS_COUNT) {
1385 chip->timer_state = T_TYPEC_SEND_SOURCECAP;
1386 fusb_timer_start(&chip->timer_state_machine,
1388 chip->sub_state = 1;
1390 set_state(chip, disabled);
1394 if (evt & EVENT_TIMER_STATE) {
1395 set_state(chip, policy_src_send_caps);
1396 } else if ((evt & EVENT_TIMER_MUX) &&
1397 (chip->hardrst_count > N_HARDRESET_COUNT)) {
1398 if (chip->notify.is_pd_connected)
1399 set_state(chip, error_recovery);
1401 set_state(chip, disabled);
1407 static void fusb_state_src_send_caps(struct fusb30x_chip *chip, int evt)
1411 switch (chip->sub_state) {
1413 set_mesg(chip, DMT_SOURCECAPABILITIES, DATAMESSAGE);
1414 chip->sub_state = 1;
1415 chip->tx_state = tx_idle;
1418 tmp = policy_send_data(chip);
1420 if (tmp == tx_success) {
1421 chip->hardrst_count = 0;
1422 chip->caps_counter = 0;
1423 chip->timer_state = T_SENDER_RESPONSE;
1424 fusb_timer_start(&chip->timer_state_machine,
1426 chip->timer_mux = T_DISABLED;
1428 } else if (tmp == tx_failed) {
1429 set_state(chip, policy_src_discovery);
1433 if (!(evt & FLAG_EVENT))
1436 if (evt & EVENT_RX) {
1437 if ((PD_HEADER_CNT(chip->rec_head) == 1) &&
1438 (PD_HEADER_TYPE(chip->rec_head) == DMT_REQUEST)) {
1439 set_state(chip, policy_src_negotiate_cap);
1441 set_state(chip, policy_src_send_softrst);
1443 } else if (evt & EVENT_TIMER_STATE) {
1444 if (chip->hardrst_count <= N_HARDRESET_COUNT)
1445 set_state(chip, policy_src_send_hardrst);
1447 set_state(chip, disabled);
1448 } else if (evt & EVENT_TIMER_MUX) {
1449 if (chip->notify.is_pd_connected)
1450 set_state(chip, disabled);
1452 set_state(chip, error_recovery);
1458 static void fusb_state_src_negotiate_cap(struct fusb30x_chip *chip, int evt)
1463 tmp = (chip->rec_load[0] >> 28) & 0x07;
1464 if (tmp > chip->n_caps_used)
1465 set_state(chip, policy_src_cap_response);
1467 set_state(chip, policy_src_transition_supply);
1470 static void fusb_state_src_transition_supply(struct fusb30x_chip *chip,
1475 switch (chip->sub_state) {
1477 set_mesg(chip, CMT_ACCEPT, CONTROLMESSAGE);
1478 chip->tx_state = tx_idle;
1482 tmp = policy_send_data(chip);
1483 if (tmp == tx_success) {
1484 chip->timer_state = T_SRC_TRANSITION;
1486 fusb_timer_start(&chip->timer_state_machine,
1488 } else if (tmp == tx_failed) {
1489 set_state(chip, policy_src_send_softrst);
1493 if (evt & EVENT_TIMER_STATE) {
1494 chip->notify.is_pd_connected = 1;
1495 platform_set_vbus_lvl_enable(chip, 1, 0);
1496 set_mesg(chip, CMT_PS_RDY, CONTROLMESSAGE);
1497 chip->tx_state = tx_idle;
1499 chip->work_continue = 1;
1503 tmp = policy_send_data(chip);
1504 if (tmp == tx_success) {
1506 "PD connected as DFP, supporting 5V\n");
1507 set_state(chip, policy_src_ready);
1508 } else if (tmp == tx_failed) {
1509 set_state(chip, policy_src_send_softrst);
1515 static void fusb_state_src_cap_response(struct fusb30x_chip *chip, int evt)
1519 switch (chip->sub_state) {
1521 set_mesg(chip, CMT_REJECT, CONTROLMESSAGE);
1522 chip->tx_state = tx_idle;
1526 tmp = policy_send_data(chip);
1527 if (tmp == tx_success) {
1528 if (chip->notify.is_pd_connected) {
1530 "PD connected as DFP, supporting 5V\n");
1531 set_state(chip, policy_src_ready);
1533 set_state(chip, policy_src_send_hardrst);
1535 } else if (tmp == tx_failed) {
1536 set_state(chip, policy_src_send_softrst);
1542 static void fusb_state_src_transition_default(struct fusb30x_chip *chip,
1545 switch (chip->sub_state) {
1547 chip->notify.is_pd_connected = 0;
1548 platform_set_vbus_lvl_enable(chip, 0, 0);
1549 if (chip->notify.data_role)
1550 regmap_update_bits(chip->regmap,
1553 SWITCHES1_DATAROLE);
1555 regmap_update_bits(chip->regmap,
1560 chip->timer_state = T_SRC_RECOVER;
1561 fusb_timer_start(&chip->timer_state_machine,
1566 if (evt & EVENT_TIMER_STATE) {
1567 platform_set_vbus_lvl_enable(chip, 1, 0);
1568 chip->timer_mux = T_NO_RESPONSE;
1569 fusb_timer_start(&chip->timer_mux_machine,
1571 set_state(chip, policy_src_startup);
1572 dev_dbg(chip->dev, "reset over-> src startup\n");
1578 static void fusb_state_src_ready(struct fusb30x_chip *chip, int evt)
1580 if (evt & EVENT_RX) {
1581 if ((PD_HEADER_CNT(chip->rec_head)) &&
1582 (PD_HEADER_TYPE(chip->rec_head) == DMT_VENDERDEFINED)) {
1583 process_vdm_msg(chip);
1584 chip->work_continue = 1;
1585 chip->timer_state = T_DISABLED;
1589 /* TODO: swap function would be added here later on*/
1591 if (!chip->partner_cap[0])
1592 set_state(chip, policy_src_get_sink_caps);
1594 auto_vdm_machine(chip, evt);
1597 static void fusb_state_src_get_sink_cap(struct fusb30x_chip *chip, int evt)
1601 switch (chip->sub_state) {
1603 set_mesg(chip, CMT_GETSINKCAP, CONTROLMESSAGE);
1604 chip->tx_state = tx_idle;
1608 tmp = policy_send_data(chip);
1609 if (tmp == tx_success) {
1610 chip->timer_state = T_SENDER_RESPONSE;
1612 fusb_timer_start(&chip->timer_state_machine,
1614 } else if (tmp == tx_failed) {
1615 set_state(chip, policy_src_send_softrst);
1618 if (!(evt & FLAG_EVENT))
1621 if (evt & EVENT_RX) {
1622 if ((PD_HEADER_CNT(chip->rec_head)) &&
1623 (PD_HEADER_TYPE(chip->rec_head) ==
1624 DMT_SINKCAPABILITIES)) {
1626 tmp < PD_HEADER_CNT(chip->rec_head);
1628 chip->partner_cap[tmp] =
1629 chip->rec_load[tmp];
1631 set_state(chip, policy_src_ready);
1633 chip->partner_cap[0] = 0xffffffff;
1634 set_state(chip, policy_src_ready);
1636 } else if (evt & EVENT_TIMER_STATE) {
1637 dev_warn(chip->dev, "Get sink cap time out\n");
1638 chip->partner_cap[0] = 0xffffffff;
1639 set_state(chip, policy_src_ready);
1644 static void fusb_state_src_send_hardreset(struct fusb30x_chip *chip, int evt)
1648 switch (chip->sub_state) {
1650 chip->tx_state = tx_idle;
1654 tmp = policy_send_hardrst(chip, evt);
1655 if (tmp == tx_success) {
1656 chip->hardrst_count++;
1657 set_state(chip, policy_src_transition_default);
1658 } else if (tmp == tx_failed) {
1659 /* can't reach here */
1660 set_state(chip, error_recovery);
1666 static void fusb_state_src_send_softreset(struct fusb30x_chip *chip, int evt)
1670 switch (chip->sub_state) {
1672 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1673 chip->tx_state = tx_idle;
1677 tmp = policy_send_data(chip);
1678 if (tmp == tx_success) {
1679 chip->timer_state = T_SENDER_RESPONSE;
1681 fusb_timer_start(&chip->timer_state_machine,
1683 } else if (tmp == tx_failed) {
1684 set_state(chip, policy_src_send_hardrst);
1687 if (!(evt & FLAG_EVENT))
1690 if (evt & EVENT_RX) {
1691 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1692 (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1693 set_state(chip, policy_src_send_caps);
1694 } else if (evt & EVENT_TIMER_STATE) {
1695 set_state(chip, policy_src_send_hardrst);
1701 static void fusb_state_snk_startup(struct fusb30x_chip *chip, int evt)
1703 chip->notify.is_pd_connected = 0;
1705 chip->vdm_state = 0;
1706 chip->vdm_substate = 0;
1707 chip->vdm_send_state = 0;
1709 chip->pos_power = 0;
1711 memset(chip->partner_cap, 0, sizeof(chip->partner_cap));
1713 tcpm_set_msg_header(chip);
1714 tcpm_set_polarity(chip, chip->cc_polarity);
1715 tcpm_set_rx_enable(chip, 1);
1716 set_state(chip, policy_snk_discovery);
1719 static void fusb_state_snk_discovery(struct fusb30x_chip *chip, int evt)
1721 set_state(chip, policy_snk_wait_caps);
1722 chip->timer_state = T_TYPEC_SINK_WAIT_CAP;
1723 fusb_timer_start(&chip->timer_state_machine,
1727 static void fusb_state_snk_wait_caps(struct fusb30x_chip *chip, int evt)
1729 if (evt & EVENT_RX) {
1730 if (PD_HEADER_CNT(chip->rec_head) &&
1731 PD_HEADER_TYPE(chip->rec_head) == DMT_SOURCECAPABILITIES) {
1732 chip->timer_mux = T_DISABLED;
1733 set_state(chip, policy_snk_evaluate_caps);
1735 } else if (evt & EVENT_TIMER_STATE) {
1736 if (chip->hardrst_count <= N_HARDRESET_COUNT)
1737 set_state(chip, policy_snk_send_hardrst);
1739 set_state(chip, disabled);
1740 } else if ((evt & EVENT_TIMER_MUX) &&
1741 (chip->hardrst_count > N_HARDRESET_COUNT)) {
1742 if (chip->notify.is_pd_connected)
1743 set_state(chip, error_recovery);
1745 set_state(chip, disabled);
1749 static void fusb_state_snk_evaluate_caps(struct fusb30x_chip *chip, int evt)
1753 chip->hardrst_count = 0;
1754 chip->pos_power = 0;
1756 for (tmp = 0; tmp < PD_HEADER_CNT(chip->rec_head); tmp++) {
1757 switch (CAP_POWER_TYPE(chip->rec_load[tmp])) {
1760 if (CAP_FPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1761 chip->pos_power = tmp + 1;
1765 if (CAP_VPDO_VOLTAGE(chip->rec_load[tmp]) <= 100)
1766 chip->pos_power = tmp + 1;
1769 /* not meet battery caps */
1774 if ((!chip->pos_power) || (chip->pos_power > 7)) {
1775 chip->pos_power = 0;
1776 set_state(chip, policy_snk_wait_caps);
1778 set_state(chip, policy_snk_select_cap);
1782 static void fusb_state_snk_select_cap(struct fusb30x_chip *chip, int evt)
1786 switch (chip->sub_state) {
1788 set_mesg(chip, DMT_REQUEST, DATAMESSAGE);
1789 chip->sub_state = 1;
1790 chip->tx_state = tx_idle;
1793 tmp = policy_send_data(chip);
1795 if (tmp == tx_success) {
1796 chip->timer_state = T_SENDER_RESPONSE;
1797 fusb_timer_start(&chip->timer_state_machine,
1800 } else if (tmp == tx_failed) {
1801 set_state(chip, policy_snk_discovery);
1805 if (!(evt & FLAG_EVENT))
1808 if (evt & EVENT_RX) {
1809 if (!PD_HEADER_CNT(chip->rec_head)) {
1810 switch (PD_HEADER_TYPE(chip->rec_head)) {
1813 policy_snk_transition_sink);
1814 chip->timer_state = T_PS_TRANSITION;
1815 fusb_timer_start(&chip->timer_state_machine,
1820 if (chip->notify.is_pd_connected) {
1822 "PD connected as UFP, fetching 5V\n");
1827 policy_snk_wait_caps);
1829 * make sure don't send
1830 * hard reset to prevent
1833 chip->hardrst_count =
1834 N_HARDRESET_COUNT + 1;
1841 } else if (evt & EVENT_TIMER_STATE) {
1842 set_state(chip, policy_snk_send_hardrst);
1848 static void fusb_state_snk_transition_sink(struct fusb30x_chip *chip, int evt)
1850 if (evt & EVENT_RX) {
1851 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1852 (PD_HEADER_TYPE(chip->rec_head) == CMT_PS_RDY)) {
1853 chip->notify.is_pd_connected = 1;
1855 "PD connected as UFP, fetching 5V\n");
1856 set_state(chip, policy_snk_ready);
1857 } else if ((PD_HEADER_CNT(chip->rec_head)) &&
1858 (PD_HEADER_TYPE(chip->rec_head) ==
1859 DMT_SOURCECAPABILITIES)) {
1860 set_state(chip, policy_snk_evaluate_caps);
1862 } else if (evt & EVENT_TIMER_STATE) {
1863 set_state(chip, policy_snk_send_hardrst);
1867 static void fusb_state_snk_transition_default(struct fusb30x_chip *chip,
1870 switch (chip->sub_state) {
1872 chip->notify.is_pd_connected = 0;
1873 chip->timer_mux = T_NO_RESPONSE;
1874 fusb_timer_start(&chip->timer_mux_machine,
1876 chip->timer_state = T_PS_HARD_RESET_MAX + T_SAFE_0V;
1877 fusb_timer_start(&chip->timer_state_machine,
1879 if (chip->notify.data_role)
1880 tcpm_set_msg_header(chip);
1884 if (!tcpm_check_vbus(chip)) {
1886 chip->timer_state = T_SRC_RECOVER_MAX + T_SRC_TURN_ON;
1887 fusb_timer_start(&chip->timer_state_machine,
1889 } else if (evt & EVENT_TIMER_STATE) {
1890 set_state(chip, policy_snk_startup);
1894 if (tcpm_check_vbus(chip)) {
1895 chip->timer_state = T_DISABLED;
1896 set_state(chip, policy_snk_startup);
1897 } else if (evt & EVENT_TIMER_STATE) {
1898 set_state(chip, policy_snk_startup);
1904 static void fusb_state_snk_ready(struct fusb30x_chip *chip, int evt)
1906 /* TODO: snk_ready_function would be added later on*/
1907 platform_fusb_notify(chip);
1910 static void fusb_state_snk_send_hardreset(struct fusb30x_chip *chip, int evt)
1914 switch (chip->sub_state) {
1916 chip->tx_state = tx_idle;
1919 tmp = policy_send_hardrst(chip, evt);
1920 if (tmp == tx_success) {
1921 chip->hardrst_count++;
1922 set_state(chip, policy_snk_transition_default);
1923 } else if (tmp == tx_failed) {
1924 set_state(chip, error_recovery);
1930 static void fusb_state_snk_send_softreset(struct fusb30x_chip *chip, int evt)
1934 switch (chip->sub_state) {
1936 set_mesg(chip, CMT_SOFTRESET, CONTROLMESSAGE);
1937 chip->tx_state = tx_idle;
1940 tmp = policy_send_data(chip);
1941 if (tmp == tx_success) {
1942 chip->timer_state = T_SENDER_RESPONSE;
1944 fusb_timer_start(&chip->timer_state_machine,
1946 } else if (tmp == tx_failed) {
1947 /* can't reach here */
1948 set_state(chip, policy_snk_send_hardrst);
1951 if (!(evt & FLAG_EVENT))
1954 if (evt & EVENT_RX) {
1955 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1956 (PD_HEADER_TYPE(chip->rec_head) == CMT_ACCEPT))
1957 set_state(chip, policy_snk_wait_caps);
1958 } else if (evt & EVENT_TIMER_STATE) {
1959 set_state(chip, policy_snk_send_hardrst);
1965 static void state_machine_typec(struct fusb30x_chip *chip)
1970 tcpc_alert(chip, &evt);
1971 mux_alert(chip, &evt);
1975 if (chip->notify.is_cc_connected) {
1976 if (evt & EVENT_CC) {
1977 if ((chip->cc_state & 0x04) &&
1978 (chip->conn_state !=
1979 policy_snk_transition_default)) {
1980 if (!tcpm_check_vbus(chip))
1981 set_state_unattached(chip);
1982 } else if (chip->conn_state !=
1983 policy_src_transition_default) {
1984 tcpm_get_cc(chip, &cc1, &cc2);
1985 if (!(chip->cc_state & 0x01))
1987 if (cc1 == TYPEC_CC_VOLT_OPEN)
1988 set_state_unattached(chip);
1993 if (evt & EVENT_RX) {
1994 tcpm_get_message(chip);
1995 if ((!PD_HEADER_CNT(chip->rec_head)) &&
1996 (PD_HEADER_TYPE(chip->rec_head) == CMT_SOFTRESET)) {
1997 if (chip->notify.power_role)
1998 set_state(chip, policy_src_send_softrst);
2000 set_state(chip, policy_snk_send_softrst);
2004 if (evt & EVENT_TX) {
2005 if (chip->tx_state == tx_success)
2008 switch (chip->conn_state) {
2010 fusb_state_disabled(chip, evt);
2012 case error_recovery:
2013 set_state_unattached(chip);
2016 fusb_state_unattached(chip, evt);
2018 case attach_wait_sink:
2019 fusb_state_attach_wait_sink(chip, evt);
2021 case attach_wait_source:
2022 fusb_state_attach_wait_source(chip, evt);
2024 case attached_source:
2025 fusb_state_attached_source(chip, evt);
2028 fusb_state_attached_sink(chip, evt);
2031 /* POWER DELIVERY */
2032 case policy_src_startup:
2033 fusb_state_src_startup(chip, evt);
2035 case policy_src_discovery:
2036 fusb_state_src_discovery(chip, evt);
2038 case policy_src_send_caps:
2039 fusb_state_src_send_caps(chip, evt);
2040 if (chip->conn_state != policy_src_negotiate_cap)
2042 case policy_src_negotiate_cap:
2043 fusb_state_src_negotiate_cap(chip, evt);
2045 case policy_src_transition_supply:
2046 fusb_state_src_transition_supply(chip, evt);
2048 case policy_src_cap_response:
2049 fusb_state_src_cap_response(chip, evt);
2051 case policy_src_transition_default:
2052 fusb_state_src_transition_default(chip, evt);
2054 case policy_src_ready:
2055 fusb_state_src_ready(chip, evt);
2057 case policy_src_get_sink_caps:
2058 fusb_state_src_get_sink_cap(chip, evt);
2060 case policy_src_send_hardrst:
2061 fusb_state_src_send_hardreset(chip, evt);
2063 case policy_src_send_softrst:
2064 fusb_state_src_send_softreset(chip, evt);
2068 case policy_snk_startup:
2069 fusb_state_snk_startup(chip, evt);
2071 case policy_snk_discovery:
2072 fusb_state_snk_discovery(chip, evt);
2074 case policy_snk_wait_caps:
2075 fusb_state_snk_wait_caps(chip, evt);
2077 case policy_snk_evaluate_caps:
2078 fusb_state_snk_evaluate_caps(chip, evt);
2080 case policy_snk_select_cap:
2081 fusb_state_snk_select_cap(chip, evt);
2083 case policy_snk_transition_sink:
2084 fusb_state_snk_transition_sink(chip, evt);
2086 case policy_snk_transition_default:
2087 fusb_state_snk_transition_default(chip, evt);
2089 case policy_snk_ready:
2090 fusb_state_snk_ready(chip, evt);
2092 case policy_snk_send_hardrst:
2093 fusb_state_snk_send_hardreset(chip, evt);
2095 case policy_snk_send_softrst:
2096 fusb_state_snk_send_softreset(chip, evt);
2104 if (chip->work_continue) {
2105 queue_work(chip->fusb30x_wq, &chip->work);
2109 if (!platform_get_device_irq_state(chip))
2110 fusb_irq_enable(chip);
2112 queue_work(chip->fusb30x_wq, &chip->work);
2115 static irqreturn_t cc_interrupt_handler(int irq, void *dev_id)
2117 struct fusb30x_chip *chip = dev_id;
2119 queue_work(chip->fusb30x_wq, &chip->work);
2120 fusb_irq_disable(chip);
2124 static int fusb_initialize_gpio(struct fusb30x_chip *chip)
2126 chip->gpio_int = devm_gpiod_get_optional(chip->dev, "int-n", GPIOD_IN);
2127 if (IS_ERR(chip->gpio_int))
2128 return PTR_ERR(chip->gpio_int);
2130 /* some board support vbus with other ways */
2131 chip->gpio_vbus_5v = devm_gpiod_get_optional(chip->dev, "vbus-5v",
2133 if (IS_ERR(chip->gpio_vbus_5v))
2135 "Could not get named GPIO for VBus5V!\n");
2137 gpiod_set_raw_value(chip->gpio_vbus_5v, 0);
2139 chip->gpio_vbus_other = devm_gpiod_get_optional(chip->dev,
2142 if (IS_ERR(chip->gpio_vbus_other))
2144 "Could not get named GPIO for VBusOther!\n");
2146 gpiod_set_raw_value(chip->gpio_vbus_other, 0);
2151 static enum hrtimer_restart fusb_timer_handler(struct hrtimer *timer)
2155 for (i = 0; i < fusb30x_port_used; i++) {
2156 if (timer == &fusb30x_port_info[i]->timer_state_machine) {
2157 if (fusb30x_port_info[i]->timer_state != T_DISABLED)
2158 fusb30x_port_info[i]->timer_state = 0;
2162 if (timer == &fusb30x_port_info[i]->timer_mux_machine) {
2163 if (fusb30x_port_info[i]->timer_mux != T_DISABLED)
2164 fusb30x_port_info[i]->timer_mux = 0;
2169 if (i != fusb30x_port_used)
2170 queue_work(fusb30x_port_info[i]->fusb30x_wq,
2171 &fusb30x_port_info[i]->work);
2173 return HRTIMER_NORESTART;
2176 static void fusb_initialize_timer(struct fusb30x_chip *chip)
2178 hrtimer_init(&chip->timer_state_machine, CLOCK_MONOTONIC,
2180 chip->timer_state_machine.function = fusb_timer_handler;
2182 hrtimer_init(&chip->timer_mux_machine, CLOCK_MONOTONIC,
2184 chip->timer_mux_machine.function = fusb_timer_handler;
2186 chip->timer_state = T_DISABLED;
2187 chip->timer_mux = T_DISABLED;
2190 static void fusb302_work_func(struct work_struct *work)
2192 struct fusb30x_chip *chip;
2194 chip = container_of(work, struct fusb30x_chip, work);
2195 state_machine_typec(chip);
2198 static int fusb30x_probe(struct i2c_client *client,
2199 const struct i2c_device_id *id)
2201 struct fusb30x_chip *chip;
2202 struct PD_CAP_INFO *pd_cap_info;
2205 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
2209 if (fusb30x_port_used == 0xff)
2212 chip->port_num = fusb30x_port_used++;
2213 fusb30x_port_info[chip->port_num] = chip;
2215 chip->dev = &client->dev;
2216 chip->regmap = devm_regmap_init_i2c(client, &fusb302_regmap_config);
2217 if (IS_ERR(chip->regmap)) {
2218 dev_err(&client->dev, "Failed to allocate regmap!\n");
2219 return PTR_ERR(chip->regmap);
2222 ret = fusb_initialize_gpio(chip);
2226 fusb_initialize_timer(chip);
2228 chip->fusb30x_wq = create_workqueue("fusb302_wq");
2229 INIT_WORK(&chip->work, fusb302_work_func);
2232 tcpm_set_rx_enable(chip, 0);
2233 chip->conn_state = unattached;
2234 tcpm_set_cc(chip, FUSB_MODE_DRP);
2236 chip->n_caps_used = 1;
2237 chip->source_power_supply[0] = 0x64;
2238 chip->source_max_current[0] = 0x96;
2241 * these two variable should be 1 if support DRP,
2242 * but now we do not support swap,
2243 * it will be blanked in future
2245 pd_cap_info = &chip->pd_cap_info;
2246 pd_cap_info->dual_role_power = 0;
2247 pd_cap_info->data_role_swap = 0;
2249 pd_cap_info->externally_powered = 1;
2250 pd_cap_info->usb_suspend_support = 0;
2251 pd_cap_info->usb_communications_cap = 0;
2252 pd_cap_info->supply_type = 0;
2253 pd_cap_info->peak_current = 0;
2255 chip->extcon = devm_extcon_dev_allocate(&client->dev, fusb302_cable);
2256 if (IS_ERR(chip->extcon)) {
2257 dev_err(&client->dev, "allocat extcon failed\n");
2258 return PTR_ERR(chip->extcon);
2261 ret = devm_extcon_dev_register(&client->dev, chip->extcon);
2263 dev_err(&client->dev, "failed to register extcon: %d\n",
2268 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB,
2269 EXTCON_PROP_USB_TYPEC_POLARITY);
2271 dev_err(&client->dev,
2272 "failed to set USB property capability: %d\n",
2277 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST,
2278 EXTCON_PROP_USB_TYPEC_POLARITY);
2280 dev_err(&client->dev,
2281 "failed to set USB_HOST property capability: %d\n",
2286 ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP,
2287 EXTCON_PROP_USB_TYPEC_POLARITY);
2289 dev_err(&client->dev,
2290 "failed to set DISP_DP property capability: %d\n",
2295 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB,
2296 EXTCON_PROP_USB_SS);
2298 dev_err(&client->dev,
2299 "failed to set USB USB_SS property capability: %d\n",
2304 ret = extcon_set_property_capability(chip->extcon, EXTCON_USB_HOST,
2305 EXTCON_PROP_USB_SS);
2307 dev_err(&client->dev,
2308 "failed to set USB_HOST USB_SS property capability: %d\n",
2313 ret = extcon_set_property_capability(chip->extcon, EXTCON_DISP_DP,
2314 EXTCON_PROP_USB_SS);
2316 dev_err(&client->dev,
2317 "failed to set DISP_DP USB_SS property capability: %d\n",
2322 i2c_set_clientdata(client, chip);
2324 spin_lock_init(&chip->irq_lock);
2325 chip->enable_irq = 1;
2327 chip->gpio_int_irq = gpiod_to_irq(chip->gpio_int);
2328 if (chip->gpio_int_irq < 0) {
2329 dev_err(&client->dev,
2330 "Unable to request IRQ for INT_N GPIO! %d\n",
2332 ret = chip->gpio_int_irq;
2336 ret = devm_request_threaded_irq(&client->dev,
2339 cc_interrupt_handler,
2340 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2344 dev_err(&client->dev, "irq request failed\n");
2348 dev_info(chip->dev, "port %d probe success\n", chip->port_num);
2353 destroy_workqueue(chip->fusb30x_wq);
2357 static int fusb30x_remove(struct i2c_client *client)
2359 struct fusb30x_chip *chip = i2c_get_clientdata(client);
2361 destroy_workqueue(chip->fusb30x_wq);
2365 static const struct of_device_id fusb30x_dt_match[] = {
2366 { .compatible = FUSB30X_I2C_DEVICETREE_NAME },
2369 MODULE_DEVICE_TABLE(of, fusb30x_dt_match);
2371 static const struct i2c_device_id fusb30x_i2c_device_id[] = {
2372 { FUSB30X_I2C_DRIVER_NAME, 0 },
2375 MODULE_DEVICE_TABLE(i2c, fusb30x_i2c_device_id);
2377 static struct i2c_driver fusb30x_driver = {
2379 .name = FUSB30X_I2C_DRIVER_NAME,
2380 .of_match_table = of_match_ptr(fusb30x_dt_match),
2382 .probe = fusb30x_probe,
2383 .remove = fusb30x_remove,
2384 .id_table = fusb30x_i2c_device_id,
2387 module_i2c_driver(fusb30x_driver);
2389 MODULE_LICENSE("GPL");
2390 MODULE_AUTHOR("zain wang <zain.wang@rock-chips.com>");
2391 MODULE_DESCRIPTION("fusb302 typec pd driver");