2 * Copyright (C) 2008-2010 Motorola, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
19 #include <linux/completion.h>
20 #include <linux/errno.h>
21 #include <linux/firmware.h>
23 #include <linux/ihex.h>
24 #include <linux/miscdevice.h>
25 #include <linux/mutex.h>
26 #include <linux/platform_device.h>
27 #include <linux/uaccess.h>
29 #include <linux/spi/cpcap.h>
30 #include <linux/spi/cpcap-regbits.h>
31 #include <linux/spi/spi.h>
34 #define ERROR_MACRO_TIMEOUT 0x81
35 #define ERROR_MACRO_WRITE 0x82
36 #define ERROR_MACRO_READ 0x83
38 #define RAM_START_TI 0x9000
39 #define RAM_END_TI 0x9FA0
40 #define RAM_START_ST 0x0000
41 #define RAM_END_ST 0x0FFF
43 #define HWCFG_ADDR_ST 0x0122
46 READ_STATE_1, /* Send size and location of RAM read. */
47 READ_STATE_2, /*!< Read MT registers. */
48 READ_STATE_3, /*!< Read data from uC. */
49 READ_STATE_4, /*!< Check for error. */
53 WRITE_STATE_1, /* Send size and location of RAM write. */
54 WRITE_STATE_2, /* Check for error. */
55 WRITE_STATE_3, /* Write data to uC. */
56 WRITE_STATE_4 /* Check for error. */
59 struct cpcap_uc_data {
60 struct cpcap_device *cpcap;
61 unsigned char is_supported;
62 unsigned char is_ready;
63 struct completion completion;
66 unsigned char uc_reset;
68 unsigned short state_cntr;
70 unsigned short address;
72 unsigned short num_words;
76 static struct cpcap_uc_data *cpcap_uc_info;
78 static int fops_open(struct inode *inode, struct file *file);
79 static long fops_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
80 static ssize_t fops_write(struct file *file, const char *buf,
81 size_t count, loff_t *ppos);
82 static ssize_t fops_read(struct file *file, char *buf,
83 size_t count, loff_t *ppos);
86 static const struct file_operations fops = {
88 .unlocked_ioctl = fops_ioctl,
94 static struct miscdevice uc_dev = {
95 .minor = MISC_DYNAMIC_MINOR,
100 static int is_valid_address(struct cpcap_device *cpcap, unsigned short address,
101 unsigned short num_words)
105 if (cpcap->vendor == CPCAP_VENDOR_TI) {
106 vld = (address >= RAM_START_TI) &&
107 ((address + num_words) <= RAM_END_TI);
108 } else if (cpcap->vendor == CPCAP_VENDOR_ST) {
109 vld = ((address + num_words) <= RAM_END_ST);
115 static void ram_read_state_machine(enum cpcap_irqs irq, void *data)
117 struct cpcap_uc_data *uc_data = data;
120 if (irq != CPCAP_IRQ_UC_PRIRAMR)
123 switch (uc_data->state) {
125 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT1,
126 uc_data->req.address, 0xFFFF);
127 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT2,
128 uc_data->req.num_words, 0xFFFF);
129 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT3, 0, 0xFFFF);
131 if (uc_data->cpcap->vendor == CPCAP_VENDOR_ST)
132 uc_data->state = READ_STATE_2;
134 uc_data->state = READ_STATE_3;
136 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
140 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT1, &temp);
142 if (temp == ERROR_MACRO_READ) {
143 uc_data->state = READ_STATE_1;
144 uc_data->state_cntr = 0;
146 cpcap_irq_mask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
148 uc_data->cb_status = -EIO;
150 complete(&uc_data->completion);
152 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT2, &temp);
153 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT3, &temp);
155 uc_data->state = READ_STATE_3;
156 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
161 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT1,
162 uc_data->req.data + uc_data->state_cntr);
164 uc_data->state_cntr += 1;
166 if (uc_data->state_cntr == uc_data->req.num_words)
167 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT2, &temp);
169 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT2,
171 uc_data->state_cntr);
173 uc_data->state_cntr += 1;
176 if (uc_data->state_cntr == uc_data->req.num_words)
177 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT3, &temp);
179 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT3,
181 uc_data->state_cntr);
183 uc_data->state_cntr += 1;
186 if (uc_data->state_cntr == uc_data->req.num_words)
187 uc_data->state = READ_STATE_4;
189 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
193 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT1, &temp);
195 if (temp != ERROR_MACRO_READ)
196 uc_data->cb_status = 0;
198 uc_data->cb_status = -EIO;
200 complete(&uc_data->completion);
202 uc_data->state = READ_STATE_1;
203 uc_data->state_cntr = 0;
207 uc_data->state = READ_STATE_1;
208 uc_data->state_cntr = 0;
213 static void ram_write_state_machine(enum cpcap_irqs irq, void *data)
215 struct cpcap_uc_data *uc_data = data;
216 unsigned short error_check;
218 if (irq != CPCAP_IRQ_UC_PRIRAMW)
221 switch (uc_data->state) {
223 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT1,
224 uc_data->req.address, 0xFFFF);
225 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT2,
226 uc_data->req.num_words, 0xFFFF);
227 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT3, 0, 0xFFFF);
229 uc_data->state = WRITE_STATE_2;
230 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMW);
234 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT1, &error_check);
236 if (error_check == ERROR_MACRO_WRITE) {
237 uc_data->state = WRITE_STATE_1;
238 uc_data->state_cntr = 0;
240 cpcap_irq_mask(uc_data->cpcap,
241 CPCAP_IRQ_UC_PRIRAMW);
243 uc_data->cb_status = -EIO;
244 complete(&uc_data->completion);
247 uc_data->state = WRITE_STATE_3;
249 /* No error has occured, fall through */
252 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT1,
253 *(uc_data->req.data + uc_data->state_cntr),
255 uc_data->state_cntr += 1;
257 if (uc_data->state_cntr == uc_data->req.num_words)
258 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT2, 0,
261 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT2,
262 *(uc_data->req.data +
263 uc_data->state_cntr), 0xFFFF);
265 uc_data->state_cntr += 1;
268 if (uc_data->state_cntr == uc_data->req.num_words)
269 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT3, 0,
272 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MT3,
273 *(uc_data->req.data +
274 uc_data->state_cntr), 0xFFFF);
276 uc_data->state_cntr += 1;
279 if (uc_data->state_cntr == uc_data->req.num_words)
280 uc_data->state = WRITE_STATE_4;
282 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMW);
286 cpcap_regacc_read(uc_data->cpcap, CPCAP_REG_MT1, &error_check);
288 if (error_check != ERROR_MACRO_WRITE)
289 uc_data->cb_status = 0;
291 uc_data->cb_status = -EIO;
293 complete(&uc_data->completion);
295 uc_data->state = WRITE_STATE_1;
296 uc_data->state_cntr = 0;
300 uc_data->state = WRITE_STATE_1;
301 uc_data->state_cntr = 0;
306 static void reset_handler(enum cpcap_irqs irq, void *data)
309 unsigned short regval;
310 struct cpcap_uc_data *uc_data = data;
312 if (irq != CPCAP_IRQ_UCRESET)
315 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_UCC1,
316 CPCAP_BIT_PRIHALT, CPCAP_BIT_PRIHALT);
318 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_PGC,
319 CPCAP_BIT_PRI_UC_SUSPEND, CPCAP_BIT_PRI_UC_SUSPEND);
321 uc_data->uc_reset = 1;
322 uc_data->cb_status = -EIO;
323 complete(&uc_data->completion);
325 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MI2, 0, 0xFFFF);
326 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MIM1, 0xFFFF, 0xFFFF);
327 cpcap_irq_mask(uc_data->cpcap, CPCAP_IRQ_PRIMAC);
328 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UCRESET);
330 for (i = 0; i <= CPCAP_REG_END; i++) {
331 cpcap_regacc_read(uc_data->cpcap, i, ®val);
332 dev_err(&uc_data->cpcap->spi->dev,
333 "cpcap reg %d = 0x%04X\n", i, regval);
339 static void primac_handler(enum cpcap_irqs irq, void *data)
341 struct cpcap_uc_data *uc_data = data;
343 if (irq == CPCAP_IRQ_PRIMAC)
344 cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_PRIMAC);
347 static int ram_write(struct cpcap_uc_data *uc_data, unsigned short address,
348 unsigned short num_words, unsigned short *data)
350 int retval = -EFAULT;
352 mutex_lock(&uc_data->lock);
354 if ((uc_data->cpcap->vendor == CPCAP_VENDOR_ST) &&
355 (uc_data->cpcap->revision <= CPCAP_REVISION_2_0)) {
356 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_UCTM,
357 CPCAP_BIT_UCTM, CPCAP_BIT_UCTM);
360 if (uc_data->is_supported && (num_words > 0) &&
362 is_valid_address(uc_data->cpcap, address, num_words) &&
363 !uc_data->uc_reset) {
364 uc_data->req.address = address;
365 uc_data->req.data = data;
366 uc_data->req.num_words = num_words;
367 uc_data->state = WRITE_STATE_1;
368 uc_data->state_cntr = 0;
369 INIT_COMPLETION(uc_data->completion);
371 retval = cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MI2,
377 /* Cannot call cpcap_irq_register() here because unregister
378 * cannot be called from the state machine. Doing so causes
380 retval = cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMW);
384 wait_for_completion(&uc_data->completion);
385 retval = uc_data->cb_status;
389 if ((uc_data->cpcap->vendor == CPCAP_VENDOR_ST) &&
390 (uc_data->cpcap->revision <= CPCAP_REVISION_2_0)) {
391 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_UCTM,
395 mutex_unlock(&uc_data->lock);
399 static int ram_read(struct cpcap_uc_data *uc_data, unsigned short address,
400 unsigned short num_words, unsigned short *data)
402 int retval = -EFAULT;
404 mutex_lock(&uc_data->lock);
406 if ((uc_data->cpcap->vendor == CPCAP_VENDOR_ST) &&
407 (uc_data->cpcap->revision <= CPCAP_REVISION_2_0)) {
408 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_UCTM,
409 CPCAP_BIT_UCTM, CPCAP_BIT_UCTM);
412 if (uc_data->is_supported && (num_words > 0) &&
413 is_valid_address(uc_data->cpcap, address, num_words) &&
414 !uc_data->uc_reset) {
415 uc_data->req.address = address;
416 uc_data->req.data = data;
417 uc_data->req.num_words = num_words;
418 uc_data->state = READ_STATE_1;
419 uc_data->state_cntr = 0;
420 INIT_COMPLETION(uc_data->completion);
422 retval = cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_MI2,
428 /* Cannot call cpcap_irq_register() here because unregister
429 * cannot be called from the state machine. Doing so causes
431 retval = cpcap_irq_unmask(uc_data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
435 wait_for_completion(&uc_data->completion);
436 retval = uc_data->cb_status;
440 if ((uc_data->cpcap->vendor == CPCAP_VENDOR_ST) &&
441 (uc_data->cpcap->revision <= CPCAP_REVISION_2_0)) {
442 cpcap_regacc_write(uc_data->cpcap, CPCAP_REG_UCTM,
446 mutex_unlock(&uc_data->lock);
450 static int ram_load(struct cpcap_uc_data *uc_data, unsigned int num_words,
451 unsigned short *data)
453 int retval = -EINVAL;
455 if ((data != NULL) && (num_words > 0))
456 retval = ram_write(uc_data, data[0], (num_words - 1),
462 static ssize_t fops_write(struct file *file, const char *buf,
463 size_t count, loff_t *ppos)
465 ssize_t retval = -EINVAL;
466 unsigned short address;
467 unsigned short num_words;
468 unsigned short *data;
469 struct cpcap_uc_data *uc_data = file->private_data;
471 if ((buf != NULL) && (ppos != NULL) && (count >= 2)) {
472 data = kzalloc(count, GFP_KERNEL);
475 num_words = (unsigned short) (count >> 1);
477 /* If the position (uC RAM address) is zero then the
478 * data contains the address */
480 if (copy_from_user((void *) data, (void *) buf,
482 retval = ram_load(uc_data, num_words,
487 /* If the position (uC RAM address) is not zero then the
488 * position holds the address to load the data */
490 address = (unsigned short) (*ppos);
492 if (copy_from_user((void *) data, (void *) buf,
494 retval = ram_write(uc_data, address,
512 static ssize_t fops_read(struct file *file, char *buf,
513 size_t count, loff_t *ppos)
515 ssize_t retval = -EFAULT;
516 unsigned short address;
517 unsigned short num_words;
518 unsigned short *data;
519 struct cpcap_uc_data *uc_data = file->private_data;
521 if ((buf != NULL) && (ppos != NULL) && (count >= 2)) {
522 data = kzalloc(count, GFP_KERNEL);
525 address = (unsigned short) (*ppos);
526 num_words = (unsigned short) (count >> 1);
528 retval = ram_read(uc_data, address, num_words, data);
532 if (copy_to_user((void *)buf, (void *)data, count) == 0)
547 static long fops_ioctl(struct file *file, unsigned int cmd,
550 int retval = -ENOTTY;
551 struct cpcap_uc_data *data = file->private_data;
554 case CPCAP_IOCTL_UC_MACRO_START:
555 /* User space will only attempt to start the init macro if
556 * the ram load requests complete successfully. This is used
557 * as an indication that kernel requests to start macros can
562 retval = cpcap_uc_start(data->cpcap, (enum cpcap_macro)arg);
566 case CPCAP_IOCTL_UC_MACRO_STOP:
567 retval = cpcap_uc_stop(data->cpcap, (enum cpcap_macro)arg);
570 case CPCAP_IOCTL_UC_GET_VENDOR:
571 retval = copy_to_user((enum cpcap_vendor *)arg,
572 &(data->cpcap->vendor),
573 sizeof(enum cpcap_vendor));
576 case CPCAP_IOCTL_UC_SET_TURBO_MODE:
579 retval = cpcap_regacc_write(data->cpcap, CPCAP_REG_UCTM,
591 static int fops_open(struct inode *inode, struct file *file)
593 int retval = -ENOTTY;
595 if (cpcap_uc_info->is_supported)
598 file->private_data = cpcap_uc_info;
599 dev_info(&cpcap_uc_info->cpcap->spi->dev, "CPCAP uC: open status:%d\n",
605 int cpcap_uc_start(struct cpcap_device *cpcap, enum cpcap_macro macro)
607 int retval = -EFAULT;
608 struct cpcap_uc_data *data = cpcap->ucdata;
610 if ((data->is_ready) &&
611 (macro > CPCAP_MACRO_USEROFF) && (macro < CPCAP_MACRO__END) &&
612 (data->uc_reset == 0)) {
613 if ((macro == CPCAP_MACRO_4) ||
614 ((cpcap->vendor == CPCAP_VENDOR_ST) &&
615 ((macro == CPCAP_MACRO_12) || (macro == CPCAP_MACRO_14) ||
616 (macro == CPCAP_MACRO_15)))) {
617 retval = cpcap_regacc_write(cpcap, CPCAP_REG_MI2,
621 retval = cpcap_regacc_write(cpcap, CPCAP_REG_MIM1,
628 EXPORT_SYMBOL_GPL(cpcap_uc_start);
630 int cpcap_uc_stop(struct cpcap_device *cpcap, enum cpcap_macro macro)
632 int retval = -EFAULT;
634 if ((macro > CPCAP_MACRO_4) &&
635 (macro < CPCAP_MACRO__END)) {
636 if ((cpcap->vendor == CPCAP_VENDOR_ST) &&
637 ((macro == CPCAP_MACRO_12) || (macro == CPCAP_MACRO_14) ||
638 (macro == CPCAP_MACRO_15))) {
639 retval = cpcap_regacc_write(cpcap, CPCAP_REG_MI2,
642 retval = cpcap_regacc_write(cpcap, CPCAP_REG_MIM1,
643 (1 << macro), (1 << macro));
649 EXPORT_SYMBOL_GPL(cpcap_uc_stop);
651 unsigned char cpcap_uc_status(struct cpcap_device *cpcap,
652 enum cpcap_macro macro)
654 unsigned char retval = 0;
655 unsigned short regval;
657 if (macro < CPCAP_MACRO__END) {
658 if ((macro <= CPCAP_MACRO_4) ||
659 ((cpcap->vendor == CPCAP_VENDOR_ST) &&
660 ((macro == CPCAP_MACRO_12) || (macro == CPCAP_MACRO_14) ||
661 (macro == CPCAP_MACRO_15)))) {
662 cpcap_regacc_read(cpcap, CPCAP_REG_MI2, ®val);
664 if (regval & (1 << macro))
667 cpcap_regacc_read(cpcap, CPCAP_REG_MIM1, ®val);
669 if (!(regval & (1 << macro)))
676 EXPORT_SYMBOL_GPL(cpcap_uc_status);
678 static int fw_load(struct cpcap_uc_data *uc_data, struct device *dev)
681 const struct ihex_binrec *rec;
682 const struct firmware *fw;
685 unsigned short num_bytes;
686 unsigned short num_words;
687 unsigned char odd_bytes;
688 struct cpcap_platform_data *data;
690 data = uc_data->cpcap->spi->controller_data;
692 if (!uc_data || !dev)
695 if (uc_data->cpcap->vendor == CPCAP_VENDOR_ST)
696 err = request_ihex_firmware(&fw, "cpcap/firmware_0_2x.fw", dev);
698 err = request_ihex_firmware(&fw, "cpcap/firmware_1_2x.fw", dev);
701 dev_err(dev, "Failed to load \"cpcap/firmware_%d_2x.fw\": %d\n",
702 uc_data->cpcap->vendor, err);
706 for (rec = (void *)fw->data; rec; rec = ihex_next_binrec(rec)) {
708 num_bytes = be16_to_cpu(rec->len);
710 /* Since loader requires words, need even number of bytes. */
711 if (be16_to_cpu(rec->len) % 2) {
716 num_words = num_bytes >> 1;
717 dev_info(dev, "Loading %d word(s) at 0x%04x\n",
718 num_words, be32_to_cpu(rec->addr));
720 buf = kzalloc(num_bytes, GFP_KERNEL);
722 for (i = 0; i < num_words; i++) {
723 if (odd_bytes && (i == (num_words - 1)))
724 buf[i] = rec->data[i * 2];
726 buf[i] = ((uint16_t *)rec->data)[i];
728 buf[i] = be16_to_cpu(buf[i]);
731 err = ram_write(uc_data, be32_to_cpu(rec->addr),
736 dev_err(dev, "RAM write failed: %d\n", err);
741 dev_err(dev, "RAM write failed: %d\n", err);
746 release_firmware(fw);
749 uc_data->is_ready = 1;
751 if (uc_data->cpcap->vendor == CPCAP_VENDOR_ST) {
752 err = ram_write(uc_data, HWCFG_ADDR_ST, CPCAP_HWCFG_NUM,
754 dev_info(dev, "Loaded HWCFG data: %d\n", err);
757 err = cpcap_uc_start(uc_data->cpcap, CPCAP_MACRO_4);
758 dev_info(dev, "Started macro 4: %d\n", err);
765 static int cpcap_uc_probe(struct platform_device *pdev)
768 struct cpcap_uc_data *data;
770 if (pdev->dev.platform_data == NULL) {
771 dev_err(&pdev->dev, "no platform_data\n");
775 data = kzalloc(sizeof(*data), GFP_KERNEL);
779 data->cpcap = pdev->dev.platform_data;
781 data->is_supported = 0;
782 data->req.address = 0;
783 data->req.data = NULL;
784 data->req.num_words = 0;
786 init_completion(&data->completion);
787 mutex_init(&data->lock);
788 platform_set_drvdata(pdev, data);
789 cpcap_uc_info = data;
790 data->cpcap->ucdata = data;
792 if (((data->cpcap->vendor == CPCAP_VENDOR_TI) &&
793 (data->cpcap->revision >= CPCAP_REVISION_2_0)) ||
794 (data->cpcap->vendor == CPCAP_VENDOR_ST)) {
795 retval = cpcap_irq_register(data->cpcap, CPCAP_IRQ_PRIMAC,
796 primac_handler, data);
800 cpcap_irq_clear(data->cpcap, CPCAP_IRQ_UCRESET);
801 retval = cpcap_irq_register(data->cpcap, CPCAP_IRQ_UCRESET,
802 reset_handler, data);
806 retval = cpcap_irq_register(data->cpcap,
807 CPCAP_IRQ_UC_PRIRAMR,
808 ram_read_state_machine, data);
812 retval = cpcap_irq_register(data->cpcap,
813 CPCAP_IRQ_UC_PRIRAMW,
814 ram_write_state_machine, data);
818 retval = misc_register(&uc_dev);
822 data->is_supported = 1;
824 cpcap_regacc_write(data->cpcap, CPCAP_REG_MIM1, 0xFFFF,
827 retval = fw_load(data, &pdev->dev);
836 misc_deregister(&uc_dev);
838 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UC_PRIRAMW);
840 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
842 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UCRESET);
844 cpcap_irq_free(data->cpcap, CPCAP_IRQ_PRIMAC);
851 static int __exit cpcap_uc_remove(struct platform_device *pdev)
853 struct cpcap_uc_data *data = platform_get_drvdata(pdev);
855 misc_deregister(&uc_dev);
857 cpcap_irq_free(data->cpcap, CPCAP_IRQ_PRIMAC);
858 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UC_PRIRAMW);
859 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UC_PRIRAMR);
860 cpcap_irq_free(data->cpcap, CPCAP_IRQ_UCRESET);
867 static struct platform_driver cpcap_uc_driver = {
868 .probe = cpcap_uc_probe,
869 .remove = __exit_p(cpcap_uc_remove),
872 .owner = THIS_MODULE,
876 static int __init cpcap_uc_init(void)
878 return platform_driver_register(&cpcap_uc_driver);
880 subsys_initcall(cpcap_uc_init);
882 static void __exit cpcap_uc_exit(void)
884 platform_driver_unregister(&cpcap_uc_driver);
886 module_exit(cpcap_uc_exit);
888 MODULE_ALIAS("platform:cpcap_uc");
889 MODULE_DESCRIPTION("CPCAP uC driver");
890 MODULE_AUTHOR("Motorola");
891 MODULE_LICENSE("GPL");
892 MODULE_FIRMWARE("cpcap/firmware_0_2x.fw");
893 MODULE_FIRMWARE("cpcap/firmware_1_2x.fw");