2 #include "camsys_soc_priv.h"
3 #include "camsys_soc_rk3399.h"
5 struct mipiphy_hsfreqrange_s {
11 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
52 static char camsys_rk3399_mipiphy0_rd_reg(camsys_mipiphy_soc_para_t *para, unsigned char addr)
55 write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
56 (1 << DPHY_RX0_TESTCLK_BIT));
57 /*TESTEN =1,TESTDIN=addr*/
58 write_grf_reg(GRF_SOC_CON25_OFFSET,
59 ((addr << DPHY_RX0_TESTDIN_BIT) |
60 DPHY_RX0_TESTDIN_MASK |
61 (1 << DPHY_RX0_TESTEN_BIT) |
62 DPHY_RX0_TESTEN_MASK));
64 write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
66 return read_grf_reg(GRF_SOC_STATUS1)&0xff;
69 static int camsys_rk3399_mipiphy0_wr_reg
70 (camsys_mipiphy_soc_para_t *para, unsigned char addr, unsigned char data)
73 write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
74 (1 << DPHY_RX0_TESTCLK_BIT));
75 /*TESTEN =1,TESTDIN=addr*/
76 write_grf_reg(GRF_SOC_CON25_OFFSET,
77 ((addr << DPHY_RX0_TESTDIN_BIT) |
78 DPHY_RX0_TESTDIN_MASK |
79 (1 << DPHY_RX0_TESTEN_BIT) |
80 DPHY_RX0_TESTEN_MASK));
82 write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK);
84 if (data != 0xff) { /*write data ?*/
85 /*TESTEN =0,TESTDIN=data*/
86 write_grf_reg(GRF_SOC_CON25_OFFSET,
87 ((data << DPHY_RX0_TESTDIN_BIT) |
88 DPHY_RX0_TESTDIN_MASK |
89 DPHY_RX0_TESTEN_MASK));
92 write_grf_reg(GRF_SOC_CON25_OFFSET, DPHY_RX0_TESTCLK_MASK |
93 (1 << DPHY_RX0_TESTCLK_BIT));
98 static char camsys_rk3399_mipiphy1_wr_reg
99 (unsigned long dsiphy_virt, unsigned char addr, unsigned char data)
101 /*TESTEN =1,TESTDIN=addr*/
102 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
104 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
105 /*TESTEN =0,TESTDIN=data*/
106 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00000000 | data));
108 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
113 static int camsys_rk3399_mipiphy1_rd_reg(unsigned long dsiphy_virt, unsigned char addr)
115 /*TESTEN =1,TESTDIN=addr*/
116 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, (0x00010000 | addr));
118 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000000);
119 return (read_dsihost_reg(DSIHOST_PHY_TEST_CTRL1)>>8);
122 static int camsys_rk3399_mipihpy_cfg
123 (camsys_mipiphy_soc_para_t *para)
125 unsigned char hsfreqrange = 0xff, i;
126 struct mipiphy_hsfreqrange_s *hsfreqrange_p;
127 unsigned long phy_virt, phy_index;
129 unsigned long csiphy_virt;
130 unsigned long dsiphy_virt;
131 unsigned long vir_base = 0;
132 unsigned char settle_bypass = 0;
133 unsigned char settle_en = 0;
134 unsigned char manu_hsfreqrange = 0x04;
136 phy_index = para->phy->phy_index;
137 if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
138 phy_virt = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
142 if (para->camsys_dev->csiphy_reg != NULL) {
144 (unsigned long)para->camsys_dev->csiphy_reg->vir_base;
148 if (para->camsys_dev->dsiphy_reg != NULL) {
150 (unsigned long)para->camsys_dev->dsiphy_reg->vir_base;
155 if ((para->phy->bit_rate == 0) ||
156 (para->phy->data_en_bit == 0)) {
157 if (para->phy->phy_index == 0) {
159 (para->camsys_dev->devmems.registermem->vir_base);
161 (base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
163 camsys_trace(1, "mipi phy 0 standby!");
169 hsfreqrange_p = mipiphy_hsfreqrange;
171 i < (sizeof(mipiphy_hsfreqrange)/
172 sizeof(struct mipiphy_hsfreqrange_s));
174 if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
175 (para->phy->bit_rate <= hsfreqrange_p->range_h)) {
176 hsfreqrange = hsfreqrange_p->cfg_bit;
182 if (hsfreqrange == 0xff) {
183 camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
184 para->phy->bit_rate);
188 if (para->phy->phy_index == 0) {
189 if (strstr(para->camsys_dev->miscdev.name, "camsys_marvin1")) {
190 camsys_err("miscdev.name = %s,mipi phy index %d is invalidate\n",
191 para->camsys_dev->miscdev.name,
192 para->phy->phy_index);
196 write_grf_reg(GRF_SOC_CON21_OFFSET,
197 DPHY_RX0_FORCERXMODE_MASK |
198 (0x0 << DPHY_RX0_FORCERXMODE_BIT) |
199 DPHY_RX0_FORCETXSTOPMODE_MASK |
200 (0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
203 write_grf_reg(GRF_SOC_CON21_OFFSET,
204 DPHY_RX0_ENABLE_MASK |
205 (para->phy->data_en_bit << DPHY_RX0_ENABLE_BIT));
207 /* set lan turndisab as 1*/
208 write_grf_reg(GRF_SOC_CON21_OFFSET,
209 DPHY_RX0_TURNDISABLE_MASK |
210 (0xf << DPHY_RX0_TURNDISABLE_BIT));
211 write_grf_reg(GRF_SOC_CON21_OFFSET, (0x0<<4) | (0xf<<20));
213 /* set lan turnrequest as 0 */
214 write_grf_reg(GRF_SOC_CON9_OFFSET,
215 DPHY_RX0_TURNREQUEST_MASK |
216 (0x0 << DPHY_RX0_TURNREQUEST_BIT));
220 write_grf_reg(GRF_SOC_CON25_OFFSET,
221 DPHY_RX0_TESTCLK_MASK |
222 (0x1 << DPHY_RX0_TESTCLK_BIT)); /*TESTCLK=1 */
223 write_grf_reg(GRF_SOC_CON25_OFFSET,
224 DPHY_RX0_TESTCLR_MASK |
225 (0x1 << DPHY_RX0_TESTCLR_BIT)); /*TESTCLR=1*/
228 write_grf_reg(GRF_SOC_CON25_OFFSET,
229 DPHY_RX0_TESTCLR_MASK);
232 camsys_rk3399_mipiphy0_wr_reg
233 (para, 0x34, settle_bypass);
234 /*HS hsfreqrange & lane 0 settle bypass*/
235 camsys_rk3399_mipiphy0_wr_reg
236 (para, 0x44, hsfreqrange | settle_bypass);
237 camsys_rk3399_mipiphy0_wr_reg
238 (para, 0x54, settle_bypass);
239 camsys_rk3399_mipiphy0_wr_reg
240 (para, 0x84, settle_bypass);
241 camsys_rk3399_mipiphy0_wr_reg
242 (para, 0x94, settle_bypass);
243 camsys_rk3399_mipiphy0_wr_reg
244 (para, 0x75, (settle_en << 7) | manu_hsfreqrange);
245 camsys_rk3399_mipiphy0_rd_reg(para, 0x75);
247 camsys_rk3399_mipiphy0_wr_reg(para, 0x0, -1);
248 write_grf_reg(GRF_SOC_CON25_OFFSET,
249 DPHY_RX0_TESTCLK_MASK |
250 (1 << DPHY_RX0_TESTCLK_BIT)); /*TESTCLK=1*/
252 write_grf_reg(GRF_SOC_CON25_OFFSET,
253 (DPHY_RX0_TESTEN_MASK));
256 base = (para->camsys_dev->devmems.registermem->vir_base);
257 *((unsigned int *)(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL))) |=
260 } else if (para->phy->phy_index == 1) {
262 if (!strstr(para->camsys_dev->miscdev.name, "camsys_marvin1")) {
264 ("miscdev.name = %s,mipi phy index %d is invalidate\n",
265 para->camsys_dev->miscdev.name,
266 para->phy->phy_index);
270 write_grf_reg(GRF_SOC_CON23_OFFSET,
271 DPHY_RX0_FORCERXMODE_MASK |
272 (0x0 << DPHY_RX0_FORCERXMODE_BIT) |
273 DPHY_RX0_FORCETXSTOPMODE_MASK |
274 (0x0 << DPHY_RX0_FORCETXSTOPMODE_BIT));
275 write_grf_reg(GRF_SOC_CON24_OFFSET,
276 DPHY_TX1RX1_MASTERSLAVEZ_MASK |
277 (0x0 << DPHY_TX1RX1_MASTERSLAVEZ_BIT) |
278 DPHY_TX1RX1_BASEDIR_MASK |
279 (0x1 << DPHY_TX1RX1_BASEDIR_BIT) |
280 DPHY_RX1_MASK | 0x0 << DPHY_RX1_SEL_BIT);
283 write_grf_reg(GRF_SOC_CON23_OFFSET,
284 DPHY_TX1RX1_ENABLE_MASK |
285 (para->phy->data_en_bit << DPHY_TX1RX1_ENABLE_BIT));
287 /* set lan turndisab as 1*/
288 write_grf_reg(GRF_SOC_CON23_OFFSET,
289 DPHY_TX1RX1_TURNDISABLE_MASK |
290 (0xf << DPHY_TX1RX1_TURNDISABLE_BIT));
291 write_grf_reg(GRF_SOC_CON23_OFFSET, (0x0<<4)|(0xf<<20));
293 /* set lan turnrequest as 0*/
294 write_grf_reg(GRF_SOC_CON24_OFFSET,
295 DPHY_TX1RX1_TURNREQUEST_MASK |
296 (0x0 << DPHY_TX1RX1_TURNREQUEST_BIT));
300 res_val = read_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ);
301 res_val &= 0xfffffffe;
303 write_dsihost_reg(DSIHOST_PHY_SHUTDOWNZ, res_val);
304 vir_base = (unsigned long)ioremap(0xff910000, 0x10000);
305 /*__raw_writel(0x60000, (void*)(0x1c00+vir_base));*/
307 res_val = read_dsihost_reg(DSIHOST_DPHY_RSTZ);
308 res_val &= 0xfffffffd;
310 write_dsihost_reg(DSIHOST_DPHY_RSTZ, res_val);
312 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
313 /*TESTCLR=1 TESTCLK=1 */
314 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000003);
316 /*TESTCLR=0 TESTCLK=1*/
317 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
320 camsys_rk3399_mipiphy1_wr_reg
321 (dsiphy_virt, 0x34, settle_bypass);
322 /*HS hsfreqrange & lane 0 settle bypass*/
323 camsys_rk3399_mipiphy1_wr_reg
324 (dsiphy_virt, 0x44, hsfreqrange | settle_bypass);
325 camsys_rk3399_mipiphy1_wr_reg
326 (dsiphy_virt, 0x54, settle_bypass);
327 camsys_rk3399_mipiphy1_wr_reg
328 (dsiphy_virt, 0x84, settle_bypass);
329 camsys_rk3399_mipiphy1_wr_reg
330 (dsiphy_virt, 0x94, settle_bypass);
331 camsys_rk3399_mipiphy1_wr_reg
332 (dsiphy_virt, 0x75, (settle_en << 7) | manu_hsfreqrange);
333 camsys_rk3399_mipiphy1_rd_reg(dsiphy_virt, 0x75);
335 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL0, 0x00000002);
337 write_dsihost_reg(DSIHOST_PHY_TEST_CTRL1, 0x00000000);
338 /*SHUTDOWNZ=1*//*RSTZ=1*/
339 /*__raw_writel(0x60f00, (void*)(0x1c00+vir_base));*/
340 write_dsihost_reg(DSIHOST_DPHY_RSTZ, 0x00000002);
344 camsys_err("mipi phy index %d is invalidate!",
345 para->phy->phy_index);
349 camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
350 para->phy->phy_index, para->phy->data_en_bit,
351 para->phy->bit_rate);
359 #define MRV_AFM_BASE 0x0000
360 #define VI_IRCL 0x0014
361 int camsys_rk3399_cfg
362 (camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
364 unsigned int *para_int;
367 case Clk_DriverStrength_Cfg: {
368 para_int = (unsigned int *)cfg_para;
369 __raw_writel((((*para_int) & 0x03) << 3) | (0x03 << 3),
370 (void *)(camsys_dev->rk_grf_base + 0x204));
371 /* set 0xffffffff to max all */
375 case Cif_IoDomain_Cfg: {
376 para_int = (unsigned int *)cfg_para;
377 if (*para_int < 28000000) {
379 __raw_writel(((1 << 1) | (1 << (1 + 16))),
380 (void *)(camsys_dev->rk_grf_base + 0x0900));
383 __raw_writel(((0 << 1) | (1 << (1 + 16))),
384 (void *)(camsys_dev->rk_grf_base + 0x0900));
390 camsys_rk3399_mipihpy_cfg
391 ((camsys_mipiphy_soc_para_t *)cfg_para);
395 case Isp_SoftRst: /* ddl@rock-chips.com: v0.d.0 */ {
397 reset = (unsigned long)cfg_para;
400 __raw_writel(0x80, (void *)(camsys_dev->rk_isp_base +
401 MRV_AFM_BASE + VI_IRCL));
403 __raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
404 MRV_AFM_BASE + VI_IRCL));
409 camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
417 #endif /* CONFIG_ARM64 */