1 #ifndef __RKCAMSYS_SOC_RK3366_H__
2 #define __RKCAMSYS_SOC_RK3366_H__
4 #include "camsys_internal.h"
7 #define MRV_MIPI_BASE 0x1C00
8 #define MRV_MIPI_CTRL 0x00
11 *#define CSIHOST_PHY_TEST_CTRL0_OFFSET 0x0030
12 #define DPHY_TX1RX1_TESTCLR (1<<0)
13 #define DPHY_TX1RX1_TESTCLK (1<<1)
15 #define CSIHOST_PHY_TEST_CTRL1_OFFSET 0x0034
16 #define DPHY_TX1RX1_TESTDIN_OFFSET_BITS (0)
17 #define DPHY_TX1RX1_TESTDOUT_OFFSET_BITS (8)
18 #define DPHY_TX1RX1_TESTEN (16)
21 #define GRF_SOC_STATUS21 (0x2D4)
23 #define CSIHOST_PHY_TEST_CTRL0 (0x30)
24 #define CSIHOST_PHY_TEST_CTRL1 (0x34)
25 #define CSIHOST_N_LANES (0x04)
26 #define CSIHOST_PHY_SHUTDOWNZ (0x08)
27 #define CSIHOST_CSI2_RESETN (0x10)
28 #define CSIHOST_DPHY_RSTZ (0x0c)
29 #define CSIHOST_PHY_STATE (0x14)
30 #define CSIHOST_DATA_IDS1 (0x18)
31 #define CSIHOST_DATA_IDS2 (0x1C)
32 #define CSIHOST_ERR1 (0x20)
33 #define CSIHOST_ERR2 (0x24)
37 *dphy_rx_forcerxmode 11:8
38 *isp_mipi_csi_host_sel:1
40 *bit 0 grf_con_disable_isp
41 *bit 1 isp_mipi_csi_host_sel 1'b0: mipi csi host
43 #define GRF_SOC_CON6_OFFSET (0x0418)
45 #define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
46 #define MIPI_PHY_DISABLE_ISP (0x0 << 0)
48 #define ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK (0x1 << 17)
49 #define ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT (0x1)
51 #define DPHY_RX_CLK_INV_SEL_MASK (0x1 << 22)
52 #define DPHY_RX_CLK_INV_SEL (0x1 << 6)
54 #define DPHY_RX_FORCERXMODE_OFFSET_MASK (0xF << 24)
55 #define DPHY_RX_FORCERXMODE_OFFSET_BITS (8)
58 /*dphy_tx0_forcerxmode*/
59 #define GRF_SOC_CON7_OFFSET (0x041c)
61 #define FORCETXSTOPMODE_OFFSET_BITS (7)
62 #define FORCETXSTOPMODE_MASK (0xF << 23)
64 #define DPHY_TX0_FORCERXMODE (6)
65 #define DPHY_TX0_FORCERXMODE_MASK (0x01 << 22)
67 #define LANE0_TURNDISABLE_BITS (5)
68 #define LANE0_TURNDISABLE_MASK (0x01 << 21)
70 #define GRF_SOC_STATUS13 (0x04b4)
71 /*dphy_rx_rxclkactivehs*/
73 /*dphy_rx_ulpsactivenot_0...3*/
75 /*LOW POWER MODE SET*/
77 #define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET (0x00)
78 #define MIPI_CSI_DPHY_CTRL_LANE_ENABLE_OFFSET_BIT (2)
80 #define MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET (0x04)
81 #define MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET (0x80)
82 #define MIPI_CSI_DPHY_CTRL_SIG_INV_OFFSET (0x84)
84 /*Configure the count time of the THS-SETTLE by protocol.*/
85 #define MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET (0x00)
86 /*MSB enable for pin_rxdatahs_
90 #define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET (0x38)
92 #define CSIHOST_N_LANES_OFFSET 0x04
93 #define CSIHOST_N_LANES_OFFSET_BIT (0)
95 #define write_grf_reg(addr, val) \
96 __raw_writel(val, (void *)(addr + para->camsys_dev->rk_grf_base))
97 #define read_grf_reg(addr) \
98 __raw_readl((void *)(addr + para->camsys_dev->rk_grf_base))
99 #define mask_grf_reg(addr, msk, val) \
100 write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
102 #define write_cru_reg(addr, val) \
103 __raw_writel(val, (void *)(addr + para->camsys_dev->rk_cru_base))
105 /*#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
109 #define write_csihost_reg(addr, val) \
110 __raw_writel(val, (void *)(addr + phy_virt))
111 #define read_csihost_reg(addr) \
112 __raw_readl((void *)(addr + phy_virt))
114 #define write_csiphy_reg(addr, val) \
115 __raw_writel(val, (void *)(addr + csiphy_virt))
116 #define read_csiphy_reg(addr) \
117 __raw_readl((void *)(addr + csiphy_virt))