1 #ifndef __RKCAMSYS_SOC_RK3288_H__
2 #define __RKCAMSYS_SOC_RK3288_H__
4 #include "camsys_internal.h"
7 #define MRV_MIPI_BASE 0x1C00
8 #define MRV_MIPI_CTRL 0x00
11 //bit 0 dphy_rx0_testclr
12 //bit 1 dphy_rx0_testclk
13 //bit 2 dphy_rx0_testen
14 //bit 3:10 dphy_rx0_testdin
15 #define GRF_SOC_CON14_OFFSET (0x027c)
16 #define DPHY_RX0_TESTCLR_MASK (0x1<<16)
17 #define DPHY_RX0_TESTCLK_MASK (0x1<<17)
18 #define DPHY_RX0_TESTEN_MASK (0x1<<18)
19 #define DPHY_RX0_TESTDIN_MASK (0xff<<19)
21 #define DPHY_RX0_TESTCLR (1<<0)
22 #define DPHY_RX0_TESTCLK (1<<1)
23 #define DPHY_RX0_TESTEN (1<<2)
24 #define DPHY_RX0_TESTDIN_OFFSET (3)
26 #define DPHY_TX1RX1_ENABLECLK_MASK (0x1<<28)
27 #define DPHY_RX1_SRC_SEL_MASK (0x1<<29)
28 #define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1<<30)
29 #define DPHY_TX1RX1_BASEDIR_OFFSET (0x1<<31)
31 #define DPHY_TX1RX1_ENABLECLK (0x1<<12)
32 #define DPHY_TX1RX1_DISABLECLK (0x0<<12)
33 #define DPHY_RX1_SRC_SEL_ISP (0x1<<13)
34 #define DPHY_TX1RX1_SLAVEZ (0x0<<14)
35 #define DPHY_TX1RX1_BASEDIR_REC (0x1<<15)
40 //bit 0 grf_con_disable_isp
41 //bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
42 #define GRF_SOC_CON6_OFFSET (0x025c)
43 #define MIPI_PHY_DISABLE_ISP_MASK (0x1<<16)
44 #define MIPI_PHY_DISABLE_ISP (0x0<<0)
46 #define DSI_CSI_TESTBUS_SEL_MASK (0x1<<30)
47 #define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
50 #define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1<<17)
51 #define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
54 //bit12:15 grf_dphy_rx0_enable
55 //bit 0:3 turn disable
56 #define GRF_SOC_CON10_OFFSET (0x026c)
57 #define DPHY_RX0_TURN_DISABLE_MASK (0xf<<16)
58 #define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
59 #define DPHY_RX0_ENABLE_MASK (0xf<<28)
60 #define DPHY_RX0_ENABLE_OFFSET_BITS (12)
63 //bit12:15 grf_dphy_rx0_enable
64 //bit 0:3 turn disable
65 #define GRF_SOC_CON9_OFFSET (0x0268)
66 #define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf<<16)
67 #define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
68 #define DPHY_TX1RX1_ENABLE_MASK (0xf<<28)
69 #define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
72 //bit 0:3 turn request
73 #define GRF_SOC_CON15_OFFSET (0x03a4)
74 #define DPHY_RX0_TURN_REQUEST_MASK (0xf<<16)
75 #define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
77 #define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf<<20)
78 #define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
81 #define GRF_SOC_STATUS21 (0x2D4)
83 #define CSIHOST_PHY_TEST_CTRL0 (0x30)
84 #define CSIHOST_PHY_TEST_CTRL1 (0x34)
85 #define CSIHOST_PHY_SHUTDOWNZ (0x08)
86 #define CSIHOST_DPHY_RSTZ (0x0c)
87 #define CSIHOST_N_LANES (0x04)
88 #define CSIHOST_CSI2_RESETN (0x10)
89 #define CSIHOST_PHY_STATE (0x14)
90 #define CSIHOST_DATA_IDS1 (0x18)
91 #define CSIHOST_DATA_IDS2 (0x1C)
92 #define CSIHOST_ERR1 (0x20)
93 #define CSIHOST_ERR2 (0x24)
96 #define write_grf_reg(addr, val) __raw_writel(val, addr+RK_GRF_VIRT)
97 #define read_grf_reg(addr) __raw_readl(addr+RK_GRF_VIRT)
98 #define mask_grf_reg(addr, msk, val) write_grf_reg(addr,(val)|((~(msk))&read_grf_reg(addr)))
100 #define write_csihost_reg(addr, val) __raw_writel(val, addr+IOMEM(phy_virt))
101 #define read_csihost_reg(addr) __raw_readl(addr+IOMEM(phy_virt))