1 #ifndef __RKCAMSYS_SOC_RK3288_H__
2 #define __RKCAMSYS_SOC_RK3288_H__
4 #include "camsys_internal.h"
7 #define MRV_MIPI_BASE 0x1C00
8 #define MRV_MIPI_CTRL 0x00
12 *bit 0 dphy_rx0_testclr
13 *bit 1 dphy_rx0_testclk
14 *bit 2 dphy_rx0_testen
15 *bit 3:10 dphy_rx0_testdin
17 #define GRF_SOC_CON14_OFFSET (0x027c)
18 #define DPHY_RX0_TESTCLR_MASK (0x1 << 16)
19 #define DPHY_RX0_TESTCLK_MASK (0x1 << 17)
20 #define DPHY_RX0_TESTEN_MASK (0x1 << 18)
21 #define DPHY_RX0_TESTDIN_MASK (0xff << 19)
23 #define DPHY_RX0_TESTCLR (0x1 << 0)
24 #define DPHY_RX0_TESTCLK (0x1 << 1)
25 #define DPHY_RX0_TESTEN (0x1 << 2)
26 #define DPHY_RX0_TESTDIN_OFFSET (3)
28 #define DPHY_TX1RX1_ENABLECLK_MASK (0x1 << 28)
29 #define DPHY_RX1_SRC_SEL_MASK (0x1 << 29)
30 #define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1 << 30)
31 #define DPHY_TX1RX1_BASEDIR_OFFSET (0x1 << 31)
33 #define DPHY_TX1RX1_ENABLECLK (0x1 << 12)
34 #define DPHY_TX1RX1_DISABLECLK (0x0 << 12)
35 #define DPHY_RX1_SRC_SEL_ISP (0x1 << 13)
36 #define DPHY_TX1RX1_SLAVEZ (0x0 << 14)
37 #define DPHY_TX1RX1_BASEDIR_REC (0x1 << 15)
41 *bit 0 grf_con_disable_isp
42 *bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
44 #define GRF_SOC_CON6_OFFSET (0x025c)
45 #define MIPI_PHY_DISABLE_ISP_MASK (0x1 << 16)
46 #define MIPI_PHY_DISABLE_ISP (0x0 << 0)
48 #define DSI_CSI_TESTBUS_SEL_MASK (0x1 << 30)
49 #define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
51 #define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1 << 17)
52 #define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
56 *bit12:15 grf_dphy_rx0_enable
59 #define GRF_SOC_CON10_OFFSET (0x026c)
60 #define DPHY_RX0_TURN_DISABLE_MASK (0xf << 16)
61 #define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
62 #define DPHY_RX0_ENABLE_MASK (0xf << 28)
63 #define DPHY_RX0_ENABLE_OFFSET_BITS (12)
67 *bit12:15 grf_dphy_rx0_enable
70 #define GRF_SOC_CON9_OFFSET (0x0268)
71 #define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf << 16)
72 #define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
73 #define DPHY_TX1RX1_ENABLE_MASK (0xf << 28)
74 #define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
80 #define GRF_SOC_CON15_OFFSET (0x03a4)
81 #define DPHY_RX0_TURN_REQUEST_MASK (0xf << 16)
82 #define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
84 #define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf << 20)
85 #define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
87 #define GRF_SOC_STATUS21 (0x2D4)
89 #define CSIHOST_PHY_TEST_CTRL0 (0x30)
90 #define CSIHOST_PHY_TEST_CTRL1 (0x34)
91 #define CSIHOST_PHY_SHUTDOWNZ (0x08)
92 #define CSIHOST_DPHY_RSTZ (0x0c)
93 #define CSIHOST_N_LANES (0x04)
94 #define CSIHOST_CSI2_RESETN (0x10)
95 #define CSIHOST_PHY_STATE (0x14)
96 #define CSIHOST_DATA_IDS1 (0x18)
97 #define CSIHOST_DATA_IDS2 (0x1C)
98 #define CSIHOST_ERR1 (0x20)
99 #define CSIHOST_ERR2 (0x24)
101 #define write_grf_reg(addr, val) \
102 __raw_writel(val, addr + RK_GRF_VIRT)
103 #define read_grf_reg(addr) \
104 __raw_readl(addr + RK_GRF_VIRT)
105 #define mask_grf_reg(addr, msk, val) \
106 write_grf_reg(addr, (val) | ((~(msk)) & read_grf_reg(addr)))
108 #define cru_writel(v, o) \
109 do {writel(v, RK_CRU_VIRT + (o)); } \
112 #define write_csihost_reg(addr, val) \
113 __raw_writel(val, addr + (void __force __iomem *)(phy_virt))
114 #define read_csihost_reg(addr) \
115 __raw_readl(addr + (void __force __iomem *)(phy_virt))
117 #define cru_writel(v, o) \
118 do {writel(v, RK_CRU_VIRT + (o)); dsb(); } \
121 #define write_csihost_reg(addr, val) \
122 __raw_writel(val, addr + IOMEM(phy_virt))
123 #define read_csihost_reg(addr) \
124 __raw_readl(addr + IOMEM(phy_virt))