drivers/media/video/rk_camsys/camsys_soc_rk3288.c

   1 #ifdef CONFIG_ARM
   2 #include "camsys_soc_priv.h"
   3 #include "camsys_soc_rk3288.h"
   4
   5
   6 struct mipiphy_hsfreqrange_s {
   7         unsigned int range_l;
   8         unsigned int range_h;
   9         unsigned char cfg_bit;
  10 };
  11
  12 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
  13         {80, 90, 0x00},
  14         {90, 100, 0x10},
  15         {100, 110, 0x20},
  16         {110, 130, 0x01},
  17         {130, 140, 0x11},
  18         {140, 150, 0x21},
  19         {150, 170, 0x02},
  20         {170, 180, 0x12},
  21         {180, 200, 0x22},
  22         {200, 220, 0x03},
  23         {220, 240, 0x13},
  24         {240, 250, 0x23},
  25         {250, 270, 0x4},
  26         {270, 300, 0x14},
  27         {300, 330, 0x5},
  28         {330, 360, 0x15},
  29         {360, 400, 0x25},
  30         {400, 450, 0x06},
  31         {450, 500, 0x16},
  32         {500, 550, 0x07},
  33         {550, 600, 0x17},
  34         {600, 650, 0x08},
  35         {650, 700, 0x18},
  36         {700, 750, 0x09},
  37         {750, 800, 0x19},
  38         {800, 850, 0x29},
  39         {850, 900, 0x39},
  40         {900, 950, 0x0a},
  41         {950, 1000, 0x1a}
  42
  43 };
  44
  45
  46 static int camsys_rk3288_mipiphy0_wr_reg(
  47 unsigned char addr, unsigned char data)
  48 {
  49     /*TESTCLK=1*/
  50         write_grf_reg(GRF_SOC_CON14_OFFSET,
  51             DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
  52     /*TESTEN =1,TESTDIN=addr*/
  53         write_grf_reg(GRF_SOC_CON14_OFFSET,
  54                 ((addr << DPHY_RX0_TESTDIN_OFFSET)
  55                 |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN|
  56                 DPHY_RX0_TESTEN_MASK));
  57     /*TESTCLK=0*/
  58         write_grf_reg(GRF_SOC_CON14_OFFSET,
  59                 DPHY_RX0_TESTCLK_MASK);
  60
  61         if (data != 0xff) { /*write data ?*/
  62                 /*TESTEN =0,TESTDIN=data*/
  63                 write_grf_reg(GRF_SOC_CON14_OFFSET,
  64                         ((data << DPHY_RX0_TESTDIN_OFFSET)
  65                         | DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
  66
  67                 /*TESTCLK=1*/
  68                 write_grf_reg(GRF_SOC_CON14_OFFSET,
  69                         DPHY_RX0_TESTCLK_MASK |
  70                         DPHY_RX0_TESTCLK);
  71         }
  72         return 0;
  73 }
  74 #if 0
  75 static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr)
  76 {
  77         return read_grf_reg(GRF_SOC_STATUS21);
  78 }
  79 #endif
  80 static int camsys_rk3288_mipiphy1_wr_reg(
  81 unsigned int phy_virt, unsigned char addr, unsigned char data)
  82 {
  83         /*TESTEN =1,TESTDIN=addr*/
  84         write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000|addr));
  85         /*TESTCLK=0*/
  86         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
  87         /*TESTEN =0,TESTDIN=data*/
  88         write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000|data));
  89         /*TESTCLK=1*/
  90         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
  91
  92         return 0;
  93 }
  94
  95 static int camsys_rk3288_mipiphy1_rd_reg(
  96 unsigned int phy_virt, unsigned char addr)
  97 {
  98         return (read_csihost_reg
  99                         (((CSIHOST_PHY_TEST_CTRL1)&0xff00)) >> 8);
 100 }
 101
 102 static int camsys_rk3288_mipihpy_cfg(
 103 camsys_mipiphy_soc_para_t *para)
 104 {
 105         unsigned char hsfreqrange = 0xff, i;
 106         struct mipiphy_hsfreqrange_s *hsfreqrange_p;
 107         unsigned int phy_virt, phy_index;
 108         unsigned int *base;
 109
 110         phy_index = para->phy->phy_index;
 111         if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
 112                 phy_virt  =
 113                 para->camsys_dev->mipiphy[phy_index].reg->vir_base;
 114         } else {
 115                 phy_virt = 0x00;
 116         }
 117
 118         if ((para->phy->bit_rate == 0) ||
 119                 (para->phy->data_en_bit == 0)) {
 120                 if (para->phy->phy_index == 0) {
 121                         base =
 122                                 (unsigned int *)
 123                                 para->camsys_dev->devmems.registermem->vir_base;
 124                         *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4)
 125                                 &= ~(0x0f<<8);
 126                         camsys_trace(1, "mipi phy 0 standby!");
 127                 } else if (para->phy->phy_index == 1) {
 128                         /*SHUTDOWNZ=0*/
 129                         write_csihost_reg
 130                                 (CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
 131                         /*RSTZ=0*/
 132                         write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
 133
 134                         camsys_trace(1, "mipi phy 1 standby!");
 135                 }
 136
 137                 return 0;
 138         }
 139
 140         hsfreqrange_p = mipiphy_hsfreqrange;
 141         for (i = 0;
 142                 i <
 143                         (sizeof(mipiphy_hsfreqrange)/
 144                         sizeof(struct mipiphy_hsfreqrange_s));
 145                 i++) {
 146
 147                 if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
 148                         (para->phy->bit_rate <= hsfreqrange_p->range_h)) {
 149                         hsfreqrange = hsfreqrange_p->cfg_bit;
 150                         break;
 151                 }
 152                 hsfreqrange_p++;
 153         }
 154
 155         if (hsfreqrange == 0xff) {
 156                 camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
 157                         para->phy->bit_rate);
 158                 hsfreqrange = 0x00;
 159         }
 160         hsfreqrange <<= 1;
 161
 162         if (para->phy->phy_index == 0) {
 163                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 164                                         MIPI_PHY_DPHYSEL_OFFSET_MASK
 165                                         | (para->phy->phy_index
 166                                         << MIPI_PHY_DPHYSEL_OFFSET_BIT));
 167
 168                 /*  set lane num*/
 169                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 170                                         DPHY_RX0_ENABLE_MASK
 171                                         | (para->phy->data_en_bit
 172                                         << DPHY_RX0_ENABLE_OFFSET_BITS));
 173                 /*  set lan turndisab as 1*/
 174                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 175                                         DPHY_RX0_TURN_DISABLE_MASK
 176                                         | (0xf
 177                                         << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
 178                 write_grf_reg(GRF_SOC_CON10_OFFSET,
 179                                         (0x0<<4)|(0xf<<20));
 180                 /*  set lan turnrequest as 0 */
 181                 write_grf_reg(GRF_SOC_CON15_OFFSET,
 182                                         DPHY_RX0_TURN_REQUEST_MASK
 183                                         | (0x0
 184                                         << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
 185
 186                 /*phy start*/
 187                 {
 188                         /*TESTCLK=1  */
 189                         write_grf_reg(GRF_SOC_CON14_OFFSET,
 190                                                 DPHY_RX0_TESTCLK_MASK
 191                                                 | DPHY_RX0_TESTCLK);
 192                         /*TESTCLR=1*/
 193                         write_grf_reg(GRF_SOC_CON14_OFFSET,
 194                                                 DPHY_RX0_TESTCLR_MASK
 195                                                 | DPHY_RX0_TESTCLR);
 196                         udelay(100);
 197                          /*TESTCLR=0  zyc*/
 198                         write_grf_reg(GRF_SOC_CON14_OFFSET,
 199                                                 DPHY_RX0_TESTCLR_MASK);
 200                         udelay(100);
 201
 202                         /*set clock lane*/
 203                         camsys_rk3288_mipiphy0_wr_reg
 204                                 (0x34, 0x15);
 205                         if (para->phy->data_en_bit >= 0x00)
 206                                 camsys_rk3288_mipiphy0_wr_reg
 207                                         (0x44, hsfreqrange);
 208                         if (para->phy->data_en_bit >= 0x01)
 209                                 camsys_rk3288_mipiphy0_wr_reg(
 210                                         0x54, hsfreqrange);
 211                         if (para->phy->data_en_bit >= 0x04) {
 212                                 camsys_rk3288_mipiphy0_wr_reg
 213                                         (0x84, hsfreqrange);
 214                                 camsys_rk3288_mipiphy0_wr_reg
 215                                         (0x94, hsfreqrange);
 216                         }
 217
 218                         /*Normal operation*/
 219                         camsys_rk3288_mipiphy0_wr_reg(0x0, -1);
 220                     /*TESTCLK=1*/
 221                         write_grf_reg(GRF_SOC_CON14_OFFSET,
 222                                         DPHY_RX0_TESTCLK_MASK
 223                                         | DPHY_RX0_TESTCLK);
 224                         /*TESTEN =0 */
 225                         write_grf_reg(GRF_SOC_CON14_OFFSET,
 226                                         (DPHY_RX0_TESTEN_MASK));
 227                 }
 228
 229                 base =
 230                         (unsigned int *)
 231                         para->camsys_dev->devmems.registermem->vir_base;
 232                 *(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)/4)
 233                         |= (0x0f<<8);
 234
 235         } else if (para->phy->phy_index == 1) {
 236
 237                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 238                                         MIPI_PHY_DPHYSEL_OFFSET_MASK
 239                                         | (para->phy->phy_index
 240                                         << MIPI_PHY_DPHYSEL_OFFSET_BIT));
 241                 write_grf_reg(GRF_SOC_CON6_OFFSET,
 242                                         DSI_CSI_TESTBUS_SEL_MASK
 243                                         | (1
 244                                         << DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
 245
 246                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 247                                         DPHY_RX1_SRC_SEL_ISP
 248                                         | DPHY_RX1_SRC_SEL_MASK);
 249                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 250                                         DPHY_TX1RX1_SLAVEZ
 251                                         | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
 252                 write_grf_reg(GRF_SOC_CON14_OFFSET,
 253                                         DPHY_TX1RX1_BASEDIR_REC
 254                                         | DPHY_TX1RX1_BASEDIR_OFFSET);
 255
 256                 /*  set lane num*/
 257                 write_grf_reg(GRF_SOC_CON9_OFFSET,
 258                                         DPHY_TX1RX1_ENABLE_MASK
 259                                         | (para->phy->data_en_bit
 260                                         << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
 261                 /*  set lan turndisab as 1*/
 262                 write_grf_reg(GRF_SOC_CON9_OFFSET,
 263                                 DPHY_TX1RX1_TURN_DISABLE_MASK
 264                                 | (0xf
 265                                 << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
 266                 /*  set lan turnrequest as 0 */
 267                 write_grf_reg(GRF_SOC_CON15_OFFSET,
 268                                 DPHY_TX1RX1_TURN_REQUEST_MASK
 269                                 | (0x0
 270                                 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
 271
 272                 /*phy1 start*/
 273                 {
 274                         /*SHUTDOWNZ=0*/
 275                         write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
 276                         /*RSTZ=0*/
 277                         write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
 278                         /*TESTCLK=1*/
 279                         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 280                         /*TESTCLR=1 TESTCLK=1*/
 281                         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003);
 282                         udelay(100);
 283                         /*TESTCLR=0 TESTCLK=1*/
 284                         write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 285                         udelay(100);
 286
 287                         /*set clock lane*/
 288                         camsys_rk3288_mipiphy1_wr_reg
 289                                 (phy_virt, 0x34, 0x15);
 290                         if (para->phy->data_en_bit >= 0x00)
 291                                 camsys_rk3288_mipiphy1_wr_reg
 292                                         (phy_virt, 0x44, hsfreqrange);
 293                         if (para->phy->data_en_bit >= 0x01)
 294                                 camsys_rk3288_mipiphy1_wr_reg
 295                                         (phy_virt, 0x54, hsfreqrange);
 296                         if (para->phy->data_en_bit >= 0x04) {
 297                                 camsys_rk3288_mipiphy1_wr_reg
 298                                         (phy_virt, 0x84, hsfreqrange);
 299                                 camsys_rk3288_mipiphy1_wr_reg
 300                                         (phy_virt, 0x94, hsfreqrange);
 301                         }
 302
 303                         camsys_rk3288_mipiphy1_rd_reg
 304                                 (phy_virt, 0x0);
 305                         /*TESTCLK=1*/
 306                         write_csihost_reg
 307                                 (CSIHOST_PHY_TEST_CTRL0, 0x00000002);
 308                         /*TESTEN =0*/
 309                         write_csihost_reg
 310                                 (CSIHOST_PHY_TEST_CTRL1, 0x00000000);
 311                         /*SHUTDOWNZ=1*/
 312                         write_csihost_reg
 313                                 (CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
 314                         /*RSTZ=1*/
 315                         write_csihost_reg
 316                                 (CSIHOST_DPHY_RSTZ, 0x00000001);
 317                 }
 318         } else {
 319                 camsys_err("mipi phy index %d is invalidate!",
 320                         para->phy->phy_index);
 321                 goto fail;
 322         }
 323
 324         camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x  bit_rate: %dMbps)",
 325                         para->phy->phy_index,
 326                         para->phy->data_en_bit,
 327                         para->phy->bit_rate);
 328
 329         return 0;
 330
 331 fail:
 332         return -1;
 333 }
 334
 335 int camsys_rk3288_cfg(
 336 camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
 337 {
 338         unsigned int *para_int;
 339
 340         switch (cfg_cmd) {
 341         case Clk_DriverStrength_Cfg: {
 342                 para_int = (unsigned int *)cfg_para;
 343                 __raw_writel((((*para_int) & 0x03) << 3)|(0x03 << 3),
 344                         RK_GRF_VIRT + 0x01d4);
 345                 break;
 346         }
 347
 348         case Cif_IoDomain_Cfg: {
 349                 para_int = (unsigned int *)cfg_para;
 350                 if (*para_int < 28000000) {
 351                         /* 1.8v IO*/
 352                         __raw_writel
 353                                 (((1 << 1) | (1 << (1 + 16))),
 354                                 RK_GRF_VIRT + 0x0380);
 355                 } else {
 356                         /* 3.3v IO*/
 357                         __raw_writel
 358                                 (((0 << 1) | (1 << (1 + 16))),
 359                                 RK_GRF_VIRT + 0x0380);
 360                 }
 361                 break;
 362         }
 363
 364         case Mipi_Phy_Cfg: {
 365                 camsys_rk3288_mipihpy_cfg
 366                         ((camsys_mipiphy_soc_para_t *)cfg_para);
 367                 break;
 368         }
 369
 370         case Isp_SoftRst: {        /* ddl@rock-chips.com: v0.d.0 */
 371                 unsigned int reset;
 372
 373                 reset = (unsigned int)cfg_para;
 374
 375                 if (reset == 1)
 376                         cru_writel(0x40004000, 0x1d0);
 377                 else
 378                         cru_writel(0x40000000, 0x1d0);
 379                         camsys_trace(2, "Isp_SoftRst: %d", reset);
 380                 break;
 381         }
 382
 383         default: {
 384                 camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
 385                 break;
 386         }
 387         }
 388
 389         return 0;
 390 }
 391 #endif /* CONFIG_ARM */