1 #include "camsys_soc_priv.h"
2 #include "camsys_soc_rk3288.h"
5 struct mipiphy_hsfreqrange_s {
11 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
45 static int camsys_rk3288_mipiphy0_wr_reg(unsigned char addr, unsigned char data)
48 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
49 //TESTEN =1,TESTDIN=addr
50 write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
52 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
54 if(data != 0xff){ //write data ?
55 //TESTEN =0,TESTDIN=data
56 write_grf_reg(GRF_SOC_CON14_OFFSET, (( data << DPHY_RX0_TESTDIN_OFFSET)|DPHY_RX0_TESTDIN_MASK |DPHY_RX0_TESTEN_MASK));
59 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
64 static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr)
66 return read_grf_reg(GRF_SOC_STATUS21);
69 static int camsys_rk3288_mipiphy1_wr_reg(unsigned int phy_virt,unsigned char addr, unsigned char data)
72 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,(0x00010000|addr)); //TESTEN =1,TESTDIN=addr
73 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000000); //TESTCLK=0
74 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,(0x00000000|data)); //TESTEN =0,TESTDIN=data
75 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002); //TESTCLK=1
80 static int camsys_rk3288_mipiphy1_rd_reg(unsigned int phy_virt,unsigned char addr)
82 return (read_csihost_reg(((CSIHOST_PHY_TEST_CTRL1)&0xff00))>>8);
85 static int camsys_rk3288_mipihpy_cfg (camsys_mipiphy_soc_para_t *para)
87 unsigned char hsfreqrange=0xff,i;
88 struct mipiphy_hsfreqrange_s *hsfreqrange_p;
89 unsigned int phy_virt, phy_index;
92 phy_index = para->phy->phy_index;
93 if (para->camsys_dev->mipiphy[phy_index].reg!=NULL) {
94 phy_virt = para->camsys_dev->mipiphy[phy_index].reg->vir_base;
99 if ((para->phy->bit_rate == 0) || (para->phy->data_en_bit == 0)) {
100 if (para->phy->phy_index == 0) {
101 base = (unsigned int *)para->camsys_dev->devmems.registermem->vir_base;
102 *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4) &= ~(0x0f<<8);
103 camsys_trace(1, "mipi phy 0 standby!");
104 } else if (para->phy->phy_index == 1) {
105 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000000); //SHUTDOWNZ=0
106 write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000000); //RSTZ=0
108 camsys_trace(1, "mipi phy 1 standby!");
115 hsfreqrange_p = mipiphy_hsfreqrange;
116 for (i=0; i<(sizeof(mipiphy_hsfreqrange)/sizeof(struct mipiphy_hsfreqrange_s)); i++) {
118 if ((para->phy->bit_rate > hsfreqrange_p->range_l) && (para->phy->bit_rate <= hsfreqrange_p->range_h)) {
119 hsfreqrange = hsfreqrange_p->cfg_bit;
125 if (hsfreqrange == 0xff) {
126 camsys_err("mipi phy config bitrate %d Mbps isn't supported!",para->phy->bit_rate);
131 if (para->phy->phy_index == 0) {
132 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (para->phy->phy_index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
135 write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_ENABLE_MASK | (para->phy->data_en_bit << DPHY_RX0_ENABLE_OFFSET_BITS));
136 // set lan turndisab as 1
137 write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_TURN_DISABLE_MASK | (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
138 write_grf_reg(GRF_SOC_CON10_OFFSET, (0x0<<4)|(0xf<<20));
139 // set lan turnrequest as 0
140 write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_RX0_TURN_REQUEST_MASK | (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
144 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK); //TESTCLK=1
145 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK |DPHY_RX0_TESTCLR); //TESTCLR=1
147 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK); //TESTCLR=0 zyc
151 camsys_rk3288_mipiphy0_wr_reg(0x34,0x15);
152 if (para->phy->data_en_bit >= 0x00)
153 camsys_rk3288_mipiphy0_wr_reg(0x44,hsfreqrange);
154 if (para->phy->data_en_bit >= 0x01)
155 camsys_rk3288_mipiphy0_wr_reg(0x54,hsfreqrange);
156 if (para->phy->data_en_bit >= 0x04) {
157 camsys_rk3288_mipiphy0_wr_reg(0x84,hsfreqrange);
158 camsys_rk3288_mipiphy0_wr_reg(0x94,hsfreqrange);
162 camsys_rk3288_mipiphy0_wr_reg(0x0,-1);
163 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK); //TESTCLK=1
164 write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN_MASK)); //TESTEN =0
167 base = (unsigned int *)para->camsys_dev->devmems.registermem->vir_base;
168 *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4) |= (0x0f<<8);
170 } else if (para->phy->phy_index == 1){
172 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (para->phy->phy_index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
173 write_grf_reg(GRF_SOC_CON6_OFFSET, DSI_CSI_TESTBUS_SEL_MASK | (1<<DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
175 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
176 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
177 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
180 write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_ENABLE_MASK | (para->phy->data_en_bit << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
181 // set lan turndisab as 1
182 write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_TURN_DISABLE_MASK | (0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
183 // set lan turnrequest as 0
184 write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_TX1RX1_TURN_REQUEST_MASK | (0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
188 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000000); //SHUTDOWNZ=0
189 write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000000); //RSTZ=0
190 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002); //TESTCLK=1
191 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000003); //TESTCLR=1 TESTCLK=1
193 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002); //TESTCLR=0 TESTCLK=1
197 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x34,0x15);
198 if (para->phy->data_en_bit >= 0x00)
199 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x44,hsfreqrange);
200 if (para->phy->data_en_bit >= 0x01)
201 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x54,hsfreqrange);
202 if (para->phy->data_en_bit >= 0x04) {
203 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x84,hsfreqrange);
204 camsys_rk3288_mipiphy1_wr_reg(phy_virt,0x94,hsfreqrange);
207 camsys_rk3288_mipiphy1_rd_reg(phy_virt,0x0);
208 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0,0x00000002); //TESTCLK=1
209 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1,0x00000000); //TESTEN =0
210 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ,0x00000001); //SHUTDOWNZ=1
211 write_csihost_reg(CSIHOST_DPHY_RSTZ,0x00000001); //RSTZ=1
214 camsys_err("mipi phy index %d is invalidate!",para->phy->phy_index);
218 camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",para->phy->phy_index,para->phy->data_en_bit, para->phy->bit_rate);
227 int camsys_rk3288_cfg (camsys_soc_cfg_t cfg_cmd, void* cfg_para)
229 unsigned int *para_int;
233 case Clk_DriverStrength_Cfg:
235 para_int = (unsigned int*)cfg_para;
236 __raw_writel((((*para_int)&0x03)<<3)|(0x03<<3), RK_GRF_VIRT+0x01d4);
240 case Cif_IoDomain_Cfg:
242 para_int = (unsigned int*)cfg_para;
243 if (*para_int < 28000000) {
244 __raw_writel(((1<<1)|(1<<(1+16))),RK_GRF_VIRT+0x0380); // 1.8v IO
246 __raw_writel(((0<<1)|(1<<(1+16))),RK_GRF_VIRT+0x0380); // 3.3v IO
253 camsys_rk3288_mipihpy_cfg((camsys_mipiphy_soc_para_t*)cfg_para);
257 case Isp_SoftRst: /* ddl@rock-chips.com: v0.d.0 */
260 reset = (unsigned int)cfg_para;
263 cru_writel(0x40004000,0x1d0);
265 cru_writel(0x40000000,0x1d0);
266 camsys_trace(1, "Isp_SoftRst: %d",reset);
272 camsys_warn("cfg_cmd: 0x%x isn't support",cfg_cmd);