2 #include "camsys_soc_priv.h"
3 #include "camsys_soc_rk3288.h"
6 struct mipiphy_hsfreqrange_s {
12 static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
46 static int camsys_rk3288_mipiphy0_wr_reg(
47 unsigned char addr, unsigned char data)
50 write_grf_reg(GRF_SOC_CON14_OFFSET,
51 DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
52 /*TESTEN =1,TESTDIN=addr*/
53 write_grf_reg(GRF_SOC_CON14_OFFSET,
54 ((addr << DPHY_RX0_TESTDIN_OFFSET)
55 |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN|
56 DPHY_RX0_TESTEN_MASK));
58 write_grf_reg(GRF_SOC_CON14_OFFSET,
59 DPHY_RX0_TESTCLK_MASK);
61 if (data != 0xff) { /*write data ?*/
62 /*TESTEN =0,TESTDIN=data*/
63 write_grf_reg(GRF_SOC_CON14_OFFSET,
64 ((data << DPHY_RX0_TESTDIN_OFFSET)
65 | DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN_MASK));
68 write_grf_reg(GRF_SOC_CON14_OFFSET,
69 DPHY_RX0_TESTCLK_MASK |
75 static int camsys_rk3288_mipiphy0_rd_reg(unsigned char addr)
77 return read_grf_reg(GRF_SOC_STATUS21);
80 static int camsys_rk3288_mipiphy1_wr_reg(
81 unsigned int phy_virt, unsigned char addr, unsigned char data)
83 /*TESTEN =1,TESTDIN=addr*/
84 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00010000|addr));
86 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000000);
87 /*TESTEN =0,TESTDIN=data*/
88 write_csihost_reg(CSIHOST_PHY_TEST_CTRL1, (0x00000000|data));
90 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
95 static int camsys_rk3288_mipiphy1_rd_reg(
96 unsigned int phy_virt, unsigned char addr)
98 return (read_csihost_reg
99 (((CSIHOST_PHY_TEST_CTRL1)&0xff00)) >> 8);
102 static int camsys_rk3288_mipihpy_cfg(
103 camsys_mipiphy_soc_para_t *para)
105 unsigned char hsfreqrange = 0xff, i;
106 struct mipiphy_hsfreqrange_s *hsfreqrange_p;
107 unsigned int phy_virt, phy_index;
110 phy_index = para->phy->phy_index;
111 if (para->camsys_dev->mipiphy[phy_index].reg != NULL) {
113 para->camsys_dev->mipiphy[phy_index].reg->vir_base;
118 if ((para->phy->bit_rate == 0) ||
119 (para->phy->data_en_bit == 0)) {
120 if (para->phy->phy_index == 0) {
123 para->camsys_dev->devmems.registermem->vir_base;
124 *(base + (MRV_MIPI_BASE+MRV_MIPI_CTRL)/4)
126 camsys_trace(1, "mipi phy 0 standby!");
127 } else if (para->phy->phy_index == 1) {
130 (CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
132 write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
134 camsys_trace(1, "mipi phy 1 standby!");
140 hsfreqrange_p = mipiphy_hsfreqrange;
143 (sizeof(mipiphy_hsfreqrange)/
144 sizeof(struct mipiphy_hsfreqrange_s));
147 if ((para->phy->bit_rate > hsfreqrange_p->range_l) &&
148 (para->phy->bit_rate <= hsfreqrange_p->range_h)) {
149 hsfreqrange = hsfreqrange_p->cfg_bit;
155 if (hsfreqrange == 0xff) {
156 camsys_err("mipi phy config bitrate %d Mbps isn't supported!",
157 para->phy->bit_rate);
162 if (para->phy->phy_index == 0) {
163 write_grf_reg(GRF_SOC_CON6_OFFSET,
164 MIPI_PHY_DPHYSEL_OFFSET_MASK
165 | (para->phy->phy_index
166 << MIPI_PHY_DPHYSEL_OFFSET_BIT));
169 write_grf_reg(GRF_SOC_CON10_OFFSET,
171 | (para->phy->data_en_bit
172 << DPHY_RX0_ENABLE_OFFSET_BITS));
173 /* set lan turndisab as 1*/
174 write_grf_reg(GRF_SOC_CON10_OFFSET,
175 DPHY_RX0_TURN_DISABLE_MASK
177 << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
178 write_grf_reg(GRF_SOC_CON10_OFFSET,
180 /* set lan turnrequest as 0 */
181 write_grf_reg(GRF_SOC_CON15_OFFSET,
182 DPHY_RX0_TURN_REQUEST_MASK
184 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
189 write_grf_reg(GRF_SOC_CON14_OFFSET,
190 DPHY_RX0_TESTCLK_MASK
193 write_grf_reg(GRF_SOC_CON14_OFFSET,
194 DPHY_RX0_TESTCLR_MASK
198 write_grf_reg(GRF_SOC_CON14_OFFSET,
199 DPHY_RX0_TESTCLR_MASK);
203 camsys_rk3288_mipiphy0_wr_reg
205 if (para->phy->data_en_bit >= 0x00)
206 camsys_rk3288_mipiphy0_wr_reg
208 if (para->phy->data_en_bit >= 0x01)
209 camsys_rk3288_mipiphy0_wr_reg(
211 if (para->phy->data_en_bit >= 0x04) {
212 camsys_rk3288_mipiphy0_wr_reg
214 camsys_rk3288_mipiphy0_wr_reg
219 camsys_rk3288_mipiphy0_wr_reg(0x0, -1);
221 write_grf_reg(GRF_SOC_CON14_OFFSET,
222 DPHY_RX0_TESTCLK_MASK
225 write_grf_reg(GRF_SOC_CON14_OFFSET,
226 (DPHY_RX0_TESTEN_MASK));
231 para->camsys_dev->devmems.registermem->vir_base;
232 *(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)/4)
235 } else if (para->phy->phy_index == 1) {
237 write_grf_reg(GRF_SOC_CON6_OFFSET,
238 MIPI_PHY_DPHYSEL_OFFSET_MASK
239 | (para->phy->phy_index
240 << MIPI_PHY_DPHYSEL_OFFSET_BIT));
241 write_grf_reg(GRF_SOC_CON6_OFFSET,
242 DSI_CSI_TESTBUS_SEL_MASK
244 << DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
246 write_grf_reg(GRF_SOC_CON14_OFFSET,
248 | DPHY_RX1_SRC_SEL_MASK);
249 write_grf_reg(GRF_SOC_CON14_OFFSET,
251 | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
252 write_grf_reg(GRF_SOC_CON14_OFFSET,
253 DPHY_TX1RX1_BASEDIR_REC
254 | DPHY_TX1RX1_BASEDIR_OFFSET);
257 write_grf_reg(GRF_SOC_CON9_OFFSET,
258 DPHY_TX1RX1_ENABLE_MASK
259 | (para->phy->data_en_bit
260 << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
261 /* set lan turndisab as 1*/
262 write_grf_reg(GRF_SOC_CON9_OFFSET,
263 DPHY_TX1RX1_TURN_DISABLE_MASK
265 << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
266 /* set lan turnrequest as 0 */
267 write_grf_reg(GRF_SOC_CON15_OFFSET,
268 DPHY_TX1RX1_TURN_REQUEST_MASK
270 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
275 write_csihost_reg(CSIHOST_PHY_SHUTDOWNZ, 0x00000000);
277 write_csihost_reg(CSIHOST_DPHY_RSTZ, 0x00000000);
279 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
280 /*TESTCLR=1 TESTCLK=1*/
281 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000003);
283 /*TESTCLR=0 TESTCLK=1*/
284 write_csihost_reg(CSIHOST_PHY_TEST_CTRL0, 0x00000002);
288 camsys_rk3288_mipiphy1_wr_reg
289 (phy_virt, 0x34, 0x15);
290 if (para->phy->data_en_bit >= 0x00)
291 camsys_rk3288_mipiphy1_wr_reg
292 (phy_virt, 0x44, hsfreqrange);
293 if (para->phy->data_en_bit >= 0x01)
294 camsys_rk3288_mipiphy1_wr_reg
295 (phy_virt, 0x54, hsfreqrange);
296 if (para->phy->data_en_bit >= 0x04) {
297 camsys_rk3288_mipiphy1_wr_reg
298 (phy_virt, 0x84, hsfreqrange);
299 camsys_rk3288_mipiphy1_wr_reg
300 (phy_virt, 0x94, hsfreqrange);
303 camsys_rk3288_mipiphy1_rd_reg
307 (CSIHOST_PHY_TEST_CTRL0, 0x00000002);
310 (CSIHOST_PHY_TEST_CTRL1, 0x00000000);
313 (CSIHOST_PHY_SHUTDOWNZ, 0x00000001);
316 (CSIHOST_DPHY_RSTZ, 0x00000001);
319 camsys_err("mipi phy index %d is invalidate!",
320 para->phy->phy_index);
324 camsys_trace(1, "mipi phy(%d) turn on(lane: 0x%x bit_rate: %dMbps)",
325 para->phy->phy_index,
326 para->phy->data_en_bit,
327 para->phy->bit_rate);
335 int camsys_rk3288_cfg(
336 camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
338 unsigned int *para_int;
341 case Clk_DriverStrength_Cfg: {
342 para_int = (unsigned int *)cfg_para;
343 __raw_writel((((*para_int) & 0x03) << 3)|(0x03 << 3),
344 RK_GRF_VIRT + 0x01d4);
348 case Cif_IoDomain_Cfg: {
349 para_int = (unsigned int *)cfg_para;
350 if (*para_int < 28000000) {
353 (((1 << 1) | (1 << (1 + 16))),
354 RK_GRF_VIRT + 0x0380);
358 (((0 << 1) | (1 << (1 + 16))),
359 RK_GRF_VIRT + 0x0380);
365 camsys_rk3288_mipihpy_cfg
366 ((camsys_mipiphy_soc_para_t *)cfg_para);
370 case Isp_SoftRst: { /* ddl@rock-chips.com: v0.d.0 */
373 reset = (unsigned int)cfg_para;
376 cru_writel(0x40004000, 0x1d0);
378 cru_writel(0x40000000, 0x1d0);
379 camsys_trace(1, "Isp_SoftRst: %d", reset);
384 camsys_warn("cfg_cmd: 0x%x isn't support", cfg_cmd);
391 #endif /* CONFIG_ARM */