1 #include "camsys_mipicsi_phy.h"
3 #if defined(CONFIG_ARCH_ROCKCHIP)
5 //bit 0 dphy_rx0_testclr
6 //bit 1 dphy_rx0_testclk
7 //bit 2 dphy_rx0_testen
8 //bit 3:10 dphy_rx0_testdin
9 #define GRF_SOC_CON14_OFFSET (0x027c)
10 #define DPHY_RX0_TESTCLR_MASK (0x1<<16)
11 #define DPHY_RX0_TESTCLK_MASK (0x1<<17)
12 #define DPHY_RX0_TESTEN_MASK (0x1<<18)
13 #define DPHY_RX0_TESTDIN_MASK (0xff<<19)
15 #define DPHY_RX0_TESTCLR (1<<0)
16 #define DPHY_RX0_TESTCLK (1<<1)
17 #define DPHY_RX0_TESTEN (1<<2)
18 #define DPHY_RX0_TESTDIN_OFFSET (3)
20 #define DPHY_TX1RX1_ENABLECLK_MASK (0x1<<28)
21 #define DPHY_RX1_SRC_SEL_MASK (0x1<<29)
22 #define DPHY_TX1RX1_MASTERSLAVEZ_MASK (0x1<<30)
23 #define DPHY_TX1RX1_BASEDIR_OFFSET (0x1<<31)
25 #define DPHY_TX1RX1_ENABLECLK (0x1<<12)
26 #define DPHY_TX1RX1_DISABLECLK (0x0<<12)
27 #define DPHY_RX1_SRC_SEL_ISP (0x1<<13)
28 #define DPHY_TX1RX1_SLAVEZ (0x0<<14)
29 #define DPHY_TX1RX1_BASEDIR_REC (0x1<<15)
34 //bit 0 grf_con_disable_isp
35 //bit 1 grf_con_isp_dphy_sel 1'b0 mipi phy rx0
36 #define GRF_SOC_CON6_OFFSET (0x025c)
37 #define MIPI_PHY_DISABLE_ISP_MASK (0x1<<16)
38 #define MIPI_PHY_DISABLE_ISP (0x0<<0)
40 #define DSI_CSI_TESTBUS_SEL_MASK (0x1<<30)
41 #define DSI_CSI_TESTBUS_SEL_OFFSET_BIT (14)
44 #define MIPI_PHY_DPHYSEL_OFFSET_MASK (0x1<<17)
45 #define MIPI_PHY_DPHYSEL_OFFSET_BIT (0x1)
48 //bit12:15 grf_dphy_rx0_enable
49 //bit 0:3 turn disable
50 #define GRF_SOC_CON10_OFFSET (0x026c)
51 #define DPHY_RX0_TURN_DISABLE_MASK (0xf<<16)
52 #define DPHY_RX0_TURN_DISABLE_OFFSET_BITS (0x0)
53 #define DPHY_RX0_ENABLE_MASK (0xf<<28)
54 #define DPHY_RX0_ENABLE_OFFSET_BITS (12)
57 //bit12:15 grf_dphy_rx0_enable
58 //bit 0:3 turn disable
59 #define GRF_SOC_CON9_OFFSET (0x0268)
60 #define DPHY_TX1RX1_TURN_DISABLE_MASK (0xf<<16)
61 #define DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS (0x0)
62 #define DPHY_TX1RX1_ENABLE_MASK (0xf<<28)
63 #define DPHY_TX1RX1_ENABLE_OFFSET_BITS (12)
66 //bit 0:3 turn request
67 #define GRF_SOC_CON15_OFFSET (0x03a4)
68 #define DPHY_RX0_TURN_REQUEST_MASK (0xf<<16)
69 #define DPHY_RX0_TURN_REQUEST_OFFSET_BITS (0x0)
71 #define DPHY_TX1RX1_TURN_REQUEST_MASK (0xf<<20)
72 #define DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS (0x0)
78 static void phy_select(uint8_t index)
80 if((index == 0) || (index == 1)){
81 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DPHYSEL_OFFSET_MASK | (index<<MIPI_PHY_DPHYSEL_OFFSET_BIT));
83 write_grf_reg(GRF_SOC_CON6_OFFSET, DSI_CSI_TESTBUS_SEL_MASK | (1<<DSI_CSI_TESTBUS_SEL_OFFSET_BIT));
85 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX1_SRC_SEL_ISP | DPHY_RX1_SRC_SEL_MASK);
86 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_SLAVEZ | DPHY_TX1RX1_MASTERSLAVEZ_MASK);
87 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_TX1RX1_BASEDIR_REC | DPHY_TX1RX1_BASEDIR_OFFSET);
91 camsys_err("phy index is erro!");
97 static void phy0_WriteReg(uint8_t addr, uint8_t data)
99 // uint8_t test_data = 0;
100 //TESTEN =1,TESTDIN=addr
101 write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
103 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
106 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
108 if(data != -1){ //write data ?
109 //TESTEN =0,TESTDIN=data
110 write_grf_reg(GRF_SOC_CON14_OFFSET, (( data << DPHY_RX0_TESTDIN_OFFSET)|DPHY_RX0_TESTDIN_MASK |DPHY_RX0_TESTEN));
113 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
117 static uint8_t phy0_ReadReg(uint8_t addr)
121 //TESTEN =1,TESTDIN=addr
122 write_grf_reg(GRF_SOC_CON14_OFFSET,(( addr << DPHY_RX0_TESTDIN_OFFSET) |DPHY_RX0_TESTDIN_MASK | DPHY_RX0_TESTEN| DPHY_RX0_TESTEN_MASK));
125 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK);
132 static void phy_config_num_lane(uint8_t index,int numLane)
134 uint8_t lane_mask =0;
137 for(i=0;i<numLane;i++){
140 camsys_trace(1,"lane num = 0x%d\n",lane_mask);
143 write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_ENABLE_MASK | (lane_mask << DPHY_RX0_ENABLE_OFFSET_BITS));
144 // set lan turndisab as 1
145 write_grf_reg(GRF_SOC_CON10_OFFSET, DPHY_RX0_TURN_DISABLE_MASK | (0xf << DPHY_RX0_TURN_DISABLE_OFFSET_BITS));
147 write_grf_reg(GRF_SOC_CON10_OFFSET, (0xc<<4)|(0xf<<20));
149 // set lan turnrequest as 0
150 write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_RX0_TURN_REQUEST_MASK | (0x0 << DPHY_RX0_TURN_REQUEST_OFFSET_BITS));
151 }else if(index == 1){
153 write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_ENABLE_MASK | (lane_mask << DPHY_TX1RX1_ENABLE_OFFSET_BITS));
154 // set lan turndisab as 1
155 write_grf_reg(GRF_SOC_CON9_OFFSET, DPHY_TX1RX1_TURN_DISABLE_MASK | (0xf << DPHY_TX1RX1_TURN_DISABLE_OFFSET_BITS));
156 // set lan turnrequest as 0
157 write_grf_reg(GRF_SOC_CON15_OFFSET, DPHY_TX1RX1_TURN_REQUEST_MASK | (0x0 << DPHY_TX1RX1_TURN_REQUEST_OFFSET_BITS));
161 static void phy0_start(int freq,int numLane)
164 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
166 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK |DPHY_RX0_TESTCLR);
168 // write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLR_MASK);
171 //**********************************************************************//
175 phy0_WriteReg(0x34,0x14);
178 /********************
184 phy0_WriteReg(0x44,0x10);
186 phy0_WriteReg(0x54,0x10);
189 //**********************************************************************//
192 phy0_WriteReg(0x0,-1);
194 write_grf_reg(GRF_SOC_CON14_OFFSET, DPHY_RX0_TESTCLK_MASK |DPHY_RX0_TESTCLK);
197 write_grf_reg(GRF_SOC_CON14_OFFSET, (DPHY_RX0_TESTEN_MASK));
203 static int camsys_mipiphy_ops (void *phy, void *phyinfo, unsigned int on)
206 camsys_phyinfo_t* phyinfo_s = (camsys_phyinfo_t*)phyinfo;
207 struct camsys_mipiphy_s* phy_s = (struct camsys_mipiphy_s*)phy;
208 if(phy_s->phy_index == 0){
209 phy_select(phy_s->phy_index);
210 phy_config_num_lane(phy_s->data_en_bit);
211 phy0_start(0,phy_s->data_en_bit);
213 }else if(phy_s->phy_index == 1){
217 camsys_err("phy index is erro!");
223 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 1);
225 // phy_config_num_lane(0,2);
228 phy_config_num_lane(0,2);
231 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 0);
236 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 1);
238 phy_config_num_lane(0,1);
243 write_grf_reg(GRF_SOC_CON6_OFFSET, MIPI_PHY_DISABLE_ISP_MASK | 0);
250 static int camsys_mipiphy_clkin_cb(void *ptr, unsigned int on)
255 static int camsys_mipiphy_remove_cb(struct platform_device *pdev)
259 int camsys_mipiphy_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev)
262 camsys_dev->mipiphy.clkin_cb = camsys_mipiphy_clkin_cb;
263 camsys_dev->mipiphy.ops = camsys_mipiphy_ops;
264 camsys_dev->mipiphy.remove = camsys_mipiphy_remove_cb;