1 #include "camsys_marvin.h"
2 #include "camsys_soc_priv.h"
3 #include "camsys_gpio.h"
5 #include <linux/rockchip/common.h>
6 #include <dt-bindings/clock/rk_system_status.h>
7 #include <linux/rockchip_ion.h>
8 #include <linux/file.h>
9 #include <linux/pm_runtime.h>
11 #include <linux/dma-iommu.h>
12 #include <drm/rockchip_drm.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dma-buf.h>
16 extern int rockchip_set_system_status(unsigned long status);
17 extern int rockchip_clear_system_status(unsigned long status);
19 static const char miscdev_name[] = CAMSYS_MARVIN_DEVNAME;
21 static int camsys_mrv_iomux_cb(camsys_extdev_t *extdev, void *ptr)
23 struct pinctrl *pinctrl;
24 struct pinctrl_state *state;
26 char state_str[64] = {0};
27 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
28 struct device *dev = &(extdev->pdev->dev);
29 camsys_soc_priv_t *soc;
33 if (extdev->phy.type == CamSys_Phy_Cif) {
34 switch (extdev->phy.info.cif.fmt) {
35 case CamSys_Fmt_Raw_8b:
36 case CamSys_Fmt_Yuv420_8b:
37 case CamSys_Fmt_Yuv422_8b:{
38 if (extdev->phy.info.cif.cifio ==
39 CamSys_SensorBit0_CifBit0) {
40 strcpy(state_str, "isp_dvp8bit0");
41 } else if (extdev->phy.info.cif.cifio ==
42 CamSys_SensorBit0_CifBit2) {
43 strcpy(state_str, "isp_dvp8bit2");
44 } else if (extdev->phy.info.cif.cifio ==
45 CamSys_SensorBit0_CifBit4) {
46 strcpy(state_str, "isp_dvp8bit4");
48 camsys_err("extdev->phy.info.cif.cifio:0x%x is invalidate!",
49 extdev->phy.info.cif.cifio);
56 case CamSys_Fmt_Raw_10b:{
57 strcpy(state_str, "isp_dvp10bit");
61 case CamSys_Fmt_Raw_12b:{
62 strcpy(state_str, "isp_dvp12bit");
67 camsys_err("extdev->phy.info.cif.fmt: 0x%x is invalidate!",
68 extdev->phy.info.cif.fmt);
73 if (extdev->dev_cfg & CAMSYS_DEVCFG_FLASHLIGHT) {
74 if (extdev->dev_cfg & CAMSYS_DEVCFG_PREFLASHLIGHT) {
75 strcpy(state_str, "isp_mipi_fl_prefl");
77 strcpy(state_str, "isp_mipi_fl");
80 /*mux triggerout as gpio*/
83 enum of_gpio_flags flags;
86 of_get_named_gpio_flags(
87 camsys_dev->pdev->dev.of_node,
88 "rockchip,gpios", 0, &flags);
89 if (gpio_is_valid(flash_trigger_io)) {
91 of_get_named_gpio_flags(
92 camsys_dev->pdev->dev.of_node,
93 "rockchip,gpios", 0, &flags);
94 gpio_request(flash_trigger_io,
96 gpio_direction_output(
98 (~(extdev->fl.fl.active) &
103 if (CHIP_TYPE == 3399) {
104 strcpy(state_str, "cif_clkout");
106 strcpy(state_str, "default");
111 camsys_trace(1, "marvin pinctrl select: %s", state_str);
113 pinctrl = devm_pinctrl_get(dev);
114 if (IS_ERR(pinctrl)) {
115 camsys_err("devm_pinctrl_get failed!");
118 state = pinctrl_lookup_state(pinctrl,
121 camsys_err("pinctrl_lookup_state failed!");
125 if (!IS_ERR(state)) {
126 retval = pinctrl_select_state(pinctrl, state);
128 camsys_err("pinctrl_select_state failed!");
133 if (camsys_dev->soc) {
134 soc = (camsys_soc_priv_t *)camsys_dev->soc;
136 (soc->soc_cfg)(camsys_dev, Cif_IoDomain_Cfg,
137 (void *)&extdev->dovdd.min_uv);
138 (soc->soc_cfg)(camsys_dev, Clk_DriverStrength_Cfg,
139 (void *)&extdev->clk.driver_strength);
141 camsys_err("camsys_dev->soc->soc_cfg is NULL!");
144 camsys_err("camsys_dev->soc is NULL!");
152 static int camsys_mrv_flash_trigger_cb(void *ptr, int mode, unsigned int on)
154 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
155 struct device *dev = &(camsys_dev->pdev->dev);
156 int flash_trigger_io;
157 struct pinctrl *pinctrl;
158 struct pinctrl_state *state;
159 char state_str[63] = {0};
161 enum of_gpio_flags flags;
162 camsys_extdev_t *extdev = NULL;
165 strcpy(state_str, "isp_flash_as_gpio");
166 pinctrl = devm_pinctrl_get(dev);
167 if (IS_ERR(pinctrl)) {
168 camsys_err("devm_pinctrl_get failed!");
170 state = pinctrl_lookup_state(pinctrl, state_str);
172 camsys_err("pinctrl_lookup_state failed!");
175 if (!IS_ERR(state)) {
176 retval = pinctrl_select_state(pinctrl, state);
178 camsys_err("pinctrl_select_state failed!");
183 flash_trigger_io = of_get_named_gpio_flags(
184 camsys_dev->pdev->dev.of_node,
185 "rockchip,gpios", 0, &flags);
186 if (gpio_is_valid(flash_trigger_io)) {
187 flash_trigger_io = of_get_named_gpio_flags(
188 camsys_dev->pdev->dev.of_node,
189 "rockchip,gpios", 0, &flags);
190 gpio_request(flash_trigger_io, "camsys_gpio");
191 /*get flash io active pol*/
192 if (!list_empty(&camsys_dev->extdevs.list)) {
194 extdev, &camsys_dev->extdevs.list,
196 if (extdev->dev_cfg &
197 CAMSYS_DEVCFG_FLASHLIGHT) {
198 gpio_direction_output(
200 (~(extdev->fl.fl.active)
207 strcpy(state_str, "isp_flash_as_trigger_out");
208 pinctrl = devm_pinctrl_get(dev);
209 if (IS_ERR(pinctrl)) {
210 camsys_err("devm_pinctrl_get failed!");
212 state = pinctrl_lookup_state(pinctrl,
215 camsys_err("pinctrl_lookup_state failed!");
218 if (!IS_ERR(state)) {
219 retval = pinctrl_select_state(pinctrl, state);
221 camsys_err("pinctrl_select_state failed!");
228 static struct device *rockchip_get_sysmmu_device_by_compatible(
231 struct device_node *dn = NULL;
232 struct platform_device *pd = NULL;
233 struct device *ret = NULL;
235 dn = of_find_compatible_node(NULL, NULL, compt);
237 camsys_err("can't find device node %s \r\n", compt);
241 pd = of_find_device_by_node(dn);
244 "can't find platform device in device node %s \r\n",
253 #ifdef CONFIG_IOMMU_API
254 static inline void platform_set_sysmmu(
255 struct device *iommu, struct device *dev)
257 dev->archdata.iommu = iommu;
260 static inline void platform_set_sysmmu(
261 struct device *iommu, struct device *dev)
267 static int camsys_mrv_iommu_cb(void *ptr, camsys_sysctrl_t *devctl)
269 struct device *iommu_dev = NULL, *dev = NULL;
270 struct file *file = NULL;
271 struct ion_client *client = NULL;
272 struct ion_handle *handle = NULL;
273 camsys_iommu_t *iommu = NULL;
274 int ret = 0, iommu_enabled = 0;
275 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
277 of_property_read_u32(camsys_dev->pdev->dev.of_node,
278 "rockchip,isp,iommu-enable", &iommu_enabled);
279 if (iommu_enabled != 1) {
280 camsys_err("isp iommu have not been enabled!\n");
285 if (strstr(camsys_dev->miscdev.name, "camsys_marvin1")) {
287 rockchip_get_sysmmu_device_by_compatible
288 (ISP1_IOMMU_COMPATIBLE_NAME);
290 if (CHIP_TYPE == 3399) {
292 rockchip_get_sysmmu_device_by_compatible
293 (ISP0_IOMMU_COMPATIBLE_NAME);
296 rockchip_get_sysmmu_device_by_compatible
297 (ISP_IOMMU_COMPATIBLE_NAME);
302 camsys_err("get iommu device erro!\n");
306 dev = &(camsys_dev->pdev->dev);
307 iommu = (camsys_iommu_t *)(devctl->rev);
308 file = fget(iommu->client_fd);
310 camsys_err("get client_fd file erro!\n");
315 client = file->private_data;
318 camsys_err("get ion_client erro!\n");
325 handle = ion_import_dma_buf(client, iommu->map_fd);
327 camsys_trace(1, "map fd %d ,client fd %d\n",
328 iommu->map_fd, iommu->client_fd);
330 camsys_err("get ion_handle erro!\n");
335 platform_set_sysmmu(iommu_dev, dev);
336 ret = rockchip_iovmm_activate(dev);
337 ret = ion_map_iommu(dev, client, handle,
338 &(iommu->linear_addr), &(iommu->len));
340 ion_unmap_iommu(dev, client, handle);
341 platform_set_sysmmu(iommu_dev, dev);
342 rockchip_iovmm_deactivate(dev);
348 static int camsys_drm_dma_attach_device(camsys_dev_t *camsys_dev)
350 struct iommu_domain *domain = camsys_dev->domain;
351 struct device *dev = &camsys_dev->pdev->dev;
354 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
358 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
359 ret = iommu_attach_device(domain, dev);
361 dev_err(dev, "Failed to attach iommu device\n");
365 if (!common_iommu_setup_dma_ops(dev, 0x10000000, SZ_2G, domain->ops)) {
366 dev_err(dev, "Failed to set dma_ops\n");
367 iommu_detach_device(domain, dev);
374 static void camsys_drm_dma_detach_device(camsys_dev_t *camsys_dev)
376 struct iommu_domain *domain = camsys_dev->domain;
377 struct device *dev = &camsys_dev->pdev->dev;
379 iommu_detach_device(domain, dev);
382 static int camsys_mrv_drm_iommu_cb(void *ptr, camsys_sysctrl_t *devctl)
384 struct device *dev = NULL;
385 camsys_iommu_t *iommu = NULL;
386 struct dma_buf *dma_buf;
387 struct dma_buf_attachment *attach;
388 struct sg_table *sgt;
392 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
394 dev = &camsys_dev->pdev->dev;
395 iommu = (camsys_iommu_t *)(devctl->rev);
397 /*ummap mapped fd first*/
398 int cur_mapped_cnt = camsys_dev->dma_buf_cnt;
400 for (index = 0; index < cur_mapped_cnt; index++) {
401 if (camsys_dev->dma_buf[index].fd == iommu->map_fd)
404 if (index != cur_mapped_cnt) {
405 attach = camsys_dev->dma_buf[index].attach;
406 dma_buf = camsys_dev->dma_buf[index].dma_buf;
407 sgt = camsys_dev->dma_buf[index].sgt;
408 dma_buf_unmap_attachment
412 dma_buf_detach(dma_buf, attach);
413 dma_buf_put(dma_buf);
414 if (camsys_dev->dma_buf_cnt == 1)
415 camsys_drm_dma_detach_device(camsys_dev);
416 camsys_dev->dma_buf_cnt--;
417 camsys_dev->dma_buf[index].fd = -1;
420 for (index = 0; index < CAMSYS_DMA_BUF_MAX_NUM; index++)
421 if (camsys_dev->dma_buf[index].fd == -1)
424 if (index == CAMSYS_DMA_BUF_MAX_NUM)
427 if (camsys_dev->dma_buf_cnt == 0) {
428 ret = camsys_drm_dma_attach_device(camsys_dev);
433 dma_buf = dma_buf_get(iommu->map_fd);
435 return PTR_ERR(dma_buf);
436 attach = dma_buf_attach(dma_buf, dev);
437 if (IS_ERR(attach)) {
438 dma_buf_put(dma_buf);
439 return PTR_ERR(attach);
441 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
443 dma_buf_detach(dma_buf, attach);
444 dma_buf_put(dma_buf);
447 dma_addr = sg_dma_address(sgt->sgl);
448 camsys_dev->dma_buf[index].dma_addr = dma_addr;
449 camsys_dev->dma_buf[index].attach = attach;
450 camsys_dev->dma_buf[index].dma_buf = dma_buf;
451 camsys_dev->dma_buf[index].sgt = sgt;
452 camsys_dev->dma_buf[index].fd = iommu->map_fd;
453 iommu->linear_addr = dma_addr;
454 iommu->len = sg_dma_len(sgt->sgl);
455 camsys_dev->dma_buf_cnt++;
459 "%s:iommu map dma_addr 0x%lx,attach %p,"
460 "dma_buf %p,sgt %p,fd %d,buf_cnt %d",
462 (unsigned long)dma_addr,
467 camsys_dev->dma_buf_cnt);
470 (camsys_dev->dma_buf_cnt == 0) ||
472 (index >= CAMSYS_DMA_BUF_MAX_NUM))
475 for (index = 0; index < camsys_dev->dma_buf_cnt; index++) {
476 if (camsys_dev->dma_buf[index].fd == iommu->map_fd)
479 if (index == camsys_dev->dma_buf_cnt) {
480 camsys_warn("can't find map fd %d", iommu->map_fd);
483 attach = camsys_dev->dma_buf[index].attach;
484 dma_buf = camsys_dev->dma_buf[index].dma_buf;
485 sgt = camsys_dev->dma_buf[index].sgt;
489 "%s:iommu map ,attach %p,"
490 "dma_buf %p,sgt %p,index %d",
496 dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
497 dma_buf_detach(dma_buf, attach);
498 dma_buf_put(dma_buf);
499 if (camsys_dev->dma_buf_cnt == 1)
500 camsys_drm_dma_detach_device(camsys_dev);
502 camsys_dev->dma_buf_cnt--;
503 camsys_dev->dma_buf[index].fd = -1;
509 static int camsys_mrv_reset_cb(void *ptr, unsigned int on)
511 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
512 camsys_soc_priv_t *soc;
514 if (camsys_dev->soc) {
515 soc = (camsys_soc_priv_t *)camsys_dev->soc;
518 (camsys_dev, Isp_SoftRst,
519 (void *)(unsigned long)on);
521 camsys_err("camsys_dev->soc->soc_cfg is NULL!");
524 camsys_err("camsys_dev->soc is NULL!");
530 static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
532 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
533 camsys_mrv_clk_t *clk = (camsys_mrv_clk_t *)camsys_dev->clk;
534 unsigned long isp_clk;
536 if (CHIP_TYPE == 3399) {
537 if (on && !clk->in_on) {
538 /* rockchip_set_system_status(SYS_STATUS_ISP); */
544 if (strstr(camsys_dev->miscdev.name,
546 clk_set_rate(clk->clk_isp1, isp_clk);
547 clk_prepare_enable(clk->hclk_isp1_noc);
548 clk_prepare_enable(clk->hclk_isp1_wrapper);
549 clk_prepare_enable(clk->aclk_isp1_noc);
550 clk_prepare_enable(clk->aclk_isp1_wrapper);
551 clk_prepare_enable(clk->clk_isp1);
553 clk_prepare_enable(clk->cif_clk_out);
554 clk_prepare_enable(clk->pclk_dphy_ref);
555 clk_prepare_enable(clk->pclk_dphytxrx);
557 clk_prepare_enable(clk->pclkin_isp);
558 clk_prepare_enable(clk->cif_clk_out);
560 clk_set_rate(clk->clk_isp0, isp_clk);
561 clk_prepare_enable(clk->hclk_isp0_noc);
562 clk_prepare_enable(clk->hclk_isp0_wrapper);
563 clk_prepare_enable(clk->aclk_isp0_noc);
564 clk_prepare_enable(clk->aclk_isp0_wrapper);
565 clk_prepare_enable(clk->clk_isp0);
566 clk_prepare_enable(clk->cif_clk_out);
567 clk_prepare_enable(clk->pclk_dphyrx);
568 clk_prepare_enable(clk->pclk_dphy_ref);
573 camsys_trace(1, "%s clock(f: %ld Hz) in turn on",
574 dev_name(camsys_dev->miscdev.this_device), isp_clk);
575 camsys_mrv_reset_cb(ptr, 1);
577 camsys_mrv_reset_cb(ptr, 0);
578 } else if (!on && clk->in_on) {
579 if (strstr(camsys_dev->miscdev.name,
581 clk_disable_unprepare(clk->hclk_isp1_noc);
582 clk_disable_unprepare(clk->hclk_isp1_wrapper);
583 clk_disable_unprepare(clk->aclk_isp1_noc);
584 clk_disable_unprepare(clk->aclk_isp1_wrapper);
585 clk_disable_unprepare(clk->clk_isp1);
587 clk_disable_unprepare(clk->cif_clk_out);
588 clk_disable_unprepare(clk->pclk_dphytxrx);
589 clk_disable_unprepare(clk->pclk_dphy_ref);
591 clk_disable_unprepare(clk->pclkin_isp);
593 clk_disable_unprepare(clk->hclk_isp0_noc);
594 clk_disable_unprepare(clk->hclk_isp0_wrapper);
595 clk_disable_unprepare(clk->aclk_isp0_noc);
596 clk_disable_unprepare(clk->aclk_isp0_wrapper);
597 clk_disable_unprepare(clk->clk_isp0);
599 clk_disable_unprepare(clk->cif_clk_out);
600 clk_disable_unprepare(clk->pclk_dphyrx);
601 clk_disable_unprepare(clk->pclk_dphy_ref);
604 /* rockchip_clear_system_status(SYS_STATUS_ISP); */
606 camsys_trace(1, "%s clock in turn off",
607 dev_name(camsys_dev->miscdev.this_device));
610 if (on && !clk->in_on) {
611 /* rockchip_set_system_status(SYS_STATUS_ISP); */
618 clk_set_rate(clk->isp, isp_clk);
619 clk_set_rate(clk->isp_jpe, isp_clk);
621 /* clk_prepare_enable(clk->pd_isp); */
622 clk_prepare_enable(clk->aclk_isp);
623 clk_prepare_enable(clk->hclk_isp);
624 clk_prepare_enable(clk->isp);
625 clk_prepare_enable(clk->isp_jpe);
626 clk_prepare_enable(clk->pclkin_isp);
627 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
628 clk_prepare_enable(clk->cif_clk_out);
629 clk_prepare_enable(clk->pclk_dphyrx);
631 clk_prepare_enable(clk->clk_mipi_24m);
635 camsys_trace(1, "%s clock(f: %ld Hz) in turn on",
636 dev_name(camsys_dev->miscdev.this_device), isp_clk);
637 camsys_mrv_reset_cb(ptr, 1);
639 camsys_mrv_reset_cb(ptr, 0);
640 } else if (!on && clk->in_on) {
641 clk_disable_unprepare(clk->aclk_isp);
642 clk_disable_unprepare(clk->hclk_isp);
643 clk_disable_unprepare(clk->isp);
644 clk_disable_unprepare(clk->isp_jpe);
645 clk_disable_unprepare(clk->pclkin_isp);
646 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
647 clk_disable_unprepare(clk->cif_clk_out);
648 clk_disable_unprepare(clk->pclk_dphyrx);
650 clk_disable_unprepare(clk->clk_mipi_24m);
652 /* clk_disable_unprepare(clk->pd_isp); */
654 /* rockchip_clear_system_status(SYS_STATUS_ISP); */
656 camsys_trace(1, "%s clock in turn off",
657 dev_name(camsys_dev->miscdev.this_device));
664 static int camsys_mrv_clkout_cb(void *ptr, unsigned int on, unsigned int inclk)
666 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
667 camsys_mrv_clk_t *clk = (camsys_mrv_clk_t *)camsys_dev->clk;
669 mutex_lock(&clk->lock);
670 if (on && (clk->out_on != on)) {
672 pm_runtime_get_sync(&camsys_dev->pdev->dev);
674 clk_set_rate(clk->cif_clk_out, inclk);
675 clk_prepare_enable(clk->cif_clk_out);
677 camsys_trace(1, "camsys %s clock out(rate: %dHz) turn on",
678 dev_name(camsys_dev->miscdev.this_device),
680 } else if (!on && clk->out_on) {
681 if (!IS_ERR_OR_NULL(clk->cif_clk_pll)) {
682 clk_set_parent(clk->cif_clk_out,
685 camsys_warn("%s clock out may be not off!",
686 dev_name(camsys_dev->miscdev.this_device));
689 clk_disable_unprepare(clk->cif_clk_out);
691 pm_runtime_disable(&camsys_dev->pdev->dev);
694 camsys_trace(1, "%s clock out turn off",
695 dev_name(camsys_dev->miscdev.this_device));
697 mutex_unlock(&clk->lock);
701 static irqreturn_t camsys_mrv_irq(int irq, void *data)
703 camsys_dev_t *camsys_dev = (camsys_dev_t *)data;
704 camsys_irqstas_t *irqsta;
705 camsys_irqpool_t *irqpool;
706 unsigned int isp_mis, mipi_mis, mi_mis, *mis, jpg_mis, jpg_err_mis;
707 unsigned int mi_ris, mi_imis;
709 isp_mis = __raw_readl((void volatile *)
710 (camsys_dev->devmems.registermem->vir_base +
712 mipi_mis = __raw_readl((void volatile *)
713 (camsys_dev->devmems.registermem->vir_base +
715 jpg_mis = __raw_readl((void volatile *)
716 (camsys_dev->devmems.registermem->vir_base +
718 jpg_err_mis = __raw_readl((void volatile *)
719 (camsys_dev->devmems.registermem->vir_base +
721 mi_mis = __raw_readl((void volatile *)
722 (camsys_dev->devmems.registermem->vir_base +
725 mi_ris = __raw_readl((void volatile *)
726 (camsys_dev->devmems.registermem->vir_base +
728 mi_imis = __raw_readl((void volatile *)
729 (camsys_dev->devmems.registermem->vir_base +
731 while ((mi_ris & mi_imis) != mi_mis) {
732 camsys_trace(2, "mi_mis status erro,mi_mis 0x%x,"
733 "mi_ris 0x%x,imis 0x%x\n",
734 mi_mis, mi_ris, mi_imis);
735 mi_mis = __raw_readl((void volatile *)
736 (camsys_dev->devmems.registermem->vir_base +
738 mi_ris = __raw_readl((void volatile *)
739 (camsys_dev->devmems.registermem->vir_base +
741 mi_imis = __raw_readl((void volatile *)
742 (camsys_dev->devmems.registermem->vir_base +
746 __raw_writel(isp_mis, (void volatile *)
747 (camsys_dev->devmems.registermem->vir_base +
749 __raw_writel(mipi_mis, (void volatile *)
750 (camsys_dev->devmems.registermem->vir_base +
752 __raw_writel(jpg_mis, (void volatile *)
753 (camsys_dev->devmems.registermem->vir_base +
755 __raw_writel(jpg_err_mis, (void volatile *)
756 (camsys_dev->devmems.registermem->vir_base +
758 __raw_writel(mi_mis, (void volatile *)
759 (camsys_dev->devmems.registermem->vir_base +
762 spin_lock(&camsys_dev->irq.lock);
763 if (!list_empty(&camsys_dev->irq.irq_pool)) {
764 list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
765 if (irqpool->pid != 0) {
766 switch (irqpool->mis) {
790 case MRV_JPG_ERR_MIS:
799 "Thread(pid:%d) irqpool mis(%d) is invalidate",
800 irqpool->pid, irqpool->mis);
806 spin_lock(&irqpool->lock);
807 if (!list_empty(&irqpool->deactive)) {
813 irqsta->sta.mis = *mis;
814 list_del_init(&irqsta->list);
815 list_add_tail(&irqsta->list,
817 wake_up(&irqpool->done);
819 spin_unlock(&irqpool->lock);
825 spin_unlock(&camsys_dev->irq.lock);
830 static int camsys_mrv_remove_cb(struct platform_device *pdev)
832 camsys_dev_t *camsys_dev = platform_get_drvdata(pdev);
833 camsys_mrv_clk_t *mrv_clk = NULL;
835 if (camsys_dev->clk != NULL) {
837 mrv_clk = (camsys_mrv_clk_t *)camsys_dev->clk;
839 camsys_mrv_clkout_cb(mrv_clk, 0, 0);
841 camsys_mrv_clkin_cb(mrv_clk, 0);
843 if (!IS_ERR_OR_NULL(mrv_clk->pd_isp)) {
844 devm_clk_put(&pdev->dev, mrv_clk->pd_isp);
846 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp)) {
847 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp);
849 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp)) {
850 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp);
852 if (!IS_ERR_OR_NULL(mrv_clk->isp)) {
853 devm_clk_put(&pdev->dev, mrv_clk->isp);
855 if (!IS_ERR_OR_NULL(mrv_clk->isp_jpe)) {
856 devm_clk_put(&pdev->dev, mrv_clk->isp_jpe);
858 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp)) {
859 devm_clk_put(&pdev->dev, mrv_clk->pclkin_isp);
861 if (!IS_ERR_OR_NULL(mrv_clk->cif_clk_out)) {
862 devm_clk_put(&pdev->dev, mrv_clk->cif_clk_out);
864 if (!IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc)) {
865 devm_clk_put(&pdev->dev, mrv_clk->clk_vio0_noc);
868 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp0_noc)) {
869 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp0_noc);
871 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp0_wrapper)) {
872 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp0_wrapper);
874 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp1_noc)) {
875 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp1_noc);
877 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp1_wrapper)) {
878 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp1_wrapper);
880 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp0_noc)) {
881 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp0_noc);
884 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp0_wrapper)) {
885 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp0_wrapper);
887 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp1_noc)) {
888 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp1_noc);
890 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp1_wrapper)) {
891 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp1_wrapper);
893 if (!IS_ERR_OR_NULL(mrv_clk->clk_isp0)) {
894 devm_clk_put(&pdev->dev, mrv_clk->clk_isp0);
896 if (!IS_ERR_OR_NULL(mrv_clk->clk_isp1)) {
897 devm_clk_put(&pdev->dev, mrv_clk->clk_isp1);
899 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp1)) {
900 devm_clk_put(&pdev->dev, mrv_clk->pclkin_isp1);
902 if (CHIP_TYPE == 3399)
903 pm_runtime_disable(&pdev->dev);
908 camsys_drm_dma_detach_device(camsys_dev);
909 iommu_group_remove_device(&camsys_dev->pdev->dev);
910 iommu_put_dma_cookie(camsys_dev->domain);
911 iommu_domain_free(camsys_dev->domain);
915 int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev)
918 camsys_mrv_clk_t *mrv_clk = NULL;
919 struct resource register_res;
920 struct iommu_domain *domain;
921 struct iommu_group *group;
922 struct device_node *np;
924 err = of_address_to_resource(pdev->dev.of_node, 0, ®ister_res);
927 "Get register resource from %s platform device failed!",
931 err = request_irq(camsys_dev->irq.irq_id, camsys_mrv_irq,
932 IRQF_SHARED, CAMSYS_MARVIN_IRQNAME,
935 camsys_err("request irq for %s failed", CAMSYS_MARVIN_IRQNAME);
939 /* Clk and Iomux init */
940 mrv_clk = kzalloc(sizeof(camsys_mrv_clk_t), GFP_KERNEL);
941 if (mrv_clk == NULL) {
942 camsys_err("Allocate camsys_mrv_clk_t failed!");
946 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
947 /* mrv_clk->pd_isp = devm_clk_get(&pdev->dev, "pd_isp"); */
948 mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
949 mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
950 mrv_clk->isp = devm_clk_get(&pdev->dev, "clk_isp");
951 mrv_clk->isp_jpe = devm_clk_get(&pdev->dev, "clk_isp_jpe");
952 mrv_clk->pclkin_isp = devm_clk_get(&pdev->dev, "pclkin_isp");
953 mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
954 mrv_clk->cif_clk_pll = devm_clk_get(&pdev->dev, "clk_cif_pll");
955 mrv_clk->pclk_dphyrx = devm_clk_get(&pdev->dev, "pclk_dphyrx");
956 if (CHIP_TYPE == 3368) {
957 mrv_clk->clk_vio0_noc =
958 devm_clk_get(&pdev->dev, "clk_vio0_noc");
959 if (IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc)) {
960 camsys_err("Get %s clock resouce failed!\n",
968 if (IS_ERR_OR_NULL(mrv_clk->aclk_isp) ||
969 IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
970 IS_ERR_OR_NULL(mrv_clk->isp) ||
971 IS_ERR_OR_NULL(mrv_clk->isp_jpe) ||
972 IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
973 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
974 IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
975 camsys_err("Get %s clock resouce failed!\n",
981 clk_set_rate(mrv_clk->isp, 210000000);
982 clk_set_rate(mrv_clk->isp_jpe, 210000000);
984 } else if (CHIP_TYPE == 3399) {
986 pm_runtime_enable(&pdev->dev);
987 if (register_res.start == 0xff920000) {
988 mrv_clk->hclk_isp1_noc =
989 devm_clk_get(&pdev->dev, "hclk_isp1_noc");
990 mrv_clk->hclk_isp1_wrapper =
991 devm_clk_get(&pdev->dev, "hclk_isp1_wrapper");
992 mrv_clk->aclk_isp1_noc =
993 devm_clk_get(&pdev->dev, "aclk_isp1_noc");
994 mrv_clk->aclk_isp1_wrapper =
995 devm_clk_get(&pdev->dev, "aclk_isp1_wrapper");
997 devm_clk_get(&pdev->dev, "clk_isp1");
998 mrv_clk->pclkin_isp =
999 devm_clk_get(&pdev->dev, "pclk_isp1");
1000 mrv_clk->pclk_dphytxrx =
1001 devm_clk_get(&pdev->dev, "pclk_dphytxrx");
1003 mrv_clk->hclk_isp0_noc =
1004 devm_clk_get(&pdev->dev, "hclk_isp0_noc");
1005 mrv_clk->hclk_isp0_wrapper =
1006 devm_clk_get(&pdev->dev, "hclk_isp0_wrapper");
1007 mrv_clk->aclk_isp0_noc =
1008 devm_clk_get(&pdev->dev, "aclk_isp0_noc");
1009 mrv_clk->aclk_isp0_wrapper =
1010 devm_clk_get(&pdev->dev, "aclk_isp0_wrapper");
1012 devm_clk_get(&pdev->dev, "clk_isp0");
1013 mrv_clk->pclk_dphyrx =
1014 devm_clk_get(&pdev->dev, "pclk_dphyrx");
1016 mrv_clk->cif_clk_out =
1017 devm_clk_get(&pdev->dev, "clk_cif_out");
1018 mrv_clk->cif_clk_pll =
1019 devm_clk_get(&pdev->dev, "clk_cif_pll");
1020 mrv_clk->pclk_dphy_ref =
1021 devm_clk_get(&pdev->dev, "pclk_dphy_ref");
1022 if (register_res.start == 0xff920000) {
1023 if (IS_ERR_OR_NULL(mrv_clk->hclk_isp1_noc) ||
1024 IS_ERR_OR_NULL(mrv_clk->hclk_isp1_wrapper) ||
1025 IS_ERR_OR_NULL(mrv_clk->aclk_isp1_noc) ||
1026 IS_ERR_OR_NULL(mrv_clk->aclk_isp1_wrapper) ||
1027 IS_ERR_OR_NULL(mrv_clk->clk_isp1) ||
1028 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
1029 IS_ERR_OR_NULL(mrv_clk->cif_clk_pll) ||
1030 IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
1031 IS_ERR_OR_NULL(mrv_clk->pclk_dphytxrx)) {
1032 camsys_err("Get %s clock resouce failed!\n",
1038 if (IS_ERR_OR_NULL(mrv_clk->hclk_isp0_noc) ||
1039 IS_ERR_OR_NULL(mrv_clk->hclk_isp0_wrapper) ||
1040 IS_ERR_OR_NULL(mrv_clk->aclk_isp0_noc) ||
1041 IS_ERR_OR_NULL(mrv_clk->aclk_isp0_wrapper) ||
1042 IS_ERR_OR_NULL(mrv_clk->clk_isp0) ||
1043 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
1044 IS_ERR_OR_NULL(mrv_clk->cif_clk_pll) ||
1045 IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
1046 camsys_err("Get %s clock resouce failed!\n",
1054 devm_clk_get(&pdev->dev, "pd_isp");
1056 devm_clk_get(&pdev->dev, "aclk_isp");
1058 devm_clk_get(&pdev->dev, "hclk_isp");
1060 devm_clk_get(&pdev->dev, "clk_isp");
1062 devm_clk_get(&pdev->dev, "clk_isp_jpe");
1063 mrv_clk->pclkin_isp =
1064 devm_clk_get(&pdev->dev, "pclkin_isp");
1065 mrv_clk->cif_clk_out =
1066 devm_clk_get(&pdev->dev, "clk_cif_out");
1067 mrv_clk->cif_clk_pll =
1068 devm_clk_get(&pdev->dev, "clk_cif_pll");
1069 mrv_clk->clk_mipi_24m =
1070 devm_clk_get(&pdev->dev, "clk_mipi_24m");
1072 if (IS_ERR_OR_NULL(mrv_clk->pd_isp) ||
1073 IS_ERR_OR_NULL(mrv_clk->aclk_isp) ||
1074 IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
1075 IS_ERR_OR_NULL(mrv_clk->isp) ||
1076 IS_ERR_OR_NULL(mrv_clk->isp_jpe) ||
1077 IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
1078 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
1079 IS_ERR_OR_NULL(mrv_clk->clk_mipi_24m)) {
1080 camsys_err("Get %s clock resouce failed!\n",
1086 clk_set_rate(mrv_clk->isp, 210000000);
1087 clk_set_rate(mrv_clk->isp_jpe, 210000000);
1091 mutex_init(&mrv_clk->lock);
1093 mrv_clk->in_on = false;
1094 mrv_clk->out_on = 0;
1096 np = of_find_node_by_name(NULL, "isp0_mmu");
1100 domain = iommu_domain_alloc(&platform_bus_type);
1104 err = iommu_get_dma_cookie(domain);
1106 goto err_free_domain;
1108 group = iommu_group_get(&pdev->dev);
1110 group = iommu_group_alloc();
1111 if (IS_ERR(group)) {
1112 dev_err(&pdev->dev, "Failed to allocate IOMMU group\n");
1113 goto err_put_cookie;
1116 err = iommu_group_add_device(group, &pdev->dev);
1117 iommu_group_put(group);
1119 dev_err(&pdev->dev, "failed to add device to IOMMU group\n");
1120 goto err_put_cookie;
1123 camsys_dev->domain = domain;
1124 camsys_dev->dma_buf_cnt = 0;
1125 camsys_dev->iommu_cb = camsys_mrv_drm_iommu_cb;
1126 for (index = 0; index < CAMSYS_DMA_BUF_MAX_NUM; index++)
1127 camsys_dev->dma_buf[index].fd = -1;
1129 camsys_dev->iommu_cb = camsys_mrv_iommu_cb;
1132 camsys_dev->clk = (void *)mrv_clk;
1133 camsys_dev->clkin_cb = camsys_mrv_clkin_cb;
1134 camsys_dev->clkout_cb = camsys_mrv_clkout_cb;
1135 camsys_dev->reset_cb = camsys_mrv_reset_cb;
1136 camsys_dev->iomux = camsys_mrv_iomux_cb;
1137 camsys_dev->flash_trigger_cb = camsys_mrv_flash_trigger_cb;
1139 camsys_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
1140 camsys_dev->miscdev.name = miscdev_name;
1141 camsys_dev->miscdev.nodename = miscdev_name;
1142 camsys_dev->miscdev.fops = &camsys_fops;
1144 if (CHIP_TYPE == 3399) {
1145 if (register_res.start == 0xff920000) {
1146 camsys_dev->miscdev.name = "camsys_marvin1";
1147 camsys_dev->miscdev.nodename = "camsys_marvin1";
1151 err = misc_register(&camsys_dev->miscdev);
1153 camsys_err("misc register %s failed!", miscdev_name);
1154 goto misc_register_failed;
1157 camsys_dev->dev_id = CAMSYS_DEVID_MARVIN;
1158 camsys_dev->platform_remove = camsys_mrv_remove_cb;
1161 misc_register_failed:
1162 if (!IS_ERR_OR_NULL(camsys_dev->miscdev.this_device))
1163 misc_deregister(&camsys_dev->miscdev);
1165 iommu_put_dma_cookie(domain);
1167 iommu_domain_free(domain);
1169 if (mrv_clk != NULL) {
1170 if (!IS_ERR_OR_NULL(mrv_clk->pd_isp))
1171 clk_put(mrv_clk->pd_isp);
1173 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp))
1174 clk_put(mrv_clk->aclk_isp);
1176 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp))
1177 clk_put(mrv_clk->hclk_isp);
1179 if (!IS_ERR_OR_NULL(mrv_clk->isp))
1180 clk_put(mrv_clk->isp);
1182 if (!IS_ERR_OR_NULL(mrv_clk->isp_jpe))
1183 clk_put(mrv_clk->isp_jpe);
1185 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp))
1186 clk_put(mrv_clk->pclkin_isp);
1188 if (!IS_ERR_OR_NULL(mrv_clk->cif_clk_out))
1189 clk_put(mrv_clk->cif_clk_out);
1191 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
1192 if (!IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx))
1193 clk_put(mrv_clk->pclk_dphyrx);
1195 if (!IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc))
1196 clk_put(mrv_clk->clk_vio0_noc);
1206 EXPORT_SYMBOL_GPL(camsys_mrv_probe_cb);