1 #include "camsys_marvin.h"
2 #include "camsys_soc_priv.h"
3 #include "camsys_gpio.h"
5 #include <linux/rockchip/common.h>
6 #include <dt-bindings/clock/rk_system_status.h>
7 #include <linux/rockchip_ion.h>
8 #include <linux/file.h>
9 #include <linux/pm_runtime.h>
11 extern int rockchip_set_system_status(unsigned long status);
12 extern int rockchip_clear_system_status(unsigned long status);
14 static const char miscdev_name[] = CAMSYS_MARVIN_DEVNAME;
16 static int camsys_mrv_iomux_cb(camsys_extdev_t *extdev, void *ptr)
18 struct pinctrl *pinctrl;
19 struct pinctrl_state *state;
21 char state_str[20] = {0};
22 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
23 struct device *dev = &(extdev->pdev->dev);
24 camsys_soc_priv_t *soc;
28 if (extdev->phy.type == CamSys_Phy_Cif) {
29 switch (extdev->phy.info.cif.fmt) {
30 case CamSys_Fmt_Raw_8b:
31 case CamSys_Fmt_Yuv420_8b:
32 case CamSys_Fmt_Yuv422_8b:{
33 if (extdev->phy.info.cif.cifio ==
34 CamSys_SensorBit0_CifBit0) {
35 strcpy(state_str, "isp_dvp8bit0");
36 } else if (extdev->phy.info.cif.cifio ==
37 CamSys_SensorBit0_CifBit2) {
38 strcpy(state_str, "isp_dvp8bit2");
39 } else if (extdev->phy.info.cif.cifio ==
40 CamSys_SensorBit0_CifBit4) {
41 strcpy(state_str, "isp_dvp8bit4");
43 camsys_err("extdev->phy.info.cif.cifio:0x%x is invalidate!",
44 extdev->phy.info.cif.cifio);
51 case CamSys_Fmt_Raw_10b:{
52 strcpy(state_str, "isp_dvp10bit");
56 case CamSys_Fmt_Raw_12b:{
57 strcpy(state_str, "isp_dvp12bit");
62 camsys_err("extdev->phy.info.cif.fmt: 0x%x is invalidate!",
63 extdev->phy.info.cif.fmt);
68 if (extdev->dev_cfg & CAMSYS_DEVCFG_FLASHLIGHT) {
69 if (extdev->dev_cfg & CAMSYS_DEVCFG_PREFLASHLIGHT) {
70 strcpy(state_str, "isp_mipi_fl_prefl");
72 strcpy(state_str, "isp_mipi_fl");
75 /*mux triggerout as gpio*/
78 enum of_gpio_flags flags;
81 of_get_named_gpio_flags(
82 camsys_dev->pdev->dev.of_node,
83 "rockchip,gpios", 0, &flags);
84 if (gpio_is_valid(flash_trigger_io)) {
86 of_get_named_gpio_flags(
87 camsys_dev->pdev->dev.of_node,
88 "rockchip,gpios", 0, &flags);
89 gpio_request(flash_trigger_io,
91 gpio_direction_output(
93 (~(extdev->fl.fl.active) &
98 if (CHIP_TYPE == 3399) {
99 strcpy(state_str, "cif_clkout");
101 strcpy(state_str, "default");
106 camsys_trace(1, "marvin pinctrl select: %s", state_str);
108 pinctrl = devm_pinctrl_get(dev);
109 if (IS_ERR(pinctrl)) {
110 camsys_err("devm_pinctrl_get failed!");
113 state = pinctrl_lookup_state(pinctrl,
116 camsys_err("pinctrl_lookup_state failed!");
120 if (!IS_ERR(state)) {
121 retval = pinctrl_select_state(pinctrl, state);
123 camsys_err("pinctrl_select_state failed!");
128 if (camsys_dev->soc) {
129 soc = (camsys_soc_priv_t *)camsys_dev->soc;
131 (soc->soc_cfg)(camsys_dev, Cif_IoDomain_Cfg,
132 (void *)&extdev->dovdd.min_uv);
133 (soc->soc_cfg)(camsys_dev, Clk_DriverStrength_Cfg,
134 (void *)&extdev->clk.driver_strength);
136 camsys_err("camsys_dev->soc->soc_cfg is NULL!");
139 camsys_err("camsys_dev->soc is NULL!");
147 static int camsys_mrv_flash_trigger_cb(void *ptr, int mode, unsigned int on)
149 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
150 struct device *dev = &(camsys_dev->pdev->dev);
151 int flash_trigger_io;
152 struct pinctrl *pinctrl;
153 struct pinctrl_state *state;
154 char state_str[20] = {0};
156 enum of_gpio_flags flags;
157 camsys_extdev_t *extdev = NULL;
160 strcpy(state_str, "isp_flash_as_gpio");
161 pinctrl = devm_pinctrl_get(dev);
162 if (IS_ERR(pinctrl)) {
163 camsys_err("devm_pinctrl_get failed!");
165 state = pinctrl_lookup_state(pinctrl, state_str);
167 camsys_err("pinctrl_lookup_state failed!");
170 if (!IS_ERR(state)) {
171 retval = pinctrl_select_state(pinctrl, state);
173 camsys_err("pinctrl_select_state failed!");
178 flash_trigger_io = of_get_named_gpio_flags(
179 camsys_dev->pdev->dev.of_node,
180 "rockchip,gpios", 0, &flags);
181 if (gpio_is_valid(flash_trigger_io)) {
182 flash_trigger_io = of_get_named_gpio_flags(
183 camsys_dev->pdev->dev.of_node,
184 "rockchip,gpios", 0, &flags);
185 gpio_request(flash_trigger_io, "camsys_gpio");
186 /*get flash io active pol*/
187 if (!list_empty(&camsys_dev->extdevs.list)) {
189 extdev, &camsys_dev->extdevs.list,
191 if (extdev->dev_cfg &
192 CAMSYS_DEVCFG_FLASHLIGHT) {
193 gpio_direction_output(
195 (~(extdev->fl.fl.active)
202 strcpy(state_str, "isp_flash_as_trigger_out");
203 pinctrl = devm_pinctrl_get(dev);
204 if (IS_ERR(pinctrl)) {
205 camsys_err("devm_pinctrl_get failed!");
207 state = pinctrl_lookup_state(pinctrl,
210 camsys_err("pinctrl_lookup_state failed!");
213 if (!IS_ERR(state)) {
214 retval = pinctrl_select_state(pinctrl, state);
216 camsys_err("pinctrl_select_state failed!");
223 static struct device *rockchip_get_sysmmu_device_by_compatible(
226 struct device_node *dn = NULL;
227 struct platform_device *pd = NULL;
228 struct device *ret = NULL;
230 dn = of_find_compatible_node(NULL, NULL, compt);
232 camsys_err("can't find device node %s \r\n", compt);
236 pd = of_find_device_by_node(dn);
239 "can't find platform device in device node %s \r\n",
248 #ifdef CONFIG_IOMMU_API
249 static inline void platform_set_sysmmu(
250 struct device *iommu, struct device *dev)
252 dev->archdata.iommu = iommu;
255 static inline void platform_set_sysmmu(
256 struct device *iommu, struct device *dev)
262 static int camsys_mrv_iommu_cb(void *ptr, camsys_sysctrl_t *devctl)
264 struct device *iommu_dev = NULL, *dev = NULL;
265 struct file *file = NULL;
266 struct ion_client *client = NULL;
267 struct ion_handle *handle = NULL;
268 camsys_iommu_t *iommu = NULL;
269 int ret = 0, iommu_enabled = 0;
270 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
272 of_property_read_u32(camsys_dev->pdev->dev.of_node,
273 "rockchip,isp,iommu_enable", &iommu_enabled);
274 if (iommu_enabled != 1) {
275 camsys_err("isp iommu have not been enabled!\n");
280 if (strstr(camsys_dev->miscdev.name, "camsys_marvin1")) {
282 rockchip_get_sysmmu_device_by_compatible
283 (ISP1_IOMMU_COMPATIBLE_NAME);
285 if (CHIP_TYPE == 3399) {
287 rockchip_get_sysmmu_device_by_compatible
288 (ISP0_IOMMU_COMPATIBLE_NAME);
291 rockchip_get_sysmmu_device_by_compatible
292 (ISP_IOMMU_COMPATIBLE_NAME);
297 camsys_err("get iommu device erro!\n");
301 dev = &(camsys_dev->pdev->dev);
302 iommu = (camsys_iommu_t *)(devctl->rev);
303 file = fget(iommu->client_fd);
305 camsys_err("get client_fd file erro!\n");
310 client = file->private_data;
313 camsys_err("get ion_client erro!\n");
320 handle = ion_import_dma_buf(client, iommu->map_fd);
322 camsys_trace(1, "map fd %d ,client fd %d\n",
323 iommu->map_fd, iommu->client_fd);
325 camsys_err("get ion_handle erro!\n");
330 platform_set_sysmmu(iommu_dev, dev);
331 ret = rockchip_iovmm_activate(dev);
332 ret = ion_map_iommu(dev, client, handle,
333 &(iommu->linear_addr), &(iommu->len));
335 ion_unmap_iommu(dev, client, handle);
336 platform_set_sysmmu(iommu_dev, dev);
337 rockchip_iovmm_deactivate(dev);
342 static int camsys_mrv_reset_cb(void *ptr, unsigned int on)
344 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
345 camsys_soc_priv_t *soc;
347 if (camsys_dev->soc) {
348 soc = (camsys_soc_priv_t *)camsys_dev->soc;
351 (camsys_dev, Isp_SoftRst,
352 (void *)(unsigned long)on);
354 camsys_err("camsys_dev->soc->soc_cfg is NULL!");
357 camsys_err("camsys_dev->soc is NULL!");
363 static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
365 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
366 camsys_mrv_clk_t *clk = (camsys_mrv_clk_t *)camsys_dev->clk;
367 unsigned long isp_clk;
369 if (CHIP_TYPE == 3399) {
370 if (on && !clk->in_on) {
371 /* rockchip_set_system_status(SYS_STATUS_ISP); */
377 if (strstr(camsys_dev->miscdev.name,
379 clk_set_rate(clk->clk_isp1, isp_clk);
380 clk_prepare_enable(clk->hclk_isp1_noc);
381 clk_prepare_enable(clk->hclk_isp1_wrapper);
382 clk_prepare_enable(clk->aclk_isp1_noc);
383 clk_prepare_enable(clk->aclk_isp1_wrapper);
384 clk_prepare_enable(clk->clk_isp1);
386 clk_prepare_enable(clk->cif_clk_out);
387 clk_prepare_enable(clk->pclk_dphy_ref);
388 clk_prepare_enable(clk->pclk_dphytxrx);
390 clk_prepare_enable(clk->pclkin_isp);
392 clk_set_rate(clk->clk_isp0, isp_clk);
393 clk_prepare_enable(clk->hclk_isp0_noc);
394 clk_prepare_enable(clk->hclk_isp0_wrapper);
395 clk_prepare_enable(clk->aclk_isp0_noc);
396 clk_prepare_enable(clk->aclk_isp0_wrapper);
397 clk_prepare_enable(clk->clk_isp0);
398 clk_prepare_enable(clk->cif_clk_out);
399 clk_prepare_enable(clk->pclk_dphyrx);
400 clk_prepare_enable(clk->pclk_dphy_ref);
403 clk_set_rate(clk->clk_isp0, isp_clk);
404 clk_set_rate(clk->clk_isp1, isp_clk);
408 camsys_trace(1, "%s clock(f: %ld Hz) in turn on",
409 dev_name(camsys_dev->miscdev.this_device), isp_clk);
410 camsys_mrv_reset_cb(ptr, 1);
412 camsys_mrv_reset_cb(ptr, 0);
413 } else if (!on && clk->in_on) {
414 if (strstr(camsys_dev->miscdev.name,
416 clk_disable_unprepare(clk->hclk_isp1_noc);
417 clk_disable_unprepare(clk->hclk_isp1_wrapper);
418 clk_disable_unprepare(clk->aclk_isp1_noc);
419 clk_disable_unprepare(clk->aclk_isp1_wrapper);
420 clk_disable_unprepare(clk->clk_isp1);
422 clk_disable_unprepare(clk->cif_clk_out);
423 clk_disable_unprepare(clk->pclk_dphytxrx);
424 clk_disable_unprepare(clk->pclk_dphy_ref);
426 clk_disable_unprepare(clk->pclkin_isp);
429 clk_disable_unprepare(clk->hclk_isp0_noc);
430 clk_disable_unprepare(clk->hclk_isp0_wrapper);
431 clk_disable_unprepare(clk->aclk_isp0_noc);
432 clk_disable_unprepare(clk->aclk_isp0_wrapper);
433 clk_disable_unprepare(clk->clk_isp0);
435 clk_disable_unprepare(clk->cif_clk_out);
436 clk_disable_unprepare(clk->pclk_dphyrx);
437 clk_disable_unprepare(clk->pclk_dphy_ref);
440 /* rockchip_clear_system_status(SYS_STATUS_ISP); */
442 camsys_trace(1, "%s clock in turn off",
443 dev_name(camsys_dev->miscdev.this_device));
446 if (on && !clk->in_on) {
447 /* rockchip_set_system_status(SYS_STATUS_ISP); */
454 clk_set_rate(clk->isp, isp_clk);
455 clk_set_rate(clk->isp_jpe, isp_clk);
457 /* clk_prepare_enable(clk->pd_isp); */
458 clk_prepare_enable(clk->aclk_isp);
459 clk_prepare_enable(clk->hclk_isp);
460 clk_prepare_enable(clk->isp);
461 clk_prepare_enable(clk->isp_jpe);
462 clk_prepare_enable(clk->pclkin_isp);
463 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
464 clk_prepare_enable(clk->cif_clk_out);
465 clk_prepare_enable(clk->pclk_dphyrx);
466 if (CHIP_TYPE == 3368)
467 clk_prepare_enable(clk->clk_vio0_noc);
469 clk_prepare_enable(clk->clk_mipi_24m);
473 camsys_trace(1, "%s clock(f: %ld Hz) in turn on",
474 dev_name(camsys_dev->miscdev.this_device), isp_clk);
475 camsys_mrv_reset_cb(ptr, 1);
477 camsys_mrv_reset_cb(ptr, 0);
478 } else if (!on && clk->in_on) {
479 clk_disable_unprepare(clk->aclk_isp);
480 clk_disable_unprepare(clk->hclk_isp);
481 clk_disable_unprepare(clk->isp);
482 clk_disable_unprepare(clk->isp_jpe);
483 clk_disable_unprepare(clk->pclkin_isp);
484 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
485 clk_disable_unprepare(clk->cif_clk_out);
486 clk_disable_unprepare(clk->pclk_dphyrx);
487 if (CHIP_TYPE == 3368)
488 clk_disable_unprepare(clk->clk_vio0_noc);
490 clk_disable_unprepare(clk->clk_mipi_24m);
492 /* clk_disable_unprepare(clk->pd_isp); */
494 /* rockchip_clear_system_status(SYS_STATUS_ISP); */
496 camsys_trace(1, "%s clock in turn off",
497 dev_name(camsys_dev->miscdev.this_device));
504 static int camsys_mrv_clkout_cb(void *ptr, unsigned int on, unsigned int inclk)
506 camsys_dev_t *camsys_dev = (camsys_dev_t *)ptr;
507 camsys_mrv_clk_t *clk = (camsys_mrv_clk_t *)camsys_dev->clk;
509 mutex_lock(&clk->lock);
510 if (on && (clk->out_on != on)) {
512 pm_runtime_get_sync(&camsys_dev->pdev->dev);
514 clk_set_rate(clk->cif_clk_out, inclk);
515 clk_prepare_enable(clk->cif_clk_out);
517 camsys_trace(1, "camsys %s clock out(rate: %dHz) turn on",
518 dev_name(camsys_dev->miscdev.this_device),
520 } else if (!on && clk->out_on) {
521 if (!IS_ERR_OR_NULL(clk->cif_clk_pll)) {
522 clk_set_parent(clk->cif_clk_out,
525 camsys_warn("%s clock out may be not off!",
526 dev_name(camsys_dev->miscdev.this_device));
529 clk_disable_unprepare(clk->cif_clk_out);
531 pm_runtime_disable(&camsys_dev->pdev->dev);
534 camsys_trace(1, "%s clock out turn off",
535 dev_name(camsys_dev->miscdev.this_device));
537 mutex_unlock(&clk->lock);
541 static irqreturn_t camsys_mrv_irq(int irq, void *data)
543 camsys_dev_t *camsys_dev = (camsys_dev_t *)data;
544 camsys_irqstas_t *irqsta;
545 camsys_irqpool_t *irqpool;
546 unsigned int isp_mis, mipi_mis, mi_mis, *mis, jpg_mis, jpg_err_mis;
547 unsigned int mi_ris, mi_imis;
549 isp_mis = __raw_readl((void volatile *)
550 (camsys_dev->devmems.registermem->vir_base +
552 mipi_mis = __raw_readl((void volatile *)
553 (camsys_dev->devmems.registermem->vir_base +
555 jpg_mis = __raw_readl((void volatile *)
556 (camsys_dev->devmems.registermem->vir_base +
558 jpg_err_mis = __raw_readl((void volatile *)
559 (camsys_dev->devmems.registermem->vir_base +
561 mi_mis = __raw_readl((void volatile *)
562 (camsys_dev->devmems.registermem->vir_base +
565 mi_ris = __raw_readl((void volatile *)
566 (camsys_dev->devmems.registermem->vir_base +
568 mi_imis = __raw_readl((void volatile *)
569 (camsys_dev->devmems.registermem->vir_base +
571 while ((mi_ris & mi_imis) != mi_mis) {
572 camsys_trace(2, "mi_mis status erro,mi_mis 0x%x,"
573 "mi_ris 0x%x,imis 0x%x\n",
574 mi_mis, mi_ris, mi_imis);
575 mi_mis = __raw_readl((void volatile *)
576 (camsys_dev->devmems.registermem->vir_base +
578 mi_ris = __raw_readl((void volatile *)
579 (camsys_dev->devmems.registermem->vir_base +
581 mi_imis = __raw_readl((void volatile *)
582 (camsys_dev->devmems.registermem->vir_base +
586 __raw_writel(isp_mis, (void volatile *)
587 (camsys_dev->devmems.registermem->vir_base +
589 __raw_writel(mipi_mis, (void volatile *)
590 (camsys_dev->devmems.registermem->vir_base +
592 __raw_writel(jpg_mis, (void volatile *)
593 (camsys_dev->devmems.registermem->vir_base +
595 __raw_writel(jpg_err_mis, (void volatile *)
596 (camsys_dev->devmems.registermem->vir_base +
598 __raw_writel(mi_mis, (void volatile *)
599 (camsys_dev->devmems.registermem->vir_base +
602 spin_lock(&camsys_dev->irq.lock);
603 if (!list_empty(&camsys_dev->irq.irq_pool)) {
604 list_for_each_entry(irqpool, &camsys_dev->irq.irq_pool, list) {
605 if (irqpool->pid != 0) {
606 switch (irqpool->mis) {
630 case MRV_JPG_ERR_MIS:
639 "Thread(pid:%d) irqpool mis(%d) is invalidate",
640 irqpool->pid, irqpool->mis);
646 spin_lock(&irqpool->lock);
647 if (!list_empty(&irqpool->deactive)) {
653 irqsta->sta.mis = *mis;
654 list_del_init(&irqsta->list);
655 list_add_tail(&irqsta->list,
657 wake_up(&irqpool->done);
659 spin_unlock(&irqpool->lock);
665 spin_unlock(&camsys_dev->irq.lock);
670 static int camsys_mrv_remove_cb(struct platform_device *pdev)
672 camsys_dev_t *camsys_dev = platform_get_drvdata(pdev);
673 camsys_mrv_clk_t *mrv_clk = NULL;
675 if (camsys_dev->clk != NULL) {
677 mrv_clk = (camsys_mrv_clk_t *)camsys_dev->clk;
679 camsys_mrv_clkout_cb(mrv_clk, 0, 0);
681 camsys_mrv_clkin_cb(mrv_clk, 0);
683 if (!IS_ERR_OR_NULL(mrv_clk->pd_isp)) {
684 devm_clk_put(&pdev->dev, mrv_clk->pd_isp);
686 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp)) {
687 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp);
689 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp)) {
690 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp);
692 if (!IS_ERR_OR_NULL(mrv_clk->isp)) {
693 devm_clk_put(&pdev->dev, mrv_clk->isp);
695 if (!IS_ERR_OR_NULL(mrv_clk->isp_jpe)) {
696 devm_clk_put(&pdev->dev, mrv_clk->isp_jpe);
698 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp)) {
699 devm_clk_put(&pdev->dev, mrv_clk->pclkin_isp);
701 if (!IS_ERR_OR_NULL(mrv_clk->cif_clk_out)) {
702 devm_clk_put(&pdev->dev, mrv_clk->cif_clk_out);
704 if (!IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc)) {
705 devm_clk_put(&pdev->dev, mrv_clk->clk_vio0_noc);
708 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp0_noc)) {
709 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp0_noc);
711 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp0_wrapper)) {
712 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp0_wrapper);
714 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp1_noc)) {
715 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp1_noc);
717 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp1_wrapper)) {
718 devm_clk_put(&pdev->dev, mrv_clk->hclk_isp1_wrapper);
720 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp0_noc)) {
721 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp0_noc);
724 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp0_wrapper)) {
725 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp0_wrapper);
727 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp1_noc)) {
728 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp1_noc);
730 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp1_wrapper)) {
731 devm_clk_put(&pdev->dev, mrv_clk->aclk_isp1_wrapper);
733 if (!IS_ERR_OR_NULL(mrv_clk->clk_isp0)) {
734 devm_clk_put(&pdev->dev, mrv_clk->clk_isp0);
736 if (!IS_ERR_OR_NULL(mrv_clk->clk_isp1)) {
737 devm_clk_put(&pdev->dev, mrv_clk->clk_isp1);
739 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp1)) {
740 devm_clk_put(&pdev->dev, mrv_clk->pclkin_isp1);
742 if (CHIP_TYPE == 3399)
743 pm_runtime_disable(&pdev->dev);
750 int camsys_mrv_probe_cb(struct platform_device *pdev, camsys_dev_t *camsys_dev)
753 camsys_mrv_clk_t *mrv_clk = NULL;
754 const char *compatible = NULL;
756 err = request_irq(camsys_dev->irq.irq_id, camsys_mrv_irq,
757 IRQF_SHARED, CAMSYS_MARVIN_IRQNAME,
760 camsys_err("request irq for %s failed", CAMSYS_MARVIN_IRQNAME);
764 /* Clk and Iomux init */
765 mrv_clk = kzalloc(sizeof(camsys_mrv_clk_t), GFP_KERNEL);
766 if (mrv_clk == NULL) {
767 camsys_err("Allocate camsys_mrv_clk_t failed!");
771 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
772 /* mrv_clk->pd_isp = devm_clk_get(&pdev->dev, "pd_isp"); */
773 mrv_clk->aclk_isp = devm_clk_get(&pdev->dev, "aclk_isp");
774 mrv_clk->hclk_isp = devm_clk_get(&pdev->dev, "hclk_isp");
775 mrv_clk->isp = devm_clk_get(&pdev->dev, "clk_isp");
776 mrv_clk->isp_jpe = devm_clk_get(&pdev->dev, "clk_isp_jpe");
777 mrv_clk->pclkin_isp = devm_clk_get(&pdev->dev, "pclkin_isp");
778 mrv_clk->cif_clk_out = devm_clk_get(&pdev->dev, "clk_cif_out");
779 mrv_clk->cif_clk_pll = devm_clk_get(&pdev->dev, "clk_cif_pll");
780 mrv_clk->pclk_dphyrx = devm_clk_get(&pdev->dev, "pclk_dphyrx");
781 if (CHIP_TYPE == 3368) {
782 mrv_clk->clk_vio0_noc =
783 devm_clk_get(&pdev->dev, "clk_vio0_noc");
784 if (IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc)) {
785 camsys_err("Get %s clock resouce failed!\n",
793 if (IS_ERR_OR_NULL(mrv_clk->aclk_isp) ||
794 IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
795 IS_ERR_OR_NULL(mrv_clk->isp) ||
796 IS_ERR_OR_NULL(mrv_clk->isp_jpe) ||
797 IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
798 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
799 IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
800 camsys_err("Get %s clock resouce failed!\n",
806 clk_set_rate(mrv_clk->isp, 210000000);
807 clk_set_rate(mrv_clk->isp_jpe, 210000000);
809 } else if (CHIP_TYPE == 3399) {
811 pm_runtime_enable(&pdev->dev);
812 mrv_clk->hclk_isp0_noc =
813 devm_clk_get(&pdev->dev, "hclk_isp0_noc");
814 mrv_clk->hclk_isp0_wrapper =
815 devm_clk_get(&pdev->dev, "hclk_isp0_wrapper");
816 mrv_clk->aclk_isp0_noc =
817 devm_clk_get(&pdev->dev, "aclk_isp0_noc");
818 mrv_clk->aclk_isp0_wrapper =
819 devm_clk_get(&pdev->dev, "aclk_isp0_wrapper");
821 devm_clk_get(&pdev->dev, "clk_isp0");
822 mrv_clk->cif_clk_out =
823 devm_clk_get(&pdev->dev, "clk_cif_out");
824 mrv_clk->cif_clk_pll =
825 devm_clk_get(&pdev->dev, "clk_cif_pll");
826 mrv_clk->pclk_dphyrx =
827 devm_clk_get(&pdev->dev, "pclk_dphyrx");
828 mrv_clk->pclk_dphy_ref =
829 devm_clk_get(&pdev->dev, "pclk_dphy_ref");
831 mrv_clk->hclk_isp1_noc =
832 devm_clk_get(&pdev->dev, "hclk_isp1_noc");
833 mrv_clk->hclk_isp1_wrapper =
834 devm_clk_get(&pdev->dev, "hclk_isp1_wrapper");
835 mrv_clk->aclk_isp1_noc =
836 devm_clk_get(&pdev->dev, "aclk_isp1_noc");
837 mrv_clk->aclk_isp1_wrapper =
838 devm_clk_get(&pdev->dev, "aclk_isp1_wrapper");
839 mrv_clk->pclkin_isp =
840 devm_clk_get(&pdev->dev, "pclk_isp1");
843 devm_clk_get(&pdev->dev, "clk_isp1");
844 mrv_clk->pclk_dphytxrx =
845 devm_clk_get(&pdev->dev, "pclk_dphytxrx");
847 if (IS_ERR_OR_NULL(mrv_clk->hclk_isp0_noc) ||
848 IS_ERR_OR_NULL(mrv_clk->hclk_isp0_wrapper) ||
849 IS_ERR_OR_NULL(mrv_clk->aclk_isp0_noc) ||
850 IS_ERR_OR_NULL(mrv_clk->aclk_isp0_wrapper) ||
851 IS_ERR_OR_NULL(mrv_clk->clk_isp0) ||
852 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
853 IS_ERR_OR_NULL(mrv_clk->cif_clk_pll) ||
854 IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx)) {
855 camsys_err("Get %s clock resouce failed!\n",
861 err = of_property_read_string(pdev->dev.of_node,
862 "compatible", &compatible);
864 camsys_err("get compatible failed!");
866 camsys_trace(1, "compatible is %s\n", compatible);
868 if (strstr(compatible, "isp1")) {
869 clk_set_rate(mrv_clk->clk_isp1, 210000000);
871 clk_set_rate(mrv_clk->clk_isp0, 210000000);
876 devm_clk_get(&pdev->dev, "pd_isp");
878 devm_clk_get(&pdev->dev, "aclk_isp");
880 devm_clk_get(&pdev->dev, "hclk_isp");
882 devm_clk_get(&pdev->dev, "clk_isp");
884 devm_clk_get(&pdev->dev, "clk_isp_jpe");
885 mrv_clk->pclkin_isp =
886 devm_clk_get(&pdev->dev, "pclkin_isp");
887 mrv_clk->cif_clk_out =
888 devm_clk_get(&pdev->dev, "clk_cif_out");
889 mrv_clk->cif_clk_pll =
890 devm_clk_get(&pdev->dev, "clk_cif_pll");
891 mrv_clk->clk_mipi_24m =
892 devm_clk_get(&pdev->dev, "clk_mipi_24m");
894 if (IS_ERR_OR_NULL(mrv_clk->pd_isp) ||
895 IS_ERR_OR_NULL(mrv_clk->aclk_isp) ||
896 IS_ERR_OR_NULL(mrv_clk->hclk_isp) ||
897 IS_ERR_OR_NULL(mrv_clk->isp) ||
898 IS_ERR_OR_NULL(mrv_clk->isp_jpe) ||
899 IS_ERR_OR_NULL(mrv_clk->pclkin_isp) ||
900 IS_ERR_OR_NULL(mrv_clk->cif_clk_out) ||
901 IS_ERR_OR_NULL(mrv_clk->clk_mipi_24m)) {
902 camsys_err("Get %s clock resouce failed!\n",
908 clk_set_rate(mrv_clk->isp, 210000000);
909 clk_set_rate(mrv_clk->isp_jpe, 210000000);
913 mutex_init(&mrv_clk->lock);
915 mrv_clk->in_on = false;
918 camsys_dev->clk = (void *)mrv_clk;
919 camsys_dev->clkin_cb = camsys_mrv_clkin_cb;
920 camsys_dev->clkout_cb = camsys_mrv_clkout_cb;
921 camsys_dev->reset_cb = camsys_mrv_reset_cb;
922 camsys_dev->iomux = camsys_mrv_iomux_cb;
923 camsys_dev->flash_trigger_cb = camsys_mrv_flash_trigger_cb;
924 camsys_dev->iommu_cb = camsys_mrv_iommu_cb;
926 camsys_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
927 camsys_dev->miscdev.name = miscdev_name;
928 camsys_dev->miscdev.nodename = miscdev_name;
929 camsys_dev->miscdev.fops = &camsys_fops;
931 if (CHIP_TYPE == 3399) {
932 if (strstr(compatible, "isp1")) {
933 camsys_dev->miscdev.name = "camsys_marvin1";
934 camsys_dev->miscdev.nodename = "camsys_marvin1";
938 err = misc_register(&camsys_dev->miscdev);
940 camsys_err("misc register %s failed!", miscdev_name);
941 goto misc_register_failed;
944 camsys_dev->dev_id = CAMSYS_DEVID_MARVIN;
945 camsys_dev->platform_remove = camsys_mrv_remove_cb;
948 misc_register_failed:
949 if (!IS_ERR_OR_NULL(camsys_dev->miscdev.this_device))
950 misc_deregister(&camsys_dev->miscdev);
953 if (mrv_clk != NULL) {
954 if (!IS_ERR_OR_NULL(mrv_clk->pd_isp))
955 clk_put(mrv_clk->pd_isp);
957 if (!IS_ERR_OR_NULL(mrv_clk->aclk_isp))
958 clk_put(mrv_clk->aclk_isp);
960 if (!IS_ERR_OR_NULL(mrv_clk->hclk_isp))
961 clk_put(mrv_clk->hclk_isp);
963 if (!IS_ERR_OR_NULL(mrv_clk->isp))
964 clk_put(mrv_clk->isp);
966 if (!IS_ERR_OR_NULL(mrv_clk->isp_jpe))
967 clk_put(mrv_clk->isp_jpe);
969 if (!IS_ERR_OR_NULL(mrv_clk->pclkin_isp))
970 clk_put(mrv_clk->pclkin_isp);
972 if (!IS_ERR_OR_NULL(mrv_clk->cif_clk_out))
973 clk_put(mrv_clk->cif_clk_out);
975 if (CHIP_TYPE == 3368 || CHIP_TYPE == 3366) {
976 if (!IS_ERR_OR_NULL(mrv_clk->pclk_dphyrx))
977 clk_put(mrv_clk->pclk_dphyrx);
979 if (!IS_ERR_OR_NULL(mrv_clk->clk_vio0_noc))
980 clk_put(mrv_clk->clk_vio0_noc);
990 EXPORT_SYMBOL_GPL(camsys_mrv_probe_cb);