2 #include <mach/iomux.h>
\r
3 #include <media/soc_camera.h>
\r
4 #include <linux/android_pmem.h>
\r
5 #include <mach/rk30_camera.h>
\r
6 #ifndef PMEM_CAM_SIZE
\r
7 #include "../../../arch/arm/plat-rk/rk_camera.c"
\r
9 /*****************************************************************************************
\r
11 * author: ddl@rock-chips.com
\r
12 *****************************************************************************************/
\r
13 #ifdef CONFIG_VIDEO_RK29
\r
15 static int rk_sensor_iomux(int pin)
\r
17 #if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
\r
18 iomux_set_gpio_mode(pin);
\r
19 #elif defined(CONFIG_ARCH_RK30)
\r
22 case RK30_PIN0_PA0:
\r
24 rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0);
\r
27 case RK30_PIN0_PA1:
\r
29 rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0);
\r
34 rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0);
\r
39 rk30_mux_api_set(GPIO0A3_PWM0_NAME,0);
\r
44 rk30_mux_api_set(GPIO0A4_PWM1_NAME,0);
\r
49 rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0);
\r
54 rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0);
\r
59 rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0);
\r
64 rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0);
\r
69 rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0);
\r
74 rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0);
\r
79 rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0);
\r
84 rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0);
\r
89 rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0);
\r
94 rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0);
\r
99 rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0);
\r
102 case RK30_PIN0_PC0:
\r
104 rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0);
\r
107 case RK30_PIN0_PC1:
\r
109 rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0);
\r
112 case RK30_PIN0_PC2:
\r
114 rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0);
\r
117 case RK30_PIN0_PC3:
\r
119 rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0);
\r
122 case RK30_PIN0_PC4:
\r
124 rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0);
\r
127 case RK30_PIN0_PC5:
\r
129 rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0);
\r
132 case RK30_PIN0_PC6:
\r
134 rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0);
\r
137 case RK30_PIN0_PC7:
\r
139 rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0);
\r
142 case RK30_PIN0_PD0:
\r
144 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0);
\r
147 case RK30_PIN0_PD1:
\r
149 rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0);
\r
152 case RK30_PIN0_PD2:
\r
154 rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0);
\r
157 case RK30_PIN0_PD3:
\r
159 rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0);
\r
162 case RK30_PIN0_PD4:
\r
164 rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0);
\r
167 case RK30_PIN0_PD5:
\r
169 rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0);
\r
172 case RK30_PIN0_PD6:
\r
174 rk30_mux_api_set(GPIO0D6_PWM2_NAME,0);
\r
177 case RK30_PIN0_PD7:
\r
179 rk30_mux_api_set(GPIO0D7_PWM3_NAME,0);
\r
182 case RK30_PIN1_PA0:
\r
184 rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);
\r
187 case RK30_PIN1_PA1:
\r
189 rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);
\r
192 case RK30_PIN1_PA2:
\r
194 rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);
\r
197 case RK30_PIN1_PA3:
\r
199 rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);
\r
202 case RK30_PIN1_PA4:
\r
204 rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0);
\r
207 case RK30_PIN1_PA5:
\r
209 rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0);
\r
212 case RK30_PIN1_PA6:
\r
214 rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0);
\r
217 case RK30_PIN1_PA7:
\r
219 rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0);
\r
222 case RK30_PIN1_PB0:
\r
224 rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0);
\r
227 case RK30_PIN1_PB1:
\r
229 rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0);
\r
232 case RK30_PIN1_PB2:
\r
234 rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0);
\r
237 case RK30_PIN1_PB3:
\r
239 rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0);
\r
242 case RK30_PIN1_PB4:
\r
244 rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0);
\r
247 case RK30_PIN1_PB5:
\r
249 rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0);
\r
252 case RK30_PIN1_PB6:
\r
254 rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0);
\r
257 case RK30_PIN1_PB7:
\r
259 rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0);
\r
262 case RK30_PIN1_PC0:
\r
264 rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0);
\r
267 case RK30_PIN1_PC1:
\r
269 rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0);
\r
272 case RK30_PIN1_PC2:
\r
274 rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0);
\r
277 case RK30_PIN1_PC3:
\r
279 rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0);
\r
282 case RK30_PIN1_PC4:
\r
284 rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0);
\r
287 case RK30_PIN1_PC5:
\r
289 rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0);
\r
292 case RK30_PIN1_PC6:
\r
294 rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0);
\r
297 case RK30_PIN1_PC7:
\r
299 rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0);
\r
302 case RK30_PIN1_PD0:
\r
304 rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0);
\r
307 case RK30_PIN1_PD1:
\r
309 rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0);
\r
312 case RK30_PIN1_PD2:
\r
314 rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0);
\r
317 case RK30_PIN1_PD3:
\r
319 rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0);
\r
322 case RK30_PIN1_PD4:
\r
324 rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0);
\r
327 case RK30_PIN1_PD5:
\r
329 rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0);
\r
332 case RK30_PIN1_PD6:
\r
334 rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0);
\r
337 case RK30_PIN1_PD7:
\r
339 rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0);
\r
342 case RK30_PIN2_PA0:
\r
344 rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0);
\r
347 case RK30_PIN2_PA1:
\r
349 rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0);
\r
352 case RK30_PIN2_PA2:
\r
354 rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0);
\r
357 case RK30_PIN2_PA3:
\r
359 rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0);
\r
362 case RK30_PIN2_PA4:
\r
364 rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0);
\r
367 case RK30_PIN2_PA5:
\r
369 rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0);
\r
372 case RK30_PIN2_PA6:
\r
374 rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0);
\r
377 case RK30_PIN2_PA7:
\r
379 rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0);
\r
382 case RK30_PIN2_PB0:
\r
384 rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0);
\r
387 case RK30_PIN2_PB1:
\r
389 rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0);
\r
392 case RK30_PIN2_PB2:
\r
394 rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0);
\r
397 case RK30_PIN2_PB3:
\r
399 rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0);
\r
402 case RK30_PIN2_PB4:
\r
404 rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0);
\r
407 case RK30_PIN2_PB5:
\r
409 rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0);
\r
412 case RK30_PIN2_PB6:
\r
414 rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0);
\r
417 case RK30_PIN2_PB7:
\r
419 rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0);
\r
422 case RK30_PIN2_PC0:
\r
424 rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0);
\r
427 case RK30_PIN2_PC1:
\r
429 rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0);
\r
432 case RK30_PIN2_PC2:
\r
434 rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0);
\r
437 case RK30_PIN2_PC3:
\r
439 rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0);
\r
442 case RK30_PIN2_PC4:
\r
444 rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0);
\r
447 case RK30_PIN2_PC5:
\r
449 rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0);
\r
452 case RK30_PIN2_PC6:
\r
454 rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0);
\r
457 case RK30_PIN2_PC7:
\r
459 rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0);
\r
462 case RK30_PIN2_PD0:
\r
464 rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0);
\r
467 case RK30_PIN2_PD1:
\r
469 rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0);
\r
472 case RK30_PIN2_PD2:
\r
474 rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0);
\r
477 case RK30_PIN2_PD3:
\r
479 rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0);
\r
482 case RK30_PIN2_PD4:
\r
484 rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0);
\r
487 case RK30_PIN2_PD5:
\r
489 rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0);
\r
492 case RK30_PIN2_PD6:
\r
494 rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0);
\r
497 case RK30_PIN2_PD7:
\r
499 rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0);
\r
502 case RK30_PIN3_PA0:
\r
504 rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0);
\r
507 case RK30_PIN3_PA1:
\r
509 rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0);
\r
512 case RK30_PIN3_PA2:
\r
514 rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0);
\r
517 case RK30_PIN3_PA3:
\r
519 rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0);
\r
522 case RK30_PIN3_PA4:
\r
524 rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0);
\r
527 case RK30_PIN3_PA5:
\r
529 rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0);
\r
532 case RK30_PIN3_PA6:
\r
534 rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0);
\r
537 case RK30_PIN3_PA7:
\r
539 rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0);
\r
542 case RK30_PIN3_PB0:
\r
544 rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0);
\r
547 case RK30_PIN3_PB1:
\r
549 rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0);
\r
552 case RK30_PIN3_PB2:
\r
554 rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0);
\r
557 case RK30_PIN3_PB3:
\r
559 rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0);
\r
562 case RK30_PIN3_PB4:
\r
564 rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0);
\r
567 case RK30_PIN3_PB5:
\r
569 rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0);
\r
572 case RK30_PIN3_PB6:
\r
574 rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0);
\r
577 case RK30_PIN3_PB7:
\r
579 rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0);
\r
582 case RK30_PIN3_PC0:
\r
584 rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0);
\r
587 case RK30_PIN3_PC1:
\r
589 rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0);
\r
592 case RK30_PIN3_PC2:
\r
594 rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0);
\r
597 case RK30_PIN3_PC3:
\r
599 rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0);
\r
602 case RK30_PIN3_PC4:
\r
604 rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0);
\r
607 case RK30_PIN3_PC5:
\r
609 rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0);
\r
612 case RK30_PIN3_PC6:
\r
614 rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0);
\r
617 case RK30_PIN3_PC7:
\r
619 rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0);
\r
622 case RK30_PIN3_PD0:
\r
624 rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0);
\r
627 case RK30_PIN3_PD1:
\r
629 rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0);
\r
632 case RK30_PIN3_PD2:
\r
634 rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);
\r
637 case RK30_PIN3_PD3:
\r
639 rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0);
\r
642 case RK30_PIN3_PD4:
\r
644 rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0);
\r
647 case RK30_PIN3_PD5:
\r
649 rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0);
\r
652 case RK30_PIN3_PD6:
\r
654 rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0);
\r
657 case RK30_PIN3_PD7:
\r
659 rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0);
\r
662 case RK30_PIN4_PA0:
\r
664 rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0);
\r
667 case RK30_PIN4_PA1:
\r
669 rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0);
\r
672 case RK30_PIN4_PA2:
\r
674 rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0);
\r
678 case RK30_PIN4_PA3:
\r
680 rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0);
\r
683 case RK30_PIN4_PA4:
\r
685 rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0);
\r
688 case RK30_PIN4_PA5:
\r
690 rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0);
\r
693 case RK30_PIN4_PA6:
\r
695 rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0);
\r
698 case RK30_PIN4_PA7:
\r
700 rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0);
\r
703 case RK30_PIN4_PB0:
\r
705 rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0);
\r
708 case RK30_PIN4_PB1:
\r
710 rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0);
\r
713 case RK30_PIN4_PB2:
\r
715 rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0);
\r
718 case RK30_PIN4_PB3:
\r
720 rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0);
\r
723 case RK30_PIN4_PB4:
\r
725 rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0);
\r
728 case RK30_PIN4_PB5:
\r
730 rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0);
\r
733 case RK30_PIN4_PB6:
\r
735 rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0);
\r
738 case RK30_PIN4_PB7:
\r
740 rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0);
\r
743 case RK30_PIN4_PC0:
\r
745 rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0);
\r
748 case RK30_PIN4_PC1:
\r
750 rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0);
\r
753 case RK30_PIN4_PC2:
\r
755 rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0);
\r
758 case RK30_PIN4_PC3:
\r
760 rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0);
\r
763 case RK30_PIN4_PC4:
\r
765 rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0);
\r
768 case RK30_PIN4_PC5:
\r
770 rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0);
\r
773 case RK30_PIN4_PC6:
\r
775 rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0);
\r
780 case RK30_PIN4_PC7:
\r
782 rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0);
\r
785 case RK30_PIN4_PD0:
\r
787 rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0);
\r
790 case RK30_PIN4_PD1:
\r
792 rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0);
\r
795 case RK30_PIN4_PD2:
\r
797 rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0);
\r
800 case RK30_PIN4_PD3:
\r
802 rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0);
\r
805 case RK30_PIN4_PD4:
\r
807 rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0);
\r
810 case RK30_PIN4_PD5:
\r
812 rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0);
\r
815 case RK30_PIN4_PD6:
\r
817 rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0);
\r
820 case RK30_PIN4_PD7:
\r
822 rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0);
\r
825 case RK30_PIN6_PA0:
\r
826 case RK30_PIN6_PA1:
\r
827 case RK30_PIN6_PA2:
\r
828 case RK30_PIN6_PA3:
\r
829 case RK30_PIN6_PA4:
\r
830 case RK30_PIN6_PA5:
\r
831 case RK30_PIN6_PA6:
\r
832 case RK30_PIN6_PA7:
\r
833 case RK30_PIN6_PB0:
\r
834 case RK30_PIN6_PB1:
\r
835 case RK30_PIN6_PB2:
\r
836 case RK30_PIN6_PB3:
\r
837 case RK30_PIN6_PB4:
\r
838 case RK30_PIN6_PB5:
\r
839 case RK30_PIN6_PB6:
\r
841 case RK30_PIN6_PB7:
\r
843 rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0);
\r
848 printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);
\r
855 #define PMEM_CAM_BASE 0 //just for compile ,no meaning
\r
856 #include "../../../arch/arm/plat-rk/rk_camera.c"
\r
860 static u64 rockchip_device_camera_dmamask = 0xffffffffUL;
\r
861 #if RK_SUPPORT_CIF0
\r
862 static struct resource rk_camera_resource_host_0[] = {
\r
864 .start = RK30_CIF0_PHYS,
\r
865 .end = RK30_CIF0_PHYS + RK30_CIF0_SIZE - 1,
\r
866 .flags = IORESOURCE_MEM,
\r
871 .flags = IORESOURCE_IRQ,
\r
875 #if RK_SUPPORT_CIF1
\r
876 static struct resource rk_camera_resource_host_1[] = {
\r
878 .start = RK30_CIF1_PHYS,
\r
879 .end = RK30_CIF1_PHYS + RK30_CIF1_SIZE - 1,
\r
880 .flags = IORESOURCE_MEM,
\r
885 .flags = IORESOURCE_IRQ,
\r
890 /*platform_device : */
\r
891 #if RK_SUPPORT_CIF0
\r
892 struct platform_device rk_device_camera_host_0 = {
\r
893 .name = RK29_CAM_DRV_NAME,
\r
894 .id = RK_CAM_PLATFORM_DEV_ID_0, /* This is used to put cameras on this interface */
\r
895 .num_resources = ARRAY_SIZE(rk_camera_resource_host_0),
\r
896 .resource = rk_camera_resource_host_0,
\r
898 .dma_mask = &rockchip_device_camera_dmamask,
\r
899 .coherent_dma_mask = 0xffffffffUL,
\r
900 .platform_data = &rk_camera_platform_data,
\r
905 #if RK_SUPPORT_CIF1
\r
906 /*platform_device : */
\r
907 struct platform_device rk_device_camera_host_1 = {
\r
908 .name = RK29_CAM_DRV_NAME,
\r
909 .id = RK_CAM_PLATFORM_DEV_ID_1, /* This is used to put cameras on this interface */
\r
910 .num_resources = ARRAY_SIZE(rk_camera_resource_host_1),
\r
911 .resource = rk_camera_resource_host_1,
\r
913 .dma_mask = &rockchip_device_camera_dmamask,
\r
914 .coherent_dma_mask = 0xffffffffUL,
\r
915 .platform_data = &rk_camera_platform_data,
\r
920 static void rk_init_camera_plateform_data(void)
\r
925 for (i=0; i<RK_CAM_NUM; i++) {
\r
926 rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];
\r
927 if (rk_camera_platform_data.register_dev[i].device_info.name) {
\r
928 rk_camera_platform_data.register_dev[i].link_info.board_info =
\r
929 &rk_camera_platform_data.register_dev[i].i2c_cam_info;
\r
930 rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;
\r
931 rk_camera_platform_data.register_dev[i].device_info.dev.platform_data =
\r
932 &rk_camera_platform_data.register_dev[i].link_info;
\r
938 static void rk30_camera_request_reserve_mem(void)
\r
940 int i,max_resolution;
\r
941 int cam_ipp_mem=PMEM_CAMIPP_NECESSARY, cam_pmem=PMEM_CAM_NECESSARY;
\r
944 max_resolution = 0x00;
\r
945 while (strstr(new_camera[i].dev.device_info.dev.init_name,"end")==NULL) {
\r
946 if (new_camera[i].resolution > max_resolution)
\r
947 max_resolution = new_camera[i].resolution;
\r
951 if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_1)
\r
952 max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_1;
\r
953 if (max_resolution < PMEM_SENSOR_FULL_RESOLUTION_CIF_0)
\r
954 max_resolution = PMEM_SENSOR_FULL_RESOLUTION_CIF_0;
\r
956 switch (max_resolution)
\r
961 cam_ipp_mem = 0x800000;
\r
962 cam_pmem = 0x1900000;
\r
968 cam_ipp_mem = 0x800000;
\r
969 cam_pmem = 0x1400000;
\r
975 cam_ipp_mem = 0x600000;
\r
976 cam_pmem = 0xf00000;
\r
982 cam_ipp_mem = 0x600000;
\r
983 cam_pmem = 0xc00000;
\r
989 cam_ipp_mem = 0x600000;
\r
990 cam_pmem = 0xa00000;
\r
996 cam_ipp_mem = 0x600000;
\r
997 cam_pmem = 0x600000;
\r
1004 #ifdef CONFIG_VIDEO_RK29_WORK_IPP
\r
1005 rk_camera_platform_data.meminfo.vbase = rk_camera_platform_data.meminfo_cif1.vbase = NULL;
\r
1006 #if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == 0)
\r
1007 rk_camera_platform_data.meminfo.name = "camera_ipp_mem";
\r
1008 rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",cam_ipp_mem);
\r
1009 rk_camera_platform_data.meminfo.size= cam_ipp_mem;
\r
1011 memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));
\r
1013 rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";
\r
1014 rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);
\r
1015 rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;
\r
1017 rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";
\r
1018 rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);
\r
1019 rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;
\r
1022 #if PMEM_CAM_NECESSARY
\r
1023 android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),cam_pmem);
\r
1024 android_pmem_cam_pdata.size= cam_pmem;
\r
1028 static int rk_register_camera_devices(void)
\r
1031 int host_registered_0,host_registered_1;
\r
1032 struct rkcamera_platform_data *new_camera;
\r
1034 rk_init_camera_plateform_data();
\r
1036 host_registered_0 = 0;
\r
1037 host_registered_1 = 0;
\r
1039 for (i=0; i<RK_CAM_NUM; i++) {
\r
1040 if (rk_camera_platform_data.register_dev[i].device_info.name) {
\r
1042 if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {
\r
1043 #if RK_SUPPORT_CIF0
\r
1044 host_registered_0 = 1;
\r
1046 printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);
\r
1050 if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {
\r
1051 #if RK_SUPPORT_CIF1
\r
1052 host_registered_1 = 1;
\r
1054 printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);
\r
1062 new_camera = rk_camera_platform_data.register_dev_new;
\r
1063 if (new_camera != NULL) {
\r
1064 while (strstr(new_camera->dev.device_info.dev.init_name,"end")==NULL) {
\r
1065 if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {
\r
1066 host_registered_1 = 1;
\r
1067 } else if (new_camera->dev.link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {
\r
1068 host_registered_0 = 1;
\r
1073 #if RK_SUPPORT_CIF0
\r
1074 if (host_registered_0) {
\r
1075 platform_device_register(&rk_device_camera_host_0);
\r
1078 #if RK_SUPPORT_CIF1
\r
1079 if (host_registered_1) {
\r
1080 platform_device_register(&rk_device_camera_host_1);
\r
1084 for (i=0; i<RK_CAM_NUM; i++) {
\r
1085 if (rk_camera_platform_data.register_dev[i].device_info.name) {
\r
1086 platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);
\r
1090 if (rk_camera_platform_data.sensor_register)
\r
1091 (rk_camera_platform_data.sensor_register)();
\r
1093 #if PMEM_CAM_NECESSARY
\r
1094 platform_device_register(&android_pmem_cam_device);
\r
1099 module_init(rk_register_camera_devices);
\r
1102 #endif //#ifdef CONFIG_VIDEO_RK
\r