drivers/media/video/rk30_camera.c

   1 \r
   2 #include <mach/iomux.h>\r
   3 #include <media/soc_camera.h>\r
   4 #include <linux/android_pmem.h>\r
   5 #include <mach/rk30_camera.h>\r
   6 #ifndef PMEM_CAM_SIZE\r
   7 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
   8 #else\r
   9 /*****************************************************************************************\r
  10  * camera  devices\r
  11  * author: ddl@rock-chips.com\r
  12  *****************************************************************************************/\r
  13 #ifdef CONFIG_VIDEO_RK29 \r
  14 \r
  15 static int rk_sensor_iomux(int pin)\r
  16 {    \r
  17 #if defined(CONFIG_ARCH_RK3066B)\r
  18     switch (pin)\r
  19     {\r
  20         case RK30_PIN0_PA0:\r
  21         case RK30_PIN0_PA1: \r
  22                 case RK30_PIN0_PA2:\r
  23                 case RK30_PIN0_PA3:\r
  24                 case RK30_PIN0_PA4:\r
  25                 case RK30_PIN0_PA5:\r
  26                 case RK30_PIN0_PA6:\r
  27         case RK30_PIN0_PA7:\r
  28         case RK30_PIN0_PB0:\r
  29         case RK30_PIN0_PB1:\r
  30         case RK30_PIN0_PB2:\r
  31         case RK30_PIN0_PB3:\r
  32         case RK30_PIN0_PB4:\r
  33         case RK30_PIN0_PB5:\r
  34         case RK30_PIN0_PB6:\r
  35         case RK30_PIN0_PB7:\r
  36         case RK30_PIN0_PC0:\r
  37         {\r
  38              rk30_mux_api_set(GPIO0C0_FLASHDATA8_NAME,0);\r
  39             break;      \r
  40         }\r
  41         case RK30_PIN0_PC1:\r
  42         {\r
  43              rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME,0);\r
  44             break;      \r
  45         }\r
  46         case RK30_PIN0_PC2:\r
  47         {\r
  48              rk30_mux_api_set(GPIO0C2_FLASHDATA10_NAME,0);\r
  49             break;      \r
  50         }\r
  51         case RK30_PIN0_PC3:\r
  52         {\r
  53              rk30_mux_api_set(GPIO0C3_FLASHDATA11_NAME,0);\r
  54             break;      \r
  55         }\r
  56         case RK30_PIN0_PC4:\r
  57         {\r
  58              rk30_mux_api_set(GPIO0C4_FLASHDATA12_NAME,0);\r
  59             break;      \r
  60         }\r
  61         case RK30_PIN0_PC5:\r
  62         {\r
  63              rk30_mux_api_set(GPIO0C5_FLASHDATA13_NAME,0);\r
  64             break;      \r
  65         }\r
  66         case RK30_PIN0_PC6:\r
  67         {\r
  68              rk30_mux_api_set(GPIO0C6_FLASHDATA14_NAME,0);\r
  69             break;      \r
  70         }\r
  71         case RK30_PIN0_PC7:\r
  72         {\r
  73              rk30_mux_api_set(GPIO0C7_FLASHDATA15_NAME,0);\r
  74             break;      \r
  75         }\r
  76         case RK30_PIN0_PD0:\r
  77         {\r
  78              rk30_mux_api_set(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,0);\r
  79             break;      \r
  80         }\r
  81         case RK30_PIN0_PD1:\r
  82         {\r
  83              rk30_mux_api_set(GPIO0D1_FLASHCSN1_NAME,0);\r
  84             break;      \r
  85         }\r
  86         case RK30_PIN0_PD2:\r
  87         {\r
  88              rk30_mux_api_set(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,0);\r
  89             break;      \r
  90         }\r
  91         case RK30_PIN0_PD3:\r
  92         {\r
  93              rk30_mux_api_set(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
  94             break;      \r
  95         }\r
  96         case RK30_PIN0_PD4:\r
  97         {\r
  98              rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME,0);\r
  99             break;      \r
 100         }\r
 101         case RK30_PIN0_PD5:\r
 102         {\r
 103              rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME,0);\r
 104             break;      \r
 105         }\r
 106         case RK30_PIN0_PD6:\r
 107         {\r
 108              rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME,0);\r
 109             break;      \r
 110         }\r
 111         case RK30_PIN0_PD7:\r
 112         {\r
 113              rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME,0);\r
 114             break;      \r
 115         }\r
 116         case RK30_PIN1_PA0:\r
 117         {\r
 118              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 119             break;      \r
 120         }\r
 121         case RK30_PIN1_PA1:\r
 122         {\r
 123              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 124             break;      \r
 125         }\r
 126         case RK30_PIN1_PA2:\r
 127         {\r
 128              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 129             break;      \r
 130         }\r
 131         case RK30_PIN1_PA3:\r
 132         {\r
 133              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 134             break;      \r
 135         }\r
 136         case RK30_PIN1_PA4:\r
 137         {\r
 138              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME,0);\r
 139             break;      \r
 140         }\r
 141         case RK30_PIN1_PA5:\r
 142         {\r
 143              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME,0);\r
 144             break;      \r
 145         }\r
 146         case RK30_PIN1_PA6:\r
 147         {\r
 148              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME,0);\r
 149             break;      \r
 150         }\r
 151         case RK30_PIN1_PA7:\r
 152         {\r
 153              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME,0);\r
 154             break;      \r
 155         }\r
 156         case RK30_PIN1_PB0:\r
 157         {\r
 158              rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME,0);\r
 159             break;      \r
 160         }\r
 161         case RK30_PIN1_PB1:\r
 162         {\r
 163              rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME,0);\r
 164             break;      \r
 165         }\r
 166         case RK30_PIN1_PB2:\r
 167         {\r
 168              rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME,0);\r
 169             break;      \r
 170         }\r
 171         case RK30_PIN1_PB3:\r
 172         {\r
 173              rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME,0);\r
 174             break;      \r
 175         }\r
 176         case RK30_PIN1_PB4:\r
 177         {\r
 178              rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME,0);\r
 179             break;      \r
 180         }\r
 181         case RK30_PIN1_PB5:\r
 182         {\r
 183              rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME,0);\r
 184             break;      \r
 185         }\r
 186         case RK30_PIN1_PB6:\r
 187         {\r
 188              rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME,0);\r
 189             break;      \r
 190         }\r
 191         case RK30_PIN1_PB7:\r
 192         {\r
 193              rk30_mux_api_set(GPIO1B7_SPI0CSN1_NAME,0);\r
 194             break;      \r
 195         }\r
 196         case RK30_PIN1_PC0:\r
 197         {\r
 198              rk30_mux_api_set(GPIO1C0_I2SCLK_NAME,0);\r
 199             break;      \r
 200         }\r
 201         case RK30_PIN1_PC1:\r
 202         {\r
 203              rk30_mux_api_set(GPIO1C1_I2SSCLK_NAME,0);\r
 204             break;      \r
 205         }\r
 206         case RK30_PIN1_PC2:\r
 207         {\r
 208              rk30_mux_api_set(GPIO1C2_I2SLRCLKRX_NAME,0);\r
 209             break;      \r
 210         }\r
 211         case RK30_PIN1_PC3:\r
 212         {\r
 213              rk30_mux_api_set(GPIO1C3_I2SLRCLKTX_NAME,0);\r
 214             break;      \r
 215         }\r
 216         case RK30_PIN1_PC4:\r
 217         {\r
 218              rk30_mux_api_set(GPIO1C4_I2SSDI_NAME,0);\r
 219             break;      \r
 220         }\r
 221         case RK30_PIN1_PC5:\r
 222         case RK30_PIN1_PC6:\r
 223         case RK30_PIN1_PC7:\r
 224             break;      \r
 225         case RK30_PIN1_PD0:\r
 226         {\r
 227              rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME,0);\r
 228             break;      \r
 229         }\r
 230         case RK30_PIN1_PD1:\r
 231         {\r
 232              rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME,0);\r
 233             break;      \r
 234         }\r
 235         case RK30_PIN1_PD2:\r
 236         {\r
 237              rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME,0);\r
 238             break;      \r
 239         }\r
 240         case RK30_PIN1_PD3:\r
 241         {\r
 242              rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME,0);\r
 243             break;      \r
 244         }\r
 245         case RK30_PIN1_PD4:\r
 246         {\r
 247              rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME,0);\r
 248             break;      \r
 249         }\r
 250         case RK30_PIN1_PD5:\r
 251         {\r
 252              rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME,0);\r
 253             break;      \r
 254         }\r
 255         case RK30_PIN1_PD6:\r
 256         {\r
 257              rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME,0);\r
 258             break;      \r
 259         }\r
 260         case RK30_PIN1_PD7:\r
 261         {\r
 262              rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME,0);\r
 263             break;      \r
 264         }\r
 265         case RK30_PIN2_PA0:\r
 266         {\r
 267              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,0);\r
 268             break;      \r
 269         }\r
 270         case RK30_PIN2_PA1:\r
 271         {\r
 272              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,0);\r
 273             break;      \r
 274         }\r
 275         case RK30_PIN2_PA2:\r
 276         {\r
 277              rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,0);\r
 278             break;      \r
 279         }\r
 280         case RK30_PIN2_PA3:\r
 281         {\r
 282              rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,0);\r
 283             break;      \r
 284         }\r
 285         case RK30_PIN2_PA4:\r
 286         {\r
 287              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,0);\r
 288             break;      \r
 289         }\r
 290         case RK30_PIN2_PA5:\r
 291         {\r
 292              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,0);\r
 293             break;      \r
 294         }\r
 295         case RK30_PIN2_PA6:\r
 296         {\r
 297              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,0);\r
 298             break;      \r
 299         }\r
 300         case RK30_PIN2_PA7:\r
 301         {\r
 302              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,0);\r
 303             break;      \r
 304         }\r
 305         case RK30_PIN2_PB0:\r
 306         {\r
 307              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,0);\r
 308             break;      \r
 309         }\r
 310         case RK30_PIN2_PB1:\r
 311         {\r
 312              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,0);\r
 313             break;      \r
 314         }\r
 315         case RK30_PIN2_PB2:\r
 316         {\r
 317              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,0);\r
 318             break;      \r
 319         }\r
 320         case RK30_PIN2_PB3:\r
 321         {\r
 322              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,0);\r
 323             break;      \r
 324         }\r
 325         case RK30_PIN2_PB4:\r
 326         {\r
 327              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,0);\r
 328             break;      \r
 329         }\r
 330         case RK30_PIN2_PB5:\r
 331         {\r
 332              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,0);\r
 333             break;      \r
 334         }\r
 335         case RK30_PIN2_PB6:\r
 336         {\r
 337              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,0);\r
 338             break;      \r
 339         }\r
 340         case RK30_PIN2_PB7:\r
 341         {\r
 342              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,0);\r
 343             break;      \r
 344         }\r
 345         case RK30_PIN2_PC0:\r
 346         {\r
 347              rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,0);\r
 348             break;      \r
 349         }\r
 350         case RK30_PIN2_PC1:\r
 351         {\r
 352              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,0);\r
 353             break;      \r
 354         }\r
 355         case RK30_PIN2_PC2:\r
 356         {\r
 357              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,0);\r
 358             break;      \r
 359         }\r
 360         case RK30_PIN2_PC3:\r
 361         {\r
 362              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,0);\r
 363             break;      \r
 364         }\r
 365         case RK30_PIN2_PC4:\r
 366         {\r
 367              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,0);\r
 368             break;      \r
 369         }\r
 370         case RK30_PIN2_PC5:\r
 371         {\r
 372              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,0);\r
 373             break;      \r
 374         }\r
 375         case RK30_PIN2_PC6:\r
 376         {\r
 377              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,0);\r
 378             break;      \r
 379         }\r
 380         case RK30_PIN2_PC7:\r
 381         {\r
 382              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,0);\r
 383             break;      \r
 384         }\r
 385         case RK30_PIN2_PD0:\r
 386         {\r
 387              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,0);\r
 388             break;      \r
 389         }\r
 390         case RK30_PIN2_PD1:\r
 391         {\r
 392              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,0);\r
 393             break;      \r
 394         }\r
 395         case RK30_PIN2_PD2:\r
 396         {\r
 397              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,0);\r
 398             break;      \r
 399         }\r
 400         case RK30_PIN2_PD3:\r
 401         {\r
 402              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,0);\r
 403             break;      \r
 404         }\r
 405         case RK30_PIN2_PD4:\r
 406         {\r
 407              rk30_mux_api_set(GPIO2D4_SMCBLSN0_NAME,0);\r
 408             break;      \r
 409         }\r
 410         case RK30_PIN2_PD5:\r
 411         {\r
 412              rk30_mux_api_set(GPIO2D5_SMCBLSN1_NAME,0);\r
 413             break;      \r
 414         }\r
 415         case RK30_PIN2_PD6:\r
 416         {\r
 417              rk30_mux_api_set(GPIO2D6_SMCCSN1_NAME,0);\r
 418             break;      \r
 419         }\r
 420         case RK30_PIN2_PD7:\r
 421         {\r
 422              rk30_mux_api_set(GPIO2D7_TESTCLOCKOUT_NAME,0);\r
 423             break;      \r
 424         }\r
 425         case RK30_PIN3_PA0:\r
 426         {\r
 427              rk30_mux_api_set(GPIO3A0_SDMMC0RSTNOUT_NAME,0);\r
 428             break;      \r
 429         }\r
 430         case RK30_PIN3_PA1:\r
 431         {\r
 432              rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME,0);\r
 433             break;      \r
 434         }\r
 435         case RK30_PIN3_PA2:\r
 436         {\r
 437              rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME,0);\r
 438             break;      \r
 439         }\r
 440         case RK30_PIN3_PA3:\r
 441         {\r
 442              rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME,0);\r
 443             break;      \r
 444         }\r
 445         case RK30_PIN3_PA4:\r
 446         {\r
 447              rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME,0);\r
 448             break;      \r
 449         }\r
 450         case RK30_PIN3_PA5:\r
 451         {\r
 452              rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME,0);\r
 453             break;      \r
 454         }\r
 455         case RK30_PIN3_PA6:\r
 456         {\r
 457              rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME,0);\r
 458             break;      \r
 459         }\r
 460         case RK30_PIN3_PA7:\r
 461         {\r
 462              rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME,0);\r
 463             break;      \r
 464         }\r
 465         case RK30_PIN3_PB0:\r
 466         {\r
 467              rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME,0);\r
 468             break;      \r
 469         }\r
 470         case RK30_PIN3_PB1:\r
 471         {\r
 472              rk30_mux_api_set(GPIO3B1_SDMMC0WRITEPRT_NAME,0);\r
 473             break;      \r
 474         }\r
 475         case RK30_PIN3_PB2:        \r
 476             break;\r
 477         case RK30_PIN3_PB3:\r
 478         {\r
 479              rk30_mux_api_set(GPIO3B3_CIFCLKOUT_NAME,0);\r
 480             break;      \r
 481         }\r
 482         case RK30_PIN3_PB4:\r
 483         {\r
 484              rk30_mux_api_set(GPIO3B4_CIFDATA0_HSADCDATA8_NAME,0);\r
 485             break;      \r
 486         }\r
 487         case RK30_PIN3_PB5:\r
 488         {\r
 489              rk30_mux_api_set(GPIO3B5_CIFDATA1_HSADCDATA9_NAME,0);\r
 490             break;      \r
 491         }\r
 492         case RK30_PIN3_PB6:\r
 493         {\r
 494              rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME,0);\r
 495             break;      \r
 496         }\r
 497         case RK30_PIN3_PB7:\r
 498         {\r
 499              rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME,0);\r
 500             break;      \r
 501         }\r
 502         case RK30_PIN3_PC0:\r
 503         {\r
 504              rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,0);\r
 505             break;      \r
 506         }\r
 507         case RK30_PIN3_PC1:\r
 508         {\r
 509              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,0);\r
 510             break;      \r
 511         }\r
 512         case RK30_PIN3_PC2:\r
 513         {\r
 514              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,0);\r
 515             break;      \r
 516         }\r
 517         case RK30_PIN3_PC3:\r
 518         {\r
 519              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,0);\r
 520             break;      \r
 521         }\r
 522         case RK30_PIN3_PC4:\r
 523         {\r
 524              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,0);\r
 525             break;      \r
 526         }\r
 527         case RK30_PIN3_PC5:\r
 528         {\r
 529              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,0);\r
 530             break;      \r
 531         }\r
 532         case RK30_PIN3_PC6:\r
 533         {\r
 534              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME,0);\r
 535             break;      \r
 536         }\r
 537         case RK30_PIN3_PC7:\r
 538         {\r
 539              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME,0);\r
 540             break;      \r
 541         }\r
 542         case RK30_PIN3_PD0:\r
 543         {\r
 544              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME,0);\r
 545             break;      \r
 546         }\r
 547         case RK30_PIN3_PD1:\r
 548         {\r
 549              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME,0);\r
 550             break;      \r
 551         }\r
 552         case RK30_PIN3_PD2:\r
 553         {\r
 554              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
 555             break;      \r
 556         }\r
 557         case RK30_PIN3_PD3:\r
 558         {\r
 559              rk30_mux_api_set(GPIO3D3_PWM0_NAME,0);\r
 560             break;      \r
 561         }\r
 562         case RK30_PIN3_PD4:\r
 563         {\r
 564              rk30_mux_api_set(GPIO3D4_PWM1_JTAGTRSTN_NAME,0);\r
 565             break;      \r
 566         }\r
 567         case RK30_PIN3_PD5:\r
 568         {\r
 569              rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME,0);\r
 570             break;      \r
 571         }\r
 572         case RK30_PIN3_PD6:\r
 573         {\r
 574              rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME,0);\r
 575             break;      \r
 576         }\r
 577         case RK30_PIN3_PD7:        \r
 578             break;        \r
 579         default:\r
 580         {\r
 581             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
 582             break;\r
 583         }\r
 584     }\r
 585 \r
 586 #elif defined(CONFIG_ARCH_RK30)\r
 587     switch (pin)\r
 588     {\r
 589         case RK30_PIN0_PA0: \r
 590                 {\r
 591                          rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0);\r
 592                         break;  \r
 593                 }\r
 594         case RK30_PIN0_PA1: \r
 595                 {\r
 596                          rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0);\r
 597                         break;  \r
 598                 }\r
 599         case RK30_PIN0_PA2:\r
 600                 {\r
 601                          rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0);\r
 602                         break;  \r
 603                 }\r
 604         case RK30_PIN0_PA3:\r
 605                 {\r
 606                          rk30_mux_api_set(GPIO0A3_PWM0_NAME,0);\r
 607                         break;  \r
 608                 }\r
 609         case RK30_PIN0_PA4:\r
 610                 {\r
 611                          rk30_mux_api_set(GPIO0A4_PWM1_NAME,0);\r
 612                         break;  \r
 613                 }\r
 614         case RK30_PIN0_PA5:\r
 615                 {\r
 616                          rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0);\r
 617                         break;  \r
 618                 }\r
 619         case RK30_PIN0_PA6:\r
 620         {\r
 621              rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0);\r
 622             break;      \r
 623         }\r
 624         case RK30_PIN0_PA7:\r
 625         {\r
 626              rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0);\r
 627             break;      \r
 628         }\r
 629         case RK30_PIN0_PB0:\r
 630         {\r
 631              rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0);\r
 632             break;      \r
 633         }\r
 634         case RK30_PIN0_PB1:\r
 635         {\r
 636              rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0);\r
 637             break;      \r
 638         }\r
 639         case RK30_PIN0_PB2:\r
 640         {\r
 641              rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0);\r
 642             break;      \r
 643         }\r
 644         case RK30_PIN0_PB3:\r
 645         {\r
 646              rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0);\r
 647             break;      \r
 648         }\r
 649         case RK30_PIN0_PB4:\r
 650         {\r
 651              rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0);\r
 652             break;      \r
 653         }\r
 654         case RK30_PIN0_PB5:\r
 655         {\r
 656              rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0);\r
 657             break;      \r
 658         }\r
 659         case RK30_PIN0_PB6:\r
 660         {\r
 661              rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0);\r
 662             break;      \r
 663         }\r
 664         case RK30_PIN0_PB7:\r
 665         {\r
 666              rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0);\r
 667             break;      \r
 668         }\r
 669         case RK30_PIN0_PC0:\r
 670         {\r
 671              rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0);\r
 672             break;      \r
 673         }\r
 674         case RK30_PIN0_PC1:\r
 675         {\r
 676              rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0);\r
 677             break;      \r
 678         }\r
 679         case RK30_PIN0_PC2:\r
 680         {\r
 681              rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0);\r
 682             break;      \r
 683         }\r
 684         case RK30_PIN0_PC3:\r
 685         {\r
 686              rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0);\r
 687             break;      \r
 688         }\r
 689         case RK30_PIN0_PC4:\r
 690         {\r
 691              rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0);\r
 692             break;      \r
 693         }\r
 694         case RK30_PIN0_PC5:\r
 695         {\r
 696              rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0);\r
 697             break;      \r
 698         }\r
 699         case RK30_PIN0_PC6:\r
 700         {\r
 701              rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0);\r
 702             break;      \r
 703         }\r
 704         case RK30_PIN0_PC7:\r
 705         {\r
 706              rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0);\r
 707             break;      \r
 708         }\r
 709         case RK30_PIN0_PD0:\r
 710         {\r
 711              rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0);\r
 712             break;      \r
 713         }\r
 714         case RK30_PIN0_PD1:\r
 715         {\r
 716              rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0);\r
 717             break;      \r
 718         }\r
 719         case RK30_PIN0_PD2:\r
 720         {\r
 721              rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0);\r
 722             break;      \r
 723         }\r
 724         case RK30_PIN0_PD3:\r
 725         {\r
 726              rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0);\r
 727             break;      \r
 728         }\r
 729         case RK30_PIN0_PD4:\r
 730         {\r
 731              rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0);\r
 732             break;      \r
 733         }\r
 734         case RK30_PIN0_PD5:\r
 735         {\r
 736              rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0);\r
 737             break;      \r
 738         }\r
 739         case RK30_PIN0_PD6:\r
 740         {\r
 741              rk30_mux_api_set(GPIO0D6_PWM2_NAME,0);\r
 742             break;      \r
 743         }\r
 744         case RK30_PIN0_PD7:\r
 745         {\r
 746              rk30_mux_api_set(GPIO0D7_PWM3_NAME,0);\r
 747             break;      \r
 748         }\r
 749         case RK30_PIN1_PA0:\r
 750         {\r
 751              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 752             break;      \r
 753         }\r
 754         case RK30_PIN1_PA1:\r
 755         {\r
 756              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 757             break;      \r
 758         }\r
 759         case RK30_PIN1_PA2:\r
 760         {\r
 761              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 762             break;      \r
 763         }\r
 764         case RK30_PIN1_PA3:\r
 765         {\r
 766              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 767             break;      \r
 768         }\r
 769         case RK30_PIN1_PA4:\r
 770         {\r
 771              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0);\r
 772             break;      \r
 773         }\r
 774         case RK30_PIN1_PA5:\r
 775         {\r
 776              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0);\r
 777             break;      \r
 778         }\r
 779         case RK30_PIN1_PA6:\r
 780         {\r
 781              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0);\r
 782             break;      \r
 783         }\r
 784         case RK30_PIN1_PA7:\r
 785         {\r
 786              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0);\r
 787             break;      \r
 788         }\r
 789         case RK30_PIN1_PB0:\r
 790         {\r
 791              rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0);\r
 792             break;      \r
 793         }\r
 794         case RK30_PIN1_PB1:\r
 795         {\r
 796              rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0);\r
 797             break;      \r
 798         }\r
 799         case RK30_PIN1_PB2:\r
 800         {\r
 801              rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0);\r
 802             break;      \r
 803         }\r
 804         case RK30_PIN1_PB3:\r
 805         {\r
 806              rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0);\r
 807             break;      \r
 808         }\r
 809         case RK30_PIN1_PB4:\r
 810         {\r
 811              rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0);\r
 812             break;      \r
 813         }\r
 814         case RK30_PIN1_PB5:\r
 815         {\r
 816              rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0);\r
 817             break;      \r
 818         }\r
 819         case RK30_PIN1_PB6:\r
 820         {\r
 821              rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0);\r
 822             break;      \r
 823         }\r
 824         case RK30_PIN1_PB7:\r
 825         {\r
 826              rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0);\r
 827             break;      \r
 828         }\r
 829         case RK30_PIN1_PC0:\r
 830         {\r
 831              rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0);\r
 832             break;      \r
 833         }\r
 834         case RK30_PIN1_PC1:\r
 835         {\r
 836              rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0);\r
 837             break;      \r
 838         }\r
 839         case RK30_PIN1_PC2:\r
 840         {\r
 841              rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0);\r
 842             break;      \r
 843         }\r
 844         case RK30_PIN1_PC3:\r
 845         {\r
 846              rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0);\r
 847             break;      \r
 848         }\r
 849         case RK30_PIN1_PC4:\r
 850         {\r
 851              rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0);\r
 852             break;      \r
 853         }\r
 854         case RK30_PIN1_PC5:\r
 855         {\r
 856              rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0);\r
 857             break;      \r
 858         }\r
 859         case RK30_PIN1_PC6:\r
 860         {\r
 861              rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0);\r
 862             break;      \r
 863         }\r
 864         case RK30_PIN1_PC7:\r
 865         {\r
 866              rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0);\r
 867             break;      \r
 868         }\r
 869         case RK30_PIN1_PD0:\r
 870         {\r
 871              rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0);\r
 872             break;      \r
 873         }\r
 874         case RK30_PIN1_PD1:\r
 875         {\r
 876              rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0);\r
 877             break;      \r
 878         }\r
 879         case RK30_PIN1_PD2:\r
 880         {\r
 881              rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0);\r
 882             break;      \r
 883         }\r
 884         case RK30_PIN1_PD3:\r
 885         {\r
 886              rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0);\r
 887             break;      \r
 888         }\r
 889         case RK30_PIN1_PD4:\r
 890         {\r
 891              rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0);\r
 892             break;      \r
 893         }\r
 894         case RK30_PIN1_PD5:\r
 895         {\r
 896              rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0);\r
 897             break;      \r
 898         }\r
 899         case RK30_PIN1_PD6:\r
 900         {\r
 901              rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0);\r
 902             break;      \r
 903         }\r
 904         case RK30_PIN1_PD7:\r
 905         {\r
 906              rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0);\r
 907             break;      \r
 908         }\r
 909         case RK30_PIN2_PA0:\r
 910         {\r
 911              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0);\r
 912             break;      \r
 913         }\r
 914         case RK30_PIN2_PA1:\r
 915         {\r
 916              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0);\r
 917             break;      \r
 918         }\r
 919         case RK30_PIN2_PA2:\r
 920         {\r
 921              rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0);\r
 922             break;      \r
 923         }\r
 924         case RK30_PIN2_PA3:\r
 925         {\r
 926              rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0);\r
 927             break;      \r
 928         }\r
 929         case RK30_PIN2_PA4:\r
 930         {\r
 931              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0);\r
 932             break;      \r
 933         }\r
 934         case RK30_PIN2_PA5:\r
 935         {\r
 936              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0);\r
 937             break;      \r
 938         }\r
 939         case RK30_PIN2_PA6:\r
 940         {\r
 941              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0);\r
 942             break;      \r
 943         }\r
 944         case RK30_PIN2_PA7:\r
 945         {\r
 946              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0);\r
 947             break;      \r
 948         }\r
 949         case RK30_PIN2_PB0:\r
 950         {\r
 951              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0);\r
 952             break;      \r
 953         }\r
 954         case RK30_PIN2_PB1:\r
 955         {\r
 956              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0);\r
 957             break;      \r
 958         }\r
 959         case RK30_PIN2_PB2:\r
 960         {\r
 961              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0);\r
 962             break;      \r
 963         }\r
 964         case RK30_PIN2_PB3:\r
 965         {\r
 966              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0);\r
 967             break;      \r
 968         }\r
 969         case RK30_PIN2_PB4:\r
 970         {\r
 971              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0);\r
 972             break;      \r
 973         }\r
 974         case RK30_PIN2_PB5:\r
 975         {\r
 976              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0);\r
 977             break;      \r
 978         }\r
 979         case RK30_PIN2_PB6:\r
 980         {\r
 981              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0);\r
 982             break;      \r
 983         }\r
 984         case RK30_PIN2_PB7:\r
 985         {\r
 986              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0);\r
 987             break;      \r
 988         }\r
 989         case RK30_PIN2_PC0:\r
 990         {\r
 991              rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0);\r
 992             break;      \r
 993         }\r
 994         case RK30_PIN2_PC1:\r
 995         {\r
 996              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0);\r
 997             break;      \r
 998         }\r
 999         case RK30_PIN2_PC2:\r
1000         {\r
1001              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0);\r
1002             break;      \r
1003         }\r
1004         case RK30_PIN2_PC3:\r
1005         {\r
1006              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0);\r
1007             break;      \r
1008         }\r
1009         case RK30_PIN2_PC4:\r
1010         {\r
1011              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0);\r
1012             break;      \r
1013         }\r
1014         case RK30_PIN2_PC5:\r
1015         {\r
1016              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0);\r
1017             break;      \r
1018         }\r
1019         case RK30_PIN2_PC6:\r
1020         {\r
1021              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0);\r
1022             break;      \r
1023         }\r
1024         case RK30_PIN2_PC7:\r
1025         {\r
1026              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0);\r
1027             break;      \r
1028         }\r
1029         case RK30_PIN2_PD0:\r
1030         {\r
1031              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0);\r
1032             break;      \r
1033         }\r
1034         case RK30_PIN2_PD1:\r
1035         {\r
1036              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0);\r
1037             break;      \r
1038         }\r
1039         case RK30_PIN2_PD2:\r
1040         {\r
1041              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0);\r
1042             break;      \r
1043         }\r
1044         case RK30_PIN2_PD3:\r
1045         {\r
1046              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0);\r
1047             break;      \r
1048         }\r
1049         case RK30_PIN2_PD4:\r
1050         {\r
1051              rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0);\r
1052             break;      \r
1053         }\r
1054         case RK30_PIN2_PD5:\r
1055         {\r
1056              rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0);\r
1057             break;      \r
1058         }\r
1059         case RK30_PIN2_PD6:\r
1060         {\r
1061              rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0);\r
1062             break;      \r
1063         }\r
1064         case RK30_PIN2_PD7:\r
1065         {\r
1066              rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0);\r
1067             break;      \r
1068         }\r
1069         case RK30_PIN3_PA0:\r
1070         {\r
1071              rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0);\r
1072             break;      \r
1073         }\r
1074         case RK30_PIN3_PA1:\r
1075         {\r
1076              rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0);\r
1077             break;      \r
1078         }\r
1079         case RK30_PIN3_PA2:\r
1080         {\r
1081              rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0);\r
1082             break;      \r
1083         }\r
1084         case RK30_PIN3_PA3:\r
1085         {\r
1086              rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0);\r
1087             break;      \r
1088         }\r
1089         case RK30_PIN3_PA4:\r
1090         {\r
1091              rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0);\r
1092             break;      \r
1093         }\r
1094         case RK30_PIN3_PA5:\r
1095         {\r
1096              rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0);\r
1097             break;      \r
1098         }\r
1099         case RK30_PIN3_PA6:\r
1100         {\r
1101              rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0);\r
1102             break;      \r
1103         }\r
1104         case RK30_PIN3_PA7:\r
1105         {\r
1106              rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0);\r
1107             break;      \r
1108         }\r
1109         case RK30_PIN3_PB0:\r
1110         {\r
1111              rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0);\r
1112             break;      \r
1113         }\r
1114         case RK30_PIN3_PB1:\r
1115         {\r
1116              rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0);\r
1117             break;      \r
1118         }\r
1119         case RK30_PIN3_PB2:\r
1120         {\r
1121              rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0);\r
1122             break;      \r
1123         }\r
1124         case RK30_PIN3_PB3:\r
1125         {\r
1126              rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0);\r
1127             break;      \r
1128         }\r
1129         case RK30_PIN3_PB4:\r
1130         {\r
1131              rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0);\r
1132             break;      \r
1133         }\r
1134         case RK30_PIN3_PB5:\r
1135         {\r
1136              rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0);\r
1137             break;      \r
1138         }\r
1139         case RK30_PIN3_PB6:\r
1140         {\r
1141              rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0);\r
1142             break;      \r
1143         }\r
1144         case RK30_PIN3_PB7:\r
1145         {\r
1146              rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0);\r
1147             break;      \r
1148         }\r
1149         case RK30_PIN3_PC0:\r
1150         {\r
1151              rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0);\r
1152             break;      \r
1153         }\r
1154         case RK30_PIN3_PC1:\r
1155         {\r
1156              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0);\r
1157             break;      \r
1158         }\r
1159         case RK30_PIN3_PC2:\r
1160         {\r
1161              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0);\r
1162             break;      \r
1163         }\r
1164         case RK30_PIN3_PC3:\r
1165         {\r
1166              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0);\r
1167             break;      \r
1168         }\r
1169         case RK30_PIN3_PC4:\r
1170         {\r
1171              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0);\r
1172             break;      \r
1173         }\r
1174         case RK30_PIN3_PC5:\r
1175         {\r
1176              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0);\r
1177             break;      \r
1178         }\r
1179         case RK30_PIN3_PC6:\r
1180         {\r
1181              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0);\r
1182             break;      \r
1183         }\r
1184         case RK30_PIN3_PC7:\r
1185         {\r
1186              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0);\r
1187             break;      \r
1188         }\r
1189         case RK30_PIN3_PD0:\r
1190         {\r
1191              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0);\r
1192             break;      \r
1193         }\r
1194         case RK30_PIN3_PD1:\r
1195         {\r
1196              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0);\r
1197             break;      \r
1198         }\r
1199         case RK30_PIN3_PD2:\r
1200         {\r
1201              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
1202             break;      \r
1203         }\r
1204         case RK30_PIN3_PD3:\r
1205         {\r
1206              rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0);\r
1207             break;      \r
1208         }\r
1209         case RK30_PIN3_PD4:\r
1210         {\r
1211              rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0);\r
1212             break;      \r
1213         }\r
1214         case RK30_PIN3_PD5:\r
1215         {\r
1216              rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0);\r
1217             break;      \r
1218         }\r
1219         case RK30_PIN3_PD6:\r
1220         {\r
1221              rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0);\r
1222             break;      \r
1223         }\r
1224         case RK30_PIN3_PD7:\r
1225         {\r
1226              rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0);\r
1227             break;      \r
1228         }\r
1229         case RK30_PIN4_PA0:\r
1230         {\r
1231                  rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0);\r
1232                 break;  \r
1233         }\r
1234         case RK30_PIN4_PA1:\r
1235         {\r
1236                  rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0);\r
1237                 break;  \r
1238         }\r
1239         case RK30_PIN4_PA2:\r
1240         {\r
1241                  rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0);\r
1242                 break;  \r
1243         }\r
1244                         \r
1245         case RK30_PIN4_PA3:\r
1246         {\r
1247                  rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0);\r
1248                 break;  \r
1249         }\r
1250         case RK30_PIN4_PA4:\r
1251         {\r
1252                  rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0);\r
1253                 break;  \r
1254         }\r
1255         case RK30_PIN4_PA5:\r
1256         {\r
1257              rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0);\r
1258             break;      \r
1259         }\r
1260         case RK30_PIN4_PA6:\r
1261         {\r
1262              rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0);\r
1263             break;      \r
1264         }\r
1265         case RK30_PIN4_PA7:\r
1266         {\r
1267              rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0);\r
1268             break;      \r
1269         }\r
1270         case RK30_PIN4_PB0:\r
1271         {\r
1272              rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0);\r
1273             break;      \r
1274         }\r
1275         case RK30_PIN4_PB1:\r
1276         {\r
1277              rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0);\r
1278             break;      \r
1279         }\r
1280         case RK30_PIN4_PB2:\r
1281         {\r
1282              rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
1283             break;      \r
1284         }\r
1285         case RK30_PIN4_PB3:\r
1286         {\r
1287              rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0);\r
1288             break;      \r
1289         }\r
1290         case RK30_PIN4_PB4:\r
1291         {\r
1292              rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0);\r
1293             break;      \r
1294         }\r
1295         case RK30_PIN4_PB5:\r
1296         {\r
1297              rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0);\r
1298             break;      \r
1299         }\r
1300         case RK30_PIN4_PB6:\r
1301         {\r
1302              rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0);\r
1303             break;      \r
1304         }\r
1305         case RK30_PIN4_PB7:\r
1306         {\r
1307              rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0);\r
1308             break;      \r
1309         }\r
1310         case RK30_PIN4_PC0:\r
1311         {\r
1312              rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0);\r
1313             break;      \r
1314         }\r
1315         case RK30_PIN4_PC1:\r
1316         {\r
1317              rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0);\r
1318             break;      \r
1319         }\r
1320         case RK30_PIN4_PC2:\r
1321         {\r
1322              rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0);\r
1323             break;      \r
1324         }\r
1325         case RK30_PIN4_PC3:\r
1326         {\r
1327              rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0);\r
1328             break;      \r
1329         }\r
1330         case RK30_PIN4_PC4:\r
1331         {\r
1332              rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0);\r
1333             break;      \r
1334         }\r
1335         case RK30_PIN4_PC5:\r
1336         {\r
1337              rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0);\r
1338             break;      \r
1339         }\r
1340         case RK30_PIN4_PC6:\r
1341         {\r
1342              rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0);\r
1343             break;      \r
1344         }\r
1345 \r
1346 \r
1347         case RK30_PIN4_PC7:\r
1348         {\r
1349              rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0);\r
1350             break;      \r
1351         }\r
1352         case RK30_PIN4_PD0:\r
1353             {\r
1354                      rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0);                         \r
1355                      break;     \r
1356             }\r
1357         case RK30_PIN4_PD1:\r
1358         {\r
1359              rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0);             \r
1360              break;     \r
1361         }\r
1362         case RK30_PIN4_PD2:\r
1363             {\r
1364                      rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0);                                \r
1365                      break;     \r
1366             }\r
1367         case RK30_PIN4_PD3:\r
1368         {\r
1369              rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0);           \r
1370              break;     \r
1371         }\r
1372         case RK30_PIN4_PD4:\r
1373         {\r
1374              rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0);\r
1375             break;      \r
1376         }\r
1377         case RK30_PIN4_PD5:\r
1378         {\r
1379              rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0);\r
1380             break;      \r
1381         }\r
1382         case RK30_PIN4_PD6:\r
1383         {\r
1384              rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0);\r
1385             break;      \r
1386         }\r
1387         case RK30_PIN4_PD7:\r
1388         {\r
1389              rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0);\r
1390             break;      \r
1391         } \r
1392         case RK30_PIN6_PA0:\r
1393         case RK30_PIN6_PA1:\r
1394         case RK30_PIN6_PA2:\r
1395         case RK30_PIN6_PA3:\r
1396         case RK30_PIN6_PA4:\r
1397         case RK30_PIN6_PA5:\r
1398         case RK30_PIN6_PA6:\r
1399         case RK30_PIN6_PA7:\r
1400         case RK30_PIN6_PB0:\r
1401         case RK30_PIN6_PB1:\r
1402         case RK30_PIN6_PB2:\r
1403         case RK30_PIN6_PB3:\r
1404         case RK30_PIN6_PB4:\r
1405         case RK30_PIN6_PB5:\r
1406         case RK30_PIN6_PB6:\r
1407                         break;\r
1408         case RK30_PIN6_PB7:\r
1409                 {\r
1410                          rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0);\r
1411                         break;  \r
1412                 } \r
1413         default:\r
1414         {\r
1415             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
1416             break;\r
1417         }\r
1418     }\r
1419 #endif\r
1420     return 0;\r
1421 }\r
1422 #define PMEM_CAM_BASE 0 //just for compile ,no meaning\r
1423 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
1424 \r
1425 \r
1426 \r
1427 static u64 rockchip_device_camera_dmamask = 0xffffffffUL;\r
1428 #if RK_SUPPORT_CIF0\r
1429 static struct resource rk_camera_resource_host_0[] = {\r
1430         [0] = {\r
1431                 .start = RK30_CIF0_PHYS,\r
1432                 .end   = RK30_CIF0_PHYS + RK30_CIF0_SIZE - 1,\r
1433                 .flags = IORESOURCE_MEM,\r
1434         },\r
1435         [1] = {\r
1436                 .start = IRQ_CIF0,\r
1437                 .end   = IRQ_CIF0,\r
1438                 .flags = IORESOURCE_IRQ,\r
1439         }\r
1440 };\r
1441 #endif\r
1442 #if RK_SUPPORT_CIF1\r
1443 static struct resource rk_camera_resource_host_1[] = {\r
1444         [0] = {\r
1445                 .start = RK30_CIF1_PHYS,\r
1446                 .end   = RK30_CIF1_PHYS + RK30_CIF1_SIZE - 1,\r
1447                 .flags = IORESOURCE_MEM,\r
1448         },\r
1449         [1] = {\r
1450                 .start = IRQ_CIF1,\r
1451                 .end   = IRQ_CIF1,\r
1452                 .flags = IORESOURCE_IRQ,\r
1453         }\r
1454 };\r
1455 #endif\r
1456 \r
1457 /*platform_device : */\r
1458 #if RK_SUPPORT_CIF0\r
1459  struct platform_device rk_device_camera_host_0 = {\r
1460         .name             = RK29_CAM_DRV_NAME,\r
1461         .id       = RK_CAM_PLATFORM_DEV_ID_0,                           /* This is used to put cameras on this interface */\r
1462         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_0),\r
1463         .resource         = rk_camera_resource_host_0,\r
1464         .dev                    = {\r
1465                 .dma_mask = &rockchip_device_camera_dmamask,\r
1466                 .coherent_dma_mask = 0xffffffffUL,\r
1467                 .platform_data  = &rk_camera_platform_data,\r
1468         }\r
1469 };\r
1470 #endif\r
1471 \r
1472 #if RK_SUPPORT_CIF1\r
1473 /*platform_device : */\r
1474  struct platform_device rk_device_camera_host_1 = {\r
1475         .name             = RK29_CAM_DRV_NAME,\r
1476         .id       = RK_CAM_PLATFORM_DEV_ID_1,                           /* This is used to put cameras on this interface */\r
1477         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_1),\r
1478         .resource         = rk_camera_resource_host_1,\r
1479         .dev                    = {\r
1480                 .dma_mask = &rockchip_device_camera_dmamask,\r
1481                 .coherent_dma_mask = 0xffffffffUL,\r
1482                 .platform_data  = &rk_camera_platform_data,\r
1483         }\r
1484 };\r
1485 #endif\r
1486 \r
1487 static void rk_init_camera_plateform_data(void)\r
1488 {\r
1489     int i,dev_idx;\r
1490     \r
1491     dev_idx = 0;\r
1492     for (i=0; i<RK_CAM_NUM; i++) {\r
1493         rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];\r
1494         if (rk_camera_platform_data.register_dev[i].device_info.name) {            \r
1495             rk_camera_platform_data.register_dev[i].link_info.board_info = \r
1496                 &rk_camera_platform_data.register_dev[i].i2c_cam_info;\r
1497             rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;\r
1498             rk_camera_platform_data.register_dev[i].device_info.dev.platform_data = \r
1499                 &rk_camera_platform_data.register_dev[i].link_info;\r
1500             dev_idx++;\r
1501         }\r
1502     }\r
1503 }\r
1504 \r
1505 static void rk30_camera_request_reserve_mem(void)\r
1506 {\r
1507 #ifdef CONFIG_VIDEO_RK29_WORK_IPP\r
1508         rk_camera_platform_data.meminfo.vbase = rk_camera_platform_data.meminfo_cif1.vbase = NULL;\r
1509     #if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == false)\r
1510         rk_camera_platform_data.meminfo.name = "camera_ipp_mem";\r
1511         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",PMEM_CAMIPP_NECESSARY);\r
1512         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY;\r
1513 \r
1514         memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));\r
1515     #else\r
1516         rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";\r
1517         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);\r
1518         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;\r
1519         \r
1520         rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";\r
1521         rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);\r
1522         rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;\r
1523     #endif\r
1524  #endif\r
1525  #if PMEM_CAM_NECESSARY\r
1526         android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),PMEM_CAM_NECESSARY);\r
1527         android_pmem_cam_pdata.size= PMEM_CAM_NECESSARY;\r
1528  #endif\r
1529 \r
1530 }\r
1531 static int rk_register_camera_devices(void)\r
1532 {\r
1533     int i;\r
1534     int host_registered_0,host_registered_1;\r
1535     \r
1536         rk_init_camera_plateform_data();\r
1537 \r
1538     host_registered_0 = 0;\r
1539     host_registered_1 = 0;\r
1540     for (i=0; i<RK_CAM_NUM; i++) {\r
1541         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1542             \r
1543             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {\r
1544             #if RK_SUPPORT_CIF0\r
1545                 if (!host_registered_0) {\r
1546                     platform_device_register(&rk_device_camera_host_0);\r
1547                     host_registered_0 = 1;\r
1548                 }\r
1549             #else\r
1550                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);\r
1551             #endif\r
1552             } \r
1553 \r
1554             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {\r
1555             #if RK_SUPPORT_CIF1\r
1556                 if (!host_registered_1) {\r
1557                     platform_device_register(&rk_device_camera_host_1);\r
1558                     host_registered_1 = 1;\r
1559                 }\r
1560             #else\r
1561                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);\r
1562             #endif\r
1563             } \r
1564         }\r
1565     }\r
1566 \r
1567     for (i=0; i<RK_CAM_NUM; i++) {\r
1568         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1569             platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);\r
1570         }\r
1571     }\r
1572  #if PMEM_CAM_NECESSARY\r
1573     platform_device_register(&android_pmem_cam_device);\r
1574  #endif\r
1575         return 0;\r
1576 }\r
1577 \r
1578 module_init(rk_register_camera_devices);\r
1579 #endif\r
1580 \r
1581 #endif //#ifdef CONFIG_VIDEO_RK\r