drivers/media/video/rk30_camera.c

   1 \r
   2 #include <mach/iomux.h>\r
   3 #include <media/soc_camera.h>\r
   4 #include <linux/android_pmem.h>\r
   5 #include <mach/rk30_camera.h>\r
   6 #ifndef PMEM_CAM_SIZE\r
   7 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
   8 #else\r
   9 /*****************************************************************************************\r
  10  * camera  devices\r
  11  * author: ddl@rock-chips.com\r
  12  *****************************************************************************************/\r
  13 #ifdef CONFIG_VIDEO_RK29 \r
  14 \r
  15 static int rk_sensor_iomux(int pin)\r
  16 {    \r
  17     switch (pin)\r
  18     {\r
  19         case RK30_PIN0_PA0: \r
  20                 {\r
  21                          rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0);\r
  22                         break;  \r
  23                 }\r
  24         case RK30_PIN0_PA1: \r
  25                 {\r
  26                          rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0);\r
  27                         break;  \r
  28                 }\r
  29         case RK30_PIN0_PA2:\r
  30                 {\r
  31                          rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0);\r
  32                         break;  \r
  33                 }\r
  34         case RK30_PIN0_PA3:\r
  35                 {\r
  36                          rk30_mux_api_set(GPIO0A3_PWM0_NAME,0);\r
  37                         break;  \r
  38                 }\r
  39         case RK30_PIN0_PA4:\r
  40                 {\r
  41                          rk30_mux_api_set(GPIO0A4_PWM1_NAME,0);\r
  42                         break;  \r
  43                 }\r
  44         case RK30_PIN0_PA5:\r
  45                 {\r
  46                          rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0);\r
  47                         break;  \r
  48                 }\r
  49         case RK30_PIN0_PA6:\r
  50         {\r
  51              rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0);\r
  52             break;      \r
  53         }\r
  54         case RK30_PIN0_PA7:\r
  55         {\r
  56              rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0);\r
  57             break;      \r
  58         }\r
  59         case RK30_PIN0_PB0:\r
  60         {\r
  61              rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0);\r
  62             break;      \r
  63         }\r
  64         case RK30_PIN0_PB1:\r
  65         {\r
  66              rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0);\r
  67             break;      \r
  68         }\r
  69         case RK30_PIN0_PB2:\r
  70         {\r
  71              rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0);\r
  72             break;      \r
  73         }\r
  74         case RK30_PIN0_PB3:\r
  75         {\r
  76              rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0);\r
  77             break;      \r
  78         }\r
  79         case RK30_PIN0_PB4:\r
  80         {\r
  81              rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0);\r
  82             break;      \r
  83         }\r
  84         case RK30_PIN0_PB5:\r
  85         {\r
  86              rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0);\r
  87             break;      \r
  88         }\r
  89         case RK30_PIN0_PB6:\r
  90         {\r
  91              rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0);\r
  92             break;      \r
  93         }\r
  94         case RK30_PIN0_PB7:\r
  95         {\r
  96              rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0);\r
  97             break;      \r
  98         }\r
  99         case RK30_PIN0_PC0:\r
 100         {\r
 101              rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0);\r
 102             break;      \r
 103         }\r
 104         case RK30_PIN0_PC1:\r
 105         {\r
 106              rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0);\r
 107             break;      \r
 108         }\r
 109         case RK30_PIN0_PC2:\r
 110         {\r
 111              rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0);\r
 112             break;      \r
 113         }\r
 114         case RK30_PIN0_PC3:\r
 115         {\r
 116              rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0);\r
 117             break;      \r
 118         }\r
 119         case RK30_PIN0_PC4:\r
 120         {\r
 121              rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0);\r
 122             break;      \r
 123         }\r
 124         case RK30_PIN0_PC5:\r
 125         {\r
 126              rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0);\r
 127             break;      \r
 128         }\r
 129         case RK30_PIN0_PC6:\r
 130         {\r
 131              rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0);\r
 132             break;      \r
 133         }\r
 134         case RK30_PIN0_PC7:\r
 135         {\r
 136              rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0);\r
 137             break;      \r
 138         }\r
 139         case RK30_PIN0_PD0:\r
 140         {\r
 141              rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0);\r
 142             break;      \r
 143         }\r
 144         case RK30_PIN0_PD1:\r
 145         {\r
 146              rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0);\r
 147             break;      \r
 148         }\r
 149         case RK30_PIN0_PD2:\r
 150         {\r
 151              rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0);\r
 152             break;      \r
 153         }\r
 154         case RK30_PIN0_PD3:\r
 155         {\r
 156              rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0);\r
 157             break;      \r
 158         }\r
 159         case RK30_PIN0_PD4:\r
 160         {\r
 161              rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0);\r
 162             break;      \r
 163         }\r
 164         case RK30_PIN0_PD5:\r
 165         {\r
 166              rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0);\r
 167             break;      \r
 168         }\r
 169         case RK30_PIN0_PD6:\r
 170         {\r
 171              rk30_mux_api_set(GPIO0D6_PWM2_NAME,0);\r
 172             break;      \r
 173         }\r
 174         case RK30_PIN0_PD7:\r
 175         {\r
 176              rk30_mux_api_set(GPIO0D7_PWM3_NAME,0);\r
 177             break;      \r
 178         }\r
 179         case RK30_PIN1_PA0:\r
 180         {\r
 181              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 182             break;      \r
 183         }\r
 184         case RK30_PIN1_PA1:\r
 185         {\r
 186              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 187             break;      \r
 188         }\r
 189         case RK30_PIN1_PA2:\r
 190         {\r
 191              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 192             break;      \r
 193         }\r
 194         case RK30_PIN1_PA3:\r
 195         {\r
 196              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 197             break;      \r
 198         }\r
 199         case RK30_PIN1_PA4:\r
 200         {\r
 201              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0);\r
 202             break;      \r
 203         }\r
 204         case RK30_PIN1_PA5:\r
 205         {\r
 206              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0);\r
 207             break;      \r
 208         }\r
 209         case RK30_PIN1_PA6:\r
 210         {\r
 211              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0);\r
 212             break;      \r
 213         }\r
 214         case RK30_PIN1_PA7:\r
 215         {\r
 216              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0);\r
 217             break;      \r
 218         }\r
 219         case RK30_PIN1_PB0:\r
 220         {\r
 221              rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0);\r
 222             break;      \r
 223         }\r
 224         case RK30_PIN1_PB1:\r
 225         {\r
 226              rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0);\r
 227             break;      \r
 228         }\r
 229         case RK30_PIN1_PB2:\r
 230         {\r
 231              rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0);\r
 232             break;      \r
 233         }\r
 234         case RK30_PIN1_PB3:\r
 235         {\r
 236              rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0);\r
 237             break;      \r
 238         }\r
 239         case RK30_PIN1_PB4:\r
 240         {\r
 241              rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0);\r
 242             break;      \r
 243         }\r
 244         case RK30_PIN1_PB5:\r
 245         {\r
 246              rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0);\r
 247             break;      \r
 248         }\r
 249         case RK30_PIN1_PB6:\r
 250         {\r
 251              rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0);\r
 252             break;      \r
 253         }\r
 254         case RK30_PIN1_PB7:\r
 255         {\r
 256              rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0);\r
 257             break;      \r
 258         }\r
 259         case RK30_PIN1_PC0:\r
 260         {\r
 261              rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0);\r
 262             break;      \r
 263         }\r
 264         case RK30_PIN1_PC1:\r
 265         {\r
 266              rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0);\r
 267             break;      \r
 268         }\r
 269         case RK30_PIN1_PC2:\r
 270         {\r
 271              rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0);\r
 272             break;      \r
 273         }\r
 274         case RK30_PIN1_PC3:\r
 275         {\r
 276              rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0);\r
 277             break;      \r
 278         }\r
 279         case RK30_PIN1_PC4:\r
 280         {\r
 281              rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0);\r
 282             break;      \r
 283         }\r
 284         case RK30_PIN1_PC5:\r
 285         {\r
 286              rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0);\r
 287             break;      \r
 288         }\r
 289         case RK30_PIN1_PC6:\r
 290         {\r
 291              rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0);\r
 292             break;      \r
 293         }\r
 294         case RK30_PIN1_PC7:\r
 295         {\r
 296              rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0);\r
 297             break;      \r
 298         }\r
 299         case RK30_PIN1_PD0:\r
 300         {\r
 301              rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0);\r
 302             break;      \r
 303         }\r
 304         case RK30_PIN1_PD1:\r
 305         {\r
 306              rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0);\r
 307             break;      \r
 308         }\r
 309         case RK30_PIN1_PD2:\r
 310         {\r
 311              rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0);\r
 312             break;      \r
 313         }\r
 314         case RK30_PIN1_PD3:\r
 315         {\r
 316              rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0);\r
 317             break;      \r
 318         }\r
 319         case RK30_PIN1_PD4:\r
 320         {\r
 321              rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0);\r
 322             break;      \r
 323         }\r
 324         case RK30_PIN1_PD5:\r
 325         {\r
 326              rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0);\r
 327             break;      \r
 328         }\r
 329         case RK30_PIN1_PD6:\r
 330         {\r
 331              rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0);\r
 332             break;      \r
 333         }\r
 334         case RK30_PIN1_PD7:\r
 335         {\r
 336              rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0);\r
 337             break;      \r
 338         }\r
 339         case RK30_PIN2_PA0:\r
 340         {\r
 341              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0);\r
 342             break;      \r
 343         }\r
 344         case RK30_PIN2_PA1:\r
 345         {\r
 346              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0);\r
 347             break;      \r
 348         }\r
 349         case RK30_PIN2_PA2:\r
 350         {\r
 351              rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0);\r
 352             break;      \r
 353         }\r
 354         case RK30_PIN2_PA3:\r
 355         {\r
 356              rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0);\r
 357             break;      \r
 358         }\r
 359         case RK30_PIN2_PA4:\r
 360         {\r
 361              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0);\r
 362             break;      \r
 363         }\r
 364         case RK30_PIN2_PA5:\r
 365         {\r
 366              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0);\r
 367             break;      \r
 368         }\r
 369         case RK30_PIN2_PA6:\r
 370         {\r
 371              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0);\r
 372             break;      \r
 373         }\r
 374         case RK30_PIN2_PA7:\r
 375         {\r
 376              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0);\r
 377             break;      \r
 378         }\r
 379         case RK30_PIN2_PB0:\r
 380         {\r
 381              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0);\r
 382             break;      \r
 383         }\r
 384         case RK30_PIN2_PB1:\r
 385         {\r
 386              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0);\r
 387             break;      \r
 388         }\r
 389         case RK30_PIN2_PB2:\r
 390         {\r
 391              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0);\r
 392             break;      \r
 393         }\r
 394         case RK30_PIN2_PB3:\r
 395         {\r
 396              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0);\r
 397             break;      \r
 398         }\r
 399         case RK30_PIN2_PB4:\r
 400         {\r
 401              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0);\r
 402             break;      \r
 403         }\r
 404         case RK30_PIN2_PB5:\r
 405         {\r
 406              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0);\r
 407             break;      \r
 408         }\r
 409         case RK30_PIN2_PB6:\r
 410         {\r
 411              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0);\r
 412             break;      \r
 413         }\r
 414         case RK30_PIN2_PB7:\r
 415         {\r
 416              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0);\r
 417             break;      \r
 418         }\r
 419         case RK30_PIN2_PC0:\r
 420         {\r
 421              rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0);\r
 422             break;      \r
 423         }\r
 424         case RK30_PIN2_PC1:\r
 425         {\r
 426              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0);\r
 427             break;      \r
 428         }\r
 429         case RK30_PIN2_PC2:\r
 430         {\r
 431              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0);\r
 432             break;      \r
 433         }\r
 434         case RK30_PIN2_PC3:\r
 435         {\r
 436              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0);\r
 437             break;      \r
 438         }\r
 439         case RK30_PIN2_PC4:\r
 440         {\r
 441              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0);\r
 442             break;      \r
 443         }\r
 444         case RK30_PIN2_PC5:\r
 445         {\r
 446              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0);\r
 447             break;      \r
 448         }\r
 449         case RK30_PIN2_PC6:\r
 450         {\r
 451              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0);\r
 452             break;      \r
 453         }\r
 454         case RK30_PIN2_PC7:\r
 455         {\r
 456              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0);\r
 457             break;      \r
 458         }\r
 459         case RK30_PIN2_PD0:\r
 460         {\r
 461              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0);\r
 462             break;      \r
 463         }\r
 464         case RK30_PIN2_PD1:\r
 465         {\r
 466              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0);\r
 467             break;      \r
 468         }\r
 469         case RK30_PIN2_PD2:\r
 470         {\r
 471              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0);\r
 472             break;      \r
 473         }\r
 474         case RK30_PIN2_PD3:\r
 475         {\r
 476              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0);\r
 477             break;      \r
 478         }\r
 479         case RK30_PIN2_PD4:\r
 480         {\r
 481              rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0);\r
 482             break;      \r
 483         }\r
 484         case RK30_PIN2_PD5:\r
 485         {\r
 486              rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0);\r
 487             break;      \r
 488         }\r
 489         case RK30_PIN2_PD6:\r
 490         {\r
 491              rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0);\r
 492             break;      \r
 493         }\r
 494         case RK30_PIN2_PD7:\r
 495         {\r
 496              rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0);\r
 497             break;      \r
 498         }\r
 499         case RK30_PIN3_PA0:\r
 500         {\r
 501              rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0);\r
 502             break;      \r
 503         }\r
 504         case RK30_PIN3_PA1:\r
 505         {\r
 506              rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0);\r
 507             break;      \r
 508         }\r
 509         case RK30_PIN3_PA2:\r
 510         {\r
 511              rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0);\r
 512             break;      \r
 513         }\r
 514         case RK30_PIN3_PA3:\r
 515         {\r
 516              rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0);\r
 517             break;      \r
 518         }\r
 519         case RK30_PIN3_PA4:\r
 520         {\r
 521              rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0);\r
 522             break;      \r
 523         }\r
 524         case RK30_PIN3_PA5:\r
 525         {\r
 526              rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0);\r
 527             break;      \r
 528         }\r
 529         case RK30_PIN3_PA6:\r
 530         {\r
 531              rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0);\r
 532             break;      \r
 533         }\r
 534         case RK30_PIN3_PA7:\r
 535         {\r
 536              rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0);\r
 537             break;      \r
 538         }\r
 539         case RK30_PIN3_PB0:\r
 540         {\r
 541              rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0);\r
 542             break;      \r
 543         }\r
 544         case RK30_PIN3_PB1:\r
 545         {\r
 546              rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0);\r
 547             break;      \r
 548         }\r
 549         case RK30_PIN3_PB2:\r
 550         {\r
 551              rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0);\r
 552             break;      \r
 553         }\r
 554         case RK30_PIN3_PB3:\r
 555         {\r
 556              rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0);\r
 557             break;      \r
 558         }\r
 559         case RK30_PIN3_PB4:\r
 560         {\r
 561              rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0);\r
 562             break;      \r
 563         }\r
 564         case RK30_PIN3_PB5:\r
 565         {\r
 566              rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0);\r
 567             break;      \r
 568         }\r
 569         case RK30_PIN3_PB6:\r
 570         {\r
 571              rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0);\r
 572             break;      \r
 573         }\r
 574         case RK30_PIN3_PB7:\r
 575         {\r
 576              rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0);\r
 577             break;      \r
 578         }\r
 579         case RK30_PIN3_PC0:\r
 580         {\r
 581              rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0);\r
 582             break;      \r
 583         }\r
 584         case RK30_PIN3_PC1:\r
 585         {\r
 586              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0);\r
 587             break;      \r
 588         }\r
 589         case RK30_PIN3_PC2:\r
 590         {\r
 591              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0);\r
 592             break;      \r
 593         }\r
 594         case RK30_PIN3_PC3:\r
 595         {\r
 596              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0);\r
 597             break;      \r
 598         }\r
 599         case RK30_PIN3_PC4:\r
 600         {\r
 601              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0);\r
 602             break;      \r
 603         }\r
 604         case RK30_PIN3_PC5:\r
 605         {\r
 606              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0);\r
 607             break;      \r
 608         }\r
 609         case RK30_PIN3_PC6:\r
 610         {\r
 611              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0);\r
 612             break;      \r
 613         }\r
 614         case RK30_PIN3_PC7:\r
 615         {\r
 616              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0);\r
 617             break;      \r
 618         }\r
 619         case RK30_PIN3_PD0:\r
 620         {\r
 621              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0);\r
 622             break;      \r
 623         }\r
 624         case RK30_PIN3_PD1:\r
 625         {\r
 626              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0);\r
 627             break;      \r
 628         }\r
 629         case RK30_PIN3_PD2:\r
 630         {\r
 631              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
 632             break;      \r
 633         }\r
 634         case RK30_PIN3_PD3:\r
 635         {\r
 636              rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0);\r
 637             break;      \r
 638         }\r
 639         case RK30_PIN3_PD4:\r
 640         {\r
 641              rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0);\r
 642             break;      \r
 643         }\r
 644         case RK30_PIN3_PD5:\r
 645         {\r
 646              rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0);\r
 647             break;      \r
 648         }\r
 649         case RK30_PIN3_PD6:\r
 650         {\r
 651              rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0);\r
 652             break;      \r
 653         }\r
 654         case RK30_PIN3_PD7:\r
 655         {\r
 656              rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0);\r
 657             break;      \r
 658         }\r
 659         case RK30_PIN4_PA0:\r
 660         {\r
 661                  rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0);\r
 662                 break;  \r
 663         }\r
 664         case RK30_PIN4_PA1:\r
 665         {\r
 666                  rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0);\r
 667                 break;  \r
 668         }\r
 669         case RK30_PIN4_PA2:\r
 670         {\r
 671                  rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0);\r
 672                 break;  \r
 673         }\r
 674                         \r
 675         case RK30_PIN4_PA3:\r
 676         {\r
 677                  rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0);\r
 678                 break;  \r
 679         }\r
 680         case RK30_PIN4_PA4:\r
 681         {\r
 682                  rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0);\r
 683                 break;  \r
 684         }\r
 685         case RK30_PIN4_PA5:\r
 686         {\r
 687              rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0);\r
 688             break;      \r
 689         }\r
 690         case RK30_PIN4_PA6:\r
 691         {\r
 692              rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0);\r
 693             break;      \r
 694         }\r
 695         case RK30_PIN4_PA7:\r
 696         {\r
 697              rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0);\r
 698             break;      \r
 699         }\r
 700         case RK30_PIN4_PB0:\r
 701         {\r
 702              rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0);\r
 703             break;      \r
 704         }\r
 705         case RK30_PIN4_PB1:\r
 706         {\r
 707              rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0);\r
 708             break;      \r
 709         }\r
 710         case RK30_PIN4_PB2:\r
 711         {\r
 712              rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
 713             break;      \r
 714         }\r
 715         case RK30_PIN4_PB3:\r
 716         {\r
 717              rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0);\r
 718             break;      \r
 719         }\r
 720         case RK30_PIN4_PB4:\r
 721         {\r
 722              rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0);\r
 723             break;      \r
 724         }\r
 725         case RK30_PIN4_PB5:\r
 726         {\r
 727              rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0);\r
 728             break;      \r
 729         }\r
 730         case RK30_PIN4_PB6:\r
 731         {\r
 732              rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0);\r
 733             break;      \r
 734         }\r
 735         case RK30_PIN4_PB7:\r
 736         {\r
 737              rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0);\r
 738             break;      \r
 739         }\r
 740         case RK30_PIN4_PC0:\r
 741         {\r
 742              rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0);\r
 743             break;      \r
 744         }\r
 745         case RK30_PIN4_PC1:\r
 746         {\r
 747              rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0);\r
 748             break;      \r
 749         }\r
 750         case RK30_PIN4_PC2:\r
 751         {\r
 752              rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0);\r
 753             break;      \r
 754         }\r
 755         case RK30_PIN4_PC3:\r
 756         {\r
 757              rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0);\r
 758             break;      \r
 759         }\r
 760         case RK30_PIN4_PC4:\r
 761         {\r
 762              rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0);\r
 763             break;      \r
 764         }\r
 765         case RK30_PIN4_PC5:\r
 766         {\r
 767              rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0);\r
 768             break;      \r
 769         }\r
 770         case RK30_PIN4_PC6:\r
 771         {\r
 772              rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0);\r
 773             break;      \r
 774         }\r
 775 \r
 776 \r
 777         case RK30_PIN4_PC7:\r
 778         {\r
 779              rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0);\r
 780             break;      \r
 781         }\r
 782         case RK30_PIN4_PD0:\r
 783             {\r
 784                      rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0);                         \r
 785                      break;     \r
 786             }\r
 787         case RK30_PIN4_PD1:\r
 788         {\r
 789              rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0);             \r
 790              break;     \r
 791         }\r
 792         case RK30_PIN4_PD2:\r
 793             {\r
 794                      rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0);                                \r
 795                      break;     \r
 796             }\r
 797         case RK30_PIN4_PD3:\r
 798         {\r
 799              rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0);           \r
 800              break;     \r
 801         }\r
 802         case RK30_PIN4_PD4:\r
 803         {\r
 804              rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0);\r
 805             break;      \r
 806         }\r
 807         case RK30_PIN4_PD5:\r
 808         {\r
 809              rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0);\r
 810             break;      \r
 811         }\r
 812         case RK30_PIN4_PD6:\r
 813         {\r
 814              rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0);\r
 815             break;      \r
 816         }\r
 817         case RK30_PIN4_PD7:\r
 818         {\r
 819              rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0);\r
 820             break;      \r
 821         } \r
 822         case RK30_PIN6_PA0:\r
 823         case RK30_PIN6_PA1:\r
 824         case RK30_PIN6_PA2:\r
 825         case RK30_PIN6_PA3:\r
 826         case RK30_PIN6_PA4:\r
 827         case RK30_PIN6_PA5:\r
 828         case RK30_PIN6_PA6:\r
 829         case RK30_PIN6_PA7:\r
 830         case RK30_PIN6_PB0:\r
 831         case RK30_PIN6_PB1:\r
 832         case RK30_PIN6_PB2:\r
 833         case RK30_PIN6_PB3:\r
 834         case RK30_PIN6_PB4:\r
 835         case RK30_PIN6_PB5:\r
 836         case RK30_PIN6_PB6:\r
 837                         break;\r
 838         case RK30_PIN6_PB7:\r
 839                 {\r
 840                          rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0);\r
 841                         break;  \r
 842                 } \r
 843         default:\r
 844         {\r
 845             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
 846             break;\r
 847         }\r
 848     }\r
 849     return 0;\r
 850 }\r
 851 #define PMEM_CAM_BASE 0 //just for compile ,no meaning\r
 852 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
 853 \r
 854 \r
 855 \r
 856 static u64 rockchip_device_camera_dmamask = 0xffffffffUL;\r
 857 #if RK_SUPPORT_CIF0\r
 858 static struct resource rk_camera_resource_host_0[] = {\r
 859         [0] = {\r
 860                 .start = RK30_CIF0_PHYS,\r
 861                 .end   = RK30_CIF0_PHYS + RK30_CIF0_SIZE - 1,\r
 862                 .flags = IORESOURCE_MEM,\r
 863         },\r
 864         [1] = {\r
 865                 .start = IRQ_CIF0,\r
 866                 .end   = IRQ_CIF0,\r
 867                 .flags = IORESOURCE_IRQ,\r
 868         }\r
 869 };\r
 870 #endif\r
 871 #if RK_SUPPORT_CIF1\r
 872 static struct resource rk_camera_resource_host_1[] = {\r
 873         [0] = {\r
 874                 .start = RK30_CIF1_PHYS,\r
 875                 .end   = RK30_CIF1_PHYS + RK30_CIF1_SIZE - 1,\r
 876                 .flags = IORESOURCE_MEM,\r
 877         },\r
 878         [1] = {\r
 879                 .start = IRQ_CIF1,\r
 880                 .end   = IRQ_CIF1,\r
 881                 .flags = IORESOURCE_IRQ,\r
 882         }\r
 883 };\r
 884 #endif\r
 885 \r
 886 /*platform_device : */\r
 887 #if RK_SUPPORT_CIF0\r
 888  struct platform_device rk_device_camera_host_0 = {\r
 889         .name             = RK29_CAM_DRV_NAME,\r
 890         .id       = RK_CAM_PLATFORM_DEV_ID_0,                           /* This is used to put cameras on this interface */\r
 891         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_0),\r
 892         .resource         = rk_camera_resource_host_0,\r
 893         .dev                    = {\r
 894                 .dma_mask = &rockchip_device_camera_dmamask,\r
 895                 .coherent_dma_mask = 0xffffffffUL,\r
 896                 .platform_data  = &rk_camera_platform_data,\r
 897         }\r
 898 };\r
 899 #endif\r
 900 \r
 901 #if RK_SUPPORT_CIF1\r
 902 /*platform_device : */\r
 903  struct platform_device rk_device_camera_host_1 = {\r
 904         .name             = RK29_CAM_DRV_NAME,\r
 905         .id       = RK_CAM_PLATFORM_DEV_ID_1,                           /* This is used to put cameras on this interface */\r
 906         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_1),\r
 907         .resource         = rk_camera_resource_host_1,\r
 908         .dev                    = {\r
 909                 .dma_mask = &rockchip_device_camera_dmamask,\r
 910                 .coherent_dma_mask = 0xffffffffUL,\r
 911                 .platform_data  = &rk_camera_platform_data,\r
 912         }\r
 913 };\r
 914 #endif\r
 915 \r
 916 static void rk_init_camera_plateform_data(void)\r
 917 {\r
 918     int i,dev_idx;\r
 919     \r
 920     dev_idx = 0;\r
 921     for (i=0; i<RK_CAM_NUM; i++) {\r
 922         rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];\r
 923         if (rk_camera_platform_data.register_dev[i].device_info.name) {            \r
 924             rk_camera_platform_data.register_dev[i].link_info.board_info = \r
 925                 &rk_camera_platform_data.register_dev[i].i2c_cam_info;\r
 926             rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;\r
 927             rk_camera_platform_data.register_dev[i].device_info.dev.platform_data = \r
 928                 &rk_camera_platform_data.register_dev[i].link_info;\r
 929             dev_idx++;\r
 930         }\r
 931     }\r
 932 }\r
 933 \r
 934 static void rk30_camera_request_reserve_mem(void)\r
 935 {\r
 936 #ifdef CONFIG_VIDEO_RK29_WORK_IPP    \r
 937     #if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == false)\r
 938         rk_camera_platform_data.meminfo.name = "camera_ipp_mem";\r
 939         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",PMEM_CAMIPP_NECESSARY);\r
 940         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY;\r
 941 \r
 942         memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));\r
 943     #else\r
 944         rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";\r
 945         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);\r
 946         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;\r
 947         \r
 948         rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";\r
 949         rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);\r
 950         rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;\r
 951     #endif\r
 952  #endif\r
 953  #if PMEM_CAM_NECESSARY\r
 954         android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),PMEM_CAM_NECESSARY);\r
 955         android_pmem_cam_pdata.size= PMEM_CAM_NECESSARY;\r
 956  #endif\r
 957 \r
 958 }\r
 959 static int rk_register_camera_devices(void)\r
 960 {\r
 961     int i;\r
 962     int host_registered_0,host_registered_1;\r
 963     \r
 964         rk_init_camera_plateform_data();\r
 965 \r
 966     host_registered_0 = 0;\r
 967     host_registered_1 = 0;\r
 968     for (i=0; i<RK_CAM_NUM; i++) {\r
 969         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
 970             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {\r
 971             #if RK_SUPPORT_CIF0\r
 972                 if (!host_registered_0) {\r
 973                     platform_device_register(&rk_device_camera_host_0);\r
 974                     host_registered_0 = 1;\r
 975                 }\r
 976             #else\r
 977                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);\r
 978             #endif\r
 979             } \r
 980 \r
 981             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {\r
 982             #if RK_SUPPORT_CIF1\r
 983                 if (!host_registered_1) {\r
 984                     platform_device_register(&rk_device_camera_host_1);\r
 985                     host_registered_1 = 1;\r
 986                 }\r
 987             #else\r
 988                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);\r
 989             #endif\r
 990             } \r
 991         }\r
 992     }\r
 993 \r
 994     for (i=0; i<RK_CAM_NUM; i++) {\r
 995         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
 996             platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);\r
 997         }\r
 998     }\r
 999  #if PMEM_CAM_NECESSARY\r
1000             platform_device_register(&android_pmem_cam_device);\r
1001  #endif\r
1002     \r
1003         return 0;\r
1004 }\r
1005 \r
1006 module_init(rk_register_camera_devices);\r
1007 #endif\r
1008 \r
1009 #endif //#ifdef CONFIG_VIDEO_RK\r