drivers/media/video/rk30_camera.c

   1 \r
   2 #include <mach/iomux.h>\r
   3 #include <media/soc_camera.h>\r
   4 #include <linux/android_pmem.h>\r
   5 #include <mach/rk30_camera.h>\r
   6 #ifndef PMEM_CAM_SIZE\r
   7 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
   8 #else\r
   9 /*****************************************************************************************\r
  10  * camera  devices\r
  11  * author: ddl@rock-chips.com\r
  12  *****************************************************************************************/\r
  13 #ifdef CONFIG_VIDEO_RK29 \r
  14 \r
  15 static int rk_sensor_iomux(int pin)\r
  16 {    \r
  17 #if defined(CONFIG_ARCH_RK30)\r
  18     switch (pin)\r
  19     {\r
  20         case RK30_PIN0_PA0: \r
  21                 {\r
  22                          rk30_mux_api_set(GPIO0A0_HDMIHOTPLUGIN_NAME,0);\r
  23                         break;  \r
  24                 }\r
  25         case RK30_PIN0_PA1: \r
  26                 {\r
  27                          rk30_mux_api_set(GPIO0A1_HDMII2CSCL_NAME,0);\r
  28                         break;  \r
  29                 }\r
  30         case RK30_PIN0_PA2:\r
  31                 {\r
  32                          rk30_mux_api_set(GPIO0A2_HDMII2CSDA_NAME,0);\r
  33                         break;  \r
  34                 }\r
  35         case RK30_PIN0_PA3:\r
  36                 {\r
  37                          rk30_mux_api_set(GPIO0A3_PWM0_NAME,0);\r
  38                         break;  \r
  39                 }\r
  40         case RK30_PIN0_PA4:\r
  41                 {\r
  42                          rk30_mux_api_set(GPIO0A4_PWM1_NAME,0);\r
  43                         break;  \r
  44                 }\r
  45         case RK30_PIN0_PA5:\r
  46                 {\r
  47                          rk30_mux_api_set(GPIO0A5_OTGDRVVBUS_NAME,0);\r
  48                         break;  \r
  49                 }\r
  50         case RK30_PIN0_PA6:\r
  51         {\r
  52              rk30_mux_api_set(GPIO0A6_HOSTDRVVBUS_NAME,0);\r
  53             break;      \r
  54         }\r
  55         case RK30_PIN0_PA7:\r
  56         {\r
  57              rk30_mux_api_set(GPIO0A7_I2S8CHSDI_NAME,0);\r
  58             break;      \r
  59         }\r
  60         case RK30_PIN0_PB0:\r
  61         {\r
  62              rk30_mux_api_set(GPIO0B0_I2S8CHCLK_NAME,0);\r
  63             break;      \r
  64         }\r
  65         case RK30_PIN0_PB1:\r
  66         {\r
  67              rk30_mux_api_set(GPIO0B1_I2S8CHSCLK_NAME,0);\r
  68             break;      \r
  69         }\r
  70         case RK30_PIN0_PB2:\r
  71         {\r
  72              rk30_mux_api_set(GPIO0B2_I2S8CHLRCKRX_NAME,0);\r
  73             break;      \r
  74         }\r
  75         case RK30_PIN0_PB3:\r
  76         {\r
  77              rk30_mux_api_set(GPIO0B3_I2S8CHLRCKTX_NAME,0);\r
  78             break;      \r
  79         }\r
  80         case RK30_PIN0_PB4:\r
  81         {\r
  82              rk30_mux_api_set(GPIO0B4_I2S8CHSDO0_NAME,0);\r
  83             break;      \r
  84         }\r
  85         case RK30_PIN0_PB5:\r
  86         {\r
  87              rk30_mux_api_set(GPIO0B5_I2S8CHSDO1_NAME,0);\r
  88             break;      \r
  89         }\r
  90         case RK30_PIN0_PB6:\r
  91         {\r
  92              rk30_mux_api_set(GPIO0B6_I2S8CHSDO2_NAME,0);\r
  93             break;      \r
  94         }\r
  95         case RK30_PIN0_PB7:\r
  96         {\r
  97              rk30_mux_api_set(GPIO0B7_I2S8CHSDO3_NAME,0);\r
  98             break;      \r
  99         }\r
 100         case RK30_PIN0_PC0:\r
 101         {\r
 102              rk30_mux_api_set(GPIO0C0_I2S12CHCLK_NAME,0);\r
 103             break;      \r
 104         }\r
 105         case RK30_PIN0_PC1:\r
 106         {\r
 107              rk30_mux_api_set(GPIO0C1_I2S12CHSCLK_NAME,0);\r
 108             break;      \r
 109         }\r
 110         case RK30_PIN0_PC2:\r
 111         {\r
 112              rk30_mux_api_set(GPIO0C2_I2S12CHLRCKRX_NAME,0);\r
 113             break;      \r
 114         }\r
 115         case RK30_PIN0_PC3:\r
 116         {\r
 117              rk30_mux_api_set(GPIO0C3_I2S12CHLRCKTX_NAME,0);\r
 118             break;      \r
 119         }\r
 120         case RK30_PIN0_PC4:\r
 121         {\r
 122              rk30_mux_api_set(GPIO0C4_I2S12CHSDI_NAME,0);\r
 123             break;      \r
 124         }\r
 125         case RK30_PIN0_PC5:\r
 126         {\r
 127              rk30_mux_api_set(GPIO0C5_I2S12CHSDO_NAME,0);\r
 128             break;      \r
 129         }\r
 130         case RK30_PIN0_PC6:\r
 131         {\r
 132              rk30_mux_api_set(GPIO0C6_TRACECLK_SMCADDR2_NAME,0);\r
 133             break;      \r
 134         }\r
 135         case RK30_PIN0_PC7:\r
 136         {\r
 137              rk30_mux_api_set(GPIO0C7_TRACECTL_SMCADDR3_NAME,0);\r
 138             break;      \r
 139         }\r
 140         case RK30_PIN0_PD0:\r
 141         {\r
 142              rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME,0);\r
 143             break;      \r
 144         }\r
 145         case RK30_PIN0_PD1:\r
 146         {\r
 147              rk30_mux_api_set(GPIO0D1_I2S22CHSCLK_SMCWEN_NAME,0);\r
 148             break;      \r
 149         }\r
 150         case RK30_PIN0_PD2:\r
 151         {\r
 152              rk30_mux_api_set(GPIO0D2_I2S22CHLRCKRX_SMCOEN_NAME,0);\r
 153             break;      \r
 154         }\r
 155         case RK30_PIN0_PD3:\r
 156         {\r
 157              rk30_mux_api_set(GPIO0D3_I2S22CHLRCKTX_SMCADVN_NAME,0);\r
 158             break;      \r
 159         }\r
 160         case RK30_PIN0_PD4:\r
 161         {\r
 162              rk30_mux_api_set(GPIO0D4_I2S22CHSDI_SMCADDR0_NAME,0);\r
 163             break;      \r
 164         }\r
 165         case RK30_PIN0_PD5:\r
 166         {\r
 167              rk30_mux_api_set(GPIO0D5_I2S22CHSDO_SMCADDR1_NAME,0);\r
 168             break;      \r
 169         }\r
 170         case RK30_PIN0_PD6:\r
 171         {\r
 172              rk30_mux_api_set(GPIO0D6_PWM2_NAME,0);\r
 173             break;      \r
 174         }\r
 175         case RK30_PIN0_PD7:\r
 176         {\r
 177              rk30_mux_api_set(GPIO0D7_PWM3_NAME,0);\r
 178             break;      \r
 179         }\r
 180         case RK30_PIN1_PA0:\r
 181         {\r
 182              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 183             break;      \r
 184         }\r
 185         case RK30_PIN1_PA1:\r
 186         {\r
 187              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 188             break;      \r
 189         }\r
 190         case RK30_PIN1_PA2:\r
 191         {\r
 192              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 193             break;      \r
 194         }\r
 195         case RK30_PIN1_PA3:\r
 196         {\r
 197              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 198             break;      \r
 199         }\r
 200         case RK30_PIN1_PA4:\r
 201         {\r
 202              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0CSN0_NAME,0);\r
 203             break;      \r
 204         }\r
 205         case RK30_PIN1_PA5:\r
 206         {\r
 207              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0CLK_NAME,0);\r
 208             break;      \r
 209         }\r
 210         case RK30_PIN1_PA6:\r
 211         {\r
 212              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0RXD_NAME,0);\r
 213             break;      \r
 214         }\r
 215         case RK30_PIN1_PA7:\r
 216         {\r
 217              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0TXD_NAME,0);\r
 218             break;      \r
 219         }\r
 220         case RK30_PIN1_PB0:\r
 221         {\r
 222              rk30_mux_api_set(GPIO1B0_UART2SIN_NAME,0);\r
 223             break;      \r
 224         }\r
 225         case RK30_PIN1_PB1:\r
 226         {\r
 227              rk30_mux_api_set(GPIO1B1_UART2SOUT_NAME,0);\r
 228             break;      \r
 229         }\r
 230         case RK30_PIN1_PB2:\r
 231         {\r
 232              rk30_mux_api_set(GPIO1B2_SPDIFTX_NAME,0);\r
 233             break;      \r
 234         }\r
 235         case RK30_PIN1_PB3:\r
 236         {\r
 237              rk30_mux_api_set(GPIO1B3_CIF0CLKOUT_NAME,0);\r
 238             break;      \r
 239         }\r
 240         case RK30_PIN1_PB4:\r
 241         {\r
 242              rk30_mux_api_set(GPIO1B4_CIF0DATA0_NAME,0);\r
 243             break;      \r
 244         }\r
 245         case RK30_PIN1_PB5:\r
 246         {\r
 247              rk30_mux_api_set(GPIO1B5_CIF0DATA1_NAME,0);\r
 248             break;      \r
 249         }\r
 250         case RK30_PIN1_PB6:\r
 251         {\r
 252              rk30_mux_api_set(GPIO1B6_CIFDATA10_NAME,0);\r
 253             break;      \r
 254         }\r
 255         case RK30_PIN1_PB7:\r
 256         {\r
 257              rk30_mux_api_set(GPIO1B7_CIFDATA11_NAME,0);\r
 258             break;      \r
 259         }\r
 260         case RK30_PIN1_PC0:\r
 261         {\r
 262              rk30_mux_api_set(GPIO1C0_CIF1DATA2_RMIICLKOUT_RMIICLKIN_NAME,0);\r
 263             break;      \r
 264         }\r
 265         case RK30_PIN1_PC1:\r
 266         {\r
 267              rk30_mux_api_set(GPIO1C1_CIFDATA3_RMIITXEN_NAME,0);\r
 268             break;      \r
 269         }\r
 270         case RK30_PIN1_PC2:\r
 271         {\r
 272              rk30_mux_api_set(GPIO1C2_CIF1DATA4_RMIITXD1_NAME,0);\r
 273             break;      \r
 274         }\r
 275         case RK30_PIN1_PC3:\r
 276         {\r
 277              rk30_mux_api_set(GPIO1C3_CIFDATA5_RMIITXD0_NAME,0);\r
 278             break;      \r
 279         }\r
 280         case RK30_PIN1_PC4:\r
 281         {\r
 282              rk30_mux_api_set(GPIO1C4_CIFDATA6_RMIIRXERR_NAME,0);\r
 283             break;      \r
 284         }\r
 285         case RK30_PIN1_PC5:\r
 286         {\r
 287              rk29_mux_api_set(GPIO1C5_CIFDATA7_RMIICRSDVALID_NAME,0);\r
 288             break;      \r
 289         }\r
 290         case RK30_PIN1_PC6:\r
 291         {\r
 292              rk30_mux_api_set(GPIO1C6_CIFDATA8_RMIIRXD1_NAME,0);\r
 293             break;      \r
 294         }\r
 295         case RK30_PIN1_PC7:\r
 296         {\r
 297              rk30_mux_api_set(GPIO1C7_CIFDATA9_RMIIRXD0_NAME,0);\r
 298             break;      \r
 299         }\r
 300         case RK30_PIN1_PD0:\r
 301         {\r
 302              rk30_mux_api_set(GPIO1D0_CIF1VSYNC_MIIMD_NAME,0);\r
 303             break;      \r
 304         }\r
 305         case RK30_PIN1_PD1:\r
 306         {\r
 307              rk30_mux_api_set(GPIO1D1_CIF1HREF_MIIMDCLK_NAME,0);\r
 308             break;      \r
 309         }\r
 310         case RK30_PIN1_PD2:\r
 311         {\r
 312              rk30_mux_api_set(GPIO1D2_CIF1CLKIN_NAME,0);\r
 313             break;      \r
 314         }\r
 315         case RK30_PIN1_PD3:\r
 316         {\r
 317              rk30_mux_api_set(GPIO1D3_CIF1DATA0_NAME,0);\r
 318             break;      \r
 319         }\r
 320         case RK30_PIN1_PD4:\r
 321         {\r
 322              rk30_mux_api_set(GPIO1D4_CIF1DATA1_NAME,0);\r
 323             break;      \r
 324         }\r
 325         case RK30_PIN1_PD5:\r
 326         {\r
 327              rk30_mux_api_set(GPIO1D5_CIF1DATA10_NAME,0);\r
 328             break;      \r
 329         }\r
 330         case RK30_PIN1_PD6:\r
 331         {\r
 332              rk30_mux_api_set(GPIO1D6_CIF1DATA11_NAME,0);\r
 333             break;      \r
 334         }\r
 335         case RK30_PIN1_PD7:\r
 336         {\r
 337              rk30_mux_api_set(GPIO1D7_CIF1CLKOUT_NAME,0);\r
 338             break;      \r
 339         }\r
 340         case RK30_PIN2_PA0:\r
 341         {\r
 342              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCADDR4_NAME,0);\r
 343             break;      \r
 344         }\r
 345         case RK30_PIN2_PA1:\r
 346         {\r
 347              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCADDR5_NAME,0);\r
 348             break;      \r
 349         }\r
 350         case RK30_PIN2_PA2:\r
 351         {\r
 352              rk30_mux_api_set(GPIO2A2_LCDCDATA2_SMCADDR6_NAME,0);\r
 353             break;      \r
 354         }\r
 355         case RK30_PIN2_PA3:\r
 356         {\r
 357              rk30_mux_api_set(GPIO2A3_LCDCDATA3_SMCADDR7_NAME,0);\r
 358             break;      \r
 359         }\r
 360         case RK30_PIN2_PA4:\r
 361         {\r
 362              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCADDR8_NAME,0);\r
 363             break;      \r
 364         }\r
 365         case RK30_PIN2_PA5:\r
 366         {\r
 367              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCADDR9_NAME,0);\r
 368             break;      \r
 369         }\r
 370         case RK30_PIN2_PA6:\r
 371         {\r
 372              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCADDR10_NAME,0);\r
 373             break;      \r
 374         }\r
 375         case RK30_PIN2_PA7:\r
 376         {\r
 377              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCADDR11_NAME,0);\r
 378             break;      \r
 379         }\r
 380         case RK30_PIN2_PB0:\r
 381         {\r
 382              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCADDR12_NAME,0);\r
 383             break;      \r
 384         }\r
 385         case RK30_PIN2_PB1:\r
 386         {\r
 387              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCADDR13_NAME,0);\r
 388             break;      \r
 389         }\r
 390         case RK30_PIN2_PB2:\r
 391         {\r
 392              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCADDR14_NAME,0);\r
 393             break;      \r
 394         }\r
 395         case RK30_PIN2_PB3:\r
 396         {\r
 397              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCADDR15_NAME,0);\r
 398             break;      \r
 399         }\r
 400         case RK30_PIN2_PB4:\r
 401         {\r
 402              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCADDR16_HSADCDATA9_NAME,0);\r
 403             break;      \r
 404         }\r
 405         case RK30_PIN2_PB5:\r
 406         {\r
 407              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCADDR17_HSADCDATA8_NAME,0);\r
 408             break;      \r
 409         }\r
 410         case RK30_PIN2_PB6:\r
 411         {\r
 412              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCADDR18_TSSYNC_NAME,0);\r
 413             break;      \r
 414         }\r
 415         case RK30_PIN2_PB7:\r
 416         {\r
 417              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCADDR19_HSADCDATA7_NAME,0);\r
 418             break;      \r
 419         }\r
 420         case RK30_PIN2_PC0:\r
 421         {\r
 422              rk30_mux_api_set(GPIO2C0_LCDCDATA16_GPSCLK_HSADCCLKOUT_NAME,0);\r
 423             break;      \r
 424         }\r
 425         case RK30_PIN2_PC1:\r
 426         {\r
 427              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCBLSN0_HSADCDATA6_NAME,0);\r
 428             break;      \r
 429         }\r
 430         case RK30_PIN2_PC2:\r
 431         {\r
 432              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME,0);\r
 433             break;      \r
 434         }\r
 435         case RK30_PIN2_PC3:\r
 436         {\r
 437              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SPI1CLK_HSADCDATA0_NAME,0);\r
 438             break;      \r
 439         }\r
 440         case RK30_PIN2_PC4:\r
 441         {\r
 442              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SPI1CSN0_HSADCDATA1_NAME,0);\r
 443             break;      \r
 444         }\r
 445         case RK30_PIN2_PC5:\r
 446         {\r
 447              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SPI1TXD_HSADCDATA2_NAME,0);\r
 448             break;      \r
 449         }\r
 450         case RK30_PIN2_PC6:\r
 451         {\r
 452              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SPI1RXD_HSADCDATA3_NAME,0);\r
 453             break;      \r
 454         }\r
 455         case RK30_PIN2_PC7:\r
 456         {\r
 457              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SPI1CSN1_HSADCDATA4_NAME,0);\r
 458             break;      \r
 459         }\r
 460         case RK30_PIN2_PD0:\r
 461         {\r
 462              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_NAME,0);\r
 463             break;      \r
 464         }\r
 465         case RK30_PIN2_PD1:\r
 466         {\r
 467              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCCSN1_NAME,0);\r
 468             break;      \r
 469         }\r
 470         case RK30_PIN2_PD2:\r
 471         {\r
 472              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_NAME,0);\r
 473             break;      \r
 474         }\r
 475         case RK30_PIN2_PD3:\r
 476         {\r
 477              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_NAME,0);\r
 478             break;      \r
 479         }\r
 480         case RK30_PIN2_PD4:\r
 481         {\r
 482              rk30_mux_api_set(GPIO2D4_I2C0SDA_NAME,0);\r
 483             break;      \r
 484         }\r
 485         case RK30_PIN2_PD5:\r
 486         {\r
 487              rk30_mux_api_set(GPIO2D5_I2C0SCL_NAME,0);\r
 488             break;      \r
 489         }\r
 490         case RK30_PIN2_PD6:\r
 491         {\r
 492              rk30_mux_api_set(GPIO2D6_I2C1SDA_NAME,0);\r
 493             break;      \r
 494         }\r
 495         case RK30_PIN2_PD7:\r
 496         {\r
 497              rk30_mux_api_set(GPIO2D7_I2C1SCL_NAME,0);\r
 498             break;      \r
 499         }\r
 500         case RK30_PIN3_PA0:\r
 501         {\r
 502              rk30_mux_api_set(GPIO3A0_I2C2SDA_NAME,0);\r
 503             break;      \r
 504         }\r
 505         case RK30_PIN3_PA1:\r
 506         {\r
 507              rk30_mux_api_set(GPIO3A1_I2C2SCL_NAME,0);\r
 508             break;      \r
 509         }\r
 510         case RK30_PIN3_PA2:\r
 511         {\r
 512              rk30_mux_api_set(GPIO3A2_I2C3SDA_NAME,0);\r
 513             break;      \r
 514         }\r
 515         case RK30_PIN3_PA3:\r
 516         {\r
 517              rk30_mux_api_set(GPIO3A3_I2C3SCL_NAME,0);\r
 518             break;      \r
 519         }\r
 520         case RK30_PIN3_PA4:\r
 521         {\r
 522              rk30_mux_api_set(GPIO3A4_I2C4SDA_NAME,0);\r
 523             break;      \r
 524         }\r
 525         case RK30_PIN3_PA5:\r
 526         {\r
 527              rk30_mux_api_set(GPIO3A5_I2C4SCL_NAME,0);\r
 528             break;      \r
 529         }\r
 530         case RK30_PIN3_PA6:\r
 531         {\r
 532              rk30_mux_api_set(GPIO3A6_SDMMC0RSTNOUT_NAME,0);\r
 533             break;      \r
 534         }\r
 535         case RK30_PIN3_PA7:\r
 536         {\r
 537              rk30_mux_api_set(GPIO3A7_SDMMC0PWREN_NAME,0);\r
 538             break;      \r
 539         }\r
 540         case RK30_PIN3_PB0:\r
 541         {\r
 542              rk30_mux_api_set(GPIO3B0_SDMMC0CLKOUT_NAME,0);\r
 543             break;      \r
 544         }\r
 545         case RK30_PIN3_PB1:\r
 546         {\r
 547              rk30_mux_api_set(GPIO3B1_SDMMC0CMD_NAME,0);\r
 548             break;      \r
 549         }\r
 550         case RK30_PIN3_PB2:\r
 551         {\r
 552              rk30_mux_api_set(GPIO3B2_SDMMC0DATA0_NAME,0);\r
 553             break;      \r
 554         }\r
 555         case RK30_PIN3_PB3:\r
 556         {\r
 557              rk30_mux_api_set(GPIO3B3_SDMMC0DATA1_NAME,0);\r
 558             break;      \r
 559         }\r
 560         case RK30_PIN3_PB4:\r
 561         {\r
 562              rk30_mux_api_set(GPIO3B4_SDMMC0DATA2_NAME,0);\r
 563             break;      \r
 564         }\r
 565         case RK30_PIN3_PB5:\r
 566         {\r
 567              rk30_mux_api_set(GPIO3B5_SDMMC0DATA3_NAME,0);\r
 568             break;      \r
 569         }\r
 570         case RK30_PIN3_PB6:\r
 571         {\r
 572              rk30_mux_api_set(GPIO3B6_SDMMC0DETECTN_NAME,0);\r
 573             break;      \r
 574         }\r
 575         case RK30_PIN3_PB7:\r
 576         {\r
 577              rk30_mux_api_set(GPIO3B7_SDMMC0WRITEPRT_NAME,0);\r
 578             break;      \r
 579         }\r
 580         case RK30_PIN3_PC0:\r
 581         {\r
 582              rk30_mux_api_set(GPIO3C0_SMMC1CMD_NAME,0);\r
 583             break;      \r
 584         }\r
 585         case RK30_PIN3_PC1:\r
 586         {\r
 587              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_NAME,0);\r
 588             break;      \r
 589         }\r
 590         case RK30_PIN3_PC2:\r
 591         {\r
 592              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_NAME,0);\r
 593             break;      \r
 594         }\r
 595         case RK30_PIN3_PC3:\r
 596         {\r
 597              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_NAME,0);\r
 598             break;      \r
 599         }\r
 600         case RK30_PIN3_PC4:\r
 601         {\r
 602              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_NAME,0);\r
 603             break;      \r
 604         }\r
 605         case RK30_PIN3_PC5:\r
 606         {\r
 607              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_NAME,0);\r
 608             break;      \r
 609         }\r
 610         case RK30_PIN3_PC6:\r
 611         {\r
 612              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_NAME,0);\r
 613             break;      \r
 614         }\r
 615         case RK30_PIN3_PC7:\r
 616         {\r
 617              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_NAME,0);\r
 618             break;      \r
 619         }\r
 620         case RK30_PIN3_PD0:\r
 621         {\r
 622              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_NAME,0);\r
 623             break;      \r
 624         }\r
 625         case RK30_PIN3_PD1:\r
 626         {\r
 627              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_NAME,0);\r
 628             break;      \r
 629         }\r
 630         case RK30_PIN3_PD2:\r
 631         {\r
 632              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
 633             break;      \r
 634         }\r
 635         case RK30_PIN3_PD3:\r
 636         {\r
 637              rk30_mux_api_set(GPIO3D3_UART3SIN_NAME,0);\r
 638             break;      \r
 639         }\r
 640         case RK30_PIN3_PD4:\r
 641         {\r
 642              rk30_mux_api_set(GPIO3D4_UART3SOUT_NAME,0);\r
 643             break;      \r
 644         }\r
 645         case RK30_PIN3_PD5:\r
 646         {\r
 647              rk30_mux_api_set(GPIO3D5_UART3CTSN_NAME,0);\r
 648             break;      \r
 649         }\r
 650         case RK30_PIN3_PD6:\r
 651         {\r
 652              rk30_mux_api_set(GPIO3D6_UART3RTSN_NAME,0);\r
 653             break;      \r
 654         }\r
 655         case RK30_PIN3_PD7:\r
 656         {\r
 657              rk30_mux_api_set(GPIO3D7_FLASHDQS_EMMCCLKOUT_NAME,0);\r
 658             break;      \r
 659         }\r
 660         case RK30_PIN4_PA0:\r
 661         {\r
 662                  rk30_mux_api_set(GPIO4A0_FLASHDATA8_NAME,0);\r
 663                 break;  \r
 664         }\r
 665         case RK30_PIN4_PA1:\r
 666         {\r
 667                  rk30_mux_api_set(GPIO4A1_FLASHDATA9_NAME,0);\r
 668                 break;  \r
 669         }\r
 670         case RK30_PIN4_PA2:\r
 671         {\r
 672                  rk30_mux_api_set(GPIO4A2_FLASHDATA10_NAME,0);\r
 673                 break;  \r
 674         }\r
 675                         \r
 676         case RK30_PIN4_PA3:\r
 677         {\r
 678                  rk30_mux_api_set(GPIO4A3_FLASHDATA11_NAME,0);\r
 679                 break;  \r
 680         }\r
 681         case RK30_PIN4_PA4:\r
 682         {\r
 683                  rk30_mux_api_set(GPIO4A4_FLASHDATA12_NAME,0);\r
 684                 break;  \r
 685         }\r
 686         case RK30_PIN4_PA5:\r
 687         {\r
 688              rk30_mux_api_set(GPIO4A5_FLASHDATA13_NAME,0);\r
 689             break;      \r
 690         }\r
 691         case RK30_PIN4_PA6:\r
 692         {\r
 693              rk30_mux_api_set(GPIO4A6_FLASHDATA14_NAME,0);\r
 694             break;      \r
 695         }\r
 696         case RK30_PIN4_PA7:\r
 697         {\r
 698              rk30_mux_api_set(GPIO4A7_FLASHDATA15_NAME,0);\r
 699             break;      \r
 700         }\r
 701         case RK30_PIN4_PB0:\r
 702         {\r
 703              rk30_mux_api_set(GPIO4B0_FLASHCSN1_NAME,0);\r
 704             break;      \r
 705         }\r
 706         case RK30_PIN4_PB1:\r
 707         {\r
 708              rk30_mux_api_set(GPIO4B1_FLASHCSN2_EMMCCMD_NAME,0);\r
 709             break;      \r
 710         }\r
 711         case RK30_PIN4_PB2:\r
 712         {\r
 713              rk30_mux_api_set(GPIO4B2_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
 714             break;      \r
 715         }\r
 716         case RK30_PIN4_PB3:\r
 717         {\r
 718              rk30_mux_api_set(GPIO4B3_FLASHCSN4_NAME,0);\r
 719             break;      \r
 720         }\r
 721         case RK30_PIN4_PB4:\r
 722         {\r
 723              rk30_mux_api_set(GPIO4B4_FLASHCSN5_NAME,0);\r
 724             break;      \r
 725         }\r
 726         case RK30_PIN4_PB5:\r
 727         {\r
 728              rk30_mux_api_set(GPIO4B5_FLASHCSN6_NAME,0);\r
 729             break;      \r
 730         }\r
 731         case RK30_PIN4_PB6:\r
 732         {\r
 733              rk30_mux_api_set(GPIO4B6_FLASHCSN7_NAME ,0);\r
 734             break;      \r
 735         }\r
 736         case RK30_PIN4_PB7:\r
 737         {\r
 738              rk30_mux_api_set(GPIO4B7_SPI0CSN1_NAME,0);\r
 739             break;      \r
 740         }\r
 741         case RK30_PIN4_PC0:\r
 742         {\r
 743              rk30_mux_api_set(GPIO4C0_SMCDATA0_TRACEDATA0_NAME,0);\r
 744             break;      \r
 745         }\r
 746         case RK30_PIN4_PC1:\r
 747         {\r
 748              rk30_mux_api_set(GPIO4C1_SMCDATA1_TRACEDATA1_NAME,0);\r
 749             break;      \r
 750         }\r
 751         case RK30_PIN4_PC2:\r
 752         {\r
 753              rk30_mux_api_set(GPIO4C2_SMCDATA2_TRACEDATA2_NAME,0);\r
 754             break;      \r
 755         }\r
 756         case RK30_PIN4_PC3:\r
 757         {\r
 758              rk30_mux_api_set(GPIO4C3_SMCDATA3_TRACEDATA3_NAME,0);\r
 759             break;      \r
 760         }\r
 761         case RK30_PIN4_PC4:\r
 762         {\r
 763              rk30_mux_api_set(GPIO4C4_SMCDATA4_TRACEDATA4_NAME,0);\r
 764             break;      \r
 765         }\r
 766         case RK30_PIN4_PC5:\r
 767         {\r
 768              rk30_mux_api_set(GPIO4C5_SMCDATA5_TRACEDATA5_NAME,0);\r
 769             break;      \r
 770         }\r
 771         case RK30_PIN4_PC6:\r
 772         {\r
 773              rk30_mux_api_set(GPIO4C6_SMCDATA6_TRACEDATA6_NAME,0);\r
 774             break;      \r
 775         }\r
 776 \r
 777 \r
 778         case RK30_PIN4_PC7:\r
 779         {\r
 780              rk30_mux_api_set(GPIO4C7_SMCDATA7_TRACEDATA7_NAME,0);\r
 781             break;      \r
 782         }\r
 783         case RK30_PIN4_PD0:\r
 784             {\r
 785                      rk30_mux_api_set(GPIO4D0_SMCDATA8_TRACEDATA8_NAME,0);                         \r
 786                      break;     \r
 787             }\r
 788         case RK30_PIN4_PD1:\r
 789         {\r
 790              rk30_mux_api_set(GPIO4D1_SMCDATA9_TRACEDATA9_NAME,0);             \r
 791              break;     \r
 792         }\r
 793         case RK30_PIN4_PD2:\r
 794             {\r
 795                      rk30_mux_api_set(GPIO4D2_SMCDATA10_TRACEDATA10_NAME,0);                                \r
 796                      break;     \r
 797             }\r
 798         case RK30_PIN4_PD3:\r
 799         {\r
 800              rk30_mux_api_set(GPIO4D3_SMCDATA11_TRACEDATA11_NAME,0);           \r
 801              break;     \r
 802         }\r
 803         case RK30_PIN4_PD4:\r
 804         {\r
 805              rk30_mux_api_set(GPIO4D4_SMCDATA12_TRACEDATA12_NAME,0);\r
 806             break;      \r
 807         }\r
 808         case RK30_PIN4_PD5:\r
 809         {\r
 810              rk30_mux_api_set(GPIO4D5_SMCDATA13_TRACEDATA13_NAME,0);\r
 811             break;      \r
 812         }\r
 813         case RK30_PIN4_PD6:\r
 814         {\r
 815              rk30_mux_api_set(GPIO4D6_SMCDATA14_TRACEDATA14_NAME,0);\r
 816             break;      \r
 817         }\r
 818         case RK30_PIN4_PD7:\r
 819         {\r
 820              rk30_mux_api_set(GPIO4D7_SMCDATA15_TRACEDATA15_NAME,0);\r
 821             break;      \r
 822         } \r
 823         case RK30_PIN6_PA0:\r
 824         case RK30_PIN6_PA1:\r
 825         case RK30_PIN6_PA2:\r
 826         case RK30_PIN6_PA3:\r
 827         case RK30_PIN6_PA4:\r
 828         case RK30_PIN6_PA5:\r
 829         case RK30_PIN6_PA6:\r
 830         case RK30_PIN6_PA7:\r
 831         case RK30_PIN6_PB0:\r
 832         case RK30_PIN6_PB1:\r
 833         case RK30_PIN6_PB2:\r
 834         case RK30_PIN6_PB3:\r
 835         case RK30_PIN6_PB4:\r
 836         case RK30_PIN6_PB5:\r
 837         case RK30_PIN6_PB6:\r
 838                         break;\r
 839         case RK30_PIN6_PB7:\r
 840                 {\r
 841                          rk30_mux_api_set(GPIO6B7_TESTCLOCKOUT_NAME,0);\r
 842                         break;  \r
 843                 } \r
 844         default:\r
 845         {\r
 846             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
 847             break;\r
 848         }\r
 849     }\r
 850 #elif defined(CONFIG_ARCH_RK31)\r
 851     switch (pin)\r
 852     {\r
 853         case RK30_PIN0_PA0:\r
 854         case RK30_PIN0_PA1: \r
 855                 case RK30_PIN0_PA2:\r
 856                 case RK30_PIN0_PA3:\r
 857                 case RK30_PIN0_PA4:\r
 858                 case RK30_PIN0_PA5:\r
 859                 case RK30_PIN0_PA6:\r
 860         case RK30_PIN0_PA7:\r
 861         case RK30_PIN0_PB0:\r
 862         case RK30_PIN0_PB1:\r
 863         case RK30_PIN0_PB2:\r
 864         case RK30_PIN0_PB3:\r
 865         case RK30_PIN0_PB4:\r
 866         case RK30_PIN0_PB5:\r
 867         case RK30_PIN0_PB6:\r
 868         case RK30_PIN0_PB7:\r
 869         case RK30_PIN0_PC0:\r
 870         {\r
 871              rk30_mux_api_set(GPIO0C0_FLASHDATA8_NAME,0);\r
 872             break;      \r
 873         }\r
 874         case RK30_PIN0_PC1:\r
 875         {\r
 876              rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME,0);\r
 877             break;      \r
 878         }\r
 879         case RK30_PIN0_PC2:\r
 880         {\r
 881              rk30_mux_api_set(GPIO0C2_FLASHDATA10_NAME,0);\r
 882             break;      \r
 883         }\r
 884         case RK30_PIN0_PC3:\r
 885         {\r
 886              rk30_mux_api_set(GPIO0C3_FLASHDATA11_NAME,0);\r
 887             break;      \r
 888         }\r
 889         case RK30_PIN0_PC4:\r
 890         {\r
 891              rk30_mux_api_set(GPIO0C4_FLASHDATA12_NAME,0);\r
 892             break;      \r
 893         }\r
 894         case RK30_PIN0_PC5:\r
 895         {\r
 896              rk30_mux_api_set(GPIO0C5_FLASHDATA13_NAME,0);\r
 897             break;      \r
 898         }\r
 899         case RK30_PIN0_PC6:\r
 900         {\r
 901              rk30_mux_api_set(GPIO0C6_FLASHDATA14_NAME,0);\r
 902             break;      \r
 903         }\r
 904         case RK30_PIN0_PC7:\r
 905         {\r
 906              rk30_mux_api_set(GPIO0C7_FLASHDATA15_NAME,0);\r
 907             break;      \r
 908         }\r
 909         case RK30_PIN0_PD0:\r
 910         {\r
 911              rk30_mux_api_set(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,0);\r
 912             break;      \r
 913         }\r
 914         case RK30_PIN0_PD1:\r
 915         {\r
 916              rk30_mux_api_set(GPIO0D1_FLASHCSN1_NAME,0);\r
 917             break;      \r
 918         }\r
 919         case RK30_PIN0_PD2:\r
 920         {\r
 921              rk30_mux_api_set(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,0);\r
 922             break;      \r
 923         }\r
 924         case RK30_PIN0_PD3:\r
 925         {\r
 926              rk30_mux_api_set(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME,0);\r
 927             break;      \r
 928         }\r
 929         case RK30_PIN0_PD4:\r
 930         {\r
 931              rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME,0);\r
 932             break;      \r
 933         }\r
 934         case RK30_PIN0_PD5:\r
 935         {\r
 936              rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME,0);\r
 937             break;      \r
 938         }\r
 939         case RK30_PIN0_PD6:\r
 940         {\r
 941              rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME,0);\r
 942             break;      \r
 943         }\r
 944         case RK30_PIN0_PD7:\r
 945         {\r
 946              rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME,0);\r
 947             break;      \r
 948         }\r
 949         case RK30_PIN1_PA0:\r
 950         {\r
 951              rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);\r
 952             break;      \r
 953         }\r
 954         case RK30_PIN1_PA1:\r
 955         {\r
 956              rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);\r
 957             break;      \r
 958         }\r
 959         case RK30_PIN1_PA2:\r
 960         {\r
 961              rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);\r
 962             break;      \r
 963         }\r
 964         case RK30_PIN1_PA3:\r
 965         {\r
 966              rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);\r
 967             break;      \r
 968         }\r
 969         case RK30_PIN1_PA4:\r
 970         {\r
 971              rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME,0);\r
 972             break;      \r
 973         }\r
 974         case RK30_PIN1_PA5:\r
 975         {\r
 976              rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME,0);\r
 977             break;      \r
 978         }\r
 979         case RK30_PIN1_PA6:\r
 980         {\r
 981              rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME,0);\r
 982             break;      \r
 983         }\r
 984         case RK30_PIN1_PA7:\r
 985         {\r
 986              rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME,0);\r
 987             break;      \r
 988         }\r
 989         case RK30_PIN1_PB0:\r
 990         {\r
 991              rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME,0);\r
 992             break;      \r
 993         }\r
 994         case RK30_PIN1_PB1:\r
 995         {\r
 996              rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME,0);\r
 997             break;      \r
 998         }\r
 999         case RK30_PIN1_PB2:\r
1000         {\r
1001              rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME,0);\r
1002             break;      \r
1003         }\r
1004         case RK30_PIN1_PB3:\r
1005         {\r
1006              rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME,0);\r
1007             break;      \r
1008         }\r
1009         case RK30_PIN1_PB4:\r
1010         {\r
1011              rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME,0);\r
1012             break;      \r
1013         }\r
1014         case RK30_PIN1_PB5:\r
1015         {\r
1016              rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME,0);\r
1017             break;      \r
1018         }\r
1019         case RK30_PIN1_PB6:\r
1020         {\r
1021              rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME,0);\r
1022             break;      \r
1023         }\r
1024         case RK30_PIN1_PB7:\r
1025         {\r
1026              rk30_mux_api_set(GPIO1B7_SPI0CSN1_NAME,0);\r
1027             break;      \r
1028         }\r
1029         case RK30_PIN1_PC0:\r
1030         {\r
1031              rk30_mux_api_set(GPIO1C0_I2SCLK_NAME,0);\r
1032             break;      \r
1033         }\r
1034         case RK30_PIN1_PC1:\r
1035         {\r
1036              rk30_mux_api_set(GPIO1C1_I2SSCLK_NAME,0);\r
1037             break;      \r
1038         }\r
1039         case RK30_PIN1_PC2:\r
1040         {\r
1041              rk30_mux_api_set(GPIO1C2_I2SLRCLKRX_NAME,0);\r
1042             break;      \r
1043         }\r
1044         case RK30_PIN1_PC3:\r
1045         {\r
1046              rk30_mux_api_set(GPIO1C3_I2SLRCLKTX_NAME,0);\r
1047             break;      \r
1048         }\r
1049         case RK30_PIN1_PC4:\r
1050         {\r
1051              rk30_mux_api_set(GPIO1C4_I2SSDI_NAME,0);\r
1052             break;      \r
1053         }\r
1054         case RK30_PIN1_PC5:\r
1055         case RK30_PIN1_PC6:\r
1056         case RK30_PIN1_PC7:\r
1057             break;      \r
1058         case RK30_PIN1_PD0:\r
1059         {\r
1060              rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME,0);\r
1061             break;      \r
1062         }\r
1063         case RK30_PIN1_PD1:\r
1064         {\r
1065              rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME,0);\r
1066             break;      \r
1067         }\r
1068         case RK30_PIN1_PD2:\r
1069         {\r
1070              rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME,0);\r
1071             break;      \r
1072         }\r
1073         case RK30_PIN1_PD3:\r
1074         {\r
1075              rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME,0);\r
1076             break;      \r
1077         }\r
1078         case RK30_PIN1_PD4:\r
1079         {\r
1080              rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME,0);\r
1081             break;      \r
1082         }\r
1083         case RK30_PIN1_PD5:\r
1084         {\r
1085              rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME,0);\r
1086             break;      \r
1087         }\r
1088         case RK30_PIN1_PD6:\r
1089         {\r
1090              rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME,0);\r
1091             break;      \r
1092         }\r
1093         case RK30_PIN1_PD7:\r
1094         {\r
1095              rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME,0);\r
1096             break;      \r
1097         }\r
1098         case RK30_PIN2_PA0:\r
1099         {\r
1100              rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,0);\r
1101             break;      \r
1102         }\r
1103         case RK30_PIN2_PA1:\r
1104         {\r
1105              rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,0);\r
1106             break;      \r
1107         }\r
1108         case RK30_PIN2_PA2:\r
1109         {\r
1110              rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,0);\r
1111             break;      \r
1112         }\r
1113         case RK30_PIN2_PA3:\r
1114         {\r
1115              rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,0);\r
1116             break;      \r
1117         }\r
1118         case RK30_PIN2_PA4:\r
1119         {\r
1120              rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,0);\r
1121             break;      \r
1122         }\r
1123         case RK30_PIN2_PA5:\r
1124         {\r
1125              rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,0);\r
1126             break;      \r
1127         }\r
1128         case RK30_PIN2_PA6:\r
1129         {\r
1130              rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,0);\r
1131             break;      \r
1132         }\r
1133         case RK30_PIN2_PA7:\r
1134         {\r
1135              rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,0);\r
1136             break;      \r
1137         }\r
1138         case RK30_PIN2_PB0:\r
1139         {\r
1140              rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,0);\r
1141             break;      \r
1142         }\r
1143         case RK30_PIN2_PB1:\r
1144         {\r
1145              rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,0);\r
1146             break;      \r
1147         }\r
1148         case RK30_PIN2_PB2:\r
1149         {\r
1150              rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,0);\r
1151             break;      \r
1152         }\r
1153         case RK30_PIN2_PB3:\r
1154         {\r
1155              rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,0);\r
1156             break;      \r
1157         }\r
1158         case RK30_PIN2_PB4:\r
1159         {\r
1160              rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,0);\r
1161             break;      \r
1162         }\r
1163         case RK30_PIN2_PB5:\r
1164         {\r
1165              rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,0);\r
1166             break;      \r
1167         }\r
1168         case RK30_PIN2_PB6:\r
1169         {\r
1170              rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,0);\r
1171             break;      \r
1172         }\r
1173         case RK30_PIN2_PB7:\r
1174         {\r
1175              rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,0);\r
1176             break;      \r
1177         }\r
1178         case RK30_PIN2_PC0:\r
1179         {\r
1180              rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,0);\r
1181             break;      \r
1182         }\r
1183         case RK30_PIN2_PC1:\r
1184         {\r
1185              rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,0);\r
1186             break;      \r
1187         }\r
1188         case RK30_PIN2_PC2:\r
1189         {\r
1190              rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,0);\r
1191             break;      \r
1192         }\r
1193         case RK30_PIN2_PC3:\r
1194         {\r
1195              rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,0);\r
1196             break;      \r
1197         }\r
1198         case RK30_PIN2_PC4:\r
1199         {\r
1200              rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,0);\r
1201             break;      \r
1202         }\r
1203         case RK30_PIN2_PC5:\r
1204         {\r
1205              rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,0);\r
1206             break;      \r
1207         }\r
1208         case RK30_PIN2_PC6:\r
1209         {\r
1210              rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,0);\r
1211             break;      \r
1212         }\r
1213         case RK30_PIN2_PC7:\r
1214         {\r
1215              rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,0);\r
1216             break;      \r
1217         }\r
1218         case RK30_PIN2_PD0:\r
1219         {\r
1220              rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,0);\r
1221             break;      \r
1222         }\r
1223         case RK30_PIN2_PD1:\r
1224         {\r
1225              rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,0);\r
1226             break;      \r
1227         }\r
1228         case RK30_PIN2_PD2:\r
1229         {\r
1230              rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,0);\r
1231             break;      \r
1232         }\r
1233         case RK30_PIN2_PD3:\r
1234         {\r
1235              rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,0);\r
1236             break;      \r
1237         }\r
1238         case RK30_PIN2_PD4:\r
1239         {\r
1240              rk30_mux_api_set(GPIO2D4_SMCBLSN0_NAME,0);\r
1241             break;      \r
1242         }\r
1243         case RK30_PIN2_PD5:\r
1244         {\r
1245              rk30_mux_api_set(GPIO2D5_SMCBLSN1_NAME,0);\r
1246             break;      \r
1247         }\r
1248         case RK30_PIN2_PD6:\r
1249         {\r
1250              rk30_mux_api_set(GPIO2D6_SMCCSN1_NAME,0);\r
1251             break;      \r
1252         }\r
1253         case RK30_PIN2_PD7:\r
1254         {\r
1255              rk30_mux_api_set(GPIO2D7_TESTCLOCKOUT_NAME,0);\r
1256             break;      \r
1257         }\r
1258         case RK30_PIN3_PA0:\r
1259         {\r
1260              rk30_mux_api_set(GPIO3A0_SDMMC0RSTNOUT_NAME,0);\r
1261             break;      \r
1262         }\r
1263         case RK30_PIN3_PA1:\r
1264         {\r
1265              rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME,0);\r
1266             break;      \r
1267         }\r
1268         case RK30_PIN3_PA2:\r
1269         {\r
1270              rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME,0);\r
1271             break;      \r
1272         }\r
1273         case RK30_PIN3_PA3:\r
1274         {\r
1275              rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME,0);\r
1276             break;      \r
1277         }\r
1278         case RK30_PIN3_PA4:\r
1279         {\r
1280              rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME,0);\r
1281             break;      \r
1282         }\r
1283         case RK30_PIN3_PA5:\r
1284         {\r
1285              rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME,0);\r
1286             break;      \r
1287         }\r
1288         case RK30_PIN3_PA6:\r
1289         {\r
1290              rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME,0);\r
1291             break;      \r
1292         }\r
1293         case RK30_PIN3_PA7:\r
1294         {\r
1295              rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME,0);\r
1296             break;      \r
1297         }\r
1298         case RK30_PIN3_PB0:\r
1299         {\r
1300              rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME,0);\r
1301             break;      \r
1302         }\r
1303         case RK30_PIN3_PB1:\r
1304         {\r
1305              rk30_mux_api_set(GPIO3B1_SDMMC0WRITEPRT_NAME,0);\r
1306             break;      \r
1307         }\r
1308         case RK30_PIN3_PB2:        \r
1309             break;\r
1310         case RK30_PIN3_PB3:\r
1311         {\r
1312              rk30_mux_api_set(GPIO3B3_CIFCLKOUT_NAME,0);\r
1313             break;      \r
1314         }\r
1315         case RK30_PIN3_PB4:\r
1316         {\r
1317              rk30_mux_api_set(GPIO3B4_CIFDATA0_HSADCDATA8_NAME,0);\r
1318             break;      \r
1319         }\r
1320         case RK30_PIN3_PB5:\r
1321         {\r
1322              rk30_mux_api_set(GPIO3B5_CIFDATA1_HSADCDATA9_NAME,0);\r
1323             break;      \r
1324         }\r
1325         case RK30_PIN3_PB6:\r
1326         {\r
1327              rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME,0);\r
1328             break;      \r
1329         }\r
1330         case RK30_PIN3_PB7:\r
1331         {\r
1332              rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME,0);\r
1333             break;      \r
1334         }\r
1335         case RK30_PIN3_PC0:\r
1336         {\r
1337              rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,0);\r
1338             break;      \r
1339         }\r
1340         case RK30_PIN3_PC1:\r
1341         {\r
1342              rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,0);\r
1343             break;      \r
1344         }\r
1345         case RK30_PIN3_PC2:\r
1346         {\r
1347              rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,0);\r
1348             break;      \r
1349         }\r
1350         case RK30_PIN3_PC3:\r
1351         {\r
1352              rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,0);\r
1353             break;      \r
1354         }\r
1355         case RK30_PIN3_PC4:\r
1356         {\r
1357              rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,0);\r
1358             break;      \r
1359         }\r
1360         case RK30_PIN3_PC5:\r
1361         {\r
1362              rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,0);\r
1363             break;      \r
1364         }\r
1365         case RK30_PIN3_PC6:\r
1366         {\r
1367              rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME,0);\r
1368             break;      \r
1369         }\r
1370         case RK30_PIN3_PC7:\r
1371         {\r
1372              rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME,0);\r
1373             break;      \r
1374         }\r
1375         case RK30_PIN3_PD0:\r
1376         {\r
1377              rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME,0);\r
1378             break;      \r
1379         }\r
1380         case RK30_PIN3_PD1:\r
1381         {\r
1382              rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME,0);\r
1383             break;      \r
1384         }\r
1385         case RK30_PIN3_PD2:\r
1386         {\r
1387              rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);\r
1388             break;      \r
1389         }\r
1390         case RK30_PIN3_PD3:\r
1391         {\r
1392              rk30_mux_api_set(GPIO3D3_PWM0_NAME,0);\r
1393             break;      \r
1394         }\r
1395         case RK30_PIN3_PD4:\r
1396         {\r
1397              rk30_mux_api_set(GPIO3D4_PWM1_JTAGTRSTN_NAME,0);\r
1398             break;      \r
1399         }\r
1400         case RK30_PIN3_PD5:\r
1401         {\r
1402              rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME,0);\r
1403             break;      \r
1404         }\r
1405         case RK30_PIN3_PD6:\r
1406         {\r
1407              rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME,0);\r
1408             break;      \r
1409         }\r
1410         case RK30_PIN3_PD7:        \r
1411             break;        \r
1412         default:\r
1413         {\r
1414             printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);\r
1415             break;\r
1416         }\r
1417     }\r
1418 \r
1419 #endif\r
1420     return 0;\r
1421 }\r
1422 #define PMEM_CAM_BASE 0 //just for compile ,no meaning\r
1423 #include "../../../arch/arm/plat-rk/rk_camera.c"\r
1424 \r
1425 \r
1426 \r
1427 static u64 rockchip_device_camera_dmamask = 0xffffffffUL;\r
1428 #if RK_SUPPORT_CIF0\r
1429 static struct resource rk_camera_resource_host_0[] = {\r
1430         [0] = {\r
1431                 .start = RK30_CIF0_PHYS,\r
1432                 .end   = RK30_CIF0_PHYS + RK30_CIF0_SIZE - 1,\r
1433                 .flags = IORESOURCE_MEM,\r
1434         },\r
1435         [1] = {\r
1436                 .start = IRQ_CIF0,\r
1437                 .end   = IRQ_CIF0,\r
1438                 .flags = IORESOURCE_IRQ,\r
1439         }\r
1440 };\r
1441 #endif\r
1442 #if RK_SUPPORT_CIF1\r
1443 static struct resource rk_camera_resource_host_1[] = {\r
1444         [0] = {\r
1445                 .start = RK30_CIF1_PHYS,\r
1446                 .end   = RK30_CIF1_PHYS + RK30_CIF1_SIZE - 1,\r
1447                 .flags = IORESOURCE_MEM,\r
1448         },\r
1449         [1] = {\r
1450                 .start = IRQ_CIF1,\r
1451                 .end   = IRQ_CIF1,\r
1452                 .flags = IORESOURCE_IRQ,\r
1453         }\r
1454 };\r
1455 #endif\r
1456 \r
1457 /*platform_device : */\r
1458 #if RK_SUPPORT_CIF0\r
1459  struct platform_device rk_device_camera_host_0 = {\r
1460         .name             = RK29_CAM_DRV_NAME,\r
1461         .id       = RK_CAM_PLATFORM_DEV_ID_0,                           /* This is used to put cameras on this interface */\r
1462         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_0),\r
1463         .resource         = rk_camera_resource_host_0,\r
1464         .dev                    = {\r
1465                 .dma_mask = &rockchip_device_camera_dmamask,\r
1466                 .coherent_dma_mask = 0xffffffffUL,\r
1467                 .platform_data  = &rk_camera_platform_data,\r
1468         }\r
1469 };\r
1470 #endif\r
1471 \r
1472 #if RK_SUPPORT_CIF1\r
1473 /*platform_device : */\r
1474  struct platform_device rk_device_camera_host_1 = {\r
1475         .name             = RK29_CAM_DRV_NAME,\r
1476         .id       = RK_CAM_PLATFORM_DEV_ID_1,                           /* This is used to put cameras on this interface */\r
1477         .num_resources    = ARRAY_SIZE(rk_camera_resource_host_1),\r
1478         .resource         = rk_camera_resource_host_1,\r
1479         .dev                    = {\r
1480                 .dma_mask = &rockchip_device_camera_dmamask,\r
1481                 .coherent_dma_mask = 0xffffffffUL,\r
1482                 .platform_data  = &rk_camera_platform_data,\r
1483         }\r
1484 };\r
1485 #endif\r
1486 \r
1487 static void rk_init_camera_plateform_data(void)\r
1488 {\r
1489     int i,dev_idx;\r
1490     \r
1491     dev_idx = 0;\r
1492     for (i=0; i<RK_CAM_NUM; i++) {\r
1493         rk_camera_platform_data.sensor_init_data[i] = &rk_init_data_sensor[i];\r
1494         if (rk_camera_platform_data.register_dev[i].device_info.name) {            \r
1495             rk_camera_platform_data.register_dev[i].link_info.board_info = \r
1496                 &rk_camera_platform_data.register_dev[i].i2c_cam_info;\r
1497             rk_camera_platform_data.register_dev[i].device_info.id = dev_idx;\r
1498             rk_camera_platform_data.register_dev[i].device_info.dev.platform_data = \r
1499                 &rk_camera_platform_data.register_dev[i].link_info;\r
1500             dev_idx++;\r
1501         }\r
1502     }\r
1503 }\r
1504 \r
1505 static void rk30_camera_request_reserve_mem(void)\r
1506 {\r
1507 #ifdef CONFIG_VIDEO_RK29_WORK_IPP    \r
1508     #if defined(CONFIG_VIDEO_RKCIF_WORK_SIMUL_OFF) || ((RK_SUPPORT_CIF0 && RK_SUPPORT_CIF1) == false)\r
1509         rk_camera_platform_data.meminfo.name = "camera_ipp_mem";\r
1510         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem",PMEM_CAMIPP_NECESSARY);\r
1511         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY;\r
1512 \r
1513         memcpy(&rk_camera_platform_data.meminfo_cif1,&rk_camera_platform_data.meminfo,sizeof(struct rk29camera_mem_res));\r
1514     #else\r
1515         rk_camera_platform_data.meminfo.name = "camera_ipp_mem_0";\r
1516         rk_camera_platform_data.meminfo.start = board_mem_reserve_add("camera_ipp_mem_0",PMEM_CAMIPP_NECESSARY_CIF_0);\r
1517         rk_camera_platform_data.meminfo.size= PMEM_CAMIPP_NECESSARY_CIF_0;\r
1518         \r
1519         rk_camera_platform_data.meminfo_cif1.name = "camera_ipp_mem_1";\r
1520         rk_camera_platform_data.meminfo_cif1.start =board_mem_reserve_add("camera_ipp_mem_1",PMEM_CAMIPP_NECESSARY_CIF_1);\r
1521         rk_camera_platform_data.meminfo_cif1.size= PMEM_CAMIPP_NECESSARY_CIF_1;\r
1522     #endif\r
1523  #endif\r
1524  #if PMEM_CAM_NECESSARY\r
1525         android_pmem_cam_pdata.start = board_mem_reserve_add((char*)(android_pmem_cam_pdata.name),PMEM_CAM_NECESSARY);\r
1526         android_pmem_cam_pdata.size= PMEM_CAM_NECESSARY;\r
1527  #endif\r
1528 \r
1529 }\r
1530 static int rk_register_camera_devices(void)\r
1531 {\r
1532     int i;\r
1533     int host_registered_0,host_registered_1;\r
1534     \r
1535         rk_init_camera_plateform_data();\r
1536 \r
1537     host_registered_0 = 0;\r
1538     host_registered_1 = 0;\r
1539     for (i=0; i<RK_CAM_NUM; i++) {\r
1540         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1541             \r
1542             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_0) {\r
1543             #if RK_SUPPORT_CIF0\r
1544                 if (!host_registered_0) {\r
1545                     platform_device_register(&rk_device_camera_host_0);\r
1546                     host_registered_0 = 1;\r
1547                 }\r
1548             #else\r
1549                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF0, Please user check ...\n",__FUNCTION__,__LINE__);\r
1550             #endif\r
1551             } \r
1552 \r
1553             if (rk_camera_platform_data.register_dev[i].link_info.bus_id == RK_CAM_PLATFORM_DEV_ID_1) {\r
1554             #if RK_SUPPORT_CIF1\r
1555                 if (!host_registered_1) {\r
1556                     platform_device_register(&rk_device_camera_host_1);\r
1557                     host_registered_1 = 1;\r
1558                 }\r
1559             #else\r
1560                 printk(KERN_ERR "%s(%d) : This chip isn't support CIF1, Please user check ...\n",__FUNCTION__,__LINE__);\r
1561             #endif\r
1562             } \r
1563         }\r
1564     }\r
1565 \r
1566     for (i=0; i<RK_CAM_NUM; i++) {\r
1567         if (rk_camera_platform_data.register_dev[i].device_info.name) {\r
1568             platform_device_register(&rk_camera_platform_data.register_dev[i].device_info);\r
1569         }\r
1570     }\r
1571  #if PMEM_CAM_NECESSARY\r
1572     platform_device_register(&android_pmem_cam_device);\r
1573  #endif\r
1574         return 0;\r
1575 }\r
1576 \r
1577 module_init(rk_register_camera_devices);\r
1578 #endif\r
1579 \r
1580 #endif //#ifdef CONFIG_VIDEO_RK\r