2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
25 #include <linux/moduleparam.h>
26 #include <linux/time.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/clk.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf2-core.h>
35 #include <media/videobuf2-dma-contig.h>
36 #include <media/soc_camera.h>
37 #include <media/soc_mediabus.h>
39 #include <linux/videodev2.h>
41 #include <mach/mx2_cam.h>
42 #include <mach/hardware.h>
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51 #define CSICR1_RESET_VAL 0x40000800
52 #define CSICR2_RESET_VAL 0x0
53 #define CSICR3_RESET_VAL 0x0
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN (1 << 31)
57 #define CSICR1_EXT_VSYNC (1 << 30)
58 #define CSICR1_EOF_INTEN (1 << 29)
59 #define CSICR1_PRP_IF_EN (1 << 28)
60 #define CSICR1_CCIR_MODE (1 << 27)
61 #define CSICR1_COF_INTEN (1 << 26)
62 #define CSICR1_SF_OR_INTEN (1 << 25)
63 #define CSICR1_RF_OR_INTEN (1 << 24)
64 #define CSICR1_STATFF_LEVEL (3 << 22)
65 #define CSICR1_STATFF_INTEN (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
67 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
68 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
69 #define CSICR1_RXFF_INTEN (1 << 18)
70 #define CSICR1_SOF_POL (1 << 17)
71 #define CSICR1_SOF_INTEN (1 << 16)
72 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
73 #define CSICR1_HSYNC_POL (1 << 11)
74 #define CSICR1_CCIR_EN (1 << 10)
75 #define CSICR1_MCLKEN (1 << 9)
76 #define CSICR1_FCC (1 << 8)
77 #define CSICR1_PACK_DIR (1 << 7)
78 #define CSICR1_CLR_STATFIFO (1 << 6)
79 #define CSICR1_CLR_RXFIFO (1 << 5)
80 #define CSICR1_GCLK_MODE (1 << 4)
81 #define CSICR1_INV_DATA (1 << 3)
82 #define CSICR1_INV_PCLK (1 << 2)
83 #define CSICR1_REDGE (1 << 1)
85 #define SHIFT_STATFF_LEVEL 22
86 #define SHIFT_RXFF_LEVEL 19
87 #define SHIFT_MCLKDIV 12
90 #define CSICR3_FRMCNT (0xFFFF << 16)
91 #define CSICR3_FRMCNT_RST (1 << 15)
92 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
93 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
94 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
95 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
96 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
97 #define CSICR3_CSI_SUP (1 << 3)
98 #define CSICR3_ZERO_PACK_EN (1 << 2)
99 #define CSICR3_ECC_INT_EN (1 << 1)
100 #define CSICR3_ECC_AUTO_EN (1 << 0)
102 #define SHIFT_FRMCNT 16
105 #define CSISR_SFF_OR_INT (1 << 25)
106 #define CSISR_RFF_OR_INT (1 << 24)
107 #define CSISR_STATFF_INT (1 << 21)
108 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
109 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
110 #define CSISR_RXFF_INT (1 << 18)
111 #define CSISR_EOF_INT (1 << 17)
112 #define CSISR_SOF_INT (1 << 16)
113 #define CSISR_F2_INT (1 << 15)
114 #define CSISR_F1_INT (1 << 14)
115 #define CSISR_COF_INT (1 << 13)
116 #define CSISR_ECC_INT (1 << 1)
117 #define CSISR_DRDY (1 << 0)
121 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
122 #define CSISTATFIFO 0x0c
123 #define CSIRFIFO 0x10
124 #define CSIRXCNT 0x14
125 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
126 #define CSIDMASA_STATFIFO 0x20
127 #define CSIDMATA_STATFIFO 0x24
128 #define CSIDMASA_FB1 0x28
129 #define CSIDMASA_FB2 0x2c
130 #define CSIFBUF_PARA 0x30
131 #define CSIIMAG_PARA 0x34
134 #define PRP_CNTL 0x00
135 #define PRP_INTR_CNTL 0x04
136 #define PRP_INTRSTATUS 0x08
137 #define PRP_SOURCE_Y_PTR 0x0c
138 #define PRP_SOURCE_CB_PTR 0x10
139 #define PRP_SOURCE_CR_PTR 0x14
140 #define PRP_DEST_RGB1_PTR 0x18
141 #define PRP_DEST_RGB2_PTR 0x1c
142 #define PRP_DEST_Y_PTR 0x20
143 #define PRP_DEST_CB_PTR 0x24
144 #define PRP_DEST_CR_PTR 0x28
145 #define PRP_SRC_FRAME_SIZE 0x2c
146 #define PRP_DEST_CH1_LINE_STRIDE 0x30
147 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
148 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
149 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
150 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
151 #define PRP_SRC_LINE_STRIDE 0x44
152 #define PRP_CSC_COEF_012 0x48
153 #define PRP_CSC_COEF_345 0x4c
154 #define PRP_CSC_COEF_678 0x50
155 #define PRP_CH1_RZ_HORI_COEF1 0x54
156 #define PRP_CH1_RZ_HORI_COEF2 0x58
157 #define PRP_CH1_RZ_HORI_VALID 0x5c
158 #define PRP_CH1_RZ_VERT_COEF1 0x60
159 #define PRP_CH1_RZ_VERT_COEF2 0x64
160 #define PRP_CH1_RZ_VERT_VALID 0x68
161 #define PRP_CH2_RZ_HORI_COEF1 0x6c
162 #define PRP_CH2_RZ_HORI_COEF2 0x70
163 #define PRP_CH2_RZ_HORI_VALID 0x74
164 #define PRP_CH2_RZ_VERT_COEF1 0x78
165 #define PRP_CH2_RZ_VERT_COEF2 0x7c
166 #define PRP_CH2_RZ_VERT_VALID 0x80
168 #define PRP_CNTL_CH1EN (1 << 0)
169 #define PRP_CNTL_CH2EN (1 << 1)
170 #define PRP_CNTL_CSIEN (1 << 2)
171 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
172 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
173 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
174 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
175 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
176 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
177 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
178 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
179 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
180 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
181 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
182 #define PRP_CNTL_CH1_LEN (1 << 9)
183 #define PRP_CNTL_CH2_LEN (1 << 10)
184 #define PRP_CNTL_SKIP_FRAME (1 << 11)
185 #define PRP_CNTL_SWRST (1 << 12)
186 #define PRP_CNTL_CLKEN (1 << 13)
187 #define PRP_CNTL_WEN (1 << 14)
188 #define PRP_CNTL_CH1BYP (1 << 15)
189 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
190 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
191 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
192 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
193 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
194 #define PRP_CNTL_CH2B1EN (1 << 29)
195 #define PRP_CNTL_CH2B2EN (1 << 30)
196 #define PRP_CNTL_CH2FEN (1 << 31)
198 /* IRQ Enable and status register */
199 #define PRP_INTR_RDERR (1 << 0)
200 #define PRP_INTR_CH1WERR (1 << 1)
201 #define PRP_INTR_CH2WERR (1 << 2)
202 #define PRP_INTR_CH1FC (1 << 3)
203 #define PRP_INTR_CH2FC (1 << 5)
204 #define PRP_INTR_LBOVF (1 << 7)
205 #define PRP_INTR_CH2OVF (1 << 8)
207 #define MAX_VIDEO_MEM 16
218 /* prp configuration for a client-host fmt pair */
220 enum v4l2_mbus_pixelcode in_fmt;
222 struct mx2_prp_cfg cfg;
225 enum mx2_buffer_state {
231 struct mx2_buf_internal {
232 struct list_head queue;
237 /* buffer for one video frame */
239 /* common v4l buffer stuff -- must be first */
240 struct vb2_buffer vb;
241 enum mx2_buffer_state state;
242 struct mx2_buf_internal internal;
245 struct mx2_camera_dev {
247 struct soc_camera_host soc_host;
248 struct soc_camera_device *icd;
249 struct clk *clk_csi, *clk_emma;
251 unsigned int irq_csi, irq_emma;
252 void __iomem *base_csi, *base_emma;
253 unsigned long base_dma;
255 struct mx2_camera_platform_data *pdata;
256 struct resource *res_csi, *res_emma;
257 unsigned long platform_flags;
259 struct list_head capture;
260 struct list_head active_bufs;
261 struct list_head discard;
266 struct mx2_buffer *active;
267 struct mx2_buffer *fb1_active;
268 struct mx2_buffer *fb2_active;
272 struct mx2_buf_internal buf_discard[2];
273 void *discard_buffer;
274 dma_addr_t discard_buffer_dma;
276 struct mx2_fmt_cfg *emma_prp;
278 struct vb2_alloc_ctx *alloc_ctx;
281 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
283 return container_of(int_buf, struct mx2_buffer, internal);
286 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
288 * This is a generic configuration which is valid for most
289 * prp input-output format combinations.
290 * We set the incomming and outgoing pixelformat to a
291 * 16 Bit wide format and adjust the bytesperline
292 * accordingly. With this configuration the inputdata
293 * will not be changed by the emma and could be any type
294 * of 16 Bit Pixelformat.
301 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
302 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
303 .src_pixel = 0x2ca00565, /* RGB565 */
304 .ch1_pixel = 0x2ca00565, /* RGB565 */
305 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
306 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
310 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
311 .out_fmt = V4L2_PIX_FMT_YUV420,
314 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
315 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
316 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
317 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
318 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
324 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
325 enum v4l2_mbus_pixelcode in_fmt,
330 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
331 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
332 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
333 return &mx27_emma_prp_table[i];
335 /* If no match return the most generic configuration */
336 return &mx27_emma_prp_table[0];
339 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
340 unsigned long phys, int bufnum)
342 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
344 if (prp->cfg.channel == 1) {
345 writel(phys, pcdev->base_emma +
346 PRP_DEST_RGB1_PTR + 4 * bufnum);
348 writel(phys, pcdev->base_emma +
349 PRP_DEST_Y_PTR - 0x14 * bufnum);
350 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
351 u32 imgsize = pcdev->icd->user_height *
352 pcdev->icd->user_width;
354 writel(phys + imgsize, pcdev->base_emma +
355 PRP_DEST_CB_PTR - 0x14 * bufnum);
356 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
357 PRP_DEST_CR_PTR - 0x14 * bufnum);
362 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
366 clk_disable(pcdev->clk_csi);
367 writel(0, pcdev->base_csi + CSICR1);
369 writel(0, pcdev->base_emma + PRP_CNTL);
370 } else if (cpu_is_mx25()) {
371 spin_lock_irqsave(&pcdev->lock, flags);
372 pcdev->fb1_active = NULL;
373 pcdev->fb2_active = NULL;
374 writel(0, pcdev->base_csi + CSIDMASA_FB1);
375 writel(0, pcdev->base_csi + CSIDMASA_FB2);
376 spin_unlock_irqrestore(&pcdev->lock, flags);
381 * The following two functions absolutely depend on the fact, that
382 * there can be only one camera on mx2 camera sensor interface
384 static int mx2_camera_add_device(struct soc_camera_device *icd)
386 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
387 struct mx2_camera_dev *pcdev = ici->priv;
394 ret = clk_enable(pcdev->clk_csi);
398 csicr1 = CSICR1_MCLKEN;
401 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
402 CSICR1_RXFF_LEVEL(0);
403 } else if (cpu_is_mx27())
404 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
406 pcdev->csicr1 = csicr1;
407 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
410 pcdev->frame_count = 0;
412 dev_info(icd->parent, "Camera driver attached to camera %d\n",
418 static void mx2_camera_remove_device(struct soc_camera_device *icd)
420 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
421 struct mx2_camera_dev *pcdev = ici->priv;
423 BUG_ON(icd != pcdev->icd);
425 dev_info(icd->parent, "Camera driver detached from camera %d\n",
428 mx2_camera_deactivate(pcdev);
433 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
436 struct vb2_buffer *vb;
437 struct mx2_buffer *buf;
438 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
440 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
443 spin_lock_irqsave(&pcdev->lock, flags);
445 if (*fb_active == NULL)
448 vb = &(*fb_active)->vb;
449 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
450 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
452 do_gettimeofday(&vb->v4l2_buf.timestamp);
453 vb->v4l2_buf.sequence++;
454 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
456 if (list_empty(&pcdev->capture)) {
458 writel(0, pcdev->base_csi + fb_reg);
460 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
463 list_del(&buf->internal.queue);
464 buf->state = MX2_STATE_ACTIVE;
465 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
466 pcdev->base_csi + fb_reg);
472 spin_unlock_irqrestore(&pcdev->lock, flags);
475 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
477 struct mx2_camera_dev *pcdev = data;
478 u32 status = readl(pcdev->base_csi + CSISR);
480 if (status & CSISR_DMA_TSF_FB1_INT)
481 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
482 else if (status & CSISR_DMA_TSF_FB2_INT)
483 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
485 /* FIXME: handle CSISR_RFF_OR_INT */
487 writel(status, pcdev->base_csi + CSISR);
493 * Videobuf operations
495 static int mx2_videobuf_setup(struct vb2_queue *vq,
496 const struct v4l2_format *fmt,
497 unsigned int *count, unsigned int *num_planes,
498 unsigned int sizes[], void *alloc_ctxs[])
500 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
501 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
502 struct mx2_camera_dev *pcdev = ici->priv;
503 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
504 icd->current_fmt->host_fmt);
506 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
508 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
512 if (bytes_per_line < 0)
513 return bytes_per_line;
515 alloc_ctxs[0] = pcdev->alloc_ctx;
517 sizes[0] = bytes_per_line * icd->user_height;
522 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
523 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
530 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
532 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
533 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
534 icd->current_fmt->host_fmt);
537 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
538 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
540 if (bytes_per_line < 0)
541 return bytes_per_line;
545 * This can be useful if you want to see if we actually fill
546 * the buffer with something
548 memset((void *)vb2_plane_vaddr(vb, 0),
549 0xaa, vb2_get_plane_payload(vb, 0));
552 vb2_set_plane_payload(vb, 0, bytes_per_line * icd->user_height);
553 if (vb2_plane_vaddr(vb, 0) &&
554 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
565 static void mx2_videobuf_queue(struct vb2_buffer *vb)
567 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
568 struct soc_camera_host *ici =
569 to_soc_camera_host(icd->parent);
570 struct mx2_camera_dev *pcdev = ici->priv;
571 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
574 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
575 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
577 spin_lock_irqsave(&pcdev->lock, flags);
579 buf->state = MX2_STATE_QUEUED;
580 list_add_tail(&buf->internal.queue, &pcdev->capture);
583 u32 csicr3, dma_inten = 0;
585 if (pcdev->fb1_active == NULL) {
586 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
587 pcdev->base_csi + CSIDMASA_FB1);
588 pcdev->fb1_active = buf;
589 dma_inten = CSICR1_FB1_DMA_INTEN;
590 } else if (pcdev->fb2_active == NULL) {
591 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
592 pcdev->base_csi + CSIDMASA_FB2);
593 pcdev->fb2_active = buf;
594 dma_inten = CSICR1_FB2_DMA_INTEN;
598 list_del(&buf->internal.queue);
599 buf->state = MX2_STATE_ACTIVE;
601 csicr3 = readl(pcdev->base_csi + CSICR3);
604 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
605 pcdev->base_csi + CSICR3);
607 /* clear & enable interrupts */
608 writel(dma_inten, pcdev->base_csi + CSISR);
609 pcdev->csicr1 |= dma_inten;
610 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
613 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
614 writel(csicr3, pcdev->base_csi + CSICR3);
618 spin_unlock_irqrestore(&pcdev->lock, flags);
621 static void mx2_videobuf_release(struct vb2_buffer *vb)
623 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
624 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
625 struct mx2_camera_dev *pcdev = ici->priv;
626 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
630 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
631 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
633 switch (buf->state) {
634 case MX2_STATE_ACTIVE:
635 dev_info(icd->parent, "%s (active)\n", __func__);
637 case MX2_STATE_QUEUED:
638 dev_info(icd->parent, "%s (queued)\n", __func__);
641 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
648 * Terminate only queued but inactive buffers. Active buffers are
649 * released when they become inactive after videobuf_waiton().
651 * FIXME: implement forced termination of active buffers for mx27 and
652 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
653 * state. This requires a specific handling for each of the these DMA
657 spin_lock_irqsave(&pcdev->lock, flags);
658 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
659 if (pcdev->fb1_active == buf) {
660 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
661 writel(0, pcdev->base_csi + CSIDMASA_FB1);
662 pcdev->fb1_active = NULL;
663 } else if (pcdev->fb2_active == buf) {
664 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
665 writel(0, pcdev->base_csi + CSIDMASA_FB2);
666 pcdev->fb2_active = NULL;
668 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
670 spin_unlock_irqrestore(&pcdev->lock, flags);
673 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
676 struct soc_camera_host *ici =
677 to_soc_camera_host(icd->parent);
678 struct mx2_camera_dev *pcdev = ici->priv;
679 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
681 writel((icd->user_width << 16) | icd->user_height,
682 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
683 writel(prp->cfg.src_pixel,
684 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
685 if (prp->cfg.channel == 1) {
686 writel((icd->user_width << 16) | icd->user_height,
687 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
689 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
690 writel(prp->cfg.ch1_pixel,
691 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
692 } else { /* channel 2 */
693 writel((icd->user_width << 16) | icd->user_height,
694 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
697 /* Enable interrupts */
698 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
701 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
703 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
704 struct soc_camera_host *ici =
705 to_soc_camera_host(icd->parent);
706 struct mx2_camera_dev *pcdev = ici->priv;
707 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
708 struct vb2_buffer *vb;
709 struct mx2_buffer *buf;
718 spin_lock_irqsave(&pcdev->lock, flags);
720 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
722 buf->internal.bufnum = 0;
724 buf->state = MX2_STATE_ACTIVE;
726 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
727 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
728 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
730 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
732 buf->internal.bufnum = 1;
734 buf->state = MX2_STATE_ACTIVE;
736 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
737 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
738 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
740 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
741 icd->current_fmt->host_fmt);
742 if (bytesperline < 0)
746 * I didn't manage to properly enable/disable the prp
747 * on a per frame basis during running transfers,
748 * thus we allocate a buffer here and use it to
749 * discard frames when no buffer is available.
750 * Feel free to work on this ;)
752 pcdev->discard_size = icd->user_height * bytesperline;
753 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
754 pcdev->discard_size, &pcdev->discard_buffer_dma,
756 if (!pcdev->discard_buffer)
759 pcdev->buf_discard[0].discard = true;
760 list_add_tail(&pcdev->buf_discard[0].queue,
763 pcdev->buf_discard[1].discard = true;
764 list_add_tail(&pcdev->buf_discard[1].queue,
767 mx27_camera_emma_buf_init(icd, bytesperline);
769 if (prp->cfg.channel == 1) {
770 writel(PRP_CNTL_CH1EN |
776 PRP_CNTL_CH1_TSKIP(0) |
777 PRP_CNTL_IN_TSKIP(0),
778 pcdev->base_emma + PRP_CNTL);
780 writel(PRP_CNTL_CH2EN |
785 PRP_CNTL_CH2_TSKIP(0) |
786 PRP_CNTL_IN_TSKIP(0),
787 pcdev->base_emma + PRP_CNTL);
789 spin_unlock_irqrestore(&pcdev->lock, flags);
795 static int mx2_stop_streaming(struct vb2_queue *q)
797 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
798 struct soc_camera_host *ici =
799 to_soc_camera_host(icd->parent);
800 struct mx2_camera_dev *pcdev = ici->priv;
801 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
807 spin_lock_irqsave(&pcdev->lock, flags);
809 cntl = readl(pcdev->base_emma + PRP_CNTL);
810 if (prp->cfg.channel == 1) {
811 writel(cntl & ~PRP_CNTL_CH1EN,
812 pcdev->base_emma + PRP_CNTL);
814 writel(cntl & ~PRP_CNTL_CH2EN,
815 pcdev->base_emma + PRP_CNTL);
817 INIT_LIST_HEAD(&pcdev->capture);
818 INIT_LIST_HEAD(&pcdev->active_bufs);
819 INIT_LIST_HEAD(&pcdev->discard);
821 b = pcdev->discard_buffer;
822 pcdev->discard_buffer = NULL;
824 spin_unlock_irqrestore(&pcdev->lock, flags);
826 dma_free_coherent(ici->v4l2_dev.dev,
827 pcdev->discard_size, b, pcdev->discard_buffer_dma);
833 static struct vb2_ops mx2_videobuf_ops = {
834 .queue_setup = mx2_videobuf_setup,
835 .buf_prepare = mx2_videobuf_prepare,
836 .buf_queue = mx2_videobuf_queue,
837 .buf_cleanup = mx2_videobuf_release,
838 .start_streaming = mx2_start_streaming,
839 .stop_streaming = mx2_stop_streaming,
842 static int mx2_camera_init_videobuf(struct vb2_queue *q,
843 struct soc_camera_device *icd)
845 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
846 q->io_modes = VB2_MMAP | VB2_USERPTR;
848 q->ops = &mx2_videobuf_ops;
849 q->mem_ops = &vb2_dma_contig_memops;
850 q->buf_struct_size = sizeof(struct mx2_buffer);
852 return vb2_queue_init(q);
855 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
856 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
857 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
858 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
859 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
860 V4L2_MBUS_PCLK_SAMPLE_RISING | \
861 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
862 V4L2_MBUS_DATA_ACTIVE_HIGH | \
863 V4L2_MBUS_DATA_ACTIVE_LOW)
865 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
870 cntl = readl(pcdev->base_emma + PRP_CNTL);
871 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
872 while (count++ < 100) {
873 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
882 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
884 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
885 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
886 struct mx2_camera_dev *pcdev = ici->priv;
887 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
888 unsigned long common_flags;
891 u32 csicr1 = pcdev->csicr1;
893 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
895 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
897 dev_warn(icd->parent,
898 "Flags incompatible: camera 0x%x, host 0x%x\n",
899 cfg.flags, MX2_BUS_FLAGS);
902 } else if (ret != -ENOIOCTLCMD) {
905 common_flags = MX2_BUS_FLAGS;
908 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
909 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
910 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
911 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
913 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
916 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
917 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
918 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
919 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
921 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
924 cfg.flags = common_flags;
925 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
926 if (ret < 0 && ret != -ENOIOCTLCMD) {
927 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
932 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
933 csicr1 |= CSICR1_REDGE;
934 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
935 csicr1 |= CSICR1_SOF_POL;
936 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
937 csicr1 |= CSICR1_HSYNC_POL;
938 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
939 csicr1 |= CSICR1_SWAP16_EN;
940 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
941 csicr1 |= CSICR1_EXT_VSYNC;
942 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
943 csicr1 |= CSICR1_CCIR_EN;
944 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
945 csicr1 |= CSICR1_CCIR_MODE;
946 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
947 csicr1 |= CSICR1_GCLK_MODE;
948 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
949 csicr1 |= CSICR1_INV_DATA;
950 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
951 csicr1 |= CSICR1_PACK_DIR;
953 pcdev->csicr1 = csicr1;
955 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
956 icd->current_fmt->host_fmt);
957 if (bytesperline < 0)
961 ret = mx27_camera_emma_prp_reset(pcdev);
964 } else if (cpu_is_mx25()) {
965 writel((bytesperline * icd->user_height) >> 2,
966 pcdev->base_csi + CSIRXCNT);
967 writel((bytesperline << 16) | icd->user_height,
968 pcdev->base_csi + CSIIMAG_PARA);
971 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
976 static int mx2_camera_set_crop(struct soc_camera_device *icd,
979 struct v4l2_rect *rect = &a->c;
980 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
981 struct v4l2_mbus_framefmt mf;
984 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
985 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
987 ret = v4l2_subdev_call(sd, video, s_crop, a);
991 /* The capture device might have changed its output */
992 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
996 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
997 mf.width, mf.height);
999 icd->user_width = mf.width;
1000 icd->user_height = mf.height;
1005 static int mx2_camera_get_formats(struct soc_camera_device *icd,
1007 struct soc_camera_format_xlate *xlate)
1009 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1010 const struct soc_mbus_pixelfmt *fmt;
1011 struct device *dev = icd->parent;
1012 enum v4l2_mbus_pixelcode code;
1013 int ret, formats = 0;
1015 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1017 /* no more formats */
1020 fmt = soc_mbus_get_fmtdesc(code);
1022 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1026 if (code == V4L2_MBUS_FMT_YUYV8_2X8) {
1030 * CH2 can output YUV420 which is a standard format in
1034 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1036 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1037 xlate->host_fmt->name, code);
1042 /* Generic pass-trough */
1045 xlate->host_fmt = fmt;
1052 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1053 struct v4l2_format *f)
1055 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1056 struct mx2_camera_dev *pcdev = ici->priv;
1057 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1058 const struct soc_camera_format_xlate *xlate;
1059 struct v4l2_pix_format *pix = &f->fmt.pix;
1060 struct v4l2_mbus_framefmt mf;
1063 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1065 dev_warn(icd->parent, "Format %x not found\n",
1070 mf.width = pix->width;
1071 mf.height = pix->height;
1072 mf.field = pix->field;
1073 mf.colorspace = pix->colorspace;
1074 mf.code = xlate->code;
1076 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1077 if (ret < 0 && ret != -ENOIOCTLCMD)
1080 if (mf.code != xlate->code)
1083 pix->width = mf.width;
1084 pix->height = mf.height;
1085 pix->field = mf.field;
1086 pix->colorspace = mf.colorspace;
1087 icd->current_fmt = xlate;
1090 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1091 xlate->host_fmt->fourcc);
1096 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1097 struct v4l2_format *f)
1099 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1100 const struct soc_camera_format_xlate *xlate;
1101 struct v4l2_pix_format *pix = &f->fmt.pix;
1102 struct v4l2_mbus_framefmt mf;
1103 __u32 pixfmt = pix->pixelformat;
1104 unsigned int width_limit;
1107 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1108 if (pixfmt && !xlate) {
1109 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1113 /* FIXME: implement MX27 limits */
1115 /* limit to MX25 hardware capabilities */
1116 if (cpu_is_mx25()) {
1117 if (xlate->host_fmt->bits_per_sample <= 8)
1118 width_limit = 0xffff * 4;
1120 width_limit = 0xffff * 2;
1121 /* CSIIMAG_PARA limit */
1122 if (pix->width > width_limit)
1123 pix->width = width_limit;
1124 if (pix->height > 0xffff)
1125 pix->height = 0xffff;
1127 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1129 if (pix->bytesperline < 0)
1130 return pix->bytesperline;
1131 pix->sizeimage = pix->height * pix->bytesperline;
1132 /* Check against the CSIRXCNT limit */
1133 if (pix->sizeimage > 4 * 0x3ffff) {
1134 /* Adjust geometry, preserve aspect ratio */
1135 unsigned int new_height = int_sqrt(4 * 0x3ffff *
1136 pix->height / pix->bytesperline);
1137 pix->width = new_height * pix->width / pix->height;
1138 pix->height = new_height;
1139 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1141 BUG_ON(pix->bytesperline < 0);
1145 /* limit to sensor capabilities */
1146 mf.width = pix->width;
1147 mf.height = pix->height;
1148 mf.field = pix->field;
1149 mf.colorspace = pix->colorspace;
1150 mf.code = xlate->code;
1152 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1156 if (mf.field == V4L2_FIELD_ANY)
1157 mf.field = V4L2_FIELD_NONE;
1159 * Driver supports interlaced images provided they have
1160 * both fields so that they can be processed as if they
1163 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1164 dev_err(icd->parent, "Field type %d unsupported.\n",
1169 pix->width = mf.width;
1170 pix->height = mf.height;
1171 pix->field = mf.field;
1172 pix->colorspace = mf.colorspace;
1177 static int mx2_camera_querycap(struct soc_camera_host *ici,
1178 struct v4l2_capability *cap)
1180 /* cap->name is set by the friendly caller:-> */
1181 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1182 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1187 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1189 struct soc_camera_device *icd = file->private_data;
1191 return vb2_poll(&icd->vb2_vidq, file, pt);
1194 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1195 .owner = THIS_MODULE,
1196 .add = mx2_camera_add_device,
1197 .remove = mx2_camera_remove_device,
1198 .set_fmt = mx2_camera_set_fmt,
1199 .set_crop = mx2_camera_set_crop,
1200 .get_formats = mx2_camera_get_formats,
1201 .try_fmt = mx2_camera_try_fmt,
1202 .init_videobuf2 = mx2_camera_init_videobuf,
1203 .poll = mx2_camera_poll,
1204 .querycap = mx2_camera_querycap,
1205 .set_bus_param = mx2_camera_set_bus_param,
1208 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1209 int bufnum, bool err)
1212 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1214 struct mx2_buf_internal *ibuf;
1215 struct mx2_buffer *buf;
1216 struct vb2_buffer *vb;
1219 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1222 BUG_ON(ibuf->bufnum != bufnum);
1224 if (ibuf->discard) {
1226 * Discard buffer must not be returned to user space.
1227 * Just return it to the discard queue.
1229 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1231 buf = mx2_ibuf_to_buf(ibuf);
1235 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1236 if (prp->cfg.channel == 1) {
1237 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1238 4 * bufnum) != phys) {
1239 dev_err(pcdev->dev, "%lx != %x\n", phys,
1240 readl(pcdev->base_emma +
1241 PRP_DEST_RGB1_PTR + 4 * bufnum));
1244 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1245 0x14 * bufnum) != phys) {
1246 dev_err(pcdev->dev, "%lx != %x\n", phys,
1247 readl(pcdev->base_emma +
1248 PRP_DEST_Y_PTR - 0x14 * bufnum));
1252 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1253 vb2_plane_vaddr(vb, 0),
1254 vb2_get_plane_payload(vb, 0));
1256 list_del_init(&buf->internal.queue);
1257 do_gettimeofday(&vb->v4l2_buf.timestamp);
1258 vb->v4l2_buf.sequence = pcdev->frame_count;
1260 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1262 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1265 pcdev->frame_count++;
1267 if (list_empty(&pcdev->capture)) {
1268 if (list_empty(&pcdev->discard)) {
1269 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1274 ibuf = list_first_entry(&pcdev->discard,
1275 struct mx2_buf_internal, queue);
1276 ibuf->bufnum = bufnum;
1278 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1279 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1283 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1286 buf->internal.bufnum = bufnum;
1288 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1291 buf->state = MX2_STATE_ACTIVE;
1293 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1294 mx27_update_emma_buf(pcdev, phys, bufnum);
1297 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1299 struct mx2_camera_dev *pcdev = data;
1300 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1301 struct mx2_buf_internal *ibuf;
1303 spin_lock(&pcdev->lock);
1305 if (list_empty(&pcdev->active_bufs)) {
1306 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1310 spin_unlock(&pcdev->lock);
1315 if (status & (1 << 7)) { /* overflow */
1316 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1317 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1318 pcdev->base_emma + PRP_CNTL);
1319 writel(cntl, pcdev->base_emma + PRP_CNTL);
1321 ibuf = list_first_entry(&pcdev->active_bufs,
1322 struct mx2_buf_internal, queue);
1323 mx27_camera_frame_done_emma(pcdev,
1324 ibuf->bufnum, true);
1326 status &= ~(1 << 7);
1327 } else if (((status & (3 << 5)) == (3 << 5)) ||
1328 ((status & (3 << 3)) == (3 << 3))) {
1330 * Both buffers have triggered, process the one we're expecting
1333 ibuf = list_first_entry(&pcdev->active_bufs,
1334 struct mx2_buf_internal, queue);
1335 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1336 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1337 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1338 mx27_camera_frame_done_emma(pcdev, 0, false);
1339 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1340 mx27_camera_frame_done_emma(pcdev, 1, false);
1343 spin_unlock(&pcdev->lock);
1344 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1349 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1351 struct resource *res_emma = pcdev->res_emma;
1354 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1355 MX2_CAM_DRV_NAME)) {
1360 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1361 if (!pcdev->base_emma) {
1366 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1367 MX2_CAM_DRV_NAME, pcdev);
1369 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1373 pcdev->clk_emma = clk_get(NULL, "emma");
1374 if (IS_ERR(pcdev->clk_emma)) {
1375 err = PTR_ERR(pcdev->clk_emma);
1379 clk_enable(pcdev->clk_emma);
1381 err = mx27_camera_emma_prp_reset(pcdev);
1383 goto exit_clk_emma_put;
1388 clk_disable(pcdev->clk_emma);
1389 clk_put(pcdev->clk_emma);
1391 free_irq(pcdev->irq_emma, pcdev);
1393 iounmap(pcdev->base_emma);
1395 release_mem_region(res_emma->start, resource_size(res_emma));
1400 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1402 struct mx2_camera_dev *pcdev;
1403 struct resource *res_csi, *res_emma;
1404 void __iomem *base_csi;
1405 int irq_csi, irq_emma;
1408 dev_dbg(&pdev->dev, "initialising\n");
1410 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1411 irq_csi = platform_get_irq(pdev, 0);
1412 if (res_csi == NULL || irq_csi < 0) {
1413 dev_err(&pdev->dev, "Missing platform resources data\n");
1418 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1420 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1425 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1426 if (IS_ERR(pcdev->clk_csi)) {
1427 dev_err(&pdev->dev, "Could not get csi clock\n");
1428 err = PTR_ERR(pcdev->clk_csi);
1432 pcdev->res_csi = res_csi;
1433 pcdev->pdata = pdev->dev.platform_data;
1437 pcdev->platform_flags = pcdev->pdata->flags;
1439 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1444 err = clk_set_rate(pcdev->clk_csi, rate);
1449 INIT_LIST_HEAD(&pcdev->capture);
1450 INIT_LIST_HEAD(&pcdev->active_bufs);
1451 INIT_LIST_HEAD(&pcdev->discard);
1452 spin_lock_init(&pcdev->lock);
1455 * Request the regions.
1457 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1458 MX2_CAM_DRV_NAME)) {
1463 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1468 pcdev->irq_csi = irq_csi;
1469 pcdev->base_csi = base_csi;
1470 pcdev->base_dma = res_csi->start;
1471 pcdev->dev = &pdev->dev;
1473 if (cpu_is_mx25()) {
1474 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0,
1475 MX2_CAM_DRV_NAME, pcdev);
1477 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1482 if (cpu_is_mx27()) {
1484 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1485 irq_emma = platform_get_irq(pdev, 1);
1487 if (!res_emma || !irq_emma) {
1488 dev_err(&pdev->dev, "no EMMA resources\n");
1492 pcdev->res_emma = res_emma;
1493 pcdev->irq_emma = irq_emma;
1494 if (mx27_camera_emma_init(pcdev))
1498 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1499 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1500 pcdev->soc_host.priv = pcdev;
1501 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1502 pcdev->soc_host.nr = pdev->id;
1504 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1505 if (IS_ERR(pcdev->alloc_ctx)) {
1506 err = PTR_ERR(pcdev->alloc_ctx);
1509 err = soc_camera_host_register(&pcdev->soc_host);
1511 goto exit_free_emma;
1513 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1514 clk_get_rate(pcdev->clk_csi));
1519 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1521 if (cpu_is_mx27()) {
1522 free_irq(pcdev->irq_emma, pcdev);
1523 clk_disable(pcdev->clk_emma);
1524 clk_put(pcdev->clk_emma);
1525 iounmap(pcdev->base_emma);
1526 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma));
1530 free_irq(pcdev->irq_csi, pcdev);
1534 release_mem_region(res_csi->start, resource_size(res_csi));
1536 clk_put(pcdev->clk_csi);
1543 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1545 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1546 struct mx2_camera_dev *pcdev = container_of(soc_host,
1547 struct mx2_camera_dev, soc_host);
1548 struct resource *res;
1550 clk_put(pcdev->clk_csi);
1552 free_irq(pcdev->irq_csi, pcdev);
1554 free_irq(pcdev->irq_emma, pcdev);
1556 soc_camera_host_unregister(&pcdev->soc_host);
1558 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1560 iounmap(pcdev->base_csi);
1562 if (cpu_is_mx27()) {
1563 clk_disable(pcdev->clk_emma);
1564 clk_put(pcdev->clk_emma);
1565 iounmap(pcdev->base_emma);
1566 res = pcdev->res_emma;
1567 release_mem_region(res->start, resource_size(res));
1570 res = pcdev->res_csi;
1571 release_mem_region(res->start, resource_size(res));
1575 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1580 static struct platform_driver mx2_camera_driver = {
1582 .name = MX2_CAM_DRV_NAME,
1584 .remove = __devexit_p(mx2_camera_remove),
1588 static int __init mx2_camera_init(void)
1590 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1593 static void __exit mx2_camera_exit(void)
1595 return platform_driver_unregister(&mx2_camera_driver);
1598 module_init(mx2_camera_init);
1599 module_exit(mx2_camera_exit);
1601 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1602 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1603 MODULE_LICENSE("GPL");
1604 MODULE_VERSION(MX2_CAM_VERSION);