2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include "cx25821-medusa-video.h"
27 #include "cx25821-biffuncs.h"
30 * medusa_enable_bluefield_output()
32 * Enable the generation of blue filed output if no video
35 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
41 int out_ctrl = OUT_CTRL1;
42 int out_ctrl_ns = OUT_CTRL_NS;
49 out_ctrl = VDEC_B_OUT_CTRL1;
50 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
53 out_ctrl = VDEC_C_OUT_CTRL1;
54 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
57 out_ctrl = VDEC_D_OUT_CTRL1;
58 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
61 out_ctrl = VDEC_E_OUT_CTRL1;
62 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
65 out_ctrl = VDEC_F_OUT_CTRL1;
66 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
69 out_ctrl = VDEC_G_OUT_CTRL1;
70 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
73 out_ctrl = VDEC_H_OUT_CTRL1;
74 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
78 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
79 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
81 value |= 0x00000080; /* set BLUE_FIELD_EN */
82 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
84 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
87 value |= 0x00000080; /* set BLUE_FIELD_EN */
88 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
91 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
98 mutex_lock(&dev->lock);
100 for (i = 0; i < MAX_DECODERS; i++) {
101 /* set video format NTSC-M */
102 value = cx25821_i2c_read(&dev->i2c_bus[0],
103 MODE_CTRL + (0x200 * i), &tmp);
105 /* enable the fast locking mode bit[16] */
107 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
108 MODE_CTRL + (0x200 * i), value);
110 /* resolution NTSC 720x480 */
111 value = cx25821_i2c_read(&dev->i2c_bus[0],
112 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
115 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
116 HORIZ_TIM_CTRL + (0x200 * i), value);
118 value = cx25821_i2c_read(&dev->i2c_bus[0],
119 VERT_TIM_CTRL + (0x200 * i), &tmp);
121 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
122 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
123 VERT_TIM_CTRL + (0x200 * i), value);
125 /* chroma subcarrier step size */
126 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
127 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
129 /* enable VIP optional active */
130 value = cx25821_i2c_read(&dev->i2c_bus[0],
131 OUT_CTRL_NS + (0x200 * i), &tmp);
134 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
135 OUT_CTRL_NS + (0x200 * i), value);
137 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
138 value = cx25821_i2c_read(&dev->i2c_bus[0],
139 OUT_CTRL1 + (0x200 * i), &tmp);
142 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
143 OUT_CTRL1 + (0x200 * i), value);
146 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
147 * when the input switching rate < 16 fields
149 value = cx25821_i2c_read(&dev->i2c_bus[0],
150 MISC_TIM_CTRL + (0x200 * i), &tmp);
151 /* disable special play detection */
152 value = setBitAtPos(value, 14);
153 value = clearBitAtPos(value, 15);
154 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
155 MISC_TIM_CTRL + (0x200 * i), value);
157 /* set vbi_gate_en to 0 */
158 value = cx25821_i2c_read(&dev->i2c_bus[0],
159 DFE_CTRL1 + (0x200 * i), &tmp);
160 value = clearBitAtPos(value, 29);
161 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
162 DFE_CTRL1 + (0x200 * i), value);
164 /* Enable the generation of blue field output if no video */
165 medusa_enable_bluefield_output(dev, i, 1);
168 for (i = 0; i < MAX_ENCODERS; i++) {
170 value = cx25821_i2c_read(&dev->i2c_bus[0],
171 DENC_A_REG_1 + (0x100 * i), &tmp);
174 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
175 DENC_A_REG_1 + (0x100 * i), value);
177 /* burst begin and burst end */
178 value = cx25821_i2c_read(&dev->i2c_bus[0],
179 DENC_A_REG_2 + (0x100 * i), &tmp);
182 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
183 DENC_A_REG_2 + (0x100 * i), value);
185 value = cx25821_i2c_read(&dev->i2c_bus[0],
186 DENC_A_REG_3 + (0x100 * i), &tmp);
189 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
190 DENC_A_REG_3 + (0x100 * i), value);
192 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
193 value = cx25821_i2c_read(&dev->i2c_bus[0],
194 DENC_A_REG_4 + (0x100 * i), &tmp);
197 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
198 DENC_A_REG_4 + (0x100 * i), value);
200 value = cx25821_i2c_read(&dev->i2c_bus[0],
201 DENC_A_REG_5 + (0x100 * i), &tmp);
204 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
205 DENC_A_REG_5 + (0x100 * i), value);
207 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
208 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
210 /* Subcarrier Increment */
211 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
212 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
215 /* set picture resolutions */
217 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
219 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
221 /* set Bypass input format to NTSC 525 lines */
222 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
224 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
226 mutex_unlock(&dev->lock);
231 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
234 u32 value = 0, tmp = 0;
236 /* Setup for 2D threshold */
237 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
238 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
239 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
240 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
241 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
242 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
244 /* Setup flat chroma and luma thresholds */
245 value = cx25821_i2c_read(&dev->i2c_bus[0],
246 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
248 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
249 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
251 /* set comb 2D blend */
252 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
253 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
255 /* COMB MISC CONTROL */
256 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
257 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
262 static int medusa_initialize_pal(struct cx25821_dev *dev)
269 mutex_lock(&dev->lock);
271 for (i = 0; i < MAX_DECODERS; i++) {
272 /* set video format PAL-BDGHI */
273 value = cx25821_i2c_read(&dev->i2c_bus[0],
274 MODE_CTRL + (0x200 * i), &tmp);
276 /* enable the fast locking mode bit[16] */
278 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
279 MODE_CTRL + (0x200 * i), value);
281 /* resolution PAL 720x576 */
282 value = cx25821_i2c_read(&dev->i2c_bus[0],
283 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
286 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
287 HORIZ_TIM_CTRL + (0x200 * i), value);
289 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
290 value = cx25821_i2c_read(&dev->i2c_bus[0],
291 VERT_TIM_CTRL + (0x200 * i), &tmp);
293 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
294 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
295 VERT_TIM_CTRL + (0x200 * i), value);
297 /* chroma subcarrier step size */
298 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
299 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
301 /* enable VIP optional active */
302 value = cx25821_i2c_read(&dev->i2c_bus[0],
303 OUT_CTRL_NS + (0x200 * i), &tmp);
306 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
307 OUT_CTRL_NS + (0x200 * i), value);
309 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
310 value = cx25821_i2c_read(&dev->i2c_bus[0],
311 OUT_CTRL1 + (0x200 * i), &tmp);
314 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
315 OUT_CTRL1 + (0x200 * i), value);
318 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
319 * when the input switching rate < 16 fields
321 value = cx25821_i2c_read(&dev->i2c_bus[0],
322 MISC_TIM_CTRL + (0x200 * i), &tmp);
323 /* disable special play detection */
324 value = setBitAtPos(value, 14);
325 value = clearBitAtPos(value, 15);
326 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
327 MISC_TIM_CTRL + (0x200 * i), value);
329 /* set vbi_gate_en to 0 */
330 value = cx25821_i2c_read(&dev->i2c_bus[0],
331 DFE_CTRL1 + (0x200 * i), &tmp);
332 value = clearBitAtPos(value, 29);
333 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
334 DFE_CTRL1 + (0x200 * i), value);
336 medusa_PALCombInit(dev, i);
338 /* Enable the generation of blue field output if no video */
339 medusa_enable_bluefield_output(dev, i, 1);
342 for (i = 0; i < MAX_ENCODERS; i++) {
344 value = cx25821_i2c_read(&dev->i2c_bus[0],
345 DENC_A_REG_1 + (0x100 * i), &tmp);
348 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
349 DENC_A_REG_1 + (0x100 * i), value);
351 /* burst begin and burst end */
352 value = cx25821_i2c_read(&dev->i2c_bus[0],
353 DENC_A_REG_2 + (0x100 * i), &tmp);
356 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
357 DENC_A_REG_2 + (0x100 * i), value);
359 /* hblank and vactive */
360 value = cx25821_i2c_read(&dev->i2c_bus[0],
361 DENC_A_REG_3 + (0x100 * i), &tmp);
364 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
365 DENC_A_REG_3 + (0x100 * i), value);
367 /* set PAL vblank, phase alternation, 0 IRE pedestal */
368 value = cx25821_i2c_read(&dev->i2c_bus[0],
369 DENC_A_REG_4 + (0x100 * i), &tmp);
372 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
373 DENC_A_REG_4 + (0x100 * i), value);
375 value = cx25821_i2c_read(&dev->i2c_bus[0],
376 DENC_A_REG_5 + (0x100 * i), &tmp);
379 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
380 DENC_A_REG_5 + (0x100 * i), value);
382 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
383 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
385 /* Subcarrier Increment */
386 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
387 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
390 /* set picture resolutions */
392 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
394 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
396 /* set Bypass input format to PAL 625 lines */
397 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
399 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
401 mutex_unlock(&dev->lock);
406 int medusa_set_videostandard(struct cx25821_dev *dev)
408 int status = STATUS_SUCCESS;
409 u32 value = 0, tmp = 0;
411 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
412 status = medusa_initialize_pal(dev);
414 status = medusa_initialize_ntsc(dev);
416 /* Enable DENC_A output */
417 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
418 value = setBitAtPos(value, 4);
419 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
421 /* Enable DENC_B output */
422 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
423 value = setBitAtPos(value, 4);
424 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
429 void medusa_set_resolution(struct cx25821_dev *dev, int width,
433 int decoder_count = 0;
437 const int MAX_WIDTH = 720;
439 mutex_lock(&dev->lock);
441 /* validate the width */
442 if (width > MAX_WIDTH) {
443 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
444 __func__, width, MAX_WIDTH);
448 if (decoder_select <= 7 && decoder_select >= 0) {
449 decoder = decoder_select;
450 decoder_count = decoder_select + 1;
453 decoder_count = _num_decoders;
483 for (; decoder < decoder_count; decoder++) {
484 /* write scaling values for each decoder */
485 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
486 HSCALE_CTRL + (0x200 * decoder), hscale);
487 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
488 VSCALE_CTRL + (0x200 * decoder), vscale);
491 mutex_unlock(&dev->lock);
494 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
500 u32 disp_cnt_reg = DISP_AB_CNT;
502 mutex_lock(&dev->lock);
505 if (decoder < VDEC_A && decoder > VDEC_H) {
506 mutex_unlock(&dev->lock);
515 disp_cnt_reg = DISP_CD_CNT;
519 disp_cnt_reg = DISP_EF_CNT;
523 disp_cnt_reg = DISP_GH_CNT;
527 _display_field_cnt[decoder] = duration;
529 /* update hardware */
530 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
532 if (!(decoder % 2)) { /* EVEN decoder */
533 fld_cnt &= 0xFFFF0000;
536 fld_cnt &= 0x0000FFFF;
537 fld_cnt |= ((u32) duration) << 16;
540 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
542 mutex_unlock(&dev->lock);
545 /* Map to Medusa register setting */
546 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
553 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
556 * This is the overall expression used:
558 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
559 * but we need to account for rounding so below we use the modulus
560 * operator to find the remainder and increment if necessary.
562 numerator = (srcVal - srcMin) * (dstMax - dstMin);
563 denominator = srcMax - srcMin;
564 quotient = numerator / denominator;
566 if (2 * (numerator % denominator) >= denominator)
569 *dstVal = quotient + dstMin;
574 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
581 temp = ~(abs(numeric) & 0xFF);
587 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
591 u32 val = 0, tmp = 0;
593 mutex_lock(&dev->lock);
594 if ((brightness > VIDEO_PROCAMP_MAX) ||
595 (brightness < VIDEO_PROCAMP_MIN)) {
596 mutex_unlock(&dev->lock);
599 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
600 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
601 value = convert_to_twos(value, 8);
602 val = cx25821_i2c_read(&dev->i2c_bus[0],
603 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
605 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
606 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
607 mutex_unlock(&dev->lock);
611 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
615 u32 val = 0, tmp = 0;
617 mutex_lock(&dev->lock);
619 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
620 mutex_unlock(&dev->lock);
624 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
625 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
626 val = cx25821_i2c_read(&dev->i2c_bus[0],
627 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
629 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
630 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
632 mutex_unlock(&dev->lock);
636 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
640 u32 val = 0, tmp = 0;
642 mutex_lock(&dev->lock);
644 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
645 mutex_unlock(&dev->lock);
649 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
650 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
652 value = convert_to_twos(value, 8);
653 val = cx25821_i2c_read(&dev->i2c_bus[0],
654 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
657 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
658 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
660 mutex_unlock(&dev->lock);
664 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
668 u32 val = 0, tmp = 0;
670 mutex_lock(&dev->lock);
672 if ((saturation > VIDEO_PROCAMP_MAX) ||
673 (saturation < VIDEO_PROCAMP_MIN)) {
674 mutex_unlock(&dev->lock);
678 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
679 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
681 val = cx25821_i2c_read(&dev->i2c_bus[0],
682 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
684 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
685 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
687 val = cx25821_i2c_read(&dev->i2c_bus[0],
688 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
690 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
691 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
693 mutex_unlock(&dev->lock);
697 /* Program the display sequence and monitor output. */
699 int medusa_video_init(struct cx25821_dev *dev)
701 u32 value = 0, tmp = 0;
705 mutex_lock(&dev->lock);
707 _num_decoders = dev->_max_num_decoders;
709 /* disable Auto source selection on all video decoders */
710 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
712 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
717 /* Turn off Master source switch enable */
718 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
720 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
725 mutex_unlock(&dev->lock);
727 for (i = 0; i < _num_decoders; i++)
728 medusa_set_decoderduration(dev, i, _display_field_cnt[i]);
730 mutex_lock(&dev->lock);
732 /* Select monitor as DENC A input, power up the DAC */
733 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
735 value |= 0x00090008; /* set en_active */
736 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
741 /* enable input is VIP/656 */
742 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
743 value |= 0x00040100; /* enable VIP */
744 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
749 /* select AFE clock to output mode */
750 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
752 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
758 /* Turn on all of the data out and control output pins. */
759 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
761 if (_num_decoders == MAX_DECODERS) {
763 * Note: The octal board does not support control pins(bit16-19)
764 * These bits are ignored in the octal board.
766 * disable VDEC A-C port, default to Mobilygen Interface
770 /* disable VDEC A-C port, default to Mobilygen Interface */
775 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
781 mutex_unlock(&dev->lock);
783 ret_val = medusa_set_videostandard(dev);
788 mutex_unlock(&dev->lock);